From c8cac8a53ce9d663b1c816bab4e0b849a837d8f5 Mon Sep 17 00:00:00 2001 From: Alin-Tudor Sferle Date: Sun, 12 Nov 2023 11:30:11 +0200 Subject: [PATCH 1/2] pwm_gen_pkg: Add support for 16 channels --- common/sv/adi_regmap_pwm_gen_pkg.sv | 207 ++++++++++++++++++++++++++-- 1 file changed, 193 insertions(+), 14 deletions(-) diff --git a/common/sv/adi_regmap_pwm_gen_pkg.sv b/common/sv/adi_regmap_pwm_gen_pkg.sv index d742130a..2b030278 100644 --- a/common/sv/adi_regmap_pwm_gen_pkg.sv +++ b/common/sv/adi_regmap_pwm_gen_pkg.sv @@ -49,70 +49,249 @@ package adi_regmap_pwm_gen_pkg; `define SET_REG_RSTN_RESET(x) SetField(REG_RSTN,"RESET",x) `define GET_REG_RSTN_RESET(x) GetField(REG_RSTN,"RESET",x) - const reg_t REG_N_PULSES = '{ 'h0014, "REG_N_PULSES" , '{ + const reg_t REG_N_PWMS = '{ 'h0014, "REG_N_PWMS" , '{ "": '{ 31, 0, RO, 'h0000 }}}; - `define SET_REG_N_PULSES_(x) SetField(REG_N_PULSES,"",x) - `define GET_REG_N_PULSES_(x) GetField(REG_N_PULSES,"",x) + `define SET_REG_N_PWMS_(x) SetField(REG_N_PWMS,"",x) + `define GET_REG_N_PWMS_(x) GetField(REG_N_PWMS,"",x) const reg_t REG_PULSE_0_PERIOD = '{ 'h0040, "REG_PULSE_0_PERIOD" , '{ "PULSE_0_PERIOD": '{ 31, 0, RW, 'h0000 }}}; `define SET_REG_PULSE_0_PERIOD_PULSE_0_PERIOD(x) SetField(REG_PULSE_0_PERIOD,"PULSE_0_PERIOD",x) `define GET_REG_PULSE_0_PERIOD_PULSE_0_PERIOD(x) GetField(REG_PULSE_0_PERIOD,"PULSE_0_PERIOD",x) - const reg_t REG_PULSE_0_WIDTH = '{ 'h0044, "REG_PULSE_0_WIDTH" , '{ + const reg_t REG_PULSE_0_WIDTH = '{ 'h0080, "REG_PULSE_0_WIDTH" , '{ "PULSE_0_WIDTH": '{ 31, 0, RW, 'h0000 }}}; `define SET_REG_PULSE_0_WIDTH_PULSE_0_WIDTH(x) SetField(REG_PULSE_0_WIDTH,"PULSE_0_WIDTH",x) `define GET_REG_PULSE_0_WIDTH_PULSE_0_WIDTH(x) GetField(REG_PULSE_0_WIDTH,"PULSE_0_WIDTH",x) - const reg_t REG_PULSE_0_OFFSET = '{ 'h0048, "REG_PULSE_0_OFFSET" , '{ + const reg_t REG_PULSE_0_OFFSET = '{ 'h00c0, "REG_PULSE_0_OFFSET" , '{ "PULSE_0_OFFSET": '{ 31, 0, RW, 'h0000 }}}; `define SET_REG_PULSE_0_OFFSET_PULSE_0_OFFSET(x) SetField(REG_PULSE_0_OFFSET,"PULSE_0_OFFSET",x) `define GET_REG_PULSE_0_OFFSET_PULSE_0_OFFSET(x) GetField(REG_PULSE_0_OFFSET,"PULSE_0_OFFSET",x) - const reg_t REG_PULSE_1_PERIOD = '{ 'h004c, "REG_PULSE_1_PERIOD" , '{ + const reg_t REG_PULSE_1_PERIOD = '{ 'h0044, "REG_PULSE_1_PERIOD" , '{ "PULSE_1_PERIOD": '{ 31, 0, RW, 'h0000 }}}; `define SET_REG_PULSE_1_PERIOD_PULSE_1_PERIOD(x) SetField(REG_PULSE_1_PERIOD,"PULSE_1_PERIOD",x) `define GET_REG_PULSE_1_PERIOD_PULSE_1_PERIOD(x) GetField(REG_PULSE_1_PERIOD,"PULSE_1_PERIOD",x) - const reg_t REG_PULSE_1_WIDTH = '{ 'h0050, "REG_PULSE_1_WIDTH" , '{ + const reg_t REG_PULSE_1_WIDTH = '{ 'h0084, "REG_PULSE_1_WIDTH" , '{ "PULSE_1_WIDTH": '{ 31, 0, RW, 'h0000 }}}; `define SET_REG_PULSE_1_WIDTH_PULSE_1_WIDTH(x) SetField(REG_PULSE_1_WIDTH,"PULSE_1_WIDTH",x) `define GET_REG_PULSE_1_WIDTH_PULSE_1_WIDTH(x) GetField(REG_PULSE_1_WIDTH,"PULSE_1_WIDTH",x) - const reg_t REG_PULSE_1_OFFSET = '{ 'h0054, "REG_PULSE_1_OFFSET" , '{ + const reg_t REG_PULSE_1_OFFSET = '{ 'h00c4, "REG_PULSE_1_OFFSET" , '{ "PULSE_1_OFFSET": '{ 31, 0, RW, 'h0000 }}}; `define SET_REG_PULSE_1_OFFSET_PULSE_1_OFFSET(x) SetField(REG_PULSE_1_OFFSET,"PULSE_1_OFFSET",x) `define GET_REG_PULSE_1_OFFSET_PULSE_1_OFFSET(x) GetField(REG_PULSE_1_OFFSET,"PULSE_1_OFFSET",x) - const reg_t REG_PULSE_2_PERIOD = '{ 'h0058, "REG_PULSE_2_PERIOD" , '{ + const reg_t REG_PULSE_2_PERIOD = '{ 'h0048, "REG_PULSE_2_PERIOD" , '{ "PULSE_2_PERIOD": '{ 31, 0, RW, 'h0000 }}}; `define SET_REG_PULSE_2_PERIOD_PULSE_2_PERIOD(x) SetField(REG_PULSE_2_PERIOD,"PULSE_2_PERIOD",x) `define GET_REG_PULSE_2_PERIOD_PULSE_2_PERIOD(x) GetField(REG_PULSE_2_PERIOD,"PULSE_2_PERIOD",x) - const reg_t REG_PULSE_2_WIDTH = '{ 'h005c, "REG_PULSE_2_WIDTH" , '{ + const reg_t REG_PULSE_2_WIDTH = '{ 'h0088, "REG_PULSE_2_WIDTH" , '{ "PULSE_2_WIDTH": '{ 31, 0, RW, 'h0000 }}}; `define SET_REG_PULSE_2_WIDTH_PULSE_2_WIDTH(x) SetField(REG_PULSE_2_WIDTH,"PULSE_2_WIDTH",x) `define GET_REG_PULSE_2_WIDTH_PULSE_2_WIDTH(x) GetField(REG_PULSE_2_WIDTH,"PULSE_2_WIDTH",x) - const reg_t REG_PULSE_2_OFFSET = '{ 'h0060, "REG_PULSE_2_OFFSET" , '{ + const reg_t REG_PULSE_2_OFFSET = '{ 'h00c8, "REG_PULSE_2_OFFSET" , '{ "PULSE_2_OFFSET": '{ 31, 0, RW, 'h0000 }}}; `define SET_REG_PULSE_2_OFFSET_PULSE_2_OFFSET(x) SetField(REG_PULSE_2_OFFSET,"PULSE_2_OFFSET",x) `define GET_REG_PULSE_2_OFFSET_PULSE_2_OFFSET(x) GetField(REG_PULSE_2_OFFSET,"PULSE_2_OFFSET",x) - const reg_t REG_PULSE_3_PERIOD = '{ 'h0064, "REG_PULSE_3_PERIOD" , '{ + const reg_t REG_PULSE_3_PERIOD = '{ 'h004c, "REG_PULSE_3_PERIOD" , '{ "PULSE_3_PERIOD": '{ 31, 0, RW, 'h0000 }}}; `define SET_REG_PULSE_3_PERIOD_PULSE_3_PERIOD(x) SetField(REG_PULSE_3_PERIOD,"PULSE_3_PERIOD",x) `define GET_REG_PULSE_3_PERIOD_PULSE_3_PERIOD(x) GetField(REG_PULSE_3_PERIOD,"PULSE_3_PERIOD",x) - const reg_t REG_PULSE_3_WIDTH = '{ 'h0068, "REG_PULSE_3_WIDTH" , '{ + const reg_t REG_PULSE_3_WIDTH = '{ 'h008c, "REG_PULSE_3_WIDTH" , '{ "PULSE_3_WIDTH": '{ 31, 0, RW, 'h0000 }}}; `define SET_REG_PULSE_3_WIDTH_PULSE_3_WIDTH(x) SetField(REG_PULSE_3_WIDTH,"PULSE_3_WIDTH",x) `define GET_REG_PULSE_3_WIDTH_PULSE_3_WIDTH(x) GetField(REG_PULSE_3_WIDTH,"PULSE_3_WIDTH",x) - const reg_t REG_PULSE_3_OFFSET = '{ 'h006c, "REG_PULSE_3_OFFSET" , '{ + const reg_t REG_PULSE_3_OFFSET = '{ 'h00cc, "REG_PULSE_3_OFFSET" , '{ "PULSE_3_OFFSET": '{ 31, 0, RW, 'h0000 }}}; `define SET_REG_PULSE_3_OFFSET_PULSE_3_OFFSET(x) SetField(REG_PULSE_3_OFFSET,"PULSE_3_OFFSET",x) `define GET_REG_PULSE_3_OFFSET_PULSE_3_OFFSET(x) GetField(REG_PULSE_3_OFFSET,"PULSE_3_OFFSET",x) + const reg_t REG_PULSE_4_PERIOD = '{ 'h0050, "REG_PULSE_4_PERIOD" , '{ + "PULSE_4_PERIOD": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_4_PERIOD_PULSE_4_PERIOD(x) SetField(REG_PULSE_4_PERIOD,"PULSE_4_PERIOD",x) + `define GET_REG_PULSE_4_PERIOD_PULSE_4_PERIOD(x) GetField(REG_PULSE_4_PERIOD,"PULSE_4_PERIOD",x) + + const reg_t REG_PULSE_4_WIDTH = '{ 'h0090, "REG_PULSE_4_WIDTH" , '{ + "PULSE_4_WIDTH": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_4_WIDTH_PULSE_4_WIDTH(x) SetField(REG_PULSE_4_WIDTH,"PULSE_4_WIDTH",x) + `define GET_REG_PULSE_4_WIDTH_PULSE_4_WIDTH(x) GetField(REG_PULSE_4_WIDTH,"PULSE_4_WIDTH",x) + + const reg_t REG_PULSE_4_OFFSET = '{ 'h00d0, "REG_PULSE_4_OFFSET" , '{ + "PULSE_4_OFFSET": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_4_OFFSET_PULSE_4_OFFSET(x) SetField(REG_PULSE_4_OFFSET,"PULSE_4_OFFSET",x) + `define GET_REG_PULSE_4_OFFSET_PULSE_4_OFFSET(x) GetField(REG_PULSE_4_OFFSET,"PULSE_4_OFFSET",x) + + const reg_t REG_PULSE_5_PERIOD = '{ 'h0054, "REG_PULSE_5_PERIOD" , '{ + "PULSE_5_PERIOD": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_5_PERIOD_PULSE_5_PERIOD(x) SetField(REG_PULSE_5_PERIOD,"PULSE_5_PERIOD",x) + `define GET_REG_PULSE_5_PERIOD_PULSE_5_PERIOD(x) GetField(REG_PULSE_5_PERIOD,"PULSE_5_PERIOD",x) + + const reg_t REG_PULSE_5_WIDTH = '{ 'h0094, "REG_PULSE_5_WIDTH" , '{ + "PULSE_5_WIDTH": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_5_WIDTH_PULSE_5_WIDTH(x) SetField(REG_PULSE_5_WIDTH,"PULSE_5_WIDTH",x) + `define GET_REG_PULSE_5_WIDTH_PULSE_5_WIDTH(x) GetField(REG_PULSE_5_WIDTH,"PULSE_5_WIDTH",x) + + const reg_t REG_PULSE_5_OFFSET = '{ 'h00d4, "REG_PULSE_5_OFFSET" , '{ + "PULSE_5_OFFSET": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_5_OFFSET_PULSE_5_OFFSET(x) SetField(REG_PULSE_5_OFFSET,"PULSE_5_OFFSET",x) + `define GET_REG_PULSE_5_OFFSET_PULSE_5_OFFSET(x) GetField(REG_PULSE_5_OFFSET,"PULSE_5_OFFSET",x) + + const reg_t REG_PULSE_6_PERIOD = '{ 'h0058, "REG_PULSE_6_PERIOD" , '{ + "PULSE_6_PERIOD": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_6_PERIOD_PULSE_6_PERIOD(x) SetField(REG_PULSE_6_PERIOD,"PULSE_6_PERIOD",x) + `define GET_REG_PULSE_6_PERIOD_PULSE_6_PERIOD(x) GetField(REG_PULSE_6_PERIOD,"PULSE_6_PERIOD",x) + + const reg_t REG_PULSE_6_WIDTH = '{ 'h0098, "REG_PULSE_6_WIDTH" , '{ + "PULSE_6_WIDTH": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_6_WIDTH_PULSE_6_WIDTH(x) SetField(REG_PULSE_6_WIDTH,"PULSE_6_WIDTH",x) + `define GET_REG_PULSE_6_WIDTH_PULSE_6_WIDTH(x) GetField(REG_PULSE_6_WIDTH,"PULSE_6_WIDTH",x) + + const reg_t REG_PULSE_6_OFFSET = '{ 'h00d8, "REG_PULSE_6_OFFSET" , '{ + "PULSE_6_OFFSET": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_6_OFFSET_PULSE_6_OFFSET(x) SetField(REG_PULSE_6_OFFSET,"PULSE_6_OFFSET",x) + `define GET_REG_PULSE_6_OFFSET_PULSE_6_OFFSET(x) GetField(REG_PULSE_6_OFFSET,"PULSE_6_OFFSET",x) + + const reg_t REG_PULSE_7_PERIOD = '{ 'h005c, "REG_PULSE_7_PERIOD" , '{ + "PULSE_7_PERIOD": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_7_PERIOD_PULSE_7_PERIOD(x) SetField(REG_PULSE_7_PERIOD,"PULSE_7_PERIOD",x) + `define GET_REG_PULSE_7_PERIOD_PULSE_7_PERIOD(x) GetField(REG_PULSE_7_PERIOD,"PULSE_7_PERIOD",x) + + const reg_t REG_PULSE_7_WIDTH = '{ 'h009c, "REG_PULSE_7_WIDTH" , '{ + "PULSE_7_WIDTH": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_7_WIDTH_PULSE_7_WIDTH(x) SetField(REG_PULSE_7_WIDTH,"PULSE_7_WIDTH",x) + `define GET_REG_PULSE_7_WIDTH_PULSE_7_WIDTH(x) GetField(REG_PULSE_7_WIDTH,"PULSE_7_WIDTH",x) + + const reg_t REG_PULSE_7_OFFSET = '{ 'h00dc, "REG_PULSE_7_OFFSET" , '{ + "PULSE_7_OFFSET": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_7_OFFSET_PULSE_7_OFFSET(x) SetField(REG_PULSE_7_OFFSET,"PULSE_7_OFFSET",x) + `define GET_REG_PULSE_7_OFFSET_PULSE_7_OFFSET(x) GetField(REG_PULSE_7_OFFSET,"PULSE_7_OFFSET",x) + + const reg_t REG_PULSE_8_PERIOD = '{ 'h0060, "REG_PULSE_8_PERIOD" , '{ + "PULSE_8_PERIOD": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_8_PERIOD_PULSE_8_PERIOD(x) SetField(REG_PULSE_8_PERIOD,"PULSE_8_PERIOD",x) + `define GET_REG_PULSE_8_PERIOD_PULSE_8_PERIOD(x) GetField(REG_PULSE_8_PERIOD,"PULSE_8_PERIOD",x) + + const reg_t REG_PULSE_8_WIDTH = '{ 'h00a0, "REG_PULSE_8_WIDTH" , '{ + "PULSE_8_WIDTH": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_8_WIDTH_PULSE_8_WIDTH(x) SetField(REG_PULSE_8_WIDTH,"PULSE_8_WIDTH",x) + `define GET_REG_PULSE_8_WIDTH_PULSE_8_WIDTH(x) GetField(REG_PULSE_8_WIDTH,"PULSE_8_WIDTH",x) + + const reg_t REG_PULSE_8_OFFSET = '{ 'h00e0, "REG_PULSE_8_OFFSET" , '{ + "PULSE_8_OFFSET": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_8_OFFSET_PULSE_8_OFFSET(x) SetField(REG_PULSE_8_OFFSET,"PULSE_8_OFFSET",x) + `define GET_REG_PULSE_8_OFFSET_PULSE_8_OFFSET(x) GetField(REG_PULSE_8_OFFSET,"PULSE_8_OFFSET",x) + + const reg_t REG_PULSE_9_PERIOD = '{ 'h0064, "REG_PULSE_9_PERIOD" , '{ + "PULSE_9_PERIOD": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_9_PERIOD_PULSE_9_PERIOD(x) SetField(REG_PULSE_9_PERIOD,"PULSE_9_PERIOD",x) + `define GET_REG_PULSE_9_PERIOD_PULSE_9_PERIOD(x) GetField(REG_PULSE_9_PERIOD,"PULSE_9_PERIOD",x) + + const reg_t REG_PULSE_9_WIDTH = '{ 'h00a4, "REG_PULSE_9_WIDTH" , '{ + "PULSE_9_WIDTH": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_9_WIDTH_PULSE_9_WIDTH(x) SetField(REG_PULSE_9_WIDTH,"PULSE_9_WIDTH",x) + `define GET_REG_PULSE_9_WIDTH_PULSE_9_WIDTH(x) GetField(REG_PULSE_9_WIDTH,"PULSE_9_WIDTH",x) + + const reg_t REG_PULSE_9_OFFSET = '{ 'h00e4, "REG_PULSE_9_OFFSET" , '{ + "PULSE_9_OFFSET": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_9_OFFSET_PULSE_9_OFFSET(x) SetField(REG_PULSE_9_OFFSET,"PULSE_9_OFFSET",x) + `define GET_REG_PULSE_9_OFFSET_PULSE_9_OFFSET(x) GetField(REG_PULSE_9_OFFSET,"PULSE_9_OFFSET",x) + + const reg_t REG_PULSE_10_PERIOD = '{ 'h0068, "REG_PULSE_10_PERIOD" , '{ + "PULSE_10_PERIOD": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_10_PERIOD_PULSE_10_PERIOD(x) SetField(REG_PULSE_10_PERIOD,"PULSE_10_PERIOD",x) + `define GET_REG_PULSE_10_PERIOD_PULSE_10_PERIOD(x) GetField(REG_PULSE_10_PERIOD,"PULSE_10_PERIOD",x) + + const reg_t REG_PULSE_10_WIDTH = '{ 'h00a8, "REG_PULSE_10_WIDTH" , '{ + "PULSE_10_WIDTH": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_10_WIDTH_PULSE_10_WIDTH(x) SetField(REG_PULSE_10_WIDTH,"PULSE_10_WIDTH",x) + `define GET_REG_PULSE_10_WIDTH_PULSE_10_WIDTH(x) GetField(REG_PULSE_10_WIDTH,"PULSE_10_WIDTH",x) + + const reg_t REG_PULSE_10_OFFSET = '{ 'h00e8, "REG_PULSE_10_OFFSET" , '{ + "PULSE_10_OFFSET": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_10_OFFSET_PULSE_10_OFFSET(x) SetField(REG_PULSE_10_OFFSET,"PULSE_10_OFFSET",x) + `define GET_REG_PULSE_10_OFFSET_PULSE_10_OFFSET(x) GetField(REG_PULSE_10_OFFSET,"PULSE_10_OFFSET",x) + + const reg_t REG_PULSE_11_PERIOD = '{ 'h006c, "REG_PULSE_11_PERIOD" , '{ + "PULSE_11_PERIOD": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_11_PERIOD_PULSE_11_PERIOD(x) SetField(REG_PULSE_11_PERIOD,"PULSE_11_PERIOD",x) + `define GET_REG_PULSE_11_PERIOD_PULSE_11_PERIOD(x) GetField(REG_PULSE_11_PERIOD,"PULSE_11_PERIOD",x) + + const reg_t REG_PULSE_11_WIDTH = '{ 'h00ac, "REG_PULSE_11_WIDTH" , '{ + "PULSE_11_WIDTH": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_11_WIDTH_PULSE_11_WIDTH(x) SetField(REG_PULSE_11_WIDTH,"PULSE_11_WIDTH",x) + `define GET_REG_PULSE_11_WIDTH_PULSE_11_WIDTH(x) GetField(REG_PULSE_11_WIDTH,"PULSE_11_WIDTH",x) + + const reg_t REG_PULSE_11_OFFSET = '{ 'h00ec, "REG_PULSE_11_OFFSET" , '{ + "PULSE_11_OFFSET": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_11_OFFSET_PULSE_11_OFFSET(x) SetField(REG_PULSE_11_OFFSET,"PULSE_11_OFFSET",x) + `define GET_REG_PULSE_11_OFFSET_PULSE_11_OFFSET(x) GetField(REG_PULSE_11_OFFSET,"PULSE_11_OFFSET",x) + + const reg_t REG_PULSE_12_PERIOD = '{ 'h0070, "REG_PULSE_12_PERIOD" , '{ + "PULSE_12_PERIOD": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_12_PERIOD_PULSE_12_PERIOD(x) SetField(REG_PULSE_12_PERIOD,"PULSE_12_PERIOD",x) + `define GET_REG_PULSE_12_PERIOD_PULSE_12_PERIOD(x) GetField(REG_PULSE_12_PERIOD,"PULSE_12_PERIOD",x) + + const reg_t REG_PULSE_12_WIDTH = '{ 'h00b0, "REG_PULSE_12_WIDTH" , '{ + "PULSE_12_WIDTH": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_12_WIDTH_PULSE_12_WIDTH(x) SetField(REG_PULSE_12_WIDTH,"PULSE_12_WIDTH",x) + `define GET_REG_PULSE_12_WIDTH_PULSE_12_WIDTH(x) GetField(REG_PULSE_12_WIDTH,"PULSE_12_WIDTH",x) + + const reg_t REG_PULSE_12_OFFSET = '{ 'h00f0, "REG_PULSE_12_OFFSET" , '{ + "PULSE_12_OFFSET": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_12_OFFSET_PULSE_12_OFFSET(x) SetField(REG_PULSE_12_OFFSET,"PULSE_12_OFFSET",x) + `define GET_REG_PULSE_12_OFFSET_PULSE_12_OFFSET(x) GetField(REG_PULSE_12_OFFSET,"PULSE_12_OFFSET",x) + + const reg_t REG_PULSE_13_PERIOD = '{ 'h0074, "REG_PULSE_13_PERIOD" , '{ + "PULSE_13_PERIOD": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_13_PERIOD_PULSE_13_PERIOD(x) SetField(REG_PULSE_13_PERIOD,"PULSE_13_PERIOD",x) + `define GET_REG_PULSE_13_PERIOD_PULSE_13_PERIOD(x) GetField(REG_PULSE_13_PERIOD,"PULSE_13_PERIOD",x) + + const reg_t REG_PULSE_13_WIDTH = '{ 'h00b4, "REG_PULSE_13_WIDTH" , '{ + "PULSE_13_WIDTH": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_13_WIDTH_PULSE_13_WIDTH(x) SetField(REG_PULSE_13_WIDTH,"PULSE_13_WIDTH",x) + `define GET_REG_PULSE_13_WIDTH_PULSE_13_WIDTH(x) GetField(REG_PULSE_13_WIDTH,"PULSE_13_WIDTH",x) + + const reg_t REG_PULSE_13_OFFSET = '{ 'h00f4, "REG_PULSE_13_OFFSET" , '{ + "PULSE_13_OFFSET": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_13_OFFSET_PULSE_13_OFFSET(x) SetField(REG_PULSE_13_OFFSET,"PULSE_13_OFFSET",x) + `define GET_REG_PULSE_13_OFFSET_PULSE_13_OFFSET(x) GetField(REG_PULSE_13_OFFSET,"PULSE_13_OFFSET",x) + + const reg_t REG_PULSE_14_PERIOD = '{ 'h0078, "REG_PULSE_14_PERIOD" , '{ + "PULSE_14_PERIOD": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_14_PERIOD_PULSE_14_PERIOD(x) SetField(REG_PULSE_14_PERIOD,"PULSE_14_PERIOD",x) + `define GET_REG_PULSE_14_PERIOD_PULSE_14_PERIOD(x) GetField(REG_PULSE_14_PERIOD,"PULSE_14_PERIOD",x) + + const reg_t REG_PULSE_14_WIDTH = '{ 'h00b8, "REG_PULSE_14_WIDTH" , '{ + "PULSE_14_WIDTH": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_14_WIDTH_PULSE_14_WIDTH(x) SetField(REG_PULSE_14_WIDTH,"PULSE_14_WIDTH",x) + `define GET_REG_PULSE_14_WIDTH_PULSE_14_WIDTH(x) GetField(REG_PULSE_14_WIDTH,"PULSE_14_WIDTH",x) + + const reg_t REG_PULSE_14_OFFSET = '{ 'h00f8, "REG_PULSE_14_OFFSET" , '{ + "PULSE_14_OFFSET": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_14_OFFSET_PULSE_14_OFFSET(x) SetField(REG_PULSE_14_OFFSET,"PULSE_14_OFFSET",x) + `define GET_REG_PULSE_14_OFFSET_PULSE_14_OFFSET(x) GetField(REG_PULSE_14_OFFSET,"PULSE_14_OFFSET",x) + + const reg_t REG_PULSE_15_PERIOD = '{ 'h007c, "REG_PULSE_15_PERIOD" , '{ + "PULSE_15_PERIOD": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_15_PERIOD_PULSE_15_PERIOD(x) SetField(REG_PULSE_15_PERIOD,"PULSE_15_PERIOD",x) + `define GET_REG_PULSE_15_PERIOD_PULSE_15_PERIOD(x) GetField(REG_PULSE_15_PERIOD,"PULSE_15_PERIOD",x) + + const reg_t REG_PULSE_15_WIDTH = '{ 'h00bc, "REG_PULSE_15_WIDTH" , '{ + "PULSE_15_WIDTH": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_15_WIDTH_PULSE_15_WIDTH(x) SetField(REG_PULSE_15_WIDTH,"PULSE_15_WIDTH",x) + `define GET_REG_PULSE_15_WIDTH_PULSE_15_WIDTH(x) GetField(REG_PULSE_15_WIDTH,"PULSE_15_WIDTH",x) + + const reg_t REG_PULSE_15_OFFSET = '{ 'h00fc, "REG_PULSE_15_OFFSET" , '{ + "PULSE_15_OFFSET": '{ 31, 0, RW, 'h0000 }}}; + `define SET_REG_PULSE_15_OFFSET_PULSE_15_OFFSET(x) SetField(REG_PULSE_15_OFFSET,"PULSE_15_OFFSET",x) + `define GET_REG_PULSE_15_OFFSET_PULSE_15_OFFSET(x) GetField(REG_PULSE_15_OFFSET,"PULSE_15_OFFSET",x) endpackage From 4357752ab574251c3a9bba428ddb98c2406b9e41 Mon Sep 17 00:00:00 2001 From: Alin-Tudor Sferle Date: Sun, 12 Nov 2023 11:30:37 +0200 Subject: [PATCH 2/2] pwm_gen: Initial commit Signed-off-by: Alin-Tudor Sferle --- pwm_gen/Makefile | 57 +++++++++++ pwm_gen/README.md | 27 +++++ pwm_gen/cfgs/cfg1.tcl | 3 + pwm_gen/system_bd.tcl | 97 ++++++++++++++++++ pwm_gen/system_project.tcl | 42 ++++++++ pwm_gen/system_tb.sv | 99 ++++++++++++++++++ pwm_gen/tests/test_program.sv | 157 +++++++++++++++++++++++++++++ pwm_gen/waves/system_tb_behav.wcfg | 106 +++++++++++++++++++ 8 files changed, 588 insertions(+) create mode 100644 pwm_gen/Makefile create mode 100644 pwm_gen/README.md create mode 100644 pwm_gen/cfgs/cfg1.tcl create mode 100644 pwm_gen/system_bd.tcl create mode 100644 pwm_gen/system_project.tcl create mode 100644 pwm_gen/system_tb.sv create mode 100644 pwm_gen/tests/test_program.sv create mode 100644 pwm_gen/waves/system_tb_behav.wcfg diff --git a/pwm_gen/Makefile b/pwm_gen/Makefile new file mode 100644 index 00000000..ce174b49 --- /dev/null +++ b/pwm_gen/Makefile @@ -0,0 +1,57 @@ +#################################################################################### +#################################################################################### +## Copyright 2023(c) Analog Devices, Inc. +#################################################################################### +#################################################################################### + +# All test-bench dependencies except test programs +SV_DEPS += ../common/sv/utils.svh +SV_DEPS += ../common/sv/logger_pkg.sv +SV_DEPS += ../common/sv/reg_accessor.sv +SV_DEPS += ../common/sv/m_axis_sequencer.sv +SV_DEPS += ../common/sv/s_axis_sequencer.sv +SV_DEPS += ../common/sv/m_axi_sequencer.sv +SV_DEPS += ../common/sv/s_axi_sequencer.sv +SV_DEPS += ../common/sv/adi_regmap_pkg.sv +SV_DEPS += ../common/sv/adi_regmap_common_pkg.sv +SV_DEPS += ../common/sv/adi_regmap_pwm_gen_pkg.sv +SV_DEPS += ../common/sv/test_harness_env.sv +SV_DEPS += system_tb.sv + +ENV_DEPS +=../../library/util_cdc/sync_bits.v +ENV_DEPS +=../../library/common/ad_edge_detect.v +ENV_DEPS += system_project.tcl +ENV_DEPS += system_bd.tcl +ENV_DEPS +=../scripts/adi_sim.tcl +ENV_DEPS +=../scripts/run_sim.tcl + +LIB_DEPS += axi_pwm_gen + +# default test program +TP := test_program + +# config files should have the following format +# cfg__.tcl +CFG_FILES := $(notdir $(wildcard cfgs/cfg*.tcl)) +#$(warning $(CFG_FILES)) + +# List of tests and configuration combinations that has to be run +# Format is: : +TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(cfg):$(TP)) +#TESTS += cfg1_mm2mm_default:directed_test +#TESTS += cfg1:test_program +#TESTS += cfg2_fsync:test_program +#TESTS += cfg2_fsync:test_frame_delay + +include ../scripts/project-sim.mk + +# usage : +# +# run specific test on a specific configuration in gui mode +# make CFG=cfg2_fsync TST=test_frame_delay MODE=gui +# +# run all test from a configuration +# make cfg1_mm2mm_default + +#################################################################################### +#################################################################################### diff --git a/pwm_gen/README.md b/pwm_gen/README.md new file mode 100644 index 00000000..f1495cb4 --- /dev/null +++ b/pwm_gen/README.md @@ -0,0 +1,27 @@ +Usage : + +Run all tests in batch mode: + + make + + +Run all tests in GUI mode: + + make MODE=gui + + +Run specific test on a specific configuration in gui mode: + + make CFG= TST= MODE=gui + + +Run all test from a configuration: + + make + + +Where: + + * is a file from the cfgs directory without the tcl extension of format cfg\* + * is a file from the tests directory without the tcl extension + diff --git a/pwm_gen/cfgs/cfg1.tcl b/pwm_gen/cfgs/cfg1.tcl new file mode 100644 index 00000000..acca7599 --- /dev/null +++ b/pwm_gen/cfgs/cfg1.tcl @@ -0,0 +1,3 @@ +global ad_project_params + + diff --git a/pwm_gen/system_bd.tcl b/pwm_gen/system_bd.tcl new file mode 100644 index 00000000..5c3e9189 --- /dev/null +++ b/pwm_gen/system_bd.tcl @@ -0,0 +1,97 @@ +# *************************************************************************** +# *************************************************************************** +# Copyright 2023 (c) Analog Devices, Inc. All rights reserved. +# +# In this HDL repository, there are many different and unique modules, consisting +# of various HDL (Verilog or VHDL) components. The individual modules are +# developed independently, and may be accompanied by separate and unique license +# terms. +# +# The user should read each of these license terms, and understand the +# freedoms and responsibilities that he or she has by using this source/core. +# +# This core is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +# A PARTICULAR PURPOSE. +# +# Redistribution and use of source or resulting binaries, with or without modification +# of this file, are permitted under one of the following two license terms: +# +# 1. The GNU General Public License version 2 as published by the +# Free Software Foundation, which can be found in the top level directory +# of this repository (LICENSE_GPL2), and also online at: +# +# +# OR +# +# 2. An ADI specific BSD license, which can be found in the top level directory +# of this repository (LICENSE_ADIBSD), and also on-line at: +# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# This will allow to generate bit files and not release the source code, +# as long as it attaches to an ADI device. +# +# *************************************************************************** +# *************************************************************************** + +source ../../scripts/adi_env.tcl + +# common zed-based bd for test +#source ../../projects/common/zed/zed_system_bd.tcl + +# ------------------ +# +# Block under test +# +# ------------------ + +create_bd_port -dir O pwm_gen_o_0 +create_bd_port -dir O pwm_gen_o_1 +create_bd_port -dir O pwm_gen_o_2 +create_bd_port -dir O pwm_gen_o_3 +create_bd_port -dir O pwm_gen_o_4 +create_bd_port -dir O pwm_gen_o_5 +create_bd_port -dir O pwm_gen_o_6 +create_bd_port -dir O pwm_gen_o_7 +create_bd_port -dir O pwm_gen_o_8 +create_bd_port -dir O pwm_gen_o_9 +create_bd_port -dir O pwm_gen_o_10 +create_bd_port -dir O pwm_gen_o_11 +create_bd_port -dir O pwm_gen_o_12 +create_bd_port -dir O pwm_gen_o_13 +create_bd_port -dir O pwm_gen_o_14 +create_bd_port -dir O pwm_gen_o_15 + +ad_ip_instance axi_pwm_gen dut_pwm_gen +ad_ip_parameter dut_pwm_gen CONFIG.ASYNC_CLK_EN 1 +ad_ip_parameter dut_pwm_gen CONFIG.N_PWMS 16 + + +ad_connect ddr_clk_vip/clk_out dut_pwm_gen/ext_clk +adi_project_files [list \ + "../../library/common/ad_edge_detect.v" \ + "../../library/util_cdc/sync_bits.v"] + +ad_connect pwm_gen_o_0 dut_pwm_gen/pwm_0 +ad_connect pwm_gen_o_1 dut_pwm_gen/pwm_1 +ad_connect pwm_gen_o_2 dut_pwm_gen/pwm_2 +ad_connect pwm_gen_o_3 dut_pwm_gen/pwm_3 +ad_connect pwm_gen_o_4 dut_pwm_gen/pwm_4 +ad_connect pwm_gen_o_5 dut_pwm_gen/pwm_5 +ad_connect pwm_gen_o_6 dut_pwm_gen/pwm_6 +ad_connect pwm_gen_o_7 dut_pwm_gen/pwm_7 +ad_connect pwm_gen_o_8 dut_pwm_gen/pwm_8 +ad_connect pwm_gen_o_9 dut_pwm_gen/pwm_9 +ad_connect pwm_gen_o_10 dut_pwm_gen/pwm_10 +ad_connect pwm_gen_o_11 dut_pwm_gen/pwm_11 +ad_connect pwm_gen_o_12 dut_pwm_gen/pwm_12 +ad_connect pwm_gen_o_13 dut_pwm_gen/pwm_13 +ad_connect pwm_gen_o_14 dut_pwm_gen/pwm_14 +ad_connect pwm_gen_o_15 dut_pwm_gen/pwm_15 + +# connect resets + +ad_cpu_interconnect 0x7c000000 dut_pwm_gen + +create_bd_port -dir O sys_clk + +ad_connect sys_clk sys_cpu_clk diff --git a/pwm_gen/system_project.tcl b/pwm_gen/system_project.tcl new file mode 100644 index 00000000..01332e5f --- /dev/null +++ b/pwm_gen/system_project.tcl @@ -0,0 +1,42 @@ +source ../scripts/adi_sim.tcl +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +if {$argc < 1} { + puts "Expecting at least one argument that specifies the test configuration" + exit 1 +} else { + set cfg_file [lindex $argv 0] +} + +# Read config file +source "cfgs/${cfg_file}" + +# Set the project name +set project_name [file rootname $cfg_file] + +# Create the project +adi_sim_project_xilinx $project_name "xc7z020clg484-1" + +# Add test files to the project +adi_sim_project_files [list \ + "../common/sv/utils.svh" \ + "../common/sv/logger_pkg.sv" \ + "../common/sv/reg_accessor.sv" \ + "../common/sv/m_axis_sequencer.sv" \ + "../common/sv/s_axis_sequencer.sv" \ + "../common/sv/m_axi_sequencer.sv" \ + "../common/sv/s_axi_sequencer.sv" \ + "../common/sv/adi_regmap_pkg.sv" \ + "../common/sv/adi_regmap_common_pkg.sv" \ + "../common/sv/adi_regmap_pwm_gen_pkg.sv" \ + "../common/sv/adi_peripheral_pkg.sv" \ + "../common/sv/test_harness_env.sv" \ + "tests/test_program.sv" \ + "system_tb.sv" \ + ] + +#set a default test program +adi_sim_add_define "TEST_PROGRAM=test_program" + +adi_sim_generate $project_name diff --git a/pwm_gen/system_tb.sv b/pwm_gen/system_tb.sv new file mode 100644 index 00000000..1e2a4ff9 --- /dev/null +++ b/pwm_gen/system_tb.sv @@ -0,0 +1,99 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014-2023 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +`include "utils.svh" + +module system_tb(); + wire pwm_gen_o_0; + wire pwm_gen_o_1; + wire pwm_gen_o_2; + wire pwm_gen_o_3; + wire pwm_gen_o_4; + wire pwm_gen_o_5; + wire pwm_gen_o_6; + wire pwm_gen_o_7; + wire pwm_gen_o_8; + wire pwm_gen_o_9; + wire pwm_gen_o_10; + wire pwm_gen_o_11; + wire pwm_gen_o_12; + wire pwm_gen_o_13; + wire pwm_gen_o_14; + wire pwm_gen_o_15; + + wire sys_clk; + + `TEST_PROGRAM test( + .pwm_gen_o_0 (pwm_gen_o_0), + .pwm_gen_o_1 (pwn_gen_o_1), + .pwm_gen_o_2 (pwm_gen_o_2), + .pwm_gen_o_3 (pwm_gen_o_3), + .pwm_gen_o_4 (pwm_gen_o_4), + .pwm_gen_o_5 (pwm_gen_o_5), + .pwm_gen_o_6 (pwm_gen_o_6), + .pwm_gen_o_7 (pwm_gen_o_7), + .pwm_gen_o_8 (pwm_gen_o_8), + .pwm_gen_o_9 (pwn_gen_o_9), + .pwm_gen_o_10 (pwm_gen_o_10), + .pwm_gen_o_11 (pwm_gen_o_11), + .pwm_gen_o_12 (pwm_gen_o_12), + .pwm_gen_o_13 (pwm_gen_o_13), + .pwm_gen_o_14 (pwm_gen_o_14), + .pwm_gen_o_15 (pwm_gen_o_15), + + .sys_clk (sys_clk)); + + test_harness `TH ( + .pwm_gen_o_0 (pwm_gen_o_0), + .pwm_gen_o_1 (pwn_gen_o_1), + .pwm_gen_o_2 (pwm_gen_o_2), + .pwm_gen_o_3 (pwm_gen_o_3), + .pwm_gen_o_4 (pwm_gen_o_4), + .pwm_gen_o_5 (pwm_gen_o_5), + .pwm_gen_o_6 (pwm_gen_o_6), + .pwm_gen_o_7 (pwm_gen_o_7), + .pwm_gen_o_8 (pwm_gen_o_8), + .pwm_gen_o_9 (pwn_gen_o_9), + .pwm_gen_o_10 (pwm_gen_o_10), + .pwm_gen_o_11 (pwm_gen_o_11), + .pwm_gen_o_12 (pwm_gen_o_12), + .pwm_gen_o_13 (pwm_gen_o_13), + .pwm_gen_o_14 (pwm_gen_o_14), + .pwm_gen_o_15 (pwm_gen_o_15), + .sys_clk (sys_clk)); + +endmodule diff --git a/pwm_gen/tests/test_program.sv b/pwm_gen/tests/test_program.sv new file mode 100644 index 00000000..10c29f80 --- /dev/null +++ b/pwm_gen/tests/test_program.sv @@ -0,0 +1,157 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// +// +// +`include "utils.svh" + +import test_harness_env_pkg::*; +import axi_vip_pkg::*; +import axi4stream_vip_pkg::*; +import logger_pkg::*; +import adi_regmap_pkg::*; +import adi_regmap_common_pkg::*; +import adi_regmap_pwm_gen_pkg::*; + +`define AXI_PWMGEN 32'h7c00_0000 + +program test_program ( + input pwm_gen_o_0, + input pwm_gen_o_1, + input pwm_gen_o_2, + input pwm_gen_o_3, + input pwm_gen_o_4, + input pwm_gen_o_5, + input pwm_gen_o_6, + input pwm_gen_o_7, + input pwm_gen_o_8, + input pwm_gen_o_9, + input pwm_gen_o_10, + input pwm_gen_o_11, + input pwm_gen_o_12, + input pwm_gen_o_13, + input pwm_gen_o_14, + input pwm_gen_o_15, + + input sys_clk); + + test_harness_env env; + +// -------------------------- +// Wrapper function for AXI read verif +// -------------------------- +task axi_read_v( + input [31:0] raddr, + input [31:0] vdata); +begin + env.mng.RegReadVerify32(raddr,vdata); +end +endtask + +task axi_read( + input [31:0] raddr, + output [31:0] data); +begin + env.mng.RegRead32(raddr,data); +end +endtask + +// -------------------------- +// Wrapper function for AXI write +// -------------------------- +task axi_write; + input [31:0] waddr; + input [31:0] wdata; +begin + env.mng.RegWrite32(waddr,wdata); +end +endtask + + initial begin + + //creating environment + env = new(`TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); + + #2ps; + setLoggerVerbosity(6); + env.start(); + + //asserts all the resets for 100 ns + `TH.`SYS_RST.inst.IF.assert_reset; + #100 + `TH.`SYS_RST.inst.IF.deassert_reset; + #100 + + #100 sanity_test; + #100 test_config; + `INFO(("Test Done")); + + $finish; + + end + +task sanity_test; + begin + // check PWM_GEN N_PWMS + logic [31:0] n_pwms = 'h0; + axi_read(`AXI_PWMGEN + GetAddrs(REG_N_PWMS),n_pwms); + $display("[%t] Sanity Test Done. %h", $time, n_pwms); + end +endtask + +task test_config; + begin + #100 axi_write (`AXI_PWMGEN + GetAddrs(REG_RSTN), `SET_REG_RSTN_RESET(0)); // PWM_GEN reset in regmap (ACTIVE HIGH) + #100 axi_write (`AXI_PWMGEN + GetAddrs(REG_PULSE_0_PERIOD), `SET_REG_PULSE_0_PERIOD_PULSE_0_PERIOD('d10)); // set PWM period + #100 axi_write (`AXI_PWMGEN + GetAddrs(REG_PULSE_0_WIDTH), `SET_REG_PULSE_0_WIDTH_PULSE_0_WIDTH('d4)); // set PWM width + #100 axi_write (`AXI_PWMGEN + GetAddrs(REG_PULSE_15_PERIOD), `SET_REG_PULSE_15_PERIOD_PULSE_15_PERIOD('d10)); // set PWM period + #100 axi_write (`AXI_PWMGEN + GetAddrs(REG_PULSE_15_WIDTH), `SET_REG_PULSE_15_WIDTH_PULSE_15_WIDTH('d6)); // set PWM width + #100 axi_write (`AXI_PWMGEN + GetAddrs(REG_PULSE_15_OFFSET), `SET_REG_PULSE_15_OFFSET_PULSE_15_OFFSET('d2)); // set PWM offset + + #100 axi_write (`AXI_PWMGEN + GetAddrs(REG_RSTN), `SET_REG_RSTN_LOAD_CONFIG(1)); // load AXI_PWM_GEN configuration + + $display("[%t] axi_pwm_gen started.", $time); + #100000; + + axi_write (`AXI_PWMGEN + 32'h00000010, 'h2); // stop PWM_GEN + $display("[%t] axi_pwm_gen stopped.", $time); + end +endtask + +endprogram diff --git a/pwm_gen/waves/system_tb_behav.wcfg b/pwm_gen/waves/system_tb_behav.wcfg new file mode 100644 index 00000000..eaafa461 --- /dev/null +++ b/pwm_gen/waves/system_tb_behav.wcfg @@ -0,0 +1,106 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + pwm_gen_o_0 + pwm_gen_o_0 + + + pwn_gen_o_1 + pwn_gen_o_1 + + + pwm_gen_o_2 + pwm_gen_o_2 + + + pwm_gen_o_3 + pwm_gen_o_3 + + + pwm_gen_o_4 + pwm_gen_o_4 + + + pwm_gen_o_5 + pwm_gen_o_5 + + + pwm_gen_o_6 + pwm_gen_o_6 + + + pwm_gen_o_7 + pwm_gen_o_7 + + + pwm_gen_o_8 + pwm_gen_o_8 + + + pwn_gen_o_9 + pwn_gen_o_9 + + + pwm_gen_o_10 + pwm_gen_o_10 + + + pwm_gen_o_11 + pwm_gen_o_11 + + + pwm_gen_o_12 + pwm_gen_o_12 + + + pwm_gen_o_13 + pwm_gen_o_13 + + + pwm_gen_o_14 + pwm_gen_o_14 + + + pwm_gen_o_15 + pwm_gen_o_15 + + + sys_clk + sys_clk + +