From a27e9ce43881c7542dd9cff7f381a77f19057e99 Mon Sep 17 00:00:00 2001
From: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
Date: Wed, 29 May 2024 08:05:53 +0100
Subject: [PATCH] scripts/adi_sim.tcl: Updated scripts

- Changed the interconnect cascading option to automatically cascade in testbenches

Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
---
 scripts/adi_sim.tcl | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/scripts/adi_sim.tcl b/scripts/adi_sim.tcl
index 14eebeb3..38624c91 100644
--- a/scripts/adi_sim.tcl
+++ b/scripts/adi_sim.tcl
@@ -30,7 +30,11 @@ proc adi_sim_project_xilinx {project_name {part "xc7vx485tffg1157-1"}} {
   create_bd_design $design_name
 
   global sys_zynq
+  global sys_cpu_interconnect_cascade
+  
   set sys_zynq -1
+  set sys_cpu_interconnect_cascade 1
+
   if { ![info exists ad_project_params(CUSTOM_HARNESS)] || !$ad_project_params(CUSTOM_HARNESS) } {
     source ../common/test_harness/test_harness_system_bd.tcl
   }