diff --git a/util_axis_fifo_asym/Makefile b/util_axis_fifo_asym/Makefile new file mode 100644 index 00000000..ba63bd4d --- /dev/null +++ b/util_axis_fifo_asym/Makefile @@ -0,0 +1,61 @@ +#################################################################################### +#################################################################################### +## Copyright 2022(c) Analog Devices, Inc. +#################################################################################### +#################################################################################### + +# All test-bench dependencies except test programs +SV_DEPS += ../common/sv/utils.svh +SV_DEPS += ../common/sv/logger_pkg.sv +SV_DEPS += ../common/sv/reg_accessor.sv +SV_DEPS += ../common/sv/m_axis_sequencer.sv +SV_DEPS += ../common/sv/s_axis_sequencer.sv +SV_DEPS += ../common/sv/m_axi_sequencer.sv +SV_DEPS += ../common/sv/s_axi_sequencer.sv +SV_DEPS += ../common/sv/test_harness_env.sv +SV_DEPS += ../common/sv/adi_peripheral_pkg.sv +SV_DEPS += ../common/sv/adi_regmap_pkg.sv +SV_DEPS += ../common/sv/mailbox.sv +SV_DEPS += ../common/sv/x_monitor.sv +SV_DEPS += ../common/sv/scoreboard.sv +SV_DEPS += ../common/sv/interfaces.svh +SV_DEPS += environment.sv +SV_DEPS += system_tb.sv + +ENV_DEPS += system_project.tcl +ENV_DEPS += system_bd.tcl +ENV_DEPS +=../scripts/adi_sim.tcl +ENV_DEPS +=../scripts/run_sim.tcl + +LIB_DEPS := util_cdc +LIB_DEPS += util_axis_fifo +LIB_DEPS += util_axis_fifo_asym + +# default test program +TP := test_program + +# config files should have the following format +# cfg__.tcl +CFG_FILES := $(notdir $(wildcard cfgs/cfg*.tcl)) +#$(warning $(CFG_FILES)) + +# List of tests and configuration combinations that has to be run +# Format is: : +TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(cfg):$(TP)) +#TESTS += cfg1_mm2mm_default:directed_test +#TESTS += cfg1:test_program +#TESTS += cfg2_fsync:test_program +#TESTS += cfg2_fsync:test_frame_delay + +include ../scripts/project-sim.mk + +# usage : +# +# run specific test on a specific configuration in gui mode +# make CFG=cfg2_fsync TST=test_frame_delay MODE=gui +# +# run all test from a configuration +# make cfg1_mm2mm_default + +#################################################################################### +#################################################################################### diff --git a/util_axis_fifo_asym/README.md b/util_axis_fifo_asym/README.md new file mode 100644 index 00000000..f1495cb4 --- /dev/null +++ b/util_axis_fifo_asym/README.md @@ -0,0 +1,27 @@ +Usage : + +Run all tests in batch mode: + + make + + +Run all tests in GUI mode: + + make MODE=gui + + +Run specific test on a specific configuration in gui mode: + + make CFG= TST= MODE=gui + + +Run all test from a configuration: + + make + + +Where: + + * is a file from the cfgs directory without the tcl extension of format cfg\* + * is a file from the tests directory without the tcl extension + diff --git a/util_axis_fifo_asym/cfgs/cfg1.tcl b/util_axis_fifo_asym/cfgs/cfg1.tcl new file mode 100644 index 00000000..ff01e386 --- /dev/null +++ b/util_axis_fifo_asym/cfgs/cfg1.tcl @@ -0,0 +1,7 @@ +global ad_project_params + +set random_width [expr int(8*pow(2, int(7.0*rand()+1)))] +set ad_project_params(INPUT_WIDTH) $random_width + +set random_width [expr int(8*pow(2, int(7.0*rand()+1)))] +set ad_project_params(OUTPUT_WIDTH) $random_width diff --git a/util_axis_fifo_asym/environment.sv b/util_axis_fifo_asym/environment.sv new file mode 100644 index 00000000..d00ba8b6 --- /dev/null +++ b/util_axis_fifo_asym/environment.sv @@ -0,0 +1,188 @@ +`include "utils.svh" + +package environment_pkg; + + import m_axi_sequencer_pkg::*; + import s_axi_sequencer_pkg::*; + import m_axis_sequencer_pkg::*; + import s_axis_sequencer_pkg::*; + import logger_pkg::*; + + import axi_vip_pkg::*; + import axi4stream_vip_pkg::*; + import test_harness_env_pkg::*; + import scoreboard_pkg::*; + import x_monitor_pkg::*; + + import `PKGIFY(test_harness, mng_axi_vip)::*; + import `PKGIFY(test_harness, ddr_axi_vip)::*; + + import `PKGIFY(test_harness, input_axis)::*; + import `PKGIFY(test_harness, output_axis)::*; + + class environment extends test_harness_env; + + virtual interface clk_if input_clk_if; + virtual interface clk_if output_clk_if; + + // agents and sequencers + `AGENT(test_harness, input_axis, mst_t) input_axis_agent; + `AGENT(test_harness, output_axis, slv_t) output_axis_agent; + + m_axis_sequencer #(`AGENT(test_harness, input_axis, mst_t), + `AXIS_VIP_PARAMS(test_harness, input_axis) + ) input_axis_seq; + s_axis_sequencer #(`AGENT(test_harness, output_axis, slv_t)) output_axis_seq; + + x_axis_monitor #(`AGENT(test_harness, input_axis, mst_t)) input_axis_mon; + x_axis_monitor #(`AGENT(test_harness, output_axis, slv_t)) output_axis_mon; + + scoreboard scoreboard_inst; + + //============================================================================ + // Constructor + //============================================================================ + function new ( + virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(10)) sys_clk_vip_if, + virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(5)) dma_clk_vip_if, + virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(2.5)) ddr_clk_vip_if, + + virtual interface rst_vip_if #(.C_ASYNCHRONOUS(1), .C_RST_POLARITY(1)) sys_rst_vip_if, + + virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, mng_axi_vip)) mng_vip_if, + virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, ddr_axi_vip)) ddr_vip_if, + + virtual interface clk_if input_clk_if, + virtual interface clk_if output_clk_if, + + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, input_axis)) input_axis_vip_if, + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, output_axis)) output_axis_vip_if + ); + + // creating the agents + super.new(sys_clk_vip_if, + dma_clk_vip_if, + ddr_clk_vip_if, + sys_rst_vip_if, + mng_vip_if, + ddr_vip_if); + + this.input_clk_if = input_clk_if; + this.output_clk_if = output_clk_if; + + input_axis_agent = new("Input AXI Stream Agent", input_axis_vip_if); + output_axis_agent = new("Output AXI Stream Agent", output_axis_vip_if); + + input_axis_seq = new(input_axis_agent); + output_axis_seq = new(output_axis_agent); + + input_axis_mon = new("Input AXIS Transaction Monitor", input_axis_agent); + output_axis_mon = new("Output AXIS Transaction Monitor", output_axis_agent); + + scoreboard_inst = new("Verification Environment Scoreboard"); + + endfunction + + //============================================================================ + // Configure environment + //============================================================================ + task configure(); + + // configuration for input + this.input_axis_seq.set_stop_policy(STOP_POLICY_PACKET); + this.input_axis_seq.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); + this.input_axis_seq.set_descriptor_gen_mode(1); + this.input_axis_seq.set_data_beat_delay(0); + this.input_axis_seq.set_descriptor_delay(0); + this.input_axis_seq.set_inactive_drive_output_0(); + + // configuration for output + this.output_axis_seq.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); + + // this.output_axis_seq.set_use_variable_ranges(); + // this.output_axis_seq.set_high_time_range(1,1); + // this.output_axis_seq.set_low_time_range(0,0); + + // this.output_axis_seq.clr_use_variable_ranges(); + // this.output_axis_seq.set_high_time(1); + // this.output_axis_seq.set_low_time(1); + + endtask + + //============================================================================ + // Start environment + // - Connect all the agents to the scoreboard + // - Start the agents + //============================================================================ + task start(); + + super.start(); + + input_clk_if.start_clock($urandom_range(1000,10000)); + output_clk_if.start_clock($urandom_range(1000,10000)); + + input_axis_agent.start_master(); + output_axis_agent.start_slave(); + + scoreboard_inst.set_source_stream(input_axis_mon); + scoreboard_inst.set_sink_stream(output_axis_mon); + + endtask + + //============================================================================ + // Start the test + // - start the RX scoreboard and sequencer + // - start the TX scoreboard and sequencer + // - setup the RX DMA + // - setup the TX DMA + //============================================================================ + task test(); + + fork + input_axis_seq.run(); + output_axis_seq.run(); + + input_axis_mon.run(); + output_axis_mon.run(); + + scoreboard_inst.run(); + join_none + + endtask + + + //============================================================================ + // Post test subroutine + //============================================================================ + task post_test(); + // Evaluate the scoreboard's results + endtask + + //============================================================================ + // Run subroutine + //============================================================================ + task run; + + //pre_test(); + test(); + + endtask + + //============================================================================ + // Stop subroutine + //============================================================================ + task stop; + + super.stop(); + + input_axis_seq.stop(); + input_axis_agent.stop_master(); + output_axis_agent.stop_slave(); + + post_test(); + + endtask + + endclass + +endpackage diff --git a/util_axis_fifo_asym/system_bd.tcl b/util_axis_fifo_asym/system_bd.tcl new file mode 100644 index 00000000..bceab254 --- /dev/null +++ b/util_axis_fifo_asym/system_bd.tcl @@ -0,0 +1,96 @@ +# *************************************************************************** +# *************************************************************************** +# Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +# +# In this HDL repository, there are many different and unique modules, consisting +# of various HDL (Verilog or VHDL) components. The individual modules are +# developed independently, and may be accompanied by separate and unique license +# terms. +# +# The user should read each of these license terms, and understand the +# freedoms and responsibilities that he or she has by using this source/core. +# +# This core is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +# A PARTICULAR PURPOSE. +# +# Redistribution and use of source or resulting binaries, with or without modification +# of this file, are permitted under one of the following two license terms: +# +# 1. The GNU General Public License version 2 as published by the +# Free Software Foundation, which can be found in the top level directory +# of this repository (LICENSE_GPL2), and also online at: +# +# +# OR +# +# 2. An ADI specific BSD license, which can be found in the top level directory +# of this repository (LICENSE_ADIBSD), and also on-line at: +# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# This will allow to generate bit files and not release the source code, +# as long as it attaches to an ADI device. +# +# *************************************************************************** +# *************************************************************************** + +global ad_hdl_dir + +source ../../scripts/adi_env.tcl + +# system level parameters +global ad_project_params + +set INPUT_WIDTH $ad_project_params(INPUT_WIDTH) +set OUTPUT_WIDTH $ad_project_params(OUTPUT_WIDTH) + +# input clock and reset +create_bd_port -dir I input_clk + +# output clock and reset +create_bd_port -dir I output_clk + + +ad_ip_instance util_axis_fifo_asym util_axis_fifo_asym_DUT [list \ + ASYNC_CLK 1 \ + S_DATA_WIDTH $INPUT_WIDTH \ + S_ADDRESS_WIDTH 5 \ + M_DATA_WIDTH $OUTPUT_WIDTH \ + M_AXIS_REGISTERED 1 \ + ALMOST_EMPTY_THRESHOLD 4 \ + ALMOST_FULL_THRESHOLD 4 \ + TLAST_EN 1 \ + TKEEP_EN 1 \ + S_FIFO_LIMITED 0 \ +] + +ad_connect input_clk util_axis_fifo_asym_DUT/s_axis_aclk +ad_connect sys_cpu_resetn util_axis_fifo_asym_DUT/s_axis_aresetn + +ad_connect output_clk util_axis_fifo_asym_DUT/m_axis_aclk +ad_connect sys_cpu_resetn util_axis_fifo_asym_DUT/m_axis_aresetn + +ad_ip_instance axi4stream_vip input_axis [list \ + INTERFACE_MODE {MASTER} \ + HAS_TREADY {1} \ + HAS_TLAST {1} \ + HAS_TKEEP {1} \ + TDATA_NUM_BYTES [expr {$INPUT_WIDTH/8}] \ +] +adi_sim_add_define "INPUT_AXIS=input_axis" + +ad_connect input_clk input_axis/aclk +ad_connect sys_cpu_resetn input_axis/aresetn + +ad_connect util_axis_fifo_asym_DUT/s_axis input_axis/m_axis + +ad_ip_instance axi4stream_vip output_axis [list \ + INTERFACE_MODE {SLAVE} \ + TDATA_NUM_BYTES [expr {$OUTPUT_WIDTH/8}] \ + HAS_TLAST {1} \ +] +adi_sim_add_define "OUTPUT_AXIS=output_axis" + +ad_connect output_clk output_axis/aclk +ad_connect sys_cpu_resetn output_axis/aresetn + +ad_connect util_axis_fifo_asym_DUT/m_axis output_axis/s_axis diff --git a/util_axis_fifo_asym/system_project.tcl b/util_axis_fifo_asym/system_project.tcl new file mode 100644 index 00000000..c4a8dec8 --- /dev/null +++ b/util_axis_fifo_asym/system_project.tcl @@ -0,0 +1,47 @@ +source ../scripts/adi_sim.tcl +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +if {$argc < 1} { + puts "Expecting at least one argument that specifies the test configuration" + exit 1 +} else { + set cfg_file [lindex $argv 0] +} + +# Read config file +source "cfgs/${cfg_file}" + +global ad_project_params + +# Set the project name +set project_name [file rootname $cfg_file] + +# Create the project +adi_sim_project_xilinx $project_name "xcvu9p-flga2104-2L-e" + +# Add test files to the project +adi_sim_project_files [list \ + "../common/sv/utils.svh" \ + "../common/sv/logger_pkg.sv" \ + "../common/sv/reg_accessor.sv" \ + "../common/sv/m_axis_sequencer.sv" \ + "../common/sv/s_axis_sequencer.sv" \ + "../common/sv/m_axi_sequencer.sv" \ + "../common/sv/s_axi_sequencer.sv" \ + "../common/sv/adi_peripheral_pkg.sv" \ + "../common/sv/adi_regmap_pkg.sv" \ + "../common/sv/test_harness_env.sv" \ + "../common/sv/mailbox.sv" \ + "../common/sv/x_monitor.sv" \ + "../common/sv/scoreboard.sv" \ + "../common/sv/interfaces.svh" \ + "environment.sv" \ + "tests/test_program.sv" \ + "system_tb.sv" \ + ] + +#set a default test program +adi_sim_add_define "TEST_PROGRAM=test_program" + +adi_sim_generate $project_name diff --git a/util_axis_fifo_asym/system_tb.sv b/util_axis_fifo_asym/system_tb.sv new file mode 100644 index 00000000..ea79f943 --- /dev/null +++ b/util_axis_fifo_asym/system_tb.sv @@ -0,0 +1,56 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +`include "utils.svh" +`include "interfaces.svh" + +module system_tb(); + + clk_if input_clk_if(); + clk_if output_clk_if(); + + `TEST_PROGRAM test( + .input_clk_if(input_clk_if), + .output_clk_if(output_clk_if) + ); + + test_harness `TH ( + .input_clk (input_clk_if.clk), + .output_clk (output_clk_if.clk) + ); + +endmodule diff --git a/util_axis_fifo_asym/tests/test_program.sv b/util_axis_fifo_asym/tests/test_program.sv new file mode 100644 index 00000000..a86886e9 --- /dev/null +++ b/util_axis_fifo_asym/tests/test_program.sv @@ -0,0 +1,103 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// +// +// +`include "utils.svh" + +import axi_vip_pkg::*; +import axi4stream_vip_pkg::*; +import logger_pkg::*; +import environment_pkg::*; +import m_axis_sequencer_pkg::*; +import s_axis_sequencer_pkg::*; + +program test_program ( + clk_if input_clk_if, + clk_if output_clk_if); + + // declare the class instances + environment env; + + + initial begin + + // create environment + env = new(`TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF, + + input_clk_if, + output_clk_if, + + `TH.`INPUT_AXIS.inst.IF, + `TH.`OUTPUT_AXIS.inst.IF + ); + + setLoggerVerbosity(5); + + env.start(); + env.sys_reset(); + + env.configure(); + + env.run(); + + // stimulus + repeat($urandom_range(10,20)) begin + env.input_axis_seq.add_xfer_descriptor_packet_size($urandom_range(1,100), 1, 0); + + env.input_axis_seq.start(); + + #($urandom_range(1,20)*1us); + + env.input_axis_seq.stop(); + + env.input_axis_seq.packet_sent(); + + env.scoreboard_inst.wait_until_complete(); + end + + env.stop(); + + `INFO(("Test bench done!")); + $finish(); + + end + +endprogram diff --git a/util_axis_fifo_asym/waves/cfg1.wcfg b/util_axis_fifo_asym/waves/cfg1.wcfg new file mode 100644 index 00000000..235e962d --- /dev/null +++ b/util_axis_fifo_asym/waves/cfg1.wcfg @@ -0,0 +1,369 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + m_axis_aclk + m_axis_aclk + + + m_axis_aresetn + m_axis_aresetn + + + M_AXIS + M_AXIS + true + STYLE_ENUM_TRANSACTION + fff,fff=blank + true + #00E600 + /system_tb/test_harness/input_axis/M_AXIS.streamWaveData + 2 + /system_tb/test_harness/input_axis/M_AXIS.linkStarve + #99E600 + /system_tb/test_harness/input_axis/M_AXIS.linkStall + #E64C00 + /system_tb/test_harness/input_axis/M_AXIS.streamTooltipData + + + s_axis_aclk + s_axis_aclk + + + s_axis_aresetn + s_axis_aresetn + + + S_AXIS + S_AXIS + true + STYLE_ENUM_TRANSACTION + fff,fff=blank + true + #00E600 + /system_tb/test_harness/output_axis/S_AXIS.streamWaveData + 2 + /system_tb/test_harness/output_axis/S_AXIS.linkStarve + #99E600 + /system_tb/test_harness/output_axis/S_AXIS.linkStall + #E64C00 + /system_tb/test_harness/output_axis/S_AXIS.streamTooltipData + + + SLAVE + label + + + Slave + label + + Blk0 + label + + + s_axis_aclk + s_axis_aclk + + + s_axis_aresetn + s_axis_aresetn + + + s_axis_ready + s_axis_ready + + + s_axis_valid + s_axis_valid + + + s_axis_data[63:0] + s_axis_data[63:0] + + + s_axis_tkeep[7:0] + s_axis_tkeep[7:0] + + + s_axis_tlast + s_axis_tlast + + + s_axis_room[4:0] + s_axis_room[4:0] + + + s_axis_full + s_axis_full + + + s_axis_almost_full + s_axis_almost_full + + + Blk1 + label + + + s_axis_aclk + s_axis_aclk + + + s_axis_aresetn + s_axis_aresetn + + + s_axis_ready + s_axis_ready + + + s_axis_valid + s_axis_valid + + + s_axis_data[63:0] + s_axis_data[63:0] + + + s_axis_tkeep[7:0] + s_axis_tkeep[7:0] + + + s_axis_tlast + s_axis_tlast + + + s_axis_room[4:0] + s_axis_room[4:0] + + + s_axis_full + s_axis_full + + + s_axis_almost_full + s_axis_almost_full + + + Higher + label + + + s_axis_counter[0:0] + s_axis_counter[0:0] + + + s_axis_ready_int_s[1:0] + s_axis_ready_int_s[1:0] + + + s_axis_valid_int_s[1:0] + s_axis_valid_int_s[1:0] + + + s_axis_data_int_s[127:0] + s_axis_data_int_s[127:0] + + + s_axis_tkeep_int_s[15:0] + s_axis_tkeep_int_s[15:0] + + + s_axis_tlast_int_s[1:0] + s_axis_tlast_int_s[1:0] + + + s_axis_full_int_s[1:0] + s_axis_full_int_s[1:0] + + + s_axis_almost_full_int_s[1:0] + s_axis_almost_full_int_s[1:0] + + + s_axis_room_int_s[9:0] + s_axis_room_int_s[9:0] + + + \small_slave.s_axis_valid_int_d [1:0] + \small_slave.s_axis_valid_int_d [1:0] + + + + MASTER + label + + + Master + label + + Blk0 + label + + + m_axis_aclk + m_axis_aclk + + + m_axis_aresetn + m_axis_aresetn + + + m_axis_ready + m_axis_ready + + + m_axis_valid + m_axis_valid + + + m_axis_data[63:0] + m_axis_data[63:0] + + + m_axis_tkeep[7:0] + m_axis_tkeep[7:0] + + + m_axis_tlast + m_axis_tlast + + + m_axis_level[4:0] + m_axis_level[4:0] + + + m_axis_empty + m_axis_empty + + + m_axis_almost_empty + m_axis_almost_empty + + + Blk1 + label + + + m_axis_aclk + m_axis_aclk + + + m_axis_aresetn + m_axis_aresetn + + + m_axis_ready + m_axis_ready + + + m_axis_valid + m_axis_valid + + + m_axis_data[63:0] + m_axis_data[63:0] + + + m_axis_tkeep[7:0] + m_axis_tkeep[7:0] + + + m_axis_tlast + m_axis_tlast + + + m_axis_level[4:0] + m_axis_level[4:0] + + + m_axis_empty + m_axis_empty + + + m_axis_almost_empty + m_axis_almost_empty + + + Higher + label + + + m_axis_counter[0:0] + m_axis_counter[0:0] + + + m_axis_ready_int_s[1:0] + m_axis_ready_int_s[1:0] + + + m_axis_valid_int_s[1:0] + m_axis_valid_int_s[1:0] + + + m_axis_data_int_s[127:0] + m_axis_data_int_s[127:0] + + + m_axis_tkeep_int_s[15:0] + m_axis_tkeep_int_s[15:0] + + + m_axis_tlast_int_s[1:0] + m_axis_tlast_int_s[1:0] + + + m_axis_empty_int_s[1:0] + m_axis_empty_int_s[1:0] + + + m_axis_almost_empty_int_s[1:0] + m_axis_almost_empty_int_s[1:0] + + + m_axis_level_int_s[9:0] + m_axis_level_int_s[9:0] + + +