diff --git a/projects/adrv9009/common/adrv9009_bd.tcl b/projects/adrv9009/common/adrv9009_bd.tcl index c72d2da9d2..eaf93dd524 100644 --- a/projects/adrv9009/common/adrv9009_bd.tcl +++ b/projects/adrv9009/common/adrv9009_bd.tcl @@ -54,7 +54,7 @@ set RX_OS_TPL_WIDTH [ expr { [info exists ad_project_params(RX_OS_TPL_WIDTH)] \ set RX_OS_DATAPATH_WIDTH [adi_jesd204_calc_tpl_width $DATAPATH_WIDTH $RX_OS_NUM_OF_LANES $RX_OS_NUM_OF_CONVERTERS $RX_OS_SAMPLES_PER_FRAME $RX_OS_SAMPLE_WIDTH $RX_OS_TPL_WIDTH] set RX_OS_SAMPLES_PER_CHANNEL [expr $RX_OS_NUM_OF_LANES * 8 * $RX_OS_DATAPATH_WIDTH / ($RX_OS_NUM_OF_CONVERTERS * $RX_OS_SAMPLE_WIDTH)] -set dac_data_offload_name adrv9009_data_offload +set dac_offload_name adrv9009_data_offload set dac_data_width [expr $TX_SAMPLE_WIDTH * $TX_NUM_OF_CONVERTERS * $TX_SAMPLES_PER_CHANNEL] # adrv9009 @@ -110,15 +110,15 @@ ad_ip_parameter axi_adrv9009_tx_dma CONFIG.MAX_BYTES_PER_BURST 256 ad_ip_parameter axi_adrv9009_tx_dma CONFIG.AXI_SLICE_DEST true ad_ip_parameter axi_adrv9009_tx_dma CONFIG.AXI_SLICE_SRC true -ad_data_offload_create $dac_data_offload_name \ +ad_data_offload_create $dac_offload_name \ 1 \ - $dac_data_offload_type \ - $dac_data_offload_size \ + $dac_offload_type \ + $dac_offload_size \ $dac_data_width \ $dac_data_width \ - $dac_axi_data_width + $plddr_offload_axi_data_width -ad_connect $dac_data_offload_name/sync_ext GND +ad_connect $dac_offload_name/sync_ext GND # adc peripherals @@ -356,21 +356,21 @@ for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} { ad_connect tx_fir_interpolator/active dac_fir_filter_active -ad_connect axi_adrv9009_tx_clkgen/clk_0 $dac_data_offload_name/m_axis_aclk -ad_connect adrv9009_tx_device_clk_rstgen/peripheral_aresetn $dac_data_offload_name/m_axis_aresetn -ad_connect util_adrv9009_tx_upack/s_axis $dac_data_offload_name/m_axis +ad_connect axi_adrv9009_tx_clkgen/clk_0 $dac_offload_name/m_axis_aclk +ad_connect adrv9009_tx_device_clk_rstgen/peripheral_aresetn $dac_offload_name/m_axis_aresetn +ad_connect util_adrv9009_tx_upack/s_axis $dac_offload_name/m_axis -ad_connect $sys_dma_clk $dac_data_offload_name/s_axis_aclk -ad_connect $sys_dma_resetn $dac_data_offload_name/s_axis_aresetn +ad_connect $sys_dma_clk $dac_offload_name/s_axis_aclk +ad_connect $sys_dma_resetn $dac_offload_name/s_axis_aresetn ad_connect $sys_dma_clk axi_adrv9009_tx_dma/m_axis_aclk ad_connect $sys_dma_resetn axi_adrv9009_tx_dma/m_src_axi_aresetn -ad_connect $dac_data_offload_name/s_axis axi_adrv9009_tx_dma/m_axis -ad_connect $dac_data_offload_name/init_req axi_adrv9009_tx_dma/m_axis_xfer_req +ad_connect $dac_offload_name/s_axis axi_adrv9009_tx_dma/m_axis +ad_connect $dac_offload_name/init_req axi_adrv9009_tx_dma/m_axis_xfer_req ad_connect tx_adrv9009_tpl_core/dac_dunf GND -ad_connect $sys_cpu_clk $dac_data_offload_name/s_axi_aclk -ad_connect $sys_cpu_resetn $dac_data_offload_name/s_axi_aresetn +ad_connect $sys_cpu_clk $dac_offload_name/s_axi_aclk +ad_connect $sys_cpu_resetn $dac_offload_name/s_axi_aresetn # connections (adc) @@ -441,7 +441,7 @@ ad_cpu_interconnect 0x44A80000 axi_adrv9009_tx_xcvr ad_cpu_interconnect 0x43C00000 axi_adrv9009_tx_clkgen ad_cpu_interconnect 0x44A90000 axi_adrv9009_tx_jesd ad_cpu_interconnect 0x7c420000 axi_adrv9009_tx_dma -ad_cpu_interconnect 0x7c430000 $dac_data_offload_name +ad_cpu_interconnect 0x7c430000 $dac_offload_name ad_cpu_interconnect 0x44A60000 axi_adrv9009_rx_xcvr ad_cpu_interconnect 0x43C10000 axi_adrv9009_rx_clkgen ad_cpu_interconnect 0x44AA0000 axi_adrv9009_rx_jesd diff --git a/projects/adrv9009/zc706/Makefile b/projects/adrv9009/zc706/Makefile index 44f70bafff..0f874401a7 100644 --- a/projects/adrv9009/zc706/Makefile +++ b/projects/adrv9009/zc706/Makefile @@ -10,12 +10,13 @@ M_DEPS += ../common/adrv9009_bd.tcl M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/zc706/zc706_system_constr.xdc M_DEPS += ../../common/zc706/zc706_system_bd.tcl +M_DEPS += ../../common/zc706/zc706_plddr3_data_offload_bd.tcl M_DEPS += ../../common/zc706/zc706_plddr3_constr.xdc M_DEPS += ../../common/xilinx/data_offload_bd.tcl M_DEPS += ../../common/xilinx/adi_fir_filter_constr.xdc M_DEPS += ../../common/xilinx/adi_fir_filter_bd.tcl -M_DEPS += ../../../library/util_cdc/sync_bits.v M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl +M_DEPS += ../../../library/util_cdc/sync_bits.v M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl M_DEPS += ../../../library/common/util_pulse_gen.v M_DEPS += ../../../library/common/ad_iobuf.v @@ -26,6 +27,7 @@ LIB_DEPS += axi_dmac LIB_DEPS += axi_hdmi_tx LIB_DEPS += axi_spdif_tx LIB_DEPS += axi_sysid +LIB_DEPS += data_offload LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac LIB_DEPS += jesd204/axi_jesd204_rx @@ -33,7 +35,6 @@ LIB_DEPS += jesd204/axi_jesd204_tx LIB_DEPS += jesd204/jesd204_rx LIB_DEPS += jesd204/jesd204_tx LIB_DEPS += sysid_rom -LIB_DEPS += data_offload LIB_DEPS += util_hbm LIB_DEPS += util_pack/util_cpack2 LIB_DEPS += util_pack/util_upack2 diff --git a/projects/adrv9009/zc706/system_bd.tcl b/projects/adrv9009/zc706/system_bd.tcl index dc9981683d..ea33bbc981 100644 --- a/projects/adrv9009/zc706/system_bd.tcl +++ b/projects/adrv9009/zc706/system_bd.tcl @@ -3,11 +3,12 @@ ### SPDX short identifier: ADIBSD ############################################################################### -set dac_data_offload_type 1 ; ## PL_DDR -set dac_data_offload_size [expr 1024*1024*1024] ; ## 1 GB -set dac_axi_data_width 512 +set dac_offload_type 1 ; ## PL_DDR +set dac_offload_size [expr 1024*1024*1024] ; ## 1 GB +set plddr_offload_axi_data_width 512 source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl +source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_data_offload_bd.tcl source $ad_hdl_dir/projects/scripts/adi_pd.tcl #system ID @@ -24,8 +25,8 @@ S=$ad_project_params(TX_JESD_S)\ RX_OS:M=$ad_project_params(RX_OS_JESD_M)\ L=$ad_project_params(RX_OS_JESD_L)\ S=$ad_project_params(RX_OS_JESD_S)\ -DAC_OFFLOAD:TYPE=$dac_data_offload_type\ -SIZE=$dac_data_offload_size" +DAC_OFFLOAD:TYPE=$dac_offload_type\ +SIZE=$dac_offload_size" sysid_gen_sys_init_file $sys_cstring @@ -46,38 +47,7 @@ set sys_dma_resetn [get_bd_nets sys_250m_resetn] source ../common/adrv9009_bd.tcl -if {$dac_data_offload_type} { - - ad_ip_instance proc_sys_reset axi_rstgen - ad_ip_instance mig_7series axi_ddr_cntrl - file copy -force $ad_hdl_dir/projects/common/zc706/zc706_plddr3_mig.prj [get_property IP_DIR \ - [get_ips [get_property CONFIG.Component_Name [get_bd_cells axi_ddr_cntrl]]]] - ad_ip_parameter axi_ddr_cntrl CONFIG.XML_INPUT_FILE zc706_plddr3_mig.prj - - # PL-DDR data offload interfaces - create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk - create_bd_port -dir I -type rst sys_rst - set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst] - create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3 - - ad_connect axi_ddr_cntrl/ui_clk axi_rstgen/slowest_sync_clk - ad_connect axi_ddr_cntrl/ui_clk $dac_data_offload_name/storage_unit/m_axi_aclk - ad_connect axi_ddr_cntrl/S_AXI $dac_data_offload_name/storage_unit/MAXI_0 - ad_connect axi_rstgen/peripheral_aresetn $dac_data_offload_name/storage_unit/m_axi_aresetn - ad_connect axi_rstgen/peripheral_aresetn axi_ddr_cntrl/aresetn - ad_connect sys_cpu_resetn axi_rstgen/ext_reset_in - - assign_bd_address [get_bd_addr_segs -of_objects [get_bd_cells axi_ddr_cntrl]] - - ad_connect sys_rst axi_ddr_cntrl/sys_rst - ad_connect sys_clk axi_ddr_cntrl/SYS_CLK - ad_connect ddr3 axi_ddr_cntrl/DDR3 - ad_connect axi_ddr_cntrl/device_temp_i GND - ad_connect $dac_data_offload_name/i_data_offload/ddr_calib_done axi_ddr_cntrl/init_calib_complete - - ad_ip_parameter $dac_data_offload_name/storage_unit CONFIG.DDR_BASE_ADDDRESS [format "%d" 0x80000000] - -} +ad_plddr_data_offload_create $dac_offload_name ad_ip_parameter axi_adrv9009_rx_dma CONFIG.FIFO_SIZE 32 ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.FIFO_SIZE 32 diff --git a/projects/adrv9009/zcu102/Makefile b/projects/adrv9009/zcu102/Makefile index 68ca870565..0d7e69f3fe 100644 --- a/projects/adrv9009/zcu102/Makefile +++ b/projects/adrv9009/zcu102/Makefile @@ -22,6 +22,7 @@ M_DEPS += ../../../library/common/ad_bus_mux.v LIB_DEPS += axi_clkgen LIB_DEPS += axi_dmac LIB_DEPS += axi_sysid +LIB_DEPS += data_offload LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac LIB_DEPS += jesd204/axi_jesd204_rx @@ -29,7 +30,6 @@ LIB_DEPS += jesd204/axi_jesd204_tx LIB_DEPS += jesd204/jesd204_rx LIB_DEPS += jesd204/jesd204_tx LIB_DEPS += sysid_rom -LIB_DEPS += data_offload LIB_DEPS += util_do_ram LIB_DEPS += util_pack/util_cpack2 LIB_DEPS += util_pack/util_upack2 diff --git a/projects/adrv9009/zcu102/system_bd.tcl b/projects/adrv9009/zcu102/system_bd.tcl index bfad9d3986..a2aaeedece 100644 --- a/projects/adrv9009/zcu102/system_bd.tcl +++ b/projects/adrv9009/zcu102/system_bd.tcl @@ -3,9 +3,9 @@ ### SPDX short identifier: ADIBSD ############################################################################### -set dac_data_offload_type 0 ; ## BRAM -set dac_data_offload_size [expr 2*1024*1024] ; ## 2 MB -set dac_axi_data_width 256 +set dac_offload_type 0 ; ## BRAM +set dac_offload_size [expr 2*1024*1024] ; ## 2 MB +set plddr_offload_axi_data_width 0 source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl source $ad_hdl_dir/projects/scripts/adi_pd.tcl @@ -24,8 +24,8 @@ S=$ad_project_params(TX_JESD_S)\ RX_OS:M=$ad_project_params(RX_OS_JESD_M)\ L=$ad_project_params(RX_OS_JESD_L)\ S=$ad_project_params(RX_OS_JESD_S)\ -DAC_OFFLOAD:TYPE=$dac_data_offload_type\ -SIZE=$dac_data_offload_size" +DAC_OFFLOAD:TYPE=$dac_offload_type\ +SIZE=$dac_offload_size" sysid_gen_sys_init_file $sys_cstring diff --git a/projects/common/zc706/zc706_plddr3_data_offload_bd.tcl b/projects/common/zc706/zc706_plddr3_data_offload_bd.tcl new file mode 100644 index 0000000000..5d8727e955 --- /dev/null +++ b/projects/common/zc706/zc706_plddr3_data_offload_bd.tcl @@ -0,0 +1,39 @@ +############################################################################### +## Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +proc ad_plddr_data_offload_create {data_offload_name} { + + upvar ad_hdl_dir ad_hdl_dir + + ad_ip_instance proc_sys_reset axi_rstgen + ad_ip_instance mig_7series axi_ddr_cntrl + file copy -force $ad_hdl_dir/projects/common/zc706/zc706_plddr3_mig.prj [get_property IP_DIR \ + [get_ips [get_property CONFIG.Component_Name [get_bd_cells axi_ddr_cntrl]]]] + ad_ip_parameter axi_ddr_cntrl CONFIG.XML_INPUT_FILE zc706_plddr3_mig.prj + + # PL-DDR data offload interfaces + create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk + create_bd_port -dir I -type rst sys_rst + set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst] + create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3 + + ad_connect axi_ddr_cntrl/ui_clk axi_rstgen/slowest_sync_clk + ad_connect axi_ddr_cntrl/ui_clk $data_offload_name/storage_unit/m_axi_aclk + ad_connect axi_ddr_cntrl/S_AXI $data_offload_name/storage_unit/MAXI_0 + ad_connect axi_rstgen/peripheral_aresetn $data_offload_name/storage_unit/m_axi_aresetn + ad_connect axi_rstgen/peripheral_aresetn axi_ddr_cntrl/aresetn + ad_connect sys_cpu_resetn axi_rstgen/ext_reset_in + + assign_bd_address [get_bd_addr_segs -of_objects [get_bd_cells axi_ddr_cntrl]] + + ad_connect sys_rst axi_ddr_cntrl/sys_rst + ad_connect sys_clk axi_ddr_cntrl/SYS_CLK + ad_connect ddr3 axi_ddr_cntrl/DDR3 + ad_connect axi_ddr_cntrl/device_temp_i GND + ad_connect $data_offload_name/i_data_offload/ddr_calib_done axi_ddr_cntrl/init_calib_complete + + ad_ip_parameter $data_offload_name/storage_unit CONFIG.DDR_BASE_ADDDRESS [format "%d" 0x80000000] + +}