Changed the default AD9081 profile for VCK190

* RX_mode=27, L=4, M=4, S=2, NP=12, Lane_rate=12.375 GHz
* TX_mode=23, L=4, M=4, S=2, NP=12, Lane_rate=12.375 GHz
* Ref_clk=375 MHz, Device_clk=125 MHz

projects/ad9081_fmca_ebz/vck190/system_project.tcl

@@ -31,10 +31,11 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
 #      make JESD_MODE=64B66B RX_LANE_RATE=24.75 TX_LANE_RATE=24.75 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=2 RX_JESD_NP=12 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=2 TX_JESD_NP=12
 
+# Limiting the lane rate because of problems at higher speeds
 adi_project ad9081_fmca_ebz_vck190 0 [list \
   JESD_MODE         [get_env_param JESD_MODE     64B66B ]\
-  RX_LANE_RATE      [get_env_param RX_LANE_RATE   24.75 ] \
-  TX_LANE_RATE      [get_env_param TX_LANE_RATE   24.75 ] \
+  RX_LANE_RATE      [get_env_param RX_LANE_RATE  12.375 ] \
+  TX_LANE_RATE      [get_env_param TX_LANE_RATE  12.375 ] \
   REF_CLK_RATE      [get_env_param REF_CLK_RATE     375 ] \
   RX_JESD_M         [get_env_param RX_JESD_M          4 ] \
   RX_JESD_L         [get_env_param RX_JESD_L          4 ] \

projects/ad9081_fmca_ebz/vck190/timing_constr.xdc

@@ -1,9 +1,9 @@
 # Primary clock definitions
-create_clock -name refclk         -period  2.667 [get_ports fpga_refclk_in_p]
+create_clock -name refclk            -period  2.667 [get_ports fpga_refclk_in_p]
 
 # device clock
-create_clock -name tx_device_clk     -period  2.667 [get_ports clkin6_p]
-create_clock -name rx_device_clk     -period  2.667 [get_ports clkin10_p]
+create_clock -name tx_device_clk     -period  8.000 [get_ports clkin6_p]
+create_clock -name rx_device_clk     -period  8.000 [get_ports clkin10_p]
 
 # Constraint SYSREFs
 # Assumption is that REFCLK and SYSREF have similar propagation delay,