From 28df7548b002cf7201ed291a85edfa7643b5f52b Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Wed, 24 Apr 2019 09:45:19 +0100 Subject: [PATCH] axi_dmac: infer interrupt line for Xilinx projects The interrupt controller from Microblaze based projects requires that all its inputs have attributes which define the sensitivity of the interrupt line. Other case it defaults to EDGE_RISING which is not the case for DMAC, leading to incorrect interrupt reporting and handling in case of such projects. --- library/axi_dmac/axi_dmac_ip.tcl | 3 +++ 1 file changed, 3 insertions(+) diff --git a/library/axi_dmac/axi_dmac_ip.tcl b/library/axi_dmac/axi_dmac_ip.tcl index 2e07e200ba..7e831347dd 100644 --- a/library/axi_dmac/axi_dmac_ip.tcl +++ b/library/axi_dmac/axi_dmac_ip.tcl @@ -191,6 +191,9 @@ foreach port {"s_axis_user" "fifo_wr_sync"} { set_property DRIVER_VALUE "1" [ipx::get_ports $port] } +# Infer interrupt +ipx::infer_bus_interface irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core] + set cc [ipx::current_core] # The core does not issue narrow bursts