diff --git a/projects/adv7511/mitx045/Makefile b/projects/adv7511/mitx045/Makefile deleted file mode 100644 index 0cf2d256f4..0000000000 --- a/projects/adv7511/mitx045/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -#################################################################################### -## Copyright 2018(c) Analog Devices, Inc. -## Auto-generated, do not modify! -#################################################################################### - -PROJECT_NAME := adv7511_mitx045 - -M_DEPS += ../../common/mitx045/mitx045_system_ps7.tcl -M_DEPS += ../../common/mitx045/mitx045_system_constr.xdc -M_DEPS += ../../common/mitx045/mitx045_system_bd.tcl -M_DEPS += ../../../library/xilinx/common/ad_iobuf.v - -LIB_DEPS += axi_clkgen -LIB_DEPS += axi_hdmi_tx -LIB_DEPS += axi_i2s_adi -LIB_DEPS += axi_spdif_tx - -include ../../scripts/project-xilinx.mk diff --git a/projects/adv7511/mitx045/system_bd.tcl b/projects/adv7511/mitx045/system_bd.tcl deleted file mode 100644 index 9125cfcd56..0000000000 --- a/projects/adv7511/mitx045/system_bd.tcl +++ /dev/null @@ -1,3 +0,0 @@ - -source $ad_hdl_dir/projects/common/mitx045/mitx045_system_bd.tcl - diff --git a/projects/adv7511/mitx045/system_project.tcl b/projects/adv7511/mitx045/system_project.tcl deleted file mode 100644 index 45f3c70a9f..0000000000 --- a/projects/adv7511/mitx045/system_project.tcl +++ /dev/null @@ -1,13 +0,0 @@ - -source ../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_project.tcl -source $ad_hdl_dir/projects/scripts/adi_board.tcl - -adi_project_xilinx adv7511_mitx045 -adi_project_files adv7511_mitx045 [list \ - "system_top.v" \ - "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ - "$ad_hdl_dir/projects/common/mitx045/mitx045_system_constr.xdc"] - -adi_project_run adv7511_mitx045 - diff --git a/projects/adv7511/mitx045/system_top.v b/projects/adv7511/mitx045/system_top.v deleted file mode 100644 index d4de5a8305..0000000000 --- a/projects/adv7511/mitx045/system_top.v +++ /dev/null @@ -1,154 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - - inout [14:0] ddr_addr, - inout [ 2:0] ddr_ba, - inout ddr_cas_n, - inout ddr_ck_n, - inout ddr_ck_p, - inout ddr_cke, - inout ddr_cs_n, - inout [ 3:0] ddr_dm, - inout [31:0] ddr_dq, - inout [ 3:0] ddr_dqs_n, - inout [ 3:0] ddr_dqs_p, - inout ddr_odt, - inout ddr_ras_n, - inout ddr_reset_n, - inout ddr_we_n, - - inout fixed_io_ddr_vrn, - inout fixed_io_ddr_vrp, - inout [53:0] fixed_io_mio, - inout fixed_io_ps_clk, - inout fixed_io_ps_porb, - inout fixed_io_ps_srstb, - - inout [11:0] gpio_bd, - - output hdmi_out_clk, - output hdmi_vsync, - output hdmi_hsync, - output hdmi_data_e, - output [15:0] hdmi_data, - - output spdif, - - output i2s_mclk, - output i2s_bclk, - output i2s_lrclk, - output i2s_sdata_out, - input i2s_sdata_in, - - inout iic_scl, - inout iic_sda); - - // internal signals - - wire [63:0] gpio_i; - wire [63:0] gpio_o; - wire [63:0] gpio_t; - wire [19:0] gpio_wire; - - // instantiations - - ad_iobuf #(.DATA_WIDTH(32)) i_iobuf ( - .dio_t (gpio_t[31:0]), - .dio_i (gpio_o[31:0]), - .dio_o (gpio_i[31:0]), - .dio_p ({ gpio_wire, - gpio_bd})); - - system_wrapper i_system_wrapper ( - .ddr_addr (ddr_addr), - .ddr_ba (ddr_ba), - .ddr_cas_n (ddr_cas_n), - .ddr_ck_n (ddr_ck_n), - .ddr_ck_p (ddr_ck_p), - .ddr_cke (ddr_cke), - .ddr_cs_n (ddr_cs_n), - .ddr_dm (ddr_dm), - .ddr_dq (ddr_dq), - .ddr_dqs_n (ddr_dqs_n), - .ddr_dqs_p (ddr_dqs_p), - .ddr_odt (ddr_odt), - .ddr_ras_n (ddr_ras_n), - .ddr_reset_n (ddr_reset_n), - .ddr_we_n (ddr_we_n), - .fixed_io_ddr_vrn (fixed_io_ddr_vrn), - .fixed_io_ddr_vrp (fixed_io_ddr_vrp), - .fixed_io_mio (fixed_io_mio), - .fixed_io_ps_clk (fixed_io_ps_clk), - .fixed_io_ps_porb (fixed_io_ps_porb), - .fixed_io_ps_srstb (fixed_io_ps_srstb), - .gpio_i (gpio_i), - .gpio_o (gpio_o), - .gpio_t (gpio_t), - .hdmi_data (hdmi_data), - .hdmi_data_e (hdmi_data_e), - .hdmi_hsync (hdmi_hsync), - .hdmi_out_clk (hdmi_out_clk), - .hdmi_vsync (hdmi_vsync), - .i2s_bclk (i2s_bclk), - .i2s_lrclk (i2s_lrclk), - .i2s_mclk (i2s_mclk), - .i2s_sdata_in (i2s_sdata_in), - .i2s_sdata_out (i2s_sdata_out), - .iic_main_scl_io (iic_scl), - .iic_main_sda_io (iic_sda), - .ps_intr_00 (1'b0), - .ps_intr_01 (1'b0), - .ps_intr_02 (1'b0), - .ps_intr_03 (1'b0), - .ps_intr_04 (1'b0), - .ps_intr_05 (1'b0), - .ps_intr_06 (1'b0), - .ps_intr_07 (1'b0), - .ps_intr_08 (1'b0), - .ps_intr_09 (1'b0), - .ps_intr_10 (1'b0), - .ps_intr_11 (1'b0), - .ps_intr_12 (1'b0), - .ps_intr_13 (1'b0), - .spdif (spdif)); - -endmodule - -// *************************************************************************** -// ***************************************************************************