From f298e45bd773dce2980700ffb60c19155f5ed753 Mon Sep 17 00:00:00 2001 From: Ian Zhang Date: Sun, 28 Apr 2024 17:31:31 -0700 Subject: [PATCH] Fix L1 TLB active memory capacity typo in paging.md --- content/english/hpc/cpu-cache/paging.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/content/english/hpc/cpu-cache/paging.md b/content/english/hpc/cpu-cache/paging.md index 8320d437..ffce4cba 100644 --- a/content/english/hpc/cpu-cache/paging.md +++ b/content/english/hpc/cpu-cache/paging.md @@ -23,7 +23,7 @@ This anomaly is also due to the cache system, although the standard L1-L3 data c On [my CPU](https://en.wikichip.org/wiki/amd/microarchitectures/zen_2), there are two levels of TLB: -- The L1 TLB has 64 entries, and if the page size is 4K, then it can handle $64 \times 4K = 512K$ of active memory without going to the L2 TLB. +- The L1 TLB has 64 entries, and if the page size is 4K, then it can handle $64 \times 4K = 256K$ of active memory without going to the L2 TLB. - The L2 TLB has 2048 entries, and it can handle $2048 \times 4K = 8M$ of memory without going to the page table. How much memory is allocated when $D$ becomes equal to 256? You've guessed it: $8K \times 256 \times 4B = 8M$, exactly the limit of what the L2 TLB can handle. When $D$ gets larger than that, some requests start getting redirected to the main page table, which has a large latency and very limited throughput, which bottlenecks the whole computation.