Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

[Question] How can I receive more than just four bytes? What I'm I doing wrong? #87

Open
sibeov opened this issue May 28, 2024 · 8 comments
Open

[Question] How can I receive more than just four bytes? What I'm I doing wrong? #87

sibeov opened this issue May 28, 2024 · 8 comments

Comments

@sibeov
Copy link

sibeov commented May 28, 2024 •
edited
Loading

Intro

So! This is probably a user error on my part, but still.

Problem

This is is the source-code I'm working on. Simple transmit and receive. Yes! I know this is not how one uses pyuvm, but
I'm in the process of learning and now I'm focusing on learning this extensions. Maybe the problem is in how i use pyuvm?

@pyuvm.test()
class TestTransmitRandom(uvm_test):
    """Test the compilation of the TB and associated source files"""

    def build_phase(self):
        self.logger.info(f"Build phase of {self.get_name()}")
        # self.bfm = BFM()
        self.dut = cocotb.top

    async def run_phase(self):
        self.logger.info(f"Run phase of {self.get_name()}")

        self.dut_in = AxiStreamSource(AxiStreamBus.from_prefix(self.dut, "axisi"),
                                       self.dut.csi_sys_clk,
                                       self.dut.rsi_sys_rst)

        self.dut_out = AxiStreamSink(AxiStreamBus.from_prefix(self.dut, "axiso"),
                                      self.dut.csi_sys_clk,
                                      self.dut.rsi_sys_rst)

        self.raise_objection()
        self.logger.info("Starting clock")
        cocotb.start_soon(Clock(self.dut.csi_sys_clk, 10, units="ns").start())

        self.logger.info("Resetting DUT")
        await FallingEdge(self.dut.csi_sys_clk)
        self.dut.rsi_sys_rst = 0

        await FallingEdge(self.dut.csi_sys_clk)
        self.dut.rsi_sys_rst = 1

        for cycle in range(4):
            await RisingEdge(self.dut.csi_sys_clk)

        await FallingEdge(self.dut.csi_sys_clk)
        self.dut.rsi_sys_rst = 0

        self.logger.info(f"Transmitting data:\n{self.data}")
        test_data = b"Hello hello hello"
        await self.dut_in.send(AxiStreamFrame(tdata=test_data))

        self.logger.info(f"Expecting data:\n{self.data}")
        rx_data = await self.dut_out.recv()

        self.logger.info(f"Sendt    data:\n{[b for b in test_data]}")
        self.logger.info(f"Received data:\n{rx_data.tdata}")

        self.drop_objection()

When I execute i get this:

VPI module loaded!
     0.00ns INFO     cocotb                             Running on GHDL version 5.0.0-dev (4.1.0.r13.g0d97a760f.dirty) [Dunoon edition]
     0.00ns INFO     cocotb                             Running tests with cocotb v1.8.1 from /opt/oss-cad-suite/lib/python3.11/site-packages/cocotb
     0.00ns INFO     cocotb                             Seeding Python random module with 1716890959
     0.00ns INFO     cocotb.regression                  Found test tb_fifo_cc_dbuff.TestTransmitRandom
     0.00ns INFO     cocotb.regression                  running TestTransmitRandom (1/1)
                                                          Test the compilation of the TB and associated source files
     0.00ns INFO     ..on/pyuvm/tb_fifo_cc_dbuff.py(94) [uvm_test_top]: Build phase of uvm_test_top
     0.00ns INFO     ..n/pyuvm/tb_fifo_cc_dbuff.py(102) [uvm_test_top]: Run phase of uvm_test_top
vpi_get_str: unhandled property
vpi_get_str: unhandled property
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axisi AXI stream source
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axisi cocotbext-axi version 0.1.24
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axisi Copyright (c) 2020 Alex Forencich
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axisi https://github.com/alexforencich/cocotbext-axi
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axisi AXI stream source configuration:
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axisi   Byte size: 8 bits
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axisi   Data width: 32 bits (4 bytes)
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axisi AXI stream source signals:
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axisi   tdata width: 32 bits
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axisi   tdest: not present
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axisi   tid: not present
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axisi   tkeep: not present
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axisi   tlast: not present
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axisi   tready width: 1 bits
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axisi   tuser: not present
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axisi   tvalid width: 1 bits
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axisi Reset de-asserted
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axiso AXI stream sink
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axiso cocotbext-axi version 0.1.24
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axiso Copyright (c) 2020 Alex Forencich
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axiso https://github.com/alexforencich/cocotbext-axi
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axiso AXI stream sink configuration:
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axiso   Byte size: 8 bits
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axiso   Data width: 32 bits (4 bytes)
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axiso AXI stream sink signals:
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axiso   tdata width: 32 bits
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axiso   tdest: not present
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axiso   tid: not present
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axiso   tkeep: not present
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axiso   tlast: not present
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axiso   tready width: 1 bits
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axiso   tuser: not present
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axiso   tvalid width: 1 bits
     0.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axiso Reset de-asserted
     0.00ns INFO     ..n/pyuvm/tb_fifo_cc_dbuff.py(113) [uvm_test_top]: Starting clock
     0.00ns INFO     ..n/pyuvm/tb_fifo_cc_dbuff.py(116) [uvm_test_top]: Resetting DUT
/home/sibeov/repos/vcp-verification/pyuvm/tb_fifo_cc_dbuff.py:118: DeprecationWarning: Setting values on handles using the ``dut.handle = value`` syntax is deprecated. Instead use the ``handle.value = value`` syntax
  self.dut.rsi_sys_rst = 0
/home/sibeov/repos/vcp-verification/pyuvm/tb_fifo_cc_dbuff.py:121: DeprecationWarning: Setting values on handles using the ``dut.handle = value`` syntax is deprecated. Instead use the ``handle.value = value`` syntax
  self.dut.rsi_sys_rst = 1
    15.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axisi Reset asserted
    15.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axiso Reset asserted
/home/sibeov/repos/vcp-verification/pyuvm/tb_fifo_cc_dbuff.py:127: DeprecationWarning: Setting values on handles using the ``dut.handle = value`` syntax is deprecated. Instead use the ``handle.value = value`` syntax
  self.dut.rsi_sys_rst = 0
    55.00ns INFO     ..n/pyuvm/tb_fifo_cc_dbuff.py(129) [uvm_test_top]: Transmitting data:
                                                        AxiStreamFrame(tdata=bytearray(b']sW\xac\x8ay\x85\xf2\x9b\xadT\\D\xa7\xf8\xee2bH\x93L\xec^'), tkeep=None, tid=None, tdest=None, tuser=None, sim_time_start=None, sim_time_end=None)
    55.00ns INFO     ..n/pyuvm/tb_fifo_cc_dbuff.py(133) [uvm_test_top]: Expecting data:
                                                        AxiStreamFrame(tdata=bytearray(b']sW\xac\x8ay\x85\xf2\x9b\xadT\\D\xa7\xf8\xee2bH\x93L\xec^'), tkeep=None, tid=None, tdest=None, tuser=None, sim_time_start=None, sim_time_end=None)
    55.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axisi Reset de-asserted
    55.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axiso Reset de-asserted
    60.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axisi TX frame: AxiStreamFrame(tdata=bytearray(b'Hello hello hello'), tkeep=None, tid=None, tdest=None, tuser=None, sim_time_start=60000000, sim_time_end=None)
    80.00ns INFO     ..tb.fifo_cc_dbuff_axis_wrap.axiso RX frame: AxiStreamFrame(tdata=bytearray(b'Hell'), tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=80000000, sim_time_end=80000000)
    80.00ns INFO     ..n/pyuvm/tb_fifo_cc_dbuff.py(136) [uvm_test_top]: Sendt    data:
                                                        [72, 101, 108, 108, 111, 32, 104, 101, 108, 108, 111, 32, 104, 101, 108, 108, 111]
    80.00ns INFO     ..n/pyuvm/tb_fifo_cc_dbuff.py(137) [uvm_test_top]: Received data:
                                                        bytearray(b'Hell')
    80.00ns INFO     cocotb.regression                  TestTransmitRandom passed
    80.00ns INFO     cocotb.regression                  *********************************************************************************************
                                                        ** TEST                                 STATUS  SIM TIME (ns)  REAL TIME (s)  RATIO (ns/s) **
                                                        *********************************************************************************************
                                                        ** tb_fifo_cc_dbuff.TestTransmitRandom   PASS          80.00           0.01       8693.31  **
                                                        *********************************************************************************************
                                                        ** TESTS=1 PASS=1 FAIL=0 SKIP=0                        80.00           0.09        851.03  **
                                                        *********************************************************************************************

It does not pass as only the first four octets have been received. I'm guessing I (the user) am the problem.
What I'm I doing wrong.

Deprecation Warning [SOLVED]

Also. Anyone can spot what I'm doing wrong to generate the deprecation warnings?

See answer: #87 (comment)

Specs

Let me know if you need to know anything in particular.
@sibeov sibeov changed the title [Question] [Question] How can I receive more than just four bytes? What I'm I doing wrong? May 28, 2024
@sibeov
Copy link
Author

sibeov commented May 28, 2024 •
edited
Loading

Same happens with this snippet:

@cocotb.test()
async def TestTransmitRandom(dut):
    """Test the compilation of the TB and associated source files"""

    cocotb.start_soon(Clock(dut.csi_sys_clk, 10, units="ns").start())

    dut_in = AxiStreamSource(AxiStreamBus.from_prefix(dut, "axisi"),
                                    dut.csi_sys_clk,
                                    dut.rsi_sys_rst)

    dut_out = AxiStreamSink(AxiStreamBus.from_prefix(dut, "axiso"),
                                    dut.csi_sys_clk,
                                    dut.rsi_sys_rst)

    await FallingEdge(dut.csi_sys_clk)
    dut.rsi_sys_rst = 0

    await FallingEdge(dut.csi_sys_clk)
    dut.rsi_sys_rst = 1

    for cycle in range(4):
        await RisingEdge(dut.csi_sys_clk)

    await FallingEdge(dut.csi_sys_clk)
    dut.rsi_sys_rst = 0

    test_data = b"Hello hello hello"
    await dut_in.send(AxiStreamFrame(tdata=test_data))

    rx_data = await dut_out.recv()

    print(f"Test     data : {test_data}")
    print(f"Received data : {rx_data.tdata}")

@Gatherer
Copy link

to get rid of the deprecation warning change to dut.rsi_sys_rst.value = 1

@sibeov
Copy link
Author

sibeov commented May 28, 2024

Of course. Thanks!

@Gatherer
Copy link

Hello,

from the log I see you do not have the tlast signal on both interfaces.
0.00ns INFO ..tb.fifo_cc_dbuff_axis_wrap.axisi tlast: not present

Maybe that is the reason you only get one beat, 32 bit / 4 byte back. As the tlast is not present the receive function may written in a way to return after one beat in this case.

@sibeov
Copy link
Author

sibeov commented May 29, 2024

Ahaa. I will check that as soon as I can.

@sibeov
Copy link
Author

sibeov commented Jun 11, 2024

Ahaa. I will check that as soon as I can.

Have not had time to check this out. Still working on it.

@sibeov
Copy link
Author

sibeov commented Sep 16, 2024

Ok. Soo.. Now I got the tlast working, but now I have som strange issues with extra zeros added to the output?
Might be a design flaw on my end, but the simulation waveforms seems ok?

msrdc_E20HcOJDHZ

make -f Makefile sim
rm -f ./out/results/tb_fifo_cc_dbuff.xml
"make" -f Makefile ./out/results/tb_fifo_cc_dbuff.xml
make[1]: Entering directory '/home/sibeov/repos/vcp-verification/pyuvm'
/opt/oss-cad-suite/bin/ghdl -i  --std=08 --workdir=./out --work=vcp ../ip/vcp/pkg/common/*.vhd ../ip/vcp/pkg/dvr/*.vhd ../ip/vcp/pkg/axi/*.vhd ../ip/vcp/modules/fifo_cc_dbuff/src/*.vhd ../ip/vcp/modules/fifo_cc_dbuff_axis_wrap/src/*.vhd  &&  \
/opt/oss-cad-suite/bin/ghdl -i  --std=08 --workdir=./out --work=work ./tb/*.vhd && \
/opt/oss-cad-suite/bin/ghdl -m  --std=08 --workdir=./out -P./out --work=work fifo_cc_dbuff_axis_tb_wrap
analyze ../ip/vcp/pkg/common/common_types_pkg.vhd
analyze ../ip/vcp/pkg/common/common_methods_pkg.vhd
analyze ../ip/vcp/pkg/axi/axistream_types_pkg.vhd
analyze ../ip/vcp/pkg/axi/axistream_methods_pkg.vhd
analyze ../ip/vcp/modules/fifo_cc_dbuff_axis_wrap/src/fifo_cc_dbuff_axis_wrap_pkg.vhd
analyze ../ip/vcp/modules/fifo_cc_dbuff/src/fifo_cc_dbuff_pkg.vhd
analyze ../ip/vcp/modules/fifo_cc_dbuff/src/fifo_cc_dbuff.vhd
analyze ../ip/vcp/modules/fifo_cc_dbuff_axis_wrap/src/fifo_cc_dbuff_axis_wrap.vhd
analyze ./tb/fifo_cc_dbuff_axis_tb_wrap.vhd
elaborate fifo_cc_dbuff_axis_tb_wrap
rm -f ./out/results/tb_fifo_cc_dbuff.xml
MODULE=tb_fifo_cc_dbuff TESTCASE= TOPLEVEL=fifo_cc_dbuff_axis_tb_wrap TOPLEVEL_LANG=vhdl \
 /opt/oss-cad-suite/bin/ghdl -r   --workdir=./out -P./out --work=work fifo_cc_dbuff_axis_tb_wrap  --vpi=/home/sibeov/.local/lib/python3.10/site-packages/cocotb/libs/libcocotbvpi_ghdl.so -gg_tdata_width=32 -gg_tid_width=0 -gg_tdest_width=0 -gg_tuser_width=0 -gg_enable_sequential_ack=false --wave=./out/tb_fifo_cc_dbuff.ghw --psl-report=out/tb_fifo_cc_dbuff_psl.json --vpi-trace=out/tb_fifo_cc_dbuff_vpi.log
loading VPI module '/home/sibeov/.local/lib/python3.10/site-packages/cocotb/libs/libcocotbvpi_ghdl.so'
     -.--ns INFO     gpi                                ..mbed/gpi_embed.cpp:79   in set_program_name_in_venv        Did not detect Python virtual environment. Using system-wide Python interpreter
     -.--ns INFO     gpi                                ../gpi/GpiCommon.cpp:101  in gpi_print_registered_impl       VPI registered
VPI module loaded!
     0.00ns INFO     cocotb                             Running on GHDL version 5.0.0-dev (4.1.0.r13.g0d97a760f.dirty) [Dunoon edition]
     0.00ns INFO     cocotb                             Running tests with cocotb v1.9.0 from /home/sibeov/.local/lib/python3.10/site-packages/cocotb
     0.00ns INFO     cocotb                             Seeding Python random module with 1726504310
/usr/lib/python3/dist-packages/xonsh/pytest_plugin.py:42: PytestRemovedIn9Warning: The (path: py.path.local) argument is deprecated, please use (file_path: pathlib.Path)
see https://docs.pytest.org/en/latest/deprecations.html#py-path-local-arguments-for-hooks-replaced-with-pathlib-path
  def pytest_collect_file(parent, path):
     0.00ns INFO     cocotb.regression                  Found test tb_fifo_cc_dbuff.TestTransmitRandom
     0.00ns INFO     cocotb.regression                  running TestTransmitRandom (1/1)
                                                          Test the compilation of the TB and associated source files
     0.00ns INFO     ..on/pyuvm/tb_fifo_cc_dbuff.py(94) [uvm_test_top]: Build phase of uvm_test_top
vpi_get_str: unhandled property
vpi_get_str: unhandled property
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axisi AXI stream source
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axisi cocotbext-axi version 0.1.24
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axisi Copyright (c) 2020 Alex Forencich
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axisi https://github.com/alexforencich/cocotbext-axi
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axisi AXI stream source configuration:
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axisi   Byte size: 8 bits
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axisi   Data width: 32 bits (4 bytes)
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axisi AXI stream source signals:
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axisi   tdata width: 32 bits
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axisi   tdest: not present
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axisi   tid: not present
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axisi   tkeep: not present
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axisi   tlast width: 1 bits
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axisi   tready width: 1 bits
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axisi   tuser: not present
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axisi   tvalid width: 1 bits
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axisi Reset de-asserted
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axiso AXI stream sink
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axiso cocotbext-axi version 0.1.24
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axiso Copyright (c) 2020 Alex Forencich
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axiso https://github.com/alexforencich/cocotbext-axi
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axiso AXI stream sink configuration:
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axiso   Byte size: 8 bits
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axiso   Data width: 32 bits (4 bytes)
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axiso AXI stream sink signals:
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axiso   tdata width: 32 bits
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axiso   tdest: not present
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axiso   tid: not present
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axiso   tkeep: not present
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axiso   tlast width: 1 bits
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axiso   tready width: 1 bits
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axiso   tuser: not present
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axiso   tvalid width: 1 bits
     0.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axiso Reset de-asserted
     0.00ns INFO     ..on/pyuvm/tb_fifo_cc_dbuff.py(99) [uvm_test_top]: Run phase of uvm_test_top
     0.00ns INFO     ..n/pyuvm/tb_fifo_cc_dbuff.py(103) [uvm_test_top]: Resetting BFM
../ip/vcp/modules/fifo_cc_dbuff/src/fifo_cc_dbuff.vhd:123:3:@0ms:(assertion warning): [WARN]: Data width not octet oriented!
    15.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axisi Reset asserted
    15.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axiso Reset asserted
    55.00ns INFO     ..n/pyuvm/tb_fifo_cc_dbuff.py(108) [uvm_test_top]: Transmitting data:
                                                        b'Hello hello hello'
    55.00ns INFO     ..n/pyuvm/tb_fifo_cc_dbuff.py(111) [uvm_test_top]: Receiving data:
                                                        b'Hello hello hello'
    55.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axisi Reset de-asserted
    55.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axiso Reset de-asserted
    60.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axisi TX frame: AxiStreamFrame(tdata=bytearray(b'Hello hello hello'), tkeep=None, tid=None, tdest=None, tuser=None, sim_time_start=60000000, sim_time_end=None)
   120.00ns INFO     ..fifo_cc_dbuff_axis_tb_wrap.axiso RX frame: AxiStreamFrame(tdata=bytearray(b'Hello hello hello\x00\x00\x00'), tkeep=[], tid=[], tdest=[], tuser=[], sim_time_start=80000000, sim_time_end=120000000)
   120.00ns INFO     ..k 9.TestTransmitRandom.run_phase Test stopped by this forked coroutine
   120.00ns INFO     cocotb.regression                  TestTransmitRandom failed

@sibeov
Copy link
Author

sibeov commented Sep 16, 2024

Ooooohkey. I think I figured it out. And it makes sence.
I do not send byte aligned data, and I do not provide tkeep to tell my sink which data to keep.
And I expect different data then what I get (padded data I guess).
Maybe someone can explain it better to me? Or perhaps this makes sense?

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
2 participants
@Gatherer @sibeov