Latencies scaling with CPU clock

[Moiralex]

Hello,
I want to increase the core clock and i was wondering if i should scale the memory latencies that are calculated based on that clock during simulation (namely gpgpu_l1_latency, gpgpu_smem_latency, gpgpu_l2_rop_latency, dram_latency as mentioned in the config files) accordingly, so as to keep these latencies constant on a time basis. Are they actually dependent on the core clock or are they just modelled as core cycles based on experimental results? Thank you in advance!

[JRPan]

Hi,

Sorry for the late reply. Changing core frequency does not help much. The final results are reported in cycles which is irrelevant with frequency. The latencies you mentioned is also independent of core frequency.

However, memory subsystem (DRAM) has individual frequency and that would determine how long a memory load come back which affects simulation results significantly.

[Moiralex]

Hello again and thanks for the reply,
I've been studying the way the simulator handles the frequencies and i noticed it uses 4 different clocks (core, icnt, l2 and dram) so i expect relative changes between those clocks to affect my results on a time basis. Is that assumption wrong? What i also noticed is that the simulator waits for the latencies i mentioned previously (gpgpu_l2_rop_latency, dram_latency) in core cycles although these latencies don't seem directly correlated to operations happening inside the core. That is why i am wondering if those latencies are just modeled as core cycles for simulation purposes but are actually constant on a time basis and as such should be scaled with the core clock if it is changed (eg 10% increase in core clock -> 10% increase in dram_latency cycles). Thank you once again for your help!

[JRPan]

i expect relative changes between those clocks to affect my results on a time basis. Is that assumption wrong?

This is absolutely correct. The 4 clock frequencies you mentioned are relative. For example, if you scale all 4 numbers by 2, the results are going to be the same. However, if you increase only dram freq to 2X while keeping everything else the same, this means a dram read is 2X faster than before, which of course, would impact simulation results.

And these these latencies are core cycles. But you don't need to scale it, I think. Just change the -gpgpu_clock_domains should be enough. This controls the relative relation between different components. If you halve the dram clock, then every dram cycle is 2X core cycle. Dram executes once after core executes twice, which increases the dram latency by 2X in terms of core latency.

Hope this makes sense.
Thanks