Model the latency and bandwidth between LLC slice and DRAM controller

[Yfeng-44]

Hi all,

I'm trying to figure out how to add an constant latency and bandwidth between LLC slice and DRAM controller without touching the DRAM timing.

Latency -wise, my current solution was to add extra cycles to read_cycle.

My problem is more at the bandwidth side. My thought as of now is change the L2 -> DRAM queue and DRAM -> L2 length. But the impact on performance seems non-trivial?

Any suggestions?

regards,
Yuan

[JRPan]

Latency wise it should be fine.
Bandwidth wise you should increase how many memory request can be served per cycle. The queue length you are changing is not relevant to bandwidth. You are just saving more requests, but still only the same number of request can be served per cycle. You can add more controllers, or add more sub-partition per controller. You can also make each L2 sub-partition serve more than 1 request per cycle. Depends on what you're trying to do.