links.in

@header Links@

<h1>Links</h1>

This page contains links to other projects.

<h2>Related Projects</h2>

<p>These tools are built by members of the Yosys devteam.</p>

<ul>
<li><a href="https://github.com/amaranth-lang">Amaranth HDL</a> -- A Python embedded DSL for hardware description that emits Yosys RTLIL
<li><a href="https://github.com/YosysHQ/sby">sby</a> -- a front-end driver program for Yosys-based formal hardware verification flows
<li><a href="https://github.com/YosysHQ/mcy">mcy</a> -- Mutation Cover with Yosys
<li><a href="https://github.com/YosysHQ/nextpnr">nextpnr</a> -- A portable FPGA place and route tool
<li><a href="https://github.com/YosysHQ/icestorm">Project IceStorm</a> -- Documenting the Lattice iCE40 FPGAs Bitstream format
<li><a href="https://github.com/YosysHQ/prjtrellis">Project Trellis</a> -- Documenting the Lattice ECP5 Bitstream format
<li><a href="https://github.com/gatecat/prjoxide">Project Oxide</a> -- Documenting Lattice's 28nm FPGA parts
<li><a href=""></a>
</ul>

<h2>Online Services</h2>

<ul>
<li><a href="http://www.edaplayground.com/">EDA Playground</a> -- Web Interface to many EDA tools, including Yosys
<li><a href="http://www.blinklight.io/">Blinklight</a> -- A visual FPGA dev tool for simple designs
</ul>

<h2>Free Verilog Simulators</h2>

<ul>
<li><a href="http://iverilog.icarus.com/">Icarus Verilog</a>
<li><a href="http://www.veripool.org/wiki/verilator">Verilator</a>
<li><a href="https://github.com/gtkwave/gtkwave">GTKWave waveform visualizer</a> -- use to view VCD files generated by the above tools
</ul>

<h2>Free Software for High-Level Circuit Synthesis and/or Analysis</h2>

<ul>
<li><a href="https://chisel.eecs.berkeley.edu/">Chisel</a> -- Constructing Hardware in a Scala Embedded Language
<li><a href="http://panda.dei.polimi.it/">PandA</a> -- high-level synthesis of C based descriptions
<li><a href="http://www.clash-lang.org">CLaSH</a> -- A compiler from Haskell to Verilog/VHDL
<li><a href="http://www.myhdl.org/">MyHDL</a> -- an open source Python package that lets you go from Python to silicon
<li><a href="https://m-labs.hk/gateware/migen/">Migen</a> -- a Python-based tool that aims at automating further the VLSI design process
<li><a href="https://github.com/enjoy-digital/litex">LiteX</a> -- Framework for rapidly assembling SoCs for use on FPGA
<li><a href="http://cx-lang.org/">Cx</a> -- A modern C-like language to create digital hardware
</ul>

<h2>Free Software for Low-Level Circuit Synthesis and/or Analysis</h2>

<ul>
<li><a href="http://www.eecs.berkeley.edu/~alanmi/abc/">ABC</a> -- extensive tools for synthesis and verification of binary sequential logic
<li><a href="http://fmv.jku.at/aiger/">AIGER</a> -- a format, library and set of utilities for And-Inverter Graphs
<li><a href="http://minisat.se/">MiniSAT</a> -- the SAT solver library used in Yosys
<li><a href="http://torc.isi.edu/">Torc</a> -- infrastructure and tool set for mapping, placing, and routing
<li><a href="http://rapidsmith.sourceforge.net/">RapidSmith</a> -- a research-based, open source FPGA CAD tool for modern Xilinx FPGAs
<li><a href="http://opencircuitdesign.com/">Open Circuit Design</a> -- collection of open-source EDA tools, including Qflow
<li><a href="https://soc-extras.lip6.fr/en/coriolis/coriolis2-users-guide/">Coriolis2</a> -- an ASIC place and route flow
<li><a href="https://workcraft.org/">Workcraft</a> -- a framework for interpreted graph models
<li><a href="https://github.com/nturley/netlistsvg">netlistsvg</a> -- SVG schematic from a Yosys JSON netlist
<li><a href="https://github.com/emsec/hal">HAL</a> -- The Hardware Analyzer
</ul>

<h2>Verilog Tutorials</h2>

<ul>
<li><a href="http://verilog.james.walms.co.uk/">Learning Verilog with Yosys</a>
<li><a href="http://numato.com/learning-fpga-and-verilog-a-beginners-guide-part-1-introduction">Numato Lab Verilog Tutorial</a>
<li><a href="http://www.asic-world.com/verilog/veritut.html">ASIC-World Verilog Tutorial</a>
<li><a href="http://www.nandland.com/">Nandland: Verilog Examples, Tutorials, and more</a>
</ul>

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