partition: ERROR: Found 2 problems in 'check -assert'.

[cassiersg]

With the following (reduced) test case, running yosys synth.ys, then eqy test_synth.eqy gives the following error:

EQY 13:50:09 [test_synth] partition: Warning: Wire gate.test.a.\a is used but has no driver.
EQY 13:50:09 [test_synth] partition: Warning: Wire gold.test.a.\a is used but has no driver.
EQY 13:50:09 [test_synth] partition: ERROR: Found 2 problems in 'check -assert'.

The generated partition test.a.il does not have any input.

test.sv:

module X (input a, output b);
assign b = 0;
endmodule

module Y(input a, input b, output c);
assign c = 0;
endmodule

module test (input a, output c);
wire b;
X x (.a(a), .b(b));
Y y(.a(a), .b(b), .c(c));
endmodule

synth.ys:

read_verilog -sv test.sv
flatten t:X
synth -top test
write_verilog test_synth.v

test_synth.eqy:

[gold]
read_verilog -formal -sv test.sv
hierarchy -check -top test
proc

[gate]
read_verilog -formal -icells test_synth.v

[script]
prep -top test
# only keep FF outputs, avoids partitioning on signals that were changed by optimizations
rename -hide t:$dff %co x:* %% w:* %D

[strategy sby]
use sby
depth 2
engine smtbmc bitwuzla

Generated partition partitions/test.a.il:

# Generated by Yosys 0.46+147 (git sha1 2999f5589, clang++ 14.0.0-1ubuntu1.1 -fPIC -O3)
autoidx 20
module \gate.test.a
  attribute \keep 1
  wire output 1 \__po_a
  attribute \keep 1
  wire output 2 \__po_x.a
  attribute \keep 1
  wire \a
  connect { \__po_x.a \__po_a } { \a \a }
end
module \gold.test.a
  attribute \keep 1
  wire output 1 \__po_a
  attribute \keep 1
  wire output 2 \__po_x.a
  attribute \keep 1
  wire \a
  attribute \keep 1
  wire \x.a
  cell $_BUF_ $auto$insbuf.cc:97:execute$18
    connect \A \a
    connect \Y \x.a
  end
  connect { \__po_x.a \__po_a } { \x.a \a }
end