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template.xml
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template.xml
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<?xml version="1.0" encoding="UTF-8"?>
<root versionMajor="1" versionMinor="6">
<kernel name="placeholder" language="ip_c" vlnv="xilinx.com:kernel:placeholder:1.0" attributes="" preferredWorkGroupSizeMultiple="0" workGroupSize="1" interrupt="false" hwControlProtocol="ap_ctrl_none">
<ports>
<port name="S_AXILITE" mode="slave" range="0x2000" dataWidth="32" portType="addressable" base="0x0"/>
<port name="S_AXIS" mode="read_only" range="" dataWidth="512" portType="stream"/>
<port name="M_AXIS" mode="write_only" range="" dataWidth="512" portType="stream"/>
</ports>
<args>
<!-- CMAC Register Map-->
<arg name="gt_reset_reg" addressQualifier="0" id="0" port="S_AXILITE" size="0x4" offset="0x0000" type="uint" hostOffset="0x00" hostSize="0x4"/>
<arg name="reset_reg" addressQualifier="0" id="1" port="S_AXILITE" size="0x4" offset="0x0004" type="uint" hostOffset="0x00" hostSize="0x4"/>
<arg name="mode" addressQualifier="0" id="2" port="S_AXILITE" size="0x4" offset="0x0008" type="uint" hostOffset="0x00" hostSize="0x4"/>
<arg name="conf_tx" addressQualifier="0" id="3" port="S_AXILITE" size="0x4" offset="0x000C" type="uint" hostOffset="0x00" hostSize="0x4"/>
<arg name="conf_rx" addressQualifier="0" id="4" port="S_AXILITE" size="0x4" offset="0x0014" type="uint" hostOffset="0x00" hostSize="0x4"/>
<arg name="core_mode" addressQualifier="0" id="5" port="S_AXILITE" size="0x4" offset="0x0020" type="uint" hostOffset="0x00" hostSize="0x4"/>
<arg name="version" addressQualifier="0" id="6" port="S_AXILITE" size="0x4" offset="0x0024" type="uint" hostOffset="0x00" hostSize="0x4"/>
<arg name="gt_loopback" addressQualifier="0" id="7" port="S_AXILITE" size="0x4" offset="0x0090" type="uint" hostOffset="0x00" hostSize="0x4"/>
<arg name="user_reg0" addressQualifier="0" id="8" port="S_AXILITE" size="0x4" offset="0x00CC" type="uint" hostOffset="0x00" hostSize="0x4"/>
<arg name="stat_tx_status" addressQualifier="0" id="9" port="S_AXILITE" size="0x4" offset="0x0200" type="uint" hostOffset="0x00" hostSize="0x4"/>
<arg name="stat_rx_status" addressQualifier="0" id="10" port="S_AXILITE" size="0x4" offset="0x0204" type="uint" hostOffset="0x00" hostSize="0x4"/>
<arg name="stat_status" addressQualifier="0" id="11" port="S_AXILITE" size="0x4" offset="0x0208" type="uint" hostOffset="0x00" hostSize="0x4"/>
<arg name="stat_rx_block_lock" addressQualifier="0" id="12" port="S_AXILITE" size="0x4" offset="0x020C" type="uint" hostOffset="0x00" hostSize="0x4"/>
<arg name="stat_rx_lane_sync" addressQualifier="0" id="13" port="S_AXILITE" size="0x4" offset="0x0210" type="uint" hostOffset="0x00" hostSize="0x4"/>
<arg name="stat_rx_lane_sync_err" addressQualifier="0" id="14" port="S_AXILITE" size="0x4" offset="0x0214" type="uint" hostOffset="0x00" hostSize="0x4"/>
<arg name="stat_an_link_ctl" addressQualifier="0" id="15" port="S_AXILITE" size="0x4" offset="0x0260" type="uint" hostOffset="0x00" hostSize="0x4"/>
<arg name="stat_lt_status" addressQualifier="0" id="16" port="S_AXILITE" size="0x4" offset="0x0264" type="uint" hostOffset="0x00" hostSize="0x4"/>
<arg name="stat_pm_tick" addressQualifier="0" id="17" port="S_AXILITE" size="0x4" offset="0x02B0" type="uint" hostOffset="0x00" hostSize="0x4"/>
<arg name="stat_cycle_count" addressQualifier="0" id="18" port="S_AXILITE" size="0x8" offset="0x02B8" type="uint" hostOffset="0x00" hostSize="0x8"/>
<!-- Tx Stats-->
<arg name="stat_tx_total_packets" addressQualifier="0" id="19" port="S_AXILITE" size="0x8" offset="0x0500" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_tx_total_good_packets" addressQualifier="0" id="20" port="S_AXILITE" size="0x8" offset="0x0508" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_tx_total_bytes" addressQualifier="0" id="21" port="S_AXILITE" size="0x8" offset="0x0510" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_tx_total_good_bytes" addressQualifier="0" id="22" port="S_AXILITE" size="0x8" offset="0x0518" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_tx_total_packets_64B" addressQualifier="0" id="23" port="S_AXILITE" size="0x8" offset="0x0520" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_tx_total_packets_65_127B" addressQualifier="0" id="24" port="S_AXILITE" size="0x8" offset="0x0528" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_tx_total_packets_128_255B" addressQualifier="0" id="25" port="S_AXILITE" size="0x8" offset="0x0530" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_tx_total_packets_256_511B" addressQualifier="0" id="26" port="S_AXILITE" size="0x8" offset="0x0538" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_tx_total_packets_512_1023B" addressQualifier="0" id="27" port="S_AXILITE" size="0x8" offset="0x0540" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_tx_total_packets_1024_1518B" addressQualifier="0" id="28" port="S_AXILITE" size="0x8" offset="0x0548" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_tx_total_packets_1519_1522B" addressQualifier="0" id="29" port="S_AXILITE" size="0x8" offset="0x0550" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_tx_total_packets_1523_1548B" addressQualifier="0" id="30" port="S_AXILITE" size="0x8" offset="0x0558" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_tx_total_packets_1549_2047B" addressQualifier="0" id="31" port="S_AXILITE" size="0x8" offset="0x0560" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_tx_total_packets_2048_4095B" addressQualifier="0" id="32" port="S_AXILITE" size="0x8" offset="0x0568" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_tx_total_packets_4096_8191B" addressQualifier="0" id="33" port="S_AXILITE" size="0x8" offset="0x0570" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_tx_total_packets_8192_9215B" addressQualifier="0" id="34" port="S_AXILITE" size="0x8" offset="0x0578" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_tx_total_packets_large" addressQualifier="0" id="35" port="S_AXILITE" size="0x8" offset="0x0580" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_tx_total_packets_small" addressQualifier="0" id="36" port="S_AXILITE" size="0x8" offset="0x0588" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_tx_total_bad_fcs" addressQualifier="0" id="37" port="S_AXILITE" size="0x8" offset="0x05B8" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_tx_pause" addressQualifier="0" id="38" port="S_AXILITE" size="0x8" offset="0x05F0" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_tx_user_pause" addressQualifier="0" id="39" port="S_AXILITE" size="0x8" offset="0x05F8" type="uint" hostOffset="0x00" hostSize="0x8"/>
<!-- Rx Stats-->
<arg name="stat_rx_total_packets" addressQualifier="0" id="40" port="S_AXILITE" size="0x8" offset="0x0608" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_rx_total_good_packets" addressQualifier="0" id="41" port="S_AXILITE" size="0x8" offset="0x0610" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_rx_total_bytes" addressQualifier="0" id="42" port="S_AXILITE" size="0x8" offset="0x0618" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_rx_total_good_bytes" addressQualifier="0" id="43" port="S_AXILITE" size="0x8" offset="0x0620" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_rx_total_packets_64B" addressQualifier="0" id="44" port="S_AXILITE" size="0x8" offset="0x0628" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_rx_total_packets_65_127B" addressQualifier="0" id="45" port="S_AXILITE" size="0x8" offset="0x0630" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_rx_total_packets_128_255B" addressQualifier="0" id="46" port="S_AXILITE" size="0x8" offset="0x0638" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_rx_total_packets_256_511B" addressQualifier="0" id="47" port="S_AXILITE" size="0x8" offset="0x0640" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_rx_total_packets_512_1023B" addressQualifier="0" id="48" port="S_AXILITE" size="0x8" offset="0x0648" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_rx_total_packets_1024_1518B" addressQualifier="0" id="49" port="S_AXILITE" size="0x8" offset="0x0650" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_rx_total_packets_1519_1522B" addressQualifier="0" id="50" port="S_AXILITE" size="0x8" offset="0x0658" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_rx_total_packets_1523_1548B" addressQualifier="0" id="51" port="S_AXILITE" size="0x8" offset="0x0660" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_rx_total_packets_1549_2047B" addressQualifier="0" id="52" port="S_AXILITE" size="0x8" offset="0x0668" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_rx_total_packets_2048_4095B" addressQualifier="0" id="53" port="S_AXILITE" size="0x8" offset="0x0670" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_rx_total_packets_4096_8191B" addressQualifier="0" id="54" port="S_AXILITE" size="0x8" offset="0x0678" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_rx_total_packets_8192_9215B" addressQualifier="0" id="55" port="S_AXILITE" size="0x8" offset="0x0680" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_rx_total_packets_large" addressQualifier="0" id="56" port="S_AXILITE" size="0x8" offset="0x0688" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_rx_total_packets_small" addressQualifier="0" id="57" port="S_AXILITE" size="0x8" offset="0x0690" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_rx_total_packets_undersize" addressQualifier="0" id="58" port="S_AXILITE" size="0x8" offset="0x0698" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_rx_total_packets_fragmented" addressQualifier="0" id="59" port="S_AXILITE" size="0x8" offset="0x06A0" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_rx_total_packets_oversize" addressQualifier="0" id="60" port="S_AXILITE" size="0x8" offset="0x06A8" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_rx_total_packets_toolong" addressQualifier="0" id="61" port="S_AXILITE" size="0x8" offset="0x06B0" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_rx_total_packets_jabber" addressQualifier="0" id="62" port="S_AXILITE" size="0x8" offset="0x06B8" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_rx_total_bad_fcs" addressQualifier="0" id="63" port="S_AXILITE" size="0x8" offset="0x06C0" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_rx_packets_bad_fcs" addressQualifier="0" id="64" port="S_AXILITE" size="0x8" offset="0x06C8" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_rx_stomped_fcs" addressQualifier="0" id="65" port="S_AXILITE" size="0x8" offset="0x06D0" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_rx_pause" addressQualifier="0" id="66" port="S_AXILITE" size="0x8" offset="0x06F8" type="uint" hostOffset="0x00" hostSize="0x8"/>
<arg name="stat_rx_user_pause" addressQualifier="0" id="67" port="S_AXILITE" size="0x8" offset="0x0700" type="uint" hostOffset="0x00" hostSize="0x8"/>
<!-- RS-FEC config -->
<arg name="rsfec_config_ind_corr" addressQualifier="0" id="68" port="S_AXILITE" size="0x4" offset="0x1000" type="uint" hostOffset="0x00" hostSize="0x4" />
<arg name="rsfec_config_enable" addressQualifier="0" id="69" port="S_AXILITE" size="0x4" offset="0x107C" type="uint" hostOffset="0x00" hostSize="0x4" />
<arg name="S_AXIS" addressQualifier="4" id="70" port="S_AXIS" size="0x0" offset="0x0" hostOffset="0x0" hostSize="0x0" memSize="0" type="stream<ap_axiu<512,0,0,0>>&" />
<arg name="M_AXIS" addressQualifier="4" id="71" port="M_AXIS" size="0x0" offset="0x0" hostOffset="0x0" hostSize="0x0" memSize="0" type="stream<ap_axiu<512,0,0,0>>&" />
</args>
</kernel>
</root>