Second port map indentation wrong

[Trooper-X]

Currently formatted document:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity top_level is
    port
    (
        -- System inputs
        clk : in std_logic;
        rst : in std_logic;

        -- Data in
        mode_sel : in std_logic;
        data_in  : in std_logic;

        -- Data out
        data_out : out std_logic
    );
end top_level;

architecture arch of top_level is
    -- Components
    component some_component is
        port
        (
            clk      : in std_logic;
            rst      : in std_logic;
            data_in  : in std_logic_vector(7 downto 0);
            data_out : out integer
        );
    end component;

    component some_other_component is
        port
        (
            clk      : in std_logic; -- More comments
            rst      : in std_logic;
            data_in  : in unsigned(7 downto 0); -- After line comment
            data_out : out std_logic
        );
    end component;

begin
    sc : some_component port map
    (
        clk      => clk,
        rst      => rst,
        data_in  => sc_data_in,
        data_out => sc_data_out
    );

    -- This one fails
    soc : some_other_component port
    map(
    clk      => clk,
    rst      => rst,
    data_in  => sc_data_in,
    data_out => sc_data_out
    );

    dido : process (all) -- Another comment
    begin
        if rst then
            data_out <= '0';
        elsif rising_edge(clk) then -- Some data thing
            --changes---
            if mode_sel then
                data_out <= data_in;
            else
                data_out <= not data_in;
            end if;
            --end of changes--

            --removed lines--
            -- data_out <= data_in when mode_sel else
            --     not data_in;
            --end of removed lines--
        end if;
    end process;      -- dido
end architecture; -- arch

Expected formatted document:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity top_level is
    port
    (
        -- System inputs
        clk : in std_logic;
        rst : in std_logic;

        -- Data in
        mode_sel : in std_logic;
        data_in  : in std_logic;

        -- Data out
        data_out : out std_logic
    );
end top_level;

architecture arch of top_level is
    -- Components
    component some_component is
        port
        (
            clk      : in std_logic;
            rst      : in std_logic;
            data_in  : in std_logic_vector(7 downto 0);
            data_out : out integer
        );
    end component;

    component some_other_component is
        port
        (
            clk      : in std_logic; -- More comments
            rst      : in std_logic;
            data_in  : in unsigned(7 downto 0); -- After line comment
            data_out : out std_logic
        );
    end component;

begin
    sc : some_component port map
    (
        clk      => clk,
        rst      => rst,
        data_in  => sc_data_in,
        data_out => sc_data_out
    );

    -- This one fails
    soc : some_other_component port
    map(
        clk      => clk,
        rst      => rst,
        data_in  => sc_data_in,
        data_out => sc_data_out
    );

    dido : process (all) -- Another comment
    begin
        if rst then
            data_out <= '0';
        elsif rising_edge(clk) then -- Some data thing
            --changes---
            if mode_sel then
                data_out <= data_in;
            else
                data_out <= not data_in;
            end if;
            --end of changes--

            --removed lines--
            -- data_out <= data_in when mode_sel else
            --     not data_in;
            --end of removed lines--
        end if;
    end process;      -- dido
end architecture; -- arch