Double empty lines completely removed

[Frame42]

Input

library ieee;
use ieee.std_logic_1164.all;

entity test_ent is
end;
architecture behav of test_ent is
begin


  procedure mde_wr (
    signal input  : in std_logic;
    signal output : out std_logic
  ) is
  begin
    output <= input;
  end procedure;


end architecture behav;

Output:

library ieee;
use ieee.std_logic_1164.all;

entity test_ent is
end;
architecture behav of test_ent is
begin
  procedure mde_wr (
    signal input  : in std_logic;
    signal output : out std_logic
  ) is
  begin
    output <= input;
  end procedure;
end architecture behav;

Expected:

library ieee;
use ieee.std_logic_1164.all;

entity test_ent is
end;
architecture behav of test_ent is
begin

  procedure mde_wr (
    signal input  : in std_logic;
    signal output : out std_logic
  ) is
  begin
    output <= input;
  end procedure;

end architecture behav;

Notice the 2 empty lines being completely removed instead of being replaced by a single empty line.