missing a linter complain on this assignment

[erik-ski]

Hi, I am working with teros HDL using VHLD-LS as the linter. I have the following piece of code. The assignment is wrong because x"0" has 4 bits, and accum_sig has 5. I've thought taking this to your attention may be useful.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;


entity acumulador_dp is
  generic (
    nbits    : positive := 5;
    nweights : positive := 10);
  
end entity;
architecture naive of acumulador_dp is


  signal accum_sig, weight, sum : signed (nbits - 1 downto 0);
  

begin
  accum_sig <= x"0"; --(others => '0');
end architecture;