Name		Name	Last commit message	Last commit date
parent directory ..
.gitignore		.gitignore
BPSK_behav_sim_+16_S1.csv		BPSK_behav_sim_+16_S1.csv
BPSK_behav_sim_+32_F.csv		BPSK_behav_sim_+32_F.csv
BPSK_behav_sim_+8_S1.csv		BPSK_behav_sim_+8_S1.csv
BPSK_behav_sim_-128_F.csv		BPSK_behav_sim_-128_F.csv
BPSK_behav_sim_-16_S0.csv		BPSK_behav_sim_-16_S0.csv
BPSK_behav_sim_-32_F.csv		BPSK_behav_sim_-32_F.csv
BPSK_behav_sim_-64_F.csv		BPSK_behav_sim_-64_F.csv
BPSK_behav_sim_-8_S0.csv		BPSK_behav_sim_-8_S0.csv
MIX_behav_sim.csv		MIX_behav_sim.csv
QPSK_behav_sim_+16_F.csv		QPSK_behav_sim_+16_F.csv
QPSK_behav_sim_+32_F.csv		QPSK_behav_sim_+32_F.csv
QPSK_behav_sim_+4_S.csv		QPSK_behav_sim_+4_S.csv
QPSK_behav_sim_+8_F.csv		QPSK_behav_sim_+8_F.csv
QPSK_behav_sim_-4_S.csv		QPSK_behav_sim_-4_S.csv
QPSK_behav_sim_-8_F.csv		QPSK_behav_sim_-8_F.csv
README.md		README.md
Tx_behav_sim.csv		Tx_behav_sim.csv

README.md

Behavioral Simulation

This directory contains the behavioral simulation of the design in CSV, saved from Verilog testbenchs via $fdisplay.