How can I initial the pipeline registers？

[ZhengJuzhong666]

Hello, I would like to initialize the pipeline registers in the code shown below. I used the method below, but when I use FPU, I get this error.

the origin code: (Line 124 at pipeline.scala)

inputDefault := RegNextWhen(stageBefore.output(key), stage.dontSample.getOrElse(key, Nil).foldLeft(!stage.arbitration.isStuck)(_ && !_)).setName(s"${stageBefore.getName()}_to_${stage.getName()}_${key.getName()}")

my code:

stageBeforeData init(B(0, stageBefore.output(key).getBitsWidth bits))
inputDefault.assignFromBits(stageBeforeData)
inputDefault.setName(s"${stageBefore.getName()}_to_${stage.getName()}_${key.getName()}")

the code where the error occurred: (Line 313 at FpuPlugin.scala)

    Component.current.afterElaboration{
      pipeline.stages.tail.foreach(_.input(FPU_FORKED).init(False))
    }

the error:

How can I initialize the registers correctly? Thank you!

[Dolu1990]

Hi,

Hmm i'm not exactly sure of your actual setup. can you share the modifications ?
Also, if i understand well, the error pop up in Line 313 at FpuPlugin.scala, while you didn't modified that file right ?

[ZhengJuzhong666]

Thank you!

I modified this part of the code.
Line 128 is the original code. The commented code above is the part I want to modify. I want to instead line 128 with commented code.

I understand this is the code used to pass signals in the CPU pipeline. But I don't know much about the specific design of the FPU unit, so it's not clear to me why this variable won't be instantiated as a register.

[Dolu1990]

Hi, sorry for the delay,

I understand this is the code used to pass signals in the CPU pipeline.

yes that's right.
So i think the issue is that it doesn't like the "assignFromBits being used here.
:= isn't working ? else, assignFrom ?