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I wanted to ask if VexRiscv would support the RISC-V vector extensions sometime in the future. Thanks!
The text was updated successfully, but these errors were encountered:
Hi,
Currently, there is no plan for it, i would say it it unlikely.
Sorry, something went wrong.
What stopping you from considering it?
Mostly the complexity of handeling the memory load / store of the vector ISA, even more when it comes with a MMU.
It may eventualy come one day in https://github.com/SpinalHDL/VexiiRiscv
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I wanted to ask if VexRiscv would support the RISC-V vector extensions sometime in the future. Thanks!
The text was updated successfully, but these errors were encountered: