From e2e2efccd5a9e52a0787078dbe40cc755f872051 Mon Sep 17 00:00:00 2001 From: DavidLP Date: Fri, 12 Jan 2018 11:02:14 +0100 Subject: [PATCH] REV: not needed logging related changes --- basil/HL/RegisterHardwareLayer.py | 2 +- basil/utils/sim/Test.py | 4 +--- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/basil/HL/RegisterHardwareLayer.py b/basil/HL/RegisterHardwareLayer.py index 2473b8f63..eb638b17f 100644 --- a/basil/HL/RegisterHardwareLayer.py +++ b/basil/HL/RegisterHardwareLayer.py @@ -62,7 +62,7 @@ def init(self): version = str(self.VERSION) else: version = None - logger.debug("Initializing %s (firmware version: %s), module %s, base_addr %s" % (self.name, version if 'VERSION' in self._registers else 'n/a', self.__class__.__module__, hex(self._base_addr))) + logger.info("Initializing %s (firmware version: %s), module %s, base_addr %s" % (self.name, version if 'VERSION' in self._registers else 'n/a', self.__class__.__module__, hex(self._base_addr))) if self._require_version and not eval(version + self._require_version): raise Exception("FPGA module %s does not satisfy version requirements (read: %s, require: %s)" % (self.__class__.__module__, version, self._require_version.strip())) for reg, value in self._registers.iteritems(): diff --git a/basil/utils/sim/Test.py b/basil/utils/sim/Test.py index 198d5cf1a..0153ac20e 100644 --- a/basil/utils/sim/Test.py +++ b/basil/utils/sim/Test.py @@ -17,8 +17,6 @@ from Protocol import WriteRequest, ReadRequest, ReadResponse, PickleInterface from cocotb.binary import BinaryValue -logger = logging.getLogger(__name__) - def get_bus(): bus_name_path = os.getenv("SIMULATION_BUS", "basil.utils.sim.BasilBusDriver") @@ -39,7 +37,7 @@ def socket_test(dut, debug=False): port = os.getenv("SIMULATION_PORT", '12345') if debug: - logger.setLevel(logging.DEBUG) + dut._log.setLevel(logging.DEBUG) bus = get_bus()(dut)