diff --git a/basil/HL/JtagMaster.py b/basil/HL/JtagMaster.py index 83208c4c1..e3b5adfa1 100644 --- a/basil/HL/JtagMaster.py +++ b/basil/HL/JtagMaster.py @@ -4,7 +4,6 @@ # SiLab, Institute of Physics, University of Bonn # ------------------------------------------------------------ # -import struct from basil.HL.RegisterHardwareLayer import RegisterHardwareLayer from basil.utils.BitLogic import BitLogic @@ -95,15 +94,19 @@ def get_data(self, size=None, addr=None): else: return self._intf.read(self._conf["base_addr"] + self._mem_offset + addr, size) - def scan_ir(self, data): + def scan_ir(self, data, readback=True): """ Data must be a list of BitLogic """ - bit_number = self._test_input(data, words=1) + bit_number = self._test_input(data) self.SIZE = bit_number - data_byte = self._bitlogic2bytes(data) + if type(data[0]) == BitLogic: + data_byte = self._bitlogic2bytes(data) + else: + data_byte = self._raw_data2bytes(data) + self.set_data(data_byte) self.WORD_COUNT = 1 @@ -112,57 +115,58 @@ def scan_ir(self, data): while not self.READY: pass - received_data = self.get_data(size=len(data_byte)) - rlist = self._bytes2bitlogic(received_data, bit_number, data) - - return rlist + if readback: + received_data = self.get_data(size=len(data_byte)) + return self._bytes2bitlogic(received_data, bit_number, data) - def scan_dr(self, data, words=1): + def scan_dr(self, data, readback=True, word_size=None): """ Data must be a list of BitLogic or string of raw data """ - bit_number = self._test_input(data, words) - if words != 1: - self.SIZE = int(bit_number / words) - else: - self.SIZE = bit_number + bit_number = self._test_input(data, word_size) self.set_command("DATA") - self.WORD_COUNT = words + + if word_size is None: + self.SIZE = bit_number + self.WORD_COUNT = 1 + else: + self.WORD_COUNT = bit_number // word_size + self.SIZE = word_size + if type(data[0]) == BitLogic: data_byte = self._bitlogic2bytes(data) - self.set_data(data_byte) else: data_byte = self._raw_data2bytes(data) - self.set_data(data_byte) + + self.set_data(data_byte) self.start() while not self.READY: pass - received_data = self.get_data(size=len(data_byte)) - rlist = self._bytes2bitlogic(received_data, bit_number, data) - - return rlist + if readback: + received_data = self.get_data(size=len(data_byte)) + return self._bytes2bitlogic(received_data, bit_number, data) - def _test_input(self, data, words): + def _test_input(self, data, word_size=None): """ Test input data and return length in bits """ - if type(data[0]) == BitLogic or type(data[0]) == str: - pass - else: + + if not isinstance(data, list): + raise ValueError("Input data must be a list of BitLogic or str") + + if type(data[0]) not in [BitLogic, str]: raise TypeError("Type of data not supported: got", type(data[0]), " and support only str and Bitlogic") bit_number = sum(len(x) for x in data) - if bit_number <= self._mem_bytes * 8: - pass - else: + if bit_number > self._mem_bytes * 8: raise ValueError("Size is too big for memory: got %d and memory is: %d" % (bit_number, self._mem_bytes * 8)) - if words != 1 and bit_number % words != 0: - raise ValueError("Number of bits doesn't match the number of words. %d bits remaining" % (bit_number % words)) + if word_size is not None and bit_number % word_size != 0: + raise ValueError("Number of bits doesn't match word_size. %d bits remaining" % (bit_number % word_size)) return bit_number @@ -172,9 +176,7 @@ def _bitlogic2bytes(self, data): device_string = data[dev].to01() original_string += device_string[::-1] # We want the original string of the Bitlogic, not the reversed one data_bitarray = bitarray(original_string) - data_byte = data_bitarray.tobytes() - - return data_byte + return data_bitarray.tobytes() def _bytes2bitlogic(self, data, bit_number, original_data): data_byte = np.byte(data) @@ -183,6 +185,7 @@ def _bytes2bitlogic(self, data, bit_number, original_data): binary_string = tmp.to01() rlist = [] + last_data_len = 0 for i in original_data: rlist.append(BitLogic(binary_string[last_data_len:len(i) + last_data_len])) @@ -191,13 +194,12 @@ def _bytes2bitlogic(self, data, bit_number, original_data): return rlist def _raw_data2bytes(self, data): - all_data = "" - for i in data: - all_data = all_data + i + + all_data = "".join(data) + # pad with zero if not a multiple of 8 if len(all_data) % 8 != 0: - all_data = all_data + "0" * (8 - (len(all_data) % 8)) + all_data += "0" * (8 - (len(all_data) % 8)) + # convert string to byte - size = len(all_data) // 8 - data_byte = struct.pack(">Q", int(all_data, 2))[8 - size:] - return data_byte + return bytes(int(all_data[i:i + 8], 2) for i in range(0, len(all_data), 8)) diff --git a/basil/firmware/modules/jtag_master/jtag_master_core.v b/basil/firmware/modules/jtag_master/jtag_master_core.v index 7b1f1bab6..5cc3f90fd 100644 --- a/basil/firmware/modules/jtag_master/jtag_master_core.v +++ b/basil/firmware/modules/jtag_master/jtag_master_core.v @@ -4,7 +4,7 @@ * SiLab, Institute of Physics, University of Bonn * ------------------------------------------------------------ */ -`timescale 1ps/1ps + `default_nettype none module jtag_master_core #( @@ -30,7 +30,7 @@ module jtag_master_core #( output reg SLD ); -localparam VERSION = 1; +localparam VERSION = 1; localparam DEF_BIT_OUT = 8*MEM_BYTES; reg [7:0] status_regs [15:0]; @@ -40,36 +40,36 @@ wire RST_SYNC; assign RST = BUS_RST || SOFT_RST; always @(posedge BUS_CLK) begin - if(RST) begin - status_regs[0] <= 0; - status_regs[1] <= 0; - status_regs[2] <= 0; - status_regs[3] <= DEF_BIT_OUT[7:0]; //bits - status_regs[4] <= DEF_BIT_OUT[15:8]; //bits - status_regs[5] <= 0; //wait - status_regs[6] <= 0; //wait - status_regs[7] <= 0; //wait - status_regs[8] <= 0; //wait - status_regs[9] <= 1; //word count + if (RST) begin + status_regs[0] <= 0; + status_regs[1] <= 0; + status_regs[2] <= 0; + status_regs[3] <= DEF_BIT_OUT[7:0]; //bits + status_regs[4] <= DEF_BIT_OUT[15:8]; //bits + status_regs[5] <= 0; //wait + status_regs[6] <= 0; //wait + status_regs[7] <= 0; //wait + status_regs[8] <= 0; //wait + status_regs[9] <= 1; //word count status_regs[10] <= 0; //word count status_regs[11] <= 0; //Jtag command status_regs[12] <= 0; //Jtag command status_regs[13] <= 0; //0:enable external start end - else if(BUS_WR && BUS_ADD < 16) + else if (BUS_WR && BUS_ADD < 16) begin status_regs[BUS_ADD[3:0]] <= BUS_DATA_IN; + end end // Parameters from registers // - reg [7:0] BUS_IN_MEM; reg [7:0] BUS_OUT_MEM; reg CONF_DONE; wire START; wire START_SYNC; -assign SOFT_RST = (BUS_ADD==0 && BUS_WR); -assign START = (BUS_ADD==1 && BUS_WR); +assign SOFT_RST = (BUS_ADD == 0 && BUS_WR); +assign START = (BUS_ADD == 1 && BUS_WR); wire [15:0] CONF_BIT_OUT; assign CONF_BIT_OUT = {status_regs[4],status_regs[3]}; @@ -93,16 +93,16 @@ assign STOP_BIT = CONF_BIT_OUT + CONF_WAIT; /// Basil Bus Communication /// reg [7:0] BUS_DATA_OUT_REG; always @(posedge BUS_CLK) begin - if(BUS_RD) begin - if(BUS_ADD == 0) + if (BUS_RD) begin + if (BUS_ADD == 0) BUS_DATA_OUT_REG <= VERSION; - else if(BUS_ADD == 1) + else if (BUS_ADD == 1) BUS_DATA_OUT_REG <= {7'b0, CONF_DONE}; - else if(BUS_ADD == 13) + else if (BUS_ADD == 13) BUS_DATA_OUT_REG <= {7'b0, CONF_EN}; - else if(BUS_ADD == 14) + else if (BUS_ADD == 14) BUS_DATA_OUT_REG <= MEM_BYTES[7:0]; - else if(BUS_ADD == 15) + else if (BUS_ADD == 15) BUS_DATA_OUT_REG <= MEM_BYTES[15:8]; else if (BUS_ADD < 16) BUS_DATA_OUT_REG <= status_regs[BUS_ADD[3:0]]; @@ -111,17 +111,17 @@ end reg [ABUSWIDTH-1:0] PREV_BUS_ADD; always @(posedge BUS_CLK) begin - if(BUS_RD) begin + if (BUS_RD) begin PREV_BUS_ADD <= BUS_ADD; end end always @(*) begin - if(PREV_BUS_ADD < 16) + if (PREV_BUS_ADD < 16) BUS_DATA_OUT = BUS_DATA_OUT_REG; - else if(PREV_BUS_ADD < 16+MEM_BYTES) + else if (PREV_BUS_ADD < 16+MEM_BYTES) BUS_DATA_OUT = BUS_IN_MEM; - else if(PREV_BUS_ADD < 16+MEM_BYTES+MEM_BYTES) + else if (PREV_BUS_ADD < 16+MEM_BYTES+MEM_BYTES) BUS_DATA_OUT = BUS_OUT_MEM; else BUS_DATA_OUT = 8'hxx; @@ -132,10 +132,10 @@ wire [7:0] BUS_IN_MEM_IB; wire [7:0] BUS_OUT_MEM_IB; integer i; always @(*) begin - for(i=0;i<8;i=i+1) begin + for(i = 0;i<8;i = i+1) begin BUS_DATA_IN_IB[i] = BUS_DATA_IN[7-i]; - BUS_IN_MEM[i] = BUS_IN_MEM_IB[7-i]; - BUS_OUT_MEM[i] = BUS_OUT_MEM_IB[7-i]; + BUS_IN_MEM[i] = BUS_IN_MEM_IB[7-i]; + BUS_OUT_MEM[i] = BUS_OUT_MEM_IB[7-i]; end end //// @@ -148,7 +148,7 @@ localparam TEST_LOGIC_RESET = 0, SHIFT_DR = 4, EXIT1_DR = 5, PAUSE_DR = 6, - EXIT2_DR = 7, + EXIT2_DR = 7, UPDATE_DR = 8, SELECT_IR_SCAN = 9, CAPTURE_IR = 10, @@ -164,46 +164,47 @@ reg [32:0] out_bit_cnt; reg [32:0] out_word_cnt; reg [32:0] reset_cnt; -wire [13:0] memout_addrb; +localparam AWIDTH = $clog2(MEM_BYTES); +wire [AWIDTH-1:0] memout_addra; +assign memout_addra = (BUS_ADD - 32'd16); +wire [AWIDTH+2:0] memout_addrb; assign memout_addrb = (out_word_cnt * CONF_BIT_OUT) + CONF_BIT_OUT - 1 - out_bit_cnt; -wire [10:0] memout_addra; -assign memout_addra = (BUS_ADD-16); - -blk_mem_gen_8_to_1_2k memout( - .CLKA(BUS_CLK), - .CLKB(JTAG_CLK), - .DOUTA(BUS_IN_MEM_IB), - .DOUTB(SDI_MEM), - .WEA(BUS_WR && BUS_ADD >=16 && BUS_ADD < 16+MEM_BYTES), - .WEB(1'b0), - .ADDRA(memout_addra), - .ADDRB(memout_addrb), - .DINA(BUS_DATA_IN_IB), - .DINB(1'b0) + + +ramb_8_to_n #(.SIZE(MEM_BYTES), .WIDTH(1)) memout ( +.clkA(BUS_CLK), +.clkB(JTAG_CLK), +.weA(BUS_WR && BUS_ADD >= 16 && BUS_ADD < 16+MEM_BYTES), +.weB(1'b0), +.addrA(memout_addra), +.addrB(memout_addrb), +.diA(BUS_DATA_IN_IB), +.doA(BUS_IN_MEM_IB), +.diB(), +.doB(SDI_MEM) ); -wire [10:0] ADDRA_MIN; +wire [AWIDTH-1:0] ADDRA_MIN; assign ADDRA_MIN = (BUS_ADD-16-MEM_BYTES); -wire [13:0] ADDRB_MIN; +wire [AWIDTH+2:0] ADDRB_MIN; assign ADDRB_MIN = (out_word_cnt * CONF_BIT_OUT) + CONF_BIT_OUT - out_bit_cnt; reg SEN_INT; -blk_mem_gen_8_to_1_2k memin( - .CLKA(BUS_CLK), - .CLKB(JTAG_CLK), - .DOUTA(BUS_OUT_MEM_IB), - .DOUTB(), - .WEA(1'b0), - .WEB(SEN_INT && (state == SHIFT_DR || state == SHIFT_IR)), - .ADDRA(ADDRA_MIN), - .ADDRB(ADDRB_MIN), - .DINA(BUS_DATA_IN_IB), - .DINB(TDO) +ramb_8_to_n #(.SIZE(MEM_BYTES), .WIDTH(1)) memin ( + .clkA(BUS_CLK), + .clkB(JTAG_CLK), + .weA(1'b0), + .weB(SEN_INT && (state == SHIFT_DR || state == SHIFT_IR)), + .addrA(ADDRA_MIN), + .addrB(ADDRB_MIN), + .diA(BUS_DATA_IN_IB), + .doA(BUS_OUT_MEM_IB), + .diB(TDO), + .doB() ); -/// // JTAG Master Machine state // -localparam DR_SCAN = 1, IR_SCAN = 0; +localparam DR_SCAN = 1, IR_SCAN = 0; reg transfert_active = 0; // Assign next state of the FSM @@ -217,17 +218,17 @@ end // State transition conditions always @(*) begin case (state) - TEST_LOGIC_RESET: + TEST_LOGIC_RESET: begin if (reset_cnt <= 5) begin next_state <= TEST_LOGIC_RESET; - SEN_INT <= 1; + SEN_INT <= 1; end else begin next_state <= RUN_TEST_IDLE; - SEN_INT <= 0; + SEN_INT <= 0; end end RUN_TEST_IDLE: @@ -235,12 +236,12 @@ always @(*) begin if (START_SYNC || (out_word_cnt != WORD_COUNT && SEN_INT)) begin next_state <= SELECT_DR_SCAN; - SEN_INT <= 1; + SEN_INT <= 1; end else begin next_state <= RUN_TEST_IDLE; - SEN_INT <= 0; + SEN_INT <= 0; end end SELECT_DR_SCAN: @@ -290,11 +291,10 @@ begin out_bit_cnt <= out_bit_cnt + 1; else out_bit_cnt <= 0; -end +end // Word counter -always @(posedge JTAG_CLK) -begin // - 1 because we must change of step on last bit +always @(posedge JTAG_CLK) begin // - 1 because we must change of step on last bit if (RST_SYNC) out_word_cnt <= 0; else if (state == UPDATE_DR || state == UPDATE_IR) @@ -383,7 +383,7 @@ begin end SELECT_IR_SCAN: begin - if(next_state == CAPTURE_IR) + if (next_state == CAPTURE_IR) TMS <= 0; else TMS <= 1; @@ -451,18 +451,18 @@ always @(posedge JTAG_CLK) begin end always @(posedge JTAG_CLK) - SLD <= (sync_ld[1]==1 && sync_ld[0]==0); + SLD <= (sync_ld[1] == 1 && sync_ld[0] == 0); wire DONE_SYNC, DONE; assign DONE = (out_word_cnt == WORD_COUNT && state == RUN_TEST_IDLE) || (reset_cnt == 5); cdc_pulse_sync done_pulse_sync (.clk_in(JTAG_CLK), .pulse_in(DONE), .clk_out(BUS_CLK), .pulse_out(DONE_SYNC)); always @(posedge BUS_CLK) - if(START || RST) + if (START || RST) CONF_DONE <= 0; - else if(DONE_SYNC) + else if (DONE_SYNC) CONF_DONE <= 1; -/// + /// // Outputs // CG_MOD_pos icg2(.ck_in(JTAG_CLK), .enable(SEN), .ck_out(TCK)); diff --git a/basil/firmware/modules/utils/ramb_8_to_n.v b/basil/firmware/modules/utils/ramb_8_to_n.v new file mode 100644 index 000000000..4fd4efa6f --- /dev/null +++ b/basil/firmware/modules/utils/ramb_8_to_n.v @@ -0,0 +1,128 @@ +/** + * ------------------------------------------------------------ + * Copyright (c) All rights reserved + * SiLab, Institute of Physics, University of Bonn + * ------------------------------------------------------------ + */ + +module ramb_8_to_n (clkA, + clkB, + weA, + weB, + addrA, + addrB, + diA, + doA, + diB, + doB); + +parameter SIZE = 1024; +parameter WIDTH = 8; + +localparam WIDTHA = 8; +localparam SIZEA = SIZE; +localparam ADDRWIDTHA = $clog2(SIZEA); + +localparam WIDTHB = WIDTH; +localparam SIZEB = SIZEA*8/WIDTHB; +localparam ADDRWIDTHB = $clog2(SIZEB); + +input wire clkA; +input wire clkB; +input wire weA, weB; +input wire [ADDRWIDTHA-1:0] addrA; +input wire [ADDRWIDTHB-1:0] addrB; +input wire [WIDTHA-1:0] diA; +input wire [WIDTHB-1:0] diB; +output reg [WIDTHA-1:0] doA; +output reg [WIDTHB-1:0] doB; + +`define max(a,b) {(a) > (b) ? (a) : (b)} +`define min(a,b) {(a) < (b) ? (a) : (b)} + +localparam maxSIZE = `max(SIZEA, SIZEB); +localparam maxWIDTH = `max(WIDTHA, WIDTHB); +localparam minWIDTH = `min(WIDTHA, WIDTHB); +localparam RATIO = maxWIDTH / minWIDTH; +localparam log2RATIO = $clog2(RATIO); + +reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; + +genvar w; +generate + for (w=0; w < SIZEA; w=w + 1) begin + initial RAM[w] = 0; + end +endgenerate + +generate + if (WIDTH == 8) begin + always @(posedge clkB) + begin + if (weB) + RAM[addrB] <= diB; + + doB <= RAM[addrB]; + end + + always @(posedge clkA) begin : portA + if (weA) + RAM[addrA] <= diA; + + doA <= RAM[addrA]; + end + end +endgenerate + +generate + if (WIDTH < 8) begin + always @(posedge clkB) + begin + if (weB) + RAM[addrB] <= diB; + + doB <= RAM[addrB]; + end + + always @(posedge clkA) begin : portA + integer i; + reg [log2RATIO-1:0] lsbaddr ; + + for (i = 0; i< RATIO; i = i + 1) begin + lsbaddr = i; + if (weA) + RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH]; + + doA[(i+1)*minWIDTH -1 -: minWIDTH] <= RAM[{addrA, lsbaddr}]; + end + end + end +endgenerate + + +generate + if (WIDTH > 8) begin + always @(posedge clkA) + begin + if (weA) + RAM[addrA] <= diA; + + doA <= RAM[addrA]; + end + + always @(posedge clkB) begin : portA + integer i; + reg [log2RATIO-1:0] lsbaddr ; + for (i = 0; i< RATIO; i = i + 1) begin + lsbaddr = i; + if (weB) + RAM[{addrB, lsbaddr}] <= diB[(i+1)*minWIDTH-1 -: minWIDTH]; + + doB[(i+1)*minWIDTH -1 -: minWIDTH] <= RAM[{addrB, lsbaddr}]; + end + end + end +endgenerate + + +endmodule diff --git a/tests/test_SimJtagMaster.py b/tests/test_SimJtagMaster.py index 8c52d79c6..2b75a0264 100644 --- a/tests/test_SimJtagMaster.py +++ b/tests/test_SimJtagMaster.py @@ -163,7 +163,12 @@ class TestSimJtagMaster(unittest.TestCase): def setUp(self): - cocotb_compile_and_run([os.path.join(os.path.dirname(__file__), "jtag_tap.v"), os.path.join(os.path.dirname(__file__), "test_SimJtagMaster.v")]) + cocotb_compile_and_run( + [ + os.path.join(os.path.dirname(__file__), "jtag_tap.v"), + os.path.join(os.path.dirname(__file__), "test_SimJtagMaster.v"), + ] + ) self.chip = Dut(cnfg_yaml) self.chip.init(init_yaml) @@ -224,7 +229,8 @@ def jtag_master_FSM_tests(self): def jtag_tests(self): - ID_CODE = BitLogic("0010") + ID_CODE_STR = "0010" + ID_CODE = BitLogic(ID_CODE_STR) BYPASS = BitLogic("1111") DEBUG = BitLogic("1000") ret_ir = BitLogic("0101") @@ -247,10 +253,22 @@ def jtag_tests(self): self.chip["JTAG"].reset() # IR CODE + with self.assertRaises(ValueError): + self.chip["JTAG"].scan_ir(ID_CODE_STR + ID_CODE_STR) + + ret = self.chip["JTAG"].scan_ir([ID_CODE] * 2, readback=False) + self.assertEqual(ret, None) + ret = self.chip["JTAG"].scan_ir([ID_CODE] * 2) self.assertEqual(ret, [ret_ir] * 2) # ID CODE + with self.assertRaises(ValueError): + self.chip["JTAG"].scan_dr("0" * 32 * 2) + + ret = self.chip["JTAG"].scan_dr(["0" * 32] * 2, readback=False) + self.assertEqual(ret, None) + id_code = BitLogic.from_value(0x149B51C3, fmt="I") ret = self.chip["JTAG"].scan_dr(["0" * 32] * 2) self.assertEqual(ret, [id_code] * 2) @@ -297,11 +315,17 @@ def jtag_tests(self): self.assertEqual(dev1ret[:], self.chip["DEV2"][:]) # REPEATING REGISTER - self.chip["JTAG"].scan_dr([self.chip["DEV"][:]], words=2) - ret1 = self.chip["JTAG"].scan_dr([self.chip["DEV"][:]], words=2) + self.chip["JTAG"].scan_dr([self.chip["DEV"][:]], word_size=len(self.chip["DEV"][:])) + ret1 = self.chip["JTAG"].scan_dr([self.chip["DEV"][:]], word_size=len(self.chip["DEV"][:])) self.chip["JTAG"].scan_dr([self.chip["DEV1"][:], self.chip["DEV2"][:]]) - ret2 = self.chip["JTAG"].scan_dr([self.chip["DEV1"][:] + self.chip["DEV2"][:]], words=2) - ret3 = self.chip["JTAG"].scan_dr([self.chip["DEV1"][:] + self.chip["DEV2"][:]], words=2) + ret2 = self.chip["JTAG"].scan_dr( + [self.chip["DEV1"][:] + self.chip["DEV2"][:]], + word_size=len(self.chip["DEV1"][:]), + ) + ret3 = self.chip["JTAG"].scan_dr( + [self.chip["DEV1"][:] + self.chip["DEV2"][:]], + word_size=len(self.chip["DEV1"][:]), + ) self.assertEqual(ret1[:], ret2[:]) self.assertEqual(ret2[:], ret3[:]) @@ -312,8 +336,14 @@ def jtag_tests(self): self.chip["DEV"].set(ret[0]) self.assertEqual(self.chip["DEV"][:], BitLogic("1" * 32 + "0" * 32)) - self.chip["JTAG"].scan_dr([self.chip["DEV1"][:] + self.chip["DEV2"][:]], words=2) - ret = self.chip["JTAG"].scan_dr([self.chip["DEV1"][:] + self.chip["DEV2"][:]], words=2) + self.chip["JTAG"].scan_dr( + [self.chip["DEV1"][:] + self.chip["DEV2"][:]], + word_size=len(self.chip["DEV1"][:]), + ) + ret = self.chip["JTAG"].scan_dr( + [self.chip["DEV1"][:] + self.chip["DEV2"][:]], + word_size=len(self.chip["DEV1"][:]), + ) self.chip["DEV"].set(ret[0]) self.assertEqual(self.chip["DEV"][:], self.chip["DEV1"][:] + self.chip["DEV2"][:]) @@ -373,7 +403,7 @@ def jtag_tests(self): fifo_tap2_content = self.chip["fifo2"].get_data() self.chip["JTAG"].scan_ir([DEBUG, BYPASS]) - self.chip["JTAG"].scan_dr([BitLogic("0" * 24 + "10101101"), BitLogic("1")] * 15, words=15) + self.chip["JTAG"].scan_dr([BitLogic("0" * 24 + "10101101"), BitLogic("1")] * 15, word_size=33) fifo_tap1_content = self.chip["fifo1"].get_data() fifo_tap2_content = self.chip["fifo2"].get_data() @@ -389,7 +419,7 @@ def jtag_tests(self): fifo_tap2_content = self.chip["fifo2"].get_data() self.chip["JTAG"].scan_ir([BYPASS, DEBUG]) - self.chip["JTAG"].scan_dr([BitLogic("1"), BitLogic("0" * 24 + "10101101")] * 15, words=15) + self.chip["JTAG"].scan_dr([BitLogic("1"), BitLogic("0" * 24 + "10101101")] * 15, word_size=33) fifo_tap1_content = self.chip["fifo1"].get_data() fifo_tap2_content = self.chip["fifo2"].get_data() @@ -403,16 +433,46 @@ def jtag_tests(self): # [WORD1(dev1) WORD1(dev2) WORD2(dev1) WORD2(dev2) ...] data = np.byte( [ - 0x01, 0x02, 0x03, 0x04, - 0x02, 0x04, 0x06, 0x08, - 0x11, 0x12, 0x13, 0x14, - 0x12, 0x14, 0x16, 0x18, - 0x21, 0x22, 0x23, 0x24, - 0x22, 0x24, 0x26, 0x28, - 0x31, 0x32, 0x33, 0x34, - 0x32, 0x34, 0x36, 0x38, - 0x41, 0x42, 0x43, 0x44, - 0x42, 0x44, 0x46, 0x48, + 0x01, + 0x02, + 0x03, + 0x04, + 0x02, + 0x04, + 0x06, + 0x08, + 0x11, + 0x12, + 0x13, + 0x14, + 0x12, + 0x14, + 0x16, + 0x18, + 0x21, + 0x22, + 0x23, + 0x24, + 0x22, + 0x24, + 0x26, + 0x28, + 0x31, + 0x32, + 0x33, + 0x34, + 0x32, + 0x34, + 0x36, + 0x38, + 0x41, + 0x42, + 0x43, + 0x44, + 0x42, + 0x44, + 0x46, + 0x48, ] ) @@ -438,8 +498,20 @@ def jtag_tests(self): fifo_tap1_content = self.chip["fifo1"].get_data() fifo_tap2_content = self.chip["fifo2"].get_data() - expected_result_tap1 = [int("0x01020304", 16), int("0x11121314", 16), int("0x21222324", 16), int("0x31323334", 16), int("41424344", 16)] - expected_result_tap2 = [int("0x02040608", 16), int("0x12141618", 16), int("0x22242628", 16), int("0x32343638", 16), int("42444648", 16)] + expected_result_tap1 = [ + int("0x01020304", 16), + int("0x11121314", 16), + int("0x21222324", 16), + int("0x31323334", 16), + int("41424344", 16), + ] + expected_result_tap2 = [ + int("0x02040608", 16), + int("0x12141618", 16), + int("0x22242628", 16), + int("0x32343638", 16), + int("42444648", 16), + ] self.assertListEqual(expected_result_tap1, list(fifo_tap1_content)) self.assertListEqual(expected_result_tap2, list(fifo_tap2_content)) diff --git a/tests/test_SimJtagMaster.v b/tests/test_SimJtagMaster.v index d0398a557..4283560f3 100644 --- a/tests/test_SimJtagMaster.v +++ b/tests/test_SimJtagMaster.v @@ -11,8 +11,8 @@ `include "gpio/gpio_core.v" `include "gpio/gpio.v" - `include "spi/blk_mem_gen_8_to_1_2k.v" +`include "utils/ramb_8_to_n.v" `include "jtag_master/jtag_master.v" `include "jtag_master/jtag_master_core.v"