From 45e3552951a246505c2c5cd1f1bf646c4f15fd91 Mon Sep 17 00:00:00 2001 From: Tomasz Hemperek Date: Mon, 14 Jun 2021 16:13:54 +0200 Subject: [PATCH] Update and improve seq_rec and seq_gen modules --- basil/HL/seq_gen.py | 20 +- basil/HL/seq_rec.py | 19 +- basil/firmware/modules/seq_gen/README.rst | 22 ++- basil/firmware/modules/seq_gen/seq_gen.v | 2 +- .../modules/seq_gen/seq_gen_blk_mem_16x8196.v | 162 --------------- .../modules/seq_gen/seq_gen_blk_mem_4x4096.v | 46 ----- basil/firmware/modules/seq_gen/seq_gen_core.v | 185 ++++++++---------- basil/firmware/modules/seq_rec/seq_rec.v | 4 +- basil/firmware/modules/seq_rec/seq_rec_core.v | 126 ++++-------- basil/firmware/modules/utils/ramb_8_to_n.v | 11 +- .../mio_pixel/tests/test_Sim_mio_pixel.py | 1 + tests/test_SimAdcRx.py | 3 +- tests/test_SimAdcRx.v | 3 +- tests/test_SimCmdSeq.py | 3 +- tests/test_SimCmdSeq.v | 1 + tests/test_SimFifo8to32.v | 6 +- tests/test_SimM26.v | 1 + tests/test_SimSeq.py | 108 +++++++++- tests/test_SimSeq.v | 30 ++- tests/test_SimTdc.py | 1 - tests/test_SimTdc.v | 3 +- 21 files changed, 304 insertions(+), 453 deletions(-) delete mode 100644 basil/firmware/modules/seq_gen/seq_gen_blk_mem_16x8196.v delete mode 100644 basil/firmware/modules/seq_gen/seq_gen_blk_mem_4x4096.v diff --git a/basil/HL/seq_gen.py b/basil/HL/seq_gen.py index f39f92cf6..33e6025f8 100644 --- a/basil/HL/seq_gen.py +++ b/basil/HL/seq_gen.py @@ -18,20 +18,20 @@ class seq_gen(RegisterHardwareLayer): 'START': {'descr': {'addr': 1, 'size': 8, 'properties': ['writeonly']}}, 'EN_EXT_START': {'descr': {'addr': 2, 'size': 1}}, 'CLK_DIV': {'descr': {'addr': 3, 'size': 8}}, - 'SIZE': {'descr': {'addr': 4, 'size': 16}}, - 'WAIT': {'descr': {'addr': 6, 'size': 16}}, - 'REPEAT': {'descr': {'addr': 8, 'size': 16}}, - 'REPEAT_START': {'descr': {'addr': 10, 'size': 16}}, - 'NESTED_START': {'descr': {'addr': 12, 'size': 16}}, - 'NESTED_STOP': {'descr': {'addr': 14, 'size': 16}}, - 'NESTED_REPEAT': {'descr': {'addr': 16, 'size': 16}}, - 'MEM_BYTES': {'descr': {'addr': 18, 'size': 16, 'properties': ['ro']}}, + 'SIZE': {'descr': {'addr': 4, 'size': 32}}, + 'WAIT': {'descr': {'addr': 8, 'size': 32}}, + 'REPEAT': {'descr': {'addr': 12, 'size': 32}}, + 'REPEAT_START': {'descr': {'addr': 16, 'size': 32}}, + 'NESTED_START': {'descr': {'addr': 20, 'size': 32}}, + 'NESTED_STOP': {'descr': {'addr': 24, 'size': 32}}, + 'NESTED_REPEAT': {'descr': {'addr': 28, 'size': 32}}, + 'MEM_BYTES': {'descr': {'addr': 32, 'size': 32, 'properties': ['ro']}}, } - _require_version = "==2" + _require_version = "==3" def __init__(self, intf, conf): super(seq_gen, self).__init__(intf, conf) - self._seq_mem_offset = 32 # in bytes + self._seq_mem_offset = 64 # in bytes def init(self): super(seq_gen, self).init() diff --git a/basil/HL/seq_rec.py b/basil/HL/seq_rec.py index 381bc683c..c990e0802 100644 --- a/basil/HL/seq_rec.py +++ b/basil/HL/seq_rec.py @@ -17,16 +17,18 @@ class seq_rec(RegisterHardwareLayer): 'READY': {'descr': {'addr': 1, 'size': 1, 'properties': ['ro']}}, 'START': {'descr': {'addr': 1, 'size': 8, 'properties': ['writeonly']}}, 'EN_EXT_START': {'descr': {'addr': 2, 'size': 8}}, - 'SIZE': {'descr': {'addr': 3, 'size': 16}}} - _require_version = "==0" + 'SIZE': {'descr': {'addr': 4, 'size': 32}}, + 'MEM_BYTES': {'descr': {'addr': 8, 'size': 32, 'properties': ['ro']}}, + } + _require_version = "==1" def __init__(self, intf, conf): super(seq_rec, self).__init__(intf, conf) self._seq_mem_offset = 16 # in bytes - try: - self._seq_mem_size = conf['mem_size'] # in bytes - except KeyError: - self._seq_mem_size = 2 * 1024 # default is 2048 bytes, user should be aware of address ranges in FPGA + + def init(self): + super(seq_rec, self).init() + self._seq_mem_size = self.get_mem_size() def reset(self): self.RESET = 0 @@ -49,6 +51,9 @@ def set_en_ext_start(self, value): def get_en_ext_start(self): return self.EN_EXT_START + def get_mem_size(self): + return self.MEM_BYTES + def is_done(self): return self.is_ready @@ -61,7 +66,7 @@ def get_done(self): def get_data(self, size=None, addr=0): if size and self._seq_mem_size < size: - raise ValueError('Size is too big') + raise ValueError('Size is too big memory=%d requested_size=%d' % (self._seq_mem_size, size)) if not size: return self._intf.read(self._conf['base_addr'] + self._seq_mem_offset + addr, self._seq_mem_size) else: diff --git a/basil/firmware/modules/seq_gen/README.rst b/basil/firmware/modules/seq_gen/README.rst index a19914ba5..4f42971b4 100644 --- a/basil/firmware/modules/seq_gen/README.rst +++ b/basil/firmware/modules/seq_gen/README.rst @@ -14,9 +14,9 @@ Parameters +--------------+---------------------+-------------------------------------------------------------------------+ | Name | Default | Description | +==============+=====================+=========================================================================+ - | MEM_BYTES | 2 | Amount of memory allocated for data (in bytes) | + | MEM_BYTES | 16384 | Amount of memory allocated for data (in bytes) | +--------------+---------------------+-------------------------------------------------------------------------+ - | OUT_BITS | 2 | Size (bit) for output pattern - word size | + | OUT_BITS | 8 | Size (bit) for output pattern - word size | +--------------+---------------------+-------------------------------------------------------------------------+ Pins @@ -42,20 +42,22 @@ Registers +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ | CLK_DIV | 3 | [7:0] | r/w | 1 | internal division factor for SEQ_CLK | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | COUNT | 6 - 5 | [15:0] | r/w | MEM_BYTES | set the size of sequence (in words) | + | COUNT | 7 - 4 | [31:0] | r/w | out_words | set the size of sequence (in output words) | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | WAIT | 7 - 6 | [15:0] | r/w | 0 | waits after every sequnce if REPEAT != 0 repeat transfer count (0 -> forever) | + | WAIT | 11 - 8 | [31:0] | r/w | 0 | waits after every sequnce if REPEAT != 0 repeat transfer count (0 -> forever) | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | REPEAT | 9 - 8 | [15:0] | r/w | 0 | repeat sequence count (0 -> forever) | + | REPEAT | 15 - 12 | [31:0] | r/w | 1 | repeat sequence count (0 -> forever) | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | REP_START | 11 - 10 | [15:0] | r/w | 0 | position from witch pattern will start in repeat mode (a first sequence always start at 0) | + | REP_START | 19 - 16 | [31:0] | r/w | 0 | position from witch pattern will start in repeat mode (a first sequence always start at 0) | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | NESTED_START | 13 - 12 | [15:0] | r/w | 0 | position from witch pattern will start for nested loop | + | NESTED_START | 23 - 20 | [31:0] | r/w | 0 | position from witch pattern will start for nested loop | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | NESTED_STOP | 15 - 14 | [15:0] | r/w | 0 | position to witch pattern will stop for nested loop | + | NESTED_STOP | 27 - 24 | [31:0] | r/w | 0 | position to witch pattern will stop for nested loop | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | NESTED_REPEAT | 17 - 16 | [15:0] | r/w | 0 | repeat count for nested loop | + | NESTED_REPEAT | 31 - 28 | [31:0] | r/w | 0 | repeat count for nested loop | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ - | DATA | 32 to 32+MEM_BYTES-1 | | r/w | unknown | memory for pattern | + | MEM_BYTES | 35 - 32 | [31:0] | r/w | MEM_BYTE | memory size | + +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ + | DATA | 64 to 64+MEM_BYTES-1 | | r/w | unknown | memory for pattern | +---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+ diff --git a/basil/firmware/modules/seq_gen/seq_gen.v b/basil/firmware/modules/seq_gen/seq_gen.v index c33ddc873..a6a51d353 100644 --- a/basil/firmware/modules/seq_gen/seq_gen.v +++ b/basil/firmware/modules/seq_gen/seq_gen.v @@ -13,7 +13,7 @@ module seq_gen #( parameter ABUSWIDTH = 16, parameter MEM_BYTES = 16384, - parameter OUT_BITS = 16 + parameter OUT_BITS = 8 ) ( input wire BUS_CLK, input wire BUS_RST, diff --git a/basil/firmware/modules/seq_gen/seq_gen_blk_mem_16x8196.v b/basil/firmware/modules/seq_gen/seq_gen_blk_mem_16x8196.v deleted file mode 100644 index b89ded3f1..000000000 --- a/basil/firmware/modules/seq_gen/seq_gen_blk_mem_16x8196.v +++ /dev/null @@ -1,162 +0,0 @@ -/** - * ------------------------------------------------------------ - * Copyright (c) All rights reserved - * SiLab, Institute of Physics, University of Bonn - * ------------------------------------------------------------ - */ -`timescale 1ps/1ps -`default_nettype none - -module seq_gen_blk_mem ( - clka, clkb, wea, addra, dina, web, addrb, dinb, douta, doutb -); - -input wire clka; -input wire clkb; -input wire [0 : 0] wea; -input wire [13 : 0] addra; -input wire [7 : 0] dina; -input wire [0 : 0] web; -input wire [12 : 0] addrb; -input wire [15 : 0] dinb; -output wire [7 : 0] douta; -output wire [15 : 0] doutb; - -RAMB16_S1_S2 mem0 ( - .CLKA(clka), - .CLKB(clkb), - .ENB(1'b1), - .SSRB(1'b0), - .WEA(wea[0]), - .WEB(web[0]), - .ENA(1'b1), - .SSRA(1'b0), - .ADDRA(addra[13:0]), - .ADDRB(addrb[12:0]), - .DIA({dina[7]}), - .DIB({dinb[15], dinb[7]}), - .DOA({douta[7]}), - .DOB({doutb[15], doutb[7]}) -); - -RAMB16_S1_S2 mem1 ( - .CLKA(clka), - .CLKB(clkb), - .ENB(1'b1), - .SSRB(1'b0), - .WEA(wea[0]), - .WEB(web[0]), - .ENA(1'b1), - .SSRA(1'b0), - .ADDRA(addra[13:0]), - .ADDRB(addrb[12:0]), - .DIA({dina[6]}), - .DIB({dinb[14], dinb[6]}), - .DOA({douta[6]}), - .DOB({doutb[14], doutb[6]}) -); - -RAMB16_S1_S2 mem2 ( - .CLKA(clka), - .CLKB(clkb), - .ENB(1'b1), - .SSRB(1'b0), - .WEA(wea[0]), - .WEB(web[0]), - .ENA(1'b1), - .SSRA(1'b0), - .ADDRA(addra[13:0]), - .ADDRB(addrb[12:0]), - .DIA({dina[5]}), - .DIB({dinb[13], dinb[5]}), - .DOA({douta[5]}), - .DOB({doutb[13], doutb[5]}) -); - -RAMB16_S1_S2 mem3 ( - .CLKA(clka), - .CLKB(clkb), - .ENB(1'b1), - .SSRB(1'b0), - .WEA(wea[0]), - .WEB(web[0]), - .ENA(1'b1), - .SSRA(1'b0), - .ADDRA(addra[13:0]), - .ADDRB(addrb[12:0]), - .DIA({dina[4]}), - .DIB({dinb[12], dinb[4]}), - .DOA({douta[4]}), - .DOB({doutb[12], doutb[4]}) -); - -RAMB16_S1_S2 mem4 ( - .CLKA(clka), - .CLKB(clkb), - .ENB(1'b1), - .SSRB(1'b0), - .WEA(wea[0]), - .WEB(web[0]), - .ENA(1'b1), - .SSRA(1'b0), - .ADDRA(addra[13:0]), - .ADDRB(addrb[12:0]), - .DIA({dina[3]}), - .DIB({dinb[11], dinb[3]}), - .DOA({douta[3]}), - .DOB({doutb[11], doutb[3]}) -); - -RAMB16_S1_S2 mem5 ( - .CLKA(clka), - .CLKB(clkb), - .ENB(1'b1), - .SSRB(1'b0), - .WEA(wea[0]), - .WEB(web[0]), - .ENA(1'b1), - .SSRA(1'b0), - .ADDRA(addra[13:0]), - .ADDRB(addrb[12:0]), - .DIA({dina[2]}), - .DIB({dinb[10], dinb[2]}), - .DOA({douta[2]}), - .DOB({doutb[10], doutb[2]}) -); - -RAMB16_S1_S2 mem6 ( - .CLKA(clka), - .CLKB(clkb), - .ENB(1'b1), - .SSRB(1'b0), - .WEA(wea[0]), - .WEB(web[0]), - .ENA(1'b1), - .SSRA(1'b0), - .ADDRA(addra[13:0]), - .ADDRB(addrb[12:0]), - .DIA({dina[1]}), - .DIB({dinb[9], dinb[1]}), - .DOA({douta[1]}), - .DOB({doutb[9], doutb[1]}) -); - -RAMB16_S1_S2 mem7 ( - .CLKA(clka), - .CLKB(clkb), - .ENB(1'b1), - .SSRB(1'b0), - .WEA(wea[0]), - .WEB(web[0]), - .ENA(1'b1), - .SSRA(1'b0), - .ADDRA(addra[13:0]), - .ADDRB(addrb[12:0]), - .DIA({dina[0]}), - .DIB({dinb[8], dinb[0]}), - .DOA({douta[0]}), - .DOB({doutb[8], doutb[0]}) -); - -endmodule - diff --git a/basil/firmware/modules/seq_gen/seq_gen_blk_mem_4x4096.v b/basil/firmware/modules/seq_gen/seq_gen_blk_mem_4x4096.v deleted file mode 100644 index c949b24e2..000000000 --- a/basil/firmware/modules/seq_gen/seq_gen_blk_mem_4x4096.v +++ /dev/null @@ -1,46 +0,0 @@ -/** - * ------------------------------------------------------------ - * Copyright (c) All rights reserved - * SiLab, Institute of Physics, University of Bonn - * ------------------------------------------------------------ - */ -`timescale 1ps/1ps -`default_nettype none - -module seq_gen_blk_mem ( - clka, clkb, wea, addra, dina, web, addrb, dinb, douta, doutb -); - -input clka; -input clkb; -input [0 : 0] wea; -input [10 : 0] addra; -input [7 : 0] dina; -input [0 : 0] web; -input [11 : 0] addrb; -input [3 : 0] dinb; -output [7 : 0] douta; -output [3 : 0] doutb; - - -RAMB16_S4_S9 mem ( - .CLKA(clkb), - .CLKB(clka), - .ENB(1'b1), - .WEA(web[0]), - .WEB(wea[0]), - .ENA(1'b1), - .SSRA(1'b0), - .SSRB(1'b0), - .DIPB({1'b0}), - .ADDRA(addrb[11:0]), - .ADDRB(addra[10:0]), - .DIA(dinb[3:0]), - .DIB(dina[7:0]), - .DOA(doutb[3:0]), - .DOB(douta[7:0]), - .DOPB() -); - -endmodule - diff --git a/basil/firmware/modules/seq_gen/seq_gen_core.v b/basil/firmware/modules/seq_gen/seq_gen_core.v index 69ab42e88..3d39836fe 100644 --- a/basil/firmware/modules/seq_gen/seq_gen_core.v +++ b/basil/firmware/modules/seq_gen/seq_gen_core.v @@ -10,7 +10,7 @@ module seq_gen_core #( parameter ABUSWIDTH = 16, parameter MEM_BYTES = 16384, - parameter OUT_BITS = 16 //4,8,16,32 + parameter OUT_BITS = 8 ) ( BUS_CLK, BUS_RST, @@ -25,7 +25,8 @@ module seq_gen_core #( SEQ_OUT ); -localparam VERSION = 2; +localparam VERSION = 3; +localparam MEM_OFFSET = 64; input wire BUS_CLK; input wire BUS_RST; @@ -39,10 +40,9 @@ input wire SEQ_EXT_START; input wire SEQ_CLK; output reg [OUT_BITS-1:0] SEQ_OUT; -`include "../includes/log2func.v" - -localparam ADDR_SIZEA = `CLOG2(MEM_BYTES); -localparam ADDR_SIZEB = (OUT_BITS > 8) ? `CLOG2(MEM_BYTES/(OUT_BITS/8)) : `CLOG2(MEM_BYTES*(8/OUT_BITS)); +localparam DEF_BIT_OUT = (OUT_BITS > 8) ? (MEM_BYTES/(OUT_BITS/8)) : (MEM_BYTES*(8/OUT_BITS)); +localparam ADDR_SIZEA = $clog2(MEM_BYTES); +localparam ADDR_SIZEB = $clog2(DEF_BIT_OUT); reg [7:0] status_regs [31:0]; @@ -51,38 +51,54 @@ wire SOFT_RST; assign RST = BUS_RST || SOFT_RST; -localparam DEF_BIT_OUT = MEM_BYTES; - always @(posedge BUS_CLK) begin if(RST) begin status_regs[0] <= 0; status_regs[1] <= 0; status_regs[2] <= 0; - status_regs[3] <= 1; + status_regs[3] <= 1; // CONF_CLK_DIV + + status_regs[4] <= DEF_BIT_OUT[7:0]; // bits + status_regs[5] <= DEF_BIT_OUT[15:8]; // -||- + status_regs[6] <= DEF_BIT_OUT[23:16]; // -||- + status_regs[7] <= DEF_BIT_OUT[31:24]; // -||- - status_regs[4] <= DEF_BIT_OUT[7:0]; //bits - status_regs[5] <= DEF_BIT_OUT[15:8]; //bits + status_regs[8] <= 0; // wait + status_regs[9] <= 0; // -||- + status_regs[10] <= 0; // -||- + status_regs[11] <= 0; // -||- - status_regs[6] <= 0; //wait - status_regs[7] <= 0; //wait - status_regs[8] <= 0; // 7 repeat - status_regs[9] <= 0; // 7 repeat - status_regs[10] <= 0; //repeat start - status_regs[11] <= 0; //repeat start - status_regs[12] <= 0; // nested loop start + status_regs[12] <= 1; // repeat status_regs[13] <= 0; // -||- - status_regs[14] <= 0; // nested loop stop + status_regs[14] <= 0; // -||- status_regs[15] <= 0; // -||- - status_regs[16] <= 0; // nested loop repat count + + status_regs[16] <= 0; //repeat start status_regs[17] <= 0; // -||- + status_regs[18] <= 0; // -||- + status_regs[19] <= 0; // -||- + + status_regs[20] <= 0; // nested loop start + status_regs[21] <= 0; // -||- + status_regs[22] <= 0; // -||- + status_regs[23] <= 0; // -||- + + status_regs[24] <= 0; // nested loop stop + status_regs[25] <= 0; // -||- + status_regs[26] <= 0; // -||- + status_regs[27] <= 0; // -||- + + status_regs[28] <= 0; // nested loop repat count + status_regs[29] <= 0; // -||- + status_regs[30] <= 0; // -||- + status_regs[31] <= 0; // -||- end - else if(BUS_WR && BUS_ADD < 32) + else if(BUS_WR && BUS_ADD < MEM_OFFSET) status_regs[BUS_ADD[4:0]] <= BUS_DATA_IN; end -reg [7:0] BUS_IN_MEM; -reg [7:0] BUS_OUT_MEM; +wire [7:0] BUS_IN_MEM; // 1 - finished @@ -97,26 +113,26 @@ wire [7:0] CONF_CLK_DIV; assign CONF_CLK_DIV = status_regs[3] - 1; reg CONF_DONE; -wire [15:0] CONF_COUNT; -assign CONF_COUNT = {status_regs[5], status_regs[4]}; +wire [31:0] CONF_COUNT; +assign CONF_COUNT = {status_regs[7], status_regs[6], status_regs[5], status_regs[4]}; -wire [15:0] CONF_WAIT; -assign CONF_WAIT = {status_regs[7], status_regs[6]}; +wire [31:0] CONF_WAIT; +assign CONF_WAIT = {status_regs[11], status_regs[10], status_regs[9], status_regs[8]}; -wire [15:0] CONF_REPEAT; -assign CONF_REPEAT = {status_regs[9], status_regs[8]}; +wire [31:0] CONF_REPEAT; +assign CONF_REPEAT = {status_regs[15], status_regs[14], status_regs[13], status_regs[12]}; -wire [15:0] CONF_REP_START; -assign CONF_REP_START = {status_regs[11], status_regs[10]}; +wire [31:0] CONF_REP_START; +assign CONF_REP_START = {status_regs[19], status_regs[18], status_regs[17], status_regs[16]}; -wire [15:0] CONF_NESTED_START; -assign CONF_NESTED_START = {status_regs[13], status_regs[12]}; +wire [31:0] CONF_NESTED_START; +assign CONF_NESTED_START = {status_regs[23], status_regs[22], status_regs[21], status_regs[20]}; -wire [15:0] CONF_NESTED_STOP; -assign CONF_NESTED_STOP = {status_regs[15], status_regs[14]}; +wire [31:0] CONF_NESTED_STOP; +assign CONF_NESTED_STOP = {status_regs[27], status_regs[26], status_regs[25], status_regs[24]}; -wire [15:0] CONF_NESTED_REPEAT; -assign CONF_NESTED_REPEAT = {status_regs[17], status_regs[16]}; +wire [31:0] CONF_NESTED_REPEAT; +assign CONF_NESTED_REPEAT = {status_regs[31], status_regs[30], status_regs[29], status_regs[28]}; wire [7:0] BUS_STATUS_OUT; assign BUS_STATUS_OUT = status_regs[BUS_ADD[4:0]]; @@ -128,11 +144,15 @@ always @(posedge BUS_CLK) begin BUS_DATA_OUT_REG <= VERSION; else if(BUS_ADD == 1) BUS_DATA_OUT_REG <= {7'b0, CONF_DONE}; - else if(BUS_ADD == 18) - BUS_DATA_OUT_REG <= DEF_BIT_OUT[7:0]; - else if(BUS_ADD == 19) - BUS_DATA_OUT_REG <= DEF_BIT_OUT[15:8]; - else if(BUS_ADD < 32) + else if(BUS_ADD == 32) + BUS_DATA_OUT_REG <= MEM_BYTES[7:0]; + else if(BUS_ADD == 33) + BUS_DATA_OUT_REG <= MEM_BYTES[15:8]; + else if(BUS_ADD == 34) + BUS_DATA_OUT_REG <= MEM_BYTES[23:16]; + else if(BUS_ADD == 35) + BUS_DATA_OUT_REG <= MEM_BYTES[31:24]; + else if(BUS_ADD < MEM_OFFSET) BUS_DATA_OUT_REG <= BUS_STATUS_OUT; end end @@ -147,15 +167,15 @@ always @(posedge BUS_CLK) begin end always @(*) begin - if(PREV_BUS_ADD < 32) + if(PREV_BUS_ADD < MEM_OFFSET) BUS_DATA_OUT = BUS_DATA_OUT_REG; - else if(PREV_BUS_ADD < 32 + MEM_BYTES ) + else if(PREV_BUS_ADD < MEM_OFFSET + MEM_BYTES ) BUS_DATA_OUT = BUS_IN_MEM; else BUS_DATA_OUT = 8'hxx; end -reg [15:0] out_bit_cnt; +reg [31:0] out_bit_cnt; wire [ADDR_SIZEB-1:0] memout_addrb; //assign memout_addrb = out_bit_cnt-1; @@ -163,59 +183,27 @@ assign memout_addrb = out_bit_cnt < CONF_COUNT ? out_bit_cnt-1 : CONF_COUNT-1; / wire [ADDR_SIZEA-1:0] memout_addra; wire [ABUSWIDTH-1:0] BUS_ADD_MEM; -assign BUS_ADD_MEM = BUS_ADD - 32; +assign BUS_ADD_MEM = BUS_ADD - MEM_OFFSET; -generate - if (OUT_BITS<=8) begin - assign memout_addra = BUS_ADD_MEM; - end else begin - assign memout_addra = {BUS_ADD_MEM[ABUSWIDTH-1:OUT_BITS/8-1], {(OUT_BITS/8-1){1'b0}}} + (OUT_BITS/8-1) - (BUS_ADD_MEM % (OUT_BITS/8)); //Byte order - end -endgenerate +assign memout_addra = BUS_ADD_MEM; -reg [OUT_BITS-1:0] SEQ_OUT_MEM; +wire [OUT_BITS-1:0] SEQ_OUT_MEM; wire WEA; -assign WEA = BUS_WR && BUS_ADD >=32 && BUS_ADD < 32+MEM_BYTES; - -generate - if (OUT_BITS==8) begin - reg [7:0] mem [(2**ADDR_SIZEA)-1:0]; - - // synthesis translate_off - //to make simulator happy (no X propagation) - integer i; - initial begin - for(i = 0; i<(2**ADDR_SIZEA); i = i + 1) - mem[i] = 0; - end - // synthesis translate_on - - always @(posedge BUS_CLK) begin - if (WEA) - mem[memout_addra] <= BUS_DATA_IN; - BUS_IN_MEM <= mem[memout_addra]; - end - - always @(posedge SEQ_CLK) - SEQ_OUT_MEM <= mem[memout_addrb]; - - end else begin - wire [7:0] douta; - wire [OUT_BITS-1:0] doutb; - seq_gen_blk_mem memout( - .clka(BUS_CLK), .clkb(SEQ_CLK), .douta(douta), .doutb(doutb), - .wea(WEA), .web(1'b0), .addra(memout_addra), .addrb(memout_addrb), - .dina(BUS_DATA_IN), .dinb({OUT_BITS{1'b0}}) - ); - - always @(*) begin - BUS_IN_MEM = douta; - SEQ_OUT_MEM = doutb; - end - end -endgenerate - +assign WEA = BUS_WR && BUS_ADD >=MEM_OFFSET && BUS_ADD < MEM_OFFSET+MEM_BYTES; + +ramb_8_to_n #(.SIZE(MEM_BYTES), .WIDTH(OUT_BITS)) mem ( + .clkA(BUS_CLK), + .clkB(SEQ_CLK), + .weA(WEA), + .weB(1'b0), + .addrA(memout_addra), + .addrB(memout_addrb), + .diA(BUS_DATA_IN), + .doA(BUS_IN_MEM), + .diB({OUT_BITS{1'b0}}), + .doB(SEQ_OUT_MEM) +); wire RST_SYNC; wire RST_SOFT_SYNC; @@ -231,14 +219,13 @@ wire START_SYNC_PRE; assign START_SYNC_PRE = (START_SYNC_CDC | (SEQ_EXT_START & CONF_EN_EXT_START)); assign START_SYNC = START_SYNC_PRE & DONE; //no START if previous not finished -wire [15:0] STOP_BIT; +wire [31:0] STOP_BIT; assign STOP_BIT = CONF_COUNT + CONF_WAIT; -reg [15:0] REPEAT_COUNT; -reg [15:0] REPEAT_NESTED_COUNT; +reg [31:0] REPEAT_COUNT; +reg [31:0] REPEAT_NESTED_COUNT; reg [7:0] dev_cnt; - wire REP_START; assign REP_START = (out_bit_cnt == STOP_BIT && dev_cnt == CONF_CLK_DIV && (CONF_REPEAT==0 || REPEAT_COUNT < CONF_REPEAT)); @@ -286,7 +273,7 @@ always @(posedge SEQ_CLK) DONE <= 1; else if(START_SYNC_PRE) DONE <= 0; - else if(REPEAT_COUNT > CONF_REPEAT) + else if(REPEAT_COUNT > CONF_REPEAT & out_bit_cnt == STOP_BIT && dev_cnt == CONF_CLK_DIV) DONE <= 1; always @(posedge SEQ_CLK) diff --git a/basil/firmware/modules/seq_rec/seq_rec.v b/basil/firmware/modules/seq_rec/seq_rec.v index 11fadc4b5..6a81e5625 100644 --- a/basil/firmware/modules/seq_rec/seq_rec.v +++ b/basil/firmware/modules/seq_rec/seq_rec.v @@ -35,7 +35,7 @@ bus_to_ip #( .BASEADDR(BASEADDR), .HIGHADDR(HIGHADDR), .ABUSWIDTH(ABUSWIDTH) -) i_bus_to_ip ( +) bus_to_ip ( .BUS_RD(BUS_RD), .BUS_WR(BUS_WR), .BUS_ADD(BUS_ADD), @@ -52,7 +52,7 @@ seq_rec_core #( .ABUSWIDTH(ABUSWIDTH), .MEM_BYTES(MEM_BYTES), .IN_BITS(IN_BITS) -) i_scope_core ( +) seq_rec_core ( .BUS_CLK(BUS_CLK), .BUS_RST(BUS_RST), .BUS_ADD(IP_ADD), diff --git a/basil/firmware/modules/seq_rec/seq_rec_core.v b/basil/firmware/modules/seq_rec/seq_rec_core.v index 644c1d4d5..1facd724b 100644 --- a/basil/firmware/modules/seq_rec/seq_rec_core.v +++ b/basil/firmware/modules/seq_rec/seq_rec_core.v @@ -7,7 +7,6 @@ `timescale 1ps/1ps `default_nettype none -// WARNING! THIS MODULE IS WORK IN PROGRESS! NOT TESTED! /* * Possible extra options: * - delay block that allow SEQ_EXT_START in past (enabled by parameter - for speed needed applications a simple memory circular buffer) @@ -34,7 +33,7 @@ module seq_rec_core #( SEQ_EXT_START ); -localparam VERSION = 0; +localparam VERSION = 1; input wire BUS_CLK; input wire BUS_RST; @@ -48,40 +47,32 @@ input wire SEQ_CLK; input wire [IN_BITS-1:0] SEQ_IN; input wire SEQ_EXT_START; -generate -if (MEM_BYTES > 2048*8*4) begin - illegal_outputs_parameter non_existing_module(); -end -endgenerate - -`include "../includes/log2func.v" - -localparam ADDR_SIZEA = `CLOG2(MEM_BYTES); -localparam ADDR_SIZEB = (IN_BITS > 8) ? `CLOG2(MEM_BYTES/(IN_BITS/8)) : `CLOG2(MEM_BYTES*(8/IN_BITS)); +localparam DEF_BIT_OUT = (IN_BITS > 8) ? (MEM_BYTES/(IN_BITS/8)) : (MEM_BYTES*(8/IN_BITS)); +localparam ADDR_SIZEA = $clog2(MEM_BYTES); +localparam ADDR_SIZEB = $clog2(DEF_BIT_OUT); -reg [7:0] status_regs [4:0]; +reg [7:0] status_regs [7:0]; wire RST; wire SOFT_RST; assign RST = BUS_RST || SOFT_RST; -localparam DEF_BIT_OUT = MEM_BYTES; - always @(posedge BUS_CLK) begin if (RST) begin status_regs[0] <= 0; status_regs[1] <= 0; status_regs[2] <= 0; - status_regs[3] <= DEF_BIT_OUT[7:0]; //bits - status_regs[4] <= DEF_BIT_OUT[15:8]; //bits - end else if (BUS_WR && BUS_ADD < 5) begin + status_regs[4] <= DEF_BIT_OUT[7:0]; // bits + status_regs[5] <= DEF_BIT_OUT[15:8]; // -||- + status_regs[6] <= DEF_BIT_OUT[23:16]; // -||- + status_regs[7] <= DEF_BIT_OUT[31:24]; // -||- + end else if (BUS_WR && BUS_ADD < 8) begin status_regs[BUS_ADD[3:0]] <= BUS_DATA_IN; end end -reg [7:0] BUS_IN_MEM; -reg [7:0] BUS_OUT_MEM; +wire [7:0] BUS_IN_MEM; // 1 - finished @@ -89,8 +80,8 @@ wire CONF_START; assign SOFT_RST = (BUS_ADD==0 && BUS_WR); assign CONF_START = (BUS_ADD==1 && BUS_WR); -wire [15:0] CONF_COUNT; -assign CONF_COUNT = {status_regs[4], status_regs[3]}; +wire [31:0] CONF_COUNT; +assign CONF_COUNT = {status_regs[7], status_regs[6], status_regs[5], status_regs[4]}; wire CONF_EN_EXT_START; assign CONF_EN_EXT_START = status_regs[2][0]; @@ -110,10 +101,16 @@ always @(posedge BUS_CLK) begin BUS_DATA_OUT_REG <= {7'b0, CONF_READY}; else if (BUS_ADD == 2) BUS_DATA_OUT_REG <= {7'b0, CONF_EN_EXT_START}; - else if (BUS_ADD < 5) - BUS_DATA_OUT <= status_regs[BUS_ADD[3:0]]; + else if (BUS_ADD == 8) + BUS_DATA_OUT_REG <= MEM_BYTES[7:0]; + else if (BUS_ADD == 9) + BUS_DATA_OUT_REG <= MEM_BYTES[15:8]; + else if (BUS_ADD == 10) + BUS_DATA_OUT_REG <= MEM_BYTES[23:16]; + else if (BUS_ADD == 11) + BUS_DATA_OUT_REG <= MEM_BYTES[31:24]; else if (BUS_ADD < 16) - BUS_DATA_OUT <= 8'b0; + BUS_DATA_OUT_REG <= BUS_STATUS_OUT; end end @@ -141,7 +138,7 @@ always @(*) begin BUS_DATA_OUT = 8'b0; end -reg [16:0] out_bit_cnt; +reg [32:0] out_bit_cnt; wire [ADDR_SIZEB-1:0] memout_addrb; assign memout_addrb = out_bit_cnt - 1; @@ -150,67 +147,25 @@ wire [ADDR_SIZEA-1:0] memout_addra; wire [ABUSWIDTH-1:0] BUS_ADD_MEM; assign BUS_ADD_MEM = BUS_ADD-16; -localparam IN_BYTES = IN_BITS/8; -localparam IN_BYTES_WIDTH = `CLOG2(IN_BYTES); - -generate - if (IN_BITS<=8) begin - assign memout_addra = BUS_ADD_MEM; - end else begin - assign memout_addra = {BUS_ADD_MEM[ADDR_SIZEA:IN_BYTES_WIDTH], {(IN_BYTES_WIDTH){1'b0}}} + (IN_BYTES-1) - BUS_ADD_MEM[IN_BYTES_WIDTH-1:0]; //Byte order - end -endgenerate +assign memout_addra = BUS_ADD_MEM; reg [IN_BITS-1:0] SEQ_IN_MEM; wire WEA, WEB; assign WEA = BUS_WR && BUS_ADD >=16 && BUS_ADD < 16 + MEM_BYTES && !WEB; -generate - if (IN_BITS==8) begin - (* RAM_STYLE="{BLOCK}" *) - reg [7:0] mem [(2**ADDR_SIZEA)-1:0]; - - - // synthesis translate_off - //to make simulator happy (no X propagation) - integer i; - initial - for(i = 0; i < (2**ADDR_SIZEA); i = i + 1) - mem[i] = 0; - // synthesis translate_on - - always @(posedge BUS_CLK) begin - if (WEA) - mem[memout_addra] <= BUS_DATA_IN; - BUS_IN_MEM <= mem[memout_addra]; - end - - always @(posedge SEQ_CLK) - if (WEB) - mem[memout_addrb] <= SEQ_IN; - - end else begin - wire [7:0] douta; - - seq_rec_blk_mem memout ( - .clka(BUS_CLK), - .clkb(SEQ_CLK), - .douta(douta), - .doutb(), - .wea(WEA), - .web(WEB), - .addra(memout_addra), - .addrb(memout_addrb), - .dina(BUS_DATA_IN), - .dinb(SEQ_IN) - ); - always @(*) begin - BUS_IN_MEM = douta; - end - - end -endgenerate +ramb_8_to_n #(.SIZE(MEM_BYTES), .WIDTH(IN_BITS)) mem ( + .clkA(BUS_CLK), + .clkB(SEQ_CLK), + .weA(WEA), + .weB(WEB), + .addrA(memout_addra), + .addrB(memout_addrb), + .diA(BUS_DATA_IN), + .doA(BUS_IN_MEM), + .diB(SEQ_IN), + .doB() +); assign WEB = out_bit_cnt != 0; @@ -232,20 +187,21 @@ flag_domain_crossing conf_start_flag_domain_crossing ( .FLAG_OUT_CLK_B(CONF_START_FLAG_SYNC) ); -wire [15:0] CONF_COUNT_SYNC; +wire [31:0] CONF_COUNT_SYNC; three_stage_synchronizer #( - .WIDTH(16) + .WIDTH(32) ) three_stage_conf_count_synchronizer ( .CLK(SEQ_CLK), .IN(CONF_COUNT), .OUT(CONF_COUNT_SYNC) ); -wire [16:0] STOP_BIT; +wire [32:0] STOP_BIT; assign STOP_BIT = {1'b0, CONF_COUNT_SYNC}; wire START_REC; assign START_REC = CONF_START_FLAG_SYNC | (CONF_EN_EXT_START_SYNC & SEQ_EXT_START); +reg DONE; always @(posedge SEQ_CLK) if (RST_SYNC) out_bit_cnt <= 0; @@ -256,7 +212,6 @@ always @(posedge SEQ_CLK) else if (out_bit_cnt != 0) out_bit_cnt <= out_bit_cnt + 1; -reg DONE; always @(posedge SEQ_CLK) if (RST_SYNC) DONE <= 1'b1; @@ -290,5 +245,4 @@ always @(posedge BUS_CLK) else if (DONE_FLAG_BUS_CLK) CONF_READY <= 1'b1; - endmodule diff --git a/basil/firmware/modules/utils/ramb_8_to_n.v b/basil/firmware/modules/utils/ramb_8_to_n.v index 4fd4efa6f..27e75487b 100644 --- a/basil/firmware/modules/utils/ramb_8_to_n.v +++ b/basil/firmware/modules/utils/ramb_8_to_n.v @@ -48,12 +48,13 @@ localparam log2RATIO = $clog2(RATIO); reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; -genvar w; -generate - for (w=0; w < SIZEA; w=w + 1) begin - initial RAM[w] = 0; +// For simualtion init with 0 +initial begin : INIT_MEM + integer w; + for (w=0; w < maxSIZE; w=w + 1) begin + RAM[w] = 0; end -endgenerate +end generate if (WIDTH == 8) begin diff --git a/examples/mio_pixel/tests/test_Sim_mio_pixel.py b/examples/mio_pixel/tests/test_Sim_mio_pixel.py index 5b16f32ff..d099711ef 100644 --- a/examples/mio_pixel/tests/test_Sim_mio_pixel.py +++ b/examples/mio_pixel/tests/test_Sim_mio_pixel.py @@ -44,6 +44,7 @@ def setUp(self): os.path.join(fw_path, 'fast_spi_rx/fast_spi_rx_core.v'), os.path.join(fw_path, 'seq_gen/seq_gen.v'), os.path.join(fw_path, 'seq_gen/seq_gen_core.v'), + os.path.join(fw_path, 'utils/ramb_8_to_n.v'), os.path.join(fw_path, 'tdc_s3/tdc_s3.v'), os.path.join(fw_path, 'tdc_s3/tdc_s3_core.v'), os.path.join(fw_path, 'sram_fifo/sram_fifo_core.v'), diff --git a/tests/test_SimAdcRx.py b/tests/test_SimAdcRx.py index d136d183a..21de46e6f 100644 --- a/tests/test_SimAdcRx.py +++ b/tests/test_SimAdcRx.py @@ -28,7 +28,6 @@ - name : SEQ_GEN type : seq_gen interface : INTF - mem_size : 8192 base_addr : 0x1000 - name : FADC @@ -61,7 +60,7 @@ def setUp(self): self.chip.init() def test_io(self): - pattern = [1, 0, 1, 1, 1, 2, 1, 3, 1, 4, 1, 5, 1, 6, 1, 7] + pattern = [0, 1, 1, 1, 2, 1, 3, 1, 4, 1, 5, 1, 6, 1, 7, 1] self.chip['SEQ_GEN'].set_data(pattern) self.chip['PULSE_GEN'].set_DELAY(1) diff --git a/tests/test_SimAdcRx.v b/tests/test_SimAdcRx.v index 6dee9a4ce..b7adc288d 100644 --- a/tests/test_SimAdcRx.v +++ b/tests/test_SimAdcRx.v @@ -15,8 +15,7 @@ `include "seq_gen/seq_gen.v" `include "seq_gen/seq_gen_core.v" -`include "utils/RAMB16_S1_S2_sim.v" -`include "seq_gen/seq_gen_blk_mem_16x8196.v" +`include "utils/ramb_8_to_n.v" `include "spi/spi.v" `include "spi/spi_core.v" diff --git a/tests/test_SimCmdSeq.py b/tests/test_SimCmdSeq.py index 17224c82d..aed171323 100644 --- a/tests/test_SimCmdSeq.py +++ b/tests/test_SimCmdSeq.py @@ -40,10 +40,9 @@ - name : SEQ_REC type : seq_rec interface : INTF - mem_size : {} base_addr : 0x2000 -""".format(max_rec_size) +""" class TestSimSeq(unittest.TestCase): diff --git a/tests/test_SimCmdSeq.v b/tests/test_SimCmdSeq.v index f9bf8d82f..f8b41eebe 100644 --- a/tests/test_SimCmdSeq.v +++ b/tests/test_SimCmdSeq.v @@ -17,6 +17,7 @@ `include "seq_rec/seq_rec.v" `include "seq_rec/seq_rec_core.v" +`include "utils/ramb_8_to_n.v" // `include "utils/glbl.v" `include "utils/ODDR_sim.v" diff --git a/tests/test_SimFifo8to32.v b/tests/test_SimFifo8to32.v index 015160450..15d4c508a 100644 --- a/tests/test_SimFifo8to32.v +++ b/tests/test_SimFifo8to32.v @@ -89,6 +89,9 @@ cdc_syncfifo_sbus #( .rinc(!fifo_full), .rclk(BUS_CLK), .rrst(BUS_RST) ); +wire FIFO_READ, FIFO_EMPTY; +wire [31:0] FIFO_DATA; + `ifndef BASIL_SBUS fifo_8_to_32 #( `else @@ -106,8 +109,7 @@ fifo_8_to_32_sbus #( .DATA_OUT(FIFO_DATA) ); -wire FIFO_READ, FIFO_EMPTY; -wire [31:0] FIFO_DATA; + `ifndef BASIL_SBUS bram_fifo #( diff --git a/tests/test_SimM26.v b/tests/test_SimM26.v index 2c141c1a9..e974321a1 100644 --- a/tests/test_SimM26.v +++ b/tests/test_SimM26.v @@ -11,6 +11,7 @@ `include "seq_gen/seq_gen.v" `include "seq_gen/seq_gen_core.v" +`include "utils/ramb_8_to_n.v" `include "m26_rx/m26_rx.v" `include "m26_rx/m26_rx_core.v" diff --git a/tests/test_SimSeq.py b/tests/test_SimSeq.py index b13bf84fa..ff7a186f3 100644 --- a/tests/test_SimSeq.py +++ b/tests/test_SimSeq.py @@ -11,6 +11,8 @@ from basil.dut import Dut from basil.utils.sim.utils import cocotb_compile_and_run, cocotb_compile_clean +# TODO: Add tests for size 1/2/4/16/32 + cnfg_yaml = """ transfer_layer: - name : INTF @@ -28,14 +30,12 @@ - name : SEQ_GEN type : seq_gen interface : INTF - mem_size : 8192 - base_addr : 0x1000 + base_addr : 0x10000000 - name : SEQ_REC type : seq_rec interface : INTF - mem_size : 8192 - base_addr : 0x3000 + base_addr : 0x20000000 registers: - name : SEQ @@ -71,7 +71,35 @@ def setUp(self): self.chip.init() def test_io(self): - self.assertEqual(self.chip['SEQ_GEN'].get_mem_size(), 8 * 1024) + MEM_KB = 1 + + self.assertEqual(self.chip['SEQ_GEN'].get_mem_size(), MEM_KB * 1024) + self.assertEqual(self.chip['SEQ_REC'].get_mem_size(), MEM_KB * 1024) + + mem_in = (list(range(256)) * 4) * MEM_KB + + self.chip["SEQ_GEN"].set_data(mem_in) + ret = self.chip['SEQ_GEN'].get_data() + self.assertEqual(ret.tolist(), mem_in) + + self.chip['SEQ_GEN'].set_EN_EXT_START(True) + self.chip['SEQ_REC'].set_EN_EXT_START(True) + + self.chip['PULSE_GEN'].set_DELAY(1) + self.chip['PULSE_GEN'].set_WIDTH(1) + self.chip['PULSE_GEN'].START + + while(not self.chip['SEQ_GEN'].is_ready): + pass + + # 2nd time + self.chip['PULSE_GEN'].START + + while(not self.chip['SEQ_GEN'].is_ready): + pass + + ret = self.chip['SEQ_REC'].get_data() + self.assertEqual(ret.tolist()[2:], mem_in[:-2]) self.chip['SEQ']['S0'][0] = 1 self.chip['SEQ']['S1'][1] = 1 @@ -111,7 +139,7 @@ def test_io(self): pass ret = self.chip['SEQ_REC'].get_data(size=rec_size) - self.assertEqual(ret.tolist(), [0x0] * 2 + pattern * 4 + [0x80] * 6) # 2 clk delay + pattern x4 + 6 x last pattern + self.assertEqual(ret.tolist()[2:], pattern * 4 + [0x80] * 6) # 2 clk delay + pattern x4 + 6 x last pattern # self.chip['SEQ'].set_REPEAT_START(12) @@ -196,5 +224,73 @@ def tearDown(self): cocotb_compile_clean() +class TestSimSeq4bit(unittest.TestCase): + def setUp(self): + cocotb_compile_and_run([os.path.join(os.path.dirname(__file__), 'test_SimSeq.v')], extra_defines=["BITS=4"]) + + self.chip = Dut(cnfg_yaml) + self.chip.init() + + def test_seq_4bit(self): + MEM_KB = 1 + + mem_in = (list(range(256)) * 4) * MEM_KB + + self.chip["SEQ_GEN"].set_data(mem_in) + ret = self.chip['SEQ_GEN'].get_data() + self.assertEqual(ret.tolist(), mem_in) + + self.chip['SEQ_GEN'].set_EN_EXT_START(True) + self.chip['SEQ_REC'].set_EN_EXT_START(True) + + self.chip['PULSE_GEN'].set_DELAY(1) + self.chip['PULSE_GEN'].set_WIDTH(1) + self.chip['PULSE_GEN'].START + + while(not self.chip['SEQ_GEN'].is_ready): + pass + + ret = self.chip['SEQ_REC'].get_data() + self.assertEqual(ret.tolist()[1:], mem_in[:-1]) + + def tearDown(self): + self.chip.close() # let it close connection and stop simulator + cocotb_compile_clean() + + +class TestSimSeq16bit(unittest.TestCase): + def setUp(self): + cocotb_compile_and_run([os.path.join(os.path.dirname(__file__), 'test_SimSeq.v')], extra_defines=["BITS=16"]) + + self.chip = Dut(cnfg_yaml) + self.chip.init() + + def test_seq_16bit(self): + MEM_KB = 1 + + mem_in = (list(range(256)) * 4) * MEM_KB + + self.chip["SEQ_GEN"].set_data(mem_in) + ret = self.chip['SEQ_GEN'].get_data() + self.assertEqual(ret.tolist(), mem_in) + + self.chip['SEQ_GEN'].set_EN_EXT_START(True) + self.chip['SEQ_REC'].set_EN_EXT_START(True) + + self.chip['PULSE_GEN'].set_DELAY(1) + self.chip['PULSE_GEN'].set_WIDTH(1) + self.chip['PULSE_GEN'].START + + while(not self.chip['SEQ_GEN'].is_ready): + pass + + ret = self.chip['SEQ_REC'].get_data() + self.assertEqual(ret.tolist()[4:], mem_in[:-4]) + + def tearDown(self): + self.chip.close() # let it close connection and stop simulator + cocotb_compile_clean() + + if __name__ == '__main__': unittest.main() diff --git a/tests/test_SimSeq.v b/tests/test_SimSeq.v index 8b493097c..e98c689f6 100644 --- a/tests/test_SimSeq.v +++ b/tests/test_SimSeq.v @@ -21,6 +21,7 @@ `include "utils/3_stage_synchronizer.v" `include "utils/flag_domain_crossing.v" `include "utils/cdc_pulse_sync.v" +`include "utils/ramb_8_to_n.v" module tb ( @@ -36,15 +37,26 @@ module tb ( localparam PULSE_BASEADDR = 32'h0000; localparam PULSE_HIGHADDR = PULSE_BASEADDR + 15; -localparam SEQ_GEN_BASEADDR = 32'h1000; -localparam SEQ_GEN_HIGHADDR = 32'h3000-1; +localparam SEQ_GEN_BASEADDR = 32'h1000_0000; +localparam SEQ_GEN_HIGHADDR = 32'h2000_0000-1; -localparam SEQ_REC_BASEADDR = 32'h3000; -localparam SEQ_REC_HIGHADDR = 32'h5000 - 1; +localparam SEQ_REC_BASEADDR = 32'h2000_0000; +localparam SEQ_REC_HIGHADDR = 32'h3000_0000 - 1; localparam ABUSWIDTH = 32; assign BUS_BYTE_ACCESS = BUS_ADD < 32'h8000_0000 ? 1'b1 : 1'b0; +`ifdef BITS + localparam BITS = `BITS; +`else + localparam BITS = 8; +`endif + +`ifdef MEM_KB + localparam MEM_KB = `MEM_KB; +`else + localparam MEM_KB = 1; +`endif wire EX_START_PULSE; pulse_gen #( @@ -64,13 +76,13 @@ pulse_gen #( .PULSE(EX_START_PULSE) ); -wire [7:0] SEQ_OUT; +wire [BITS-1:0] SEQ_OUT; seq_gen #( .BASEADDR(SEQ_GEN_BASEADDR), .HIGHADDR(SEQ_GEN_HIGHADDR), .ABUSWIDTH(ABUSWIDTH), - .MEM_BYTES(8*1024), - .OUT_BITS(8) + .MEM_BYTES(MEM_KB*1024), + .OUT_BITS(BITS) ) i_seq_gen ( .BUS_CLK(BUS_CLK), .BUS_RST(BUS_RST), @@ -88,8 +100,8 @@ seq_rec #( .BASEADDR(SEQ_REC_BASEADDR), .HIGHADDR(SEQ_REC_HIGHADDR), .ABUSWIDTH(ABUSWIDTH), - .MEM_BYTES(8*1024), - .IN_BITS(8) + .MEM_BYTES(MEM_KB*1024), + .IN_BITS(BITS) ) i_seq_rec ( .BUS_CLK(BUS_CLK), .BUS_RST(BUS_RST), diff --git a/tests/test_SimTdc.py b/tests/test_SimTdc.py index 81b7ecdac..000a2000b 100644 --- a/tests/test_SimTdc.py +++ b/tests/test_SimTdc.py @@ -23,7 +23,6 @@ - name : SEQ_GEN type : seq_gen interface : INTF - mem_size : 65535 base_addr : 0x0000 - name : TDC0 diff --git a/tests/test_SimTdc.v b/tests/test_SimTdc.v index 3d964141d..821ba43a0 100644 --- a/tests/test_SimTdc.v +++ b/tests/test_SimTdc.v @@ -14,6 +14,7 @@ `include "seq_gen/seq_gen.v" `include "seq_gen/seq_gen_core.v" +`include "utils/ramb_8_to_n.v" `include "tdc_s3/tdc_s3_core.v" `include "tdc_s3/tdc_s3.v" @@ -94,7 +95,7 @@ seq_gen #( .BASEADDR(SEQ_GEN_BASEADDR), .HIGHADDR(SEQ_GEN_HIGHADDR), .ABUSWIDTH(ABUSWIDTH), - .MEM_BYTES(8 * 8 * 1024 - 1), + .MEM_BYTES(8 * 8 * 1024), .OUT_BITS(8) ) i_seq_gen ( .BUS_CLK(BUS_CLK),