\n
---
---------------------------------------------------------------------------------
---
--- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
---
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-USE ieee.numeric_std.all;
-
-USE work.ipbus.all;
-
-ENTITY i2c_master IS
- PORT(
- i2c_scl_i : IN std_logic;
- i2c_sda_i : IN std_logic;
- ipbus_clk_i : IN std_logic;
- ipbus_i : IN ipb_wbus; -- Signals from IPBus core to slave
- ipbus_reset_i : IN std_logic;
- i2c_scl_enb_o : OUT std_logic;
- i2c_sda_enb_o : OUT std_logic;
- ipbus_o : OUT ipb_rbus -- signals from slave to IPBus core
- );
-
--- Declarations
-
-END ENTITY i2c_master ;
-
---
-ARCHITECTURE rtl OF i2c_master IS
-
- --signal s_i2c_scl, s_i2c_scl_o, s_i2c_scl_enb, s_i2c_sda, s_i2c_sda_enb : std_logic ;
-
-BEGIN
-
- --i2c_scl_b <= s_i2c_scl when (s_i2c_scl_enb = '0') else 'Z';
- --i2c_sda_b <= s_i2c_sda when (s_i2c_sda_enb = '0') else 'Z';
-
- i2c_interface: entity work.i2c_master_top port map(
- wb_clk_i => ipbus_clk_i,
- wb_rst_i => ipbus_reset_i,
- arst_i => '1',
- wb_adr_i => ipbus_i.ipb_addr(2 downto 0),
- wb_dat_i => ipbus_i.ipb_wdata(7 downto 0),
- wb_dat_o => ipbus_o.ipb_rdata(7 downto 0),
- wb_we_i => ipbus_i.ipb_write,
- wb_stb_i => ipbus_i.ipb_strobe,
- wb_cyc_i => '1',
- wb_ack_o => ipbus_o.ipb_ack,
- wb_inta_o => open,
- scl_pad_i => i2c_scl_i,
- scl_pad_o => open,
- scl_padoen_o => i2c_scl_enb_o,
- sda_pad_i => i2c_sda_i,
- sda_pad_o => open,
- sda_padoen_o => i2c_sda_enb_o
- );
-
-
- ipbus_o.ipb_rdata(31 downto 8) <= ( others => '0');
- ipbus_o.ipb_err <= '0'; -- never return an error.
-
-END ARCHITECTURE rtl;
-
diff --git a/EUDETdummy/hdl/i2c/i2c_master_top.vhd b/EUDETdummy/hdl/i2c/i2c_master_top.vhd
deleted file mode 100644
index a6f0aab..0000000
--- a/EUDETdummy/hdl/i2c/i2c_master_top.vhd
+++ /dev/null
@@ -1,344 +0,0 @@
-----------------------------------------------------------------------
--- >>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<
-----------------------------------------------------------------------
---///////////////////////////////////////////////////////////////////
---// ////
---// WISHBONE rev.B2 compliant I2C Master bit-controller ////
---// ////
---// ////
---// Author: Richard Herveille ////
---// richard@asics.ws ////
---// www.asics.ws ////
---// ////
---// Downloaded from: http://www.opencores.org/projects/i2c/ ////
---// ////
---///////////////////////////////////////////////////////////////////
---// ////
---// Copyright (C) 2001 Richard Herveille ////
---// richard@asics.ws ////
---// ////
---// This source file may be used and distributed without ////
---// restriction provided that this copyright statement is not ////
---// removed from the file and that any derivative work contains ////
---// the original copyright notice and the associated disclaimer.////
---// ////
---// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
---// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
---// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
---// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
---// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
---// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
---// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
---// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
---// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
---// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
---// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
---// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
---// POSSIBILITY OF SUCH DAMAGE. ////
---// ////
---///////////////////////////////////////////////////////////////////
--- --------------------------------------------------------------------
--- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
--- --------------------------------------------------------------------
--- Copyright (c) 2008 - 2010 by Lattice Semiconductor Corporation
--- --------------------------------------------------------------------
---
--- Disclaimer:
---
--- This VHDL or Verilog source code is intended as a design reference
--- which illustrates how these types of functions can be implemented.
--- It is the user's responsibility to verify their design for
--- consistency and functionality through the use of formal
--- verification methods. Lattice Semiconductor provides no warranty
--- regarding the use or functionality of this code.
---
--- --------------------------------------------------------------------
---
--- Lattice Semiconductor Corporation
--- 5555 NE Moore Court
--- Hillsboro, OR 97214
--- U.S.A
---
--- TEL: 1-800-Lattice (USA and Canada)
--- 503-268-8001 (other locations)
---
--- web: http://www.latticesemi.com/
--- email: techsupport@latticesemi.com
---
--- --------------------------------------------------------------------
--- Code Revision History :
--- --------------------------------------------------------------------
--- Ver: | Author |Mod. Date |Changes Made:
--- V1.0 |K.P. | 7/09 | Initial ver for VHDL
--- | converted from LSC ref design RD1046
--------------------------------------------------------------------------------
--- Changes at University of bristol:
--- V1.0A|D.G.C | 5/11 | Changed name and ports to fit OC original
--- --------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-
-entity i2c_master_top is
- generic (
- ARST_LVL : integer := 0
- );
- port (
- wb_clk_i : in std_logic;
- wb_rst_i : in std_logic;
- arst_i : in std_logic;
- wb_adr_i : in std_logic_vector(2 downto 0);
- wb_dat_i : in std_logic_vector(7 downto 0);
- wb_dat_o : out std_logic_vector(7 downto 0);
- wb_we_i : in std_logic;
- wb_stb_i : in std_logic;
- wb_cyc_i : in std_logic;
- wb_ack_o : out std_logic;
- wb_inta_o: out std_logic;
- scl_pad_i: in std_logic;
- scl_pad_o: out std_logic;
- scl_padoen_o: out std_logic;
- sda_pad_i: in std_logic;
- sda_pad_o: out std_logic;
- sda_padoen_o: out std_logic
--- scl : inout std_logic;
--- sda : inout std_logic
- );
-end;
-
-architecture arch of i2c_master_top is
-
-component i2c_master_bit_ctrl
- port (
- clk : in std_logic;
- rst : in std_logic;
- nReset : in std_logic;
- clk_cnt : in std_logic_vector(15 downto 0); -- clock prescale value
- ena : in std_logic; -- core enable signal
- cmd : in std_logic_vector(3 downto 0);
- cmd_ack : out std_logic; -- command complete acknowledge
- busy : out std_logic; -- i2c bus busy
- al : out std_logic; -- i2c bus arbitration lost
- din : in std_logic;
- dout : out std_logic;
- scl_i : in std_logic; -- i2c clock line input
- scl_o : out std_logic; -- i2c clock line output
- scl_oen : out std_logic; -- i2c clock line output enable (active low)
- sda_i : in std_logic; -- i2c data line input
- sda_o : out std_logic; -- i2c data line output
- sda_oen : out std_logic -- i2c data line output enable (active low)
- );
-end component;
-
-component i2c_master_byte_ctrl
- port (
- clk : in std_logic; -- master clock
- rst : in std_logic; -- synchronous active high reset
- nReset : in std_logic; -- asynchronous active low reset
- clk_cnt : in std_logic_vector(15 downto 0); -- 4x SCL
- -- control inputs
- start : in std_logic;
- stop : in std_logic;
- read : in std_logic;
- write : in std_logic;
- ack_in : in std_logic;
- din : in std_logic_vector(7 downto 0);
- -- status outputs
- cmd_ack : out std_logic;
- ack_out : out std_logic; -- i2c clock line input
- dout : out std_logic_vector(7 downto 0);
- i2c_al : in std_logic;
- -- signals for bit_controller
- core_cmd : out std_logic_vector(3 downto 0);
- core_txd : out std_logic;
- core_rxd : in std_logic;
- core_ack : in std_logic
- );
-end component;
-
-component i2c_master_registers
- port (
- wb_clk_i : in std_logic;
- rst_i : in std_logic;
- wb_rst_i : in std_logic;
- wb_dat_i : in std_logic_vector(7 downto 0);
- wb_adr_i : in std_logic_vector(2 downto 0);
- wb_wacc : in std_logic;
- i2c_al : in std_logic;
- i2c_busy : in std_logic;
- done : in std_logic;
- irxack : in std_logic;
- prer : out std_logic_vector(15 downto 0); -- clock prescale register
- ctr : out std_logic_vector(7 downto 0); -- control register
- txr : out std_logic_vector(7 downto 0); -- transmit register
- cr : out std_logic_vector(7 downto 0); -- command register
- sr : out std_logic_vector(7 downto 0) -- status register
- );
-end component;
-
-
-signal prer : std_logic_vector(15 downto 0);
-signal ctr : std_logic_vector(7 downto 0);
-signal txr : std_logic_vector(7 downto 0);
-signal rxr : std_logic_vector(7 downto 0);
-signal cr : std_logic_vector(7 downto 0);
-signal sr : std_logic_vector(7 downto 0);
-
-signal done : std_logic;
-signal core_en : std_logic;
-signal ien : std_logic;
-signal irxack : std_logic;
-signal irq_flag : std_logic;
-signal i2c_busy : std_logic;
-signal i2c_al : std_logic;
-
-signal core_cmd : std_logic_vector(3 downto 0);
-signal core_txd : std_logic;
-signal core_ack, core_rxd : std_logic;
-
--- Don't need these signals, since passing them through
--- component interface
---signal scl_pad_i : std_logic;
---signal scl_pad_o : std_logic;
---signal scl_padoen_o : std_logic;
---
---signal sda_pad_i : std_logic;
---signal sda_pad_o : std_logic;
---signal sda_padoen_o : std_logic;
-
-signal rst_i : std_logic;
-
-signal sta : std_logic;
-signal sto : std_logic;
-signal rd : std_logic;
-signal wr : std_logic;
-signal ack : std_logic;
-signal iack : std_logic;
-
-signal wb_ack_o_int : std_logic;
-
-signal wb_wacc : std_logic;
-signal acki : std_logic;
-
-begin
-
- -- Don't need to copy these signal - passing through
- -- component interface
---scl_pad_i <= scl;
---sda_pad_i <= sda;
-
-rst_i <= arst_i when (ARST_LVL = 0) else NOT(arst_i);
-
-wb_wacc <= wb_cyc_i AND wb_stb_i AND wb_we_i;
-
-sta <= cr(7);
-sto <= cr(6);
-rd <= cr(5);
-wr <= cr(4);
-ack <= cr(3);
-acki <= cr(0);
-
-core_en <= ctr(7);
-ien <= ctr(6);
-
-process(wb_clk_i)
-begin
- if rising_edge(wb_clk_i) then
- wb_ack_o_int <= wb_cyc_i AND wb_stb_i AND NOT(wb_ack_o_int);
- end if;
-end process;
-
-wb_ack_o <= wb_ack_o_int;
-
-process(wb_clk_i)
-begin
- if rising_edge(wb_clk_i) then
- case (wb_adr_i) is
- when "000" => wb_dat_o <= prer(7 downto 0);
- when "001" => wb_dat_o <= prer(15 downto 8);
- when "010" => wb_dat_o <= ctr;
- when "011" => wb_dat_o <= rxr;
- when "100" => wb_dat_o <= sr;
- when "101" => wb_dat_o <= txr;
- when "110" => wb_dat_o <= cr;
- when "111" => wb_dat_o <= "00000000";
- when others => NULL;
- end case;
- end if;
-end process;
-
-process(wb_clk_i,rst_i)
-begin
- if (rst_i = '0') then
- wb_inta_o <= '0';
- elsif rising_edge(wb_clk_i) then
- wb_inta_o <= sr(0) AND ien;
- end if;
-end process;
-
-
-
-byte_controller: i2c_master_byte_ctrl port map(
- clk => wb_clk_i,
- rst => wb_rst_i,
- nReset => rst_i,
- clk_cnt => prer,
- start => sta,
- stop => sto,
- read => rd,
- write => wr,
- ack_in => ack,
- din => txr,
- cmd_ack => done,
- ack_out => irxack,
- dout => rxr,
- i2c_al => i2c_al,
- core_cmd => core_cmd,
- core_ack => core_ack,
- core_txd => core_txd,
- core_rxd => core_rxd);
-
-bit_controller: i2c_master_bit_ctrl port map(
- clk => wb_clk_i,
- rst => wb_rst_i,
- nReset => rst_i,
- ena => core_en,
- clk_cnt => prer,
- cmd => core_cmd,
- cmd_ack => core_ack,
- busy => i2c_busy,
- al => i2c_al,
- din => core_txd,
- dout => core_rxd,
- scl_i => scl_pad_i,
- scl_o => scl_pad_o,
- scl_oen => scl_padoen_o,
- sda_i => sda_pad_i,
- sda_o => sda_pad_o,
- sda_oen => sda_padoen_o);
-
-registers: i2c_master_registers port map(
- wb_clk_i => wb_clk_i,
- rst_i => rst_i,
- wb_rst_i => wb_rst_i,
- wb_dat_i => wb_dat_i,
- wb_wacc => wb_wacc,
- wb_adr_i => wb_adr_i,
- i2c_al => i2c_al,
- i2c_busy => i2c_busy,
- done => done,
- irxack => irxack,
- prer => prer,
- ctr => ctr,
- txr => txr,
- cr => cr,
- sr => sr);
-
-
--- edited from Lattice original to pass uni-directional signals
---scl <= scl_pad_o when (scl_padoen_o = '0') else 'Z';
---sda <= sda_pad_o when (sda_padoen_o = '0') else 'Z';
-
-end arch;
diff --git a/EUDETdummy/hdl/ipbus_addr_decode.vhd b/EUDETdummy/hdl/ipbus_addr_decode.vhd
deleted file mode 100644
index dc630e8..0000000
--- a/EUDETdummy/hdl/ipbus_addr_decode.vhd
+++ /dev/null
@@ -1,50 +0,0 @@
--- Address decode logic for ipbus fabric
---
--- This file has been AUTOGENERATED from the address table - do not hand edit
---
--- We assume the synthesis tool is clever enough to recognise exclusive conditions
--- in the if statement.
---
--- Dave Newbold, February 2011
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use ieee.numeric_std.all;
-use work.ipbus.all;
-
-package ipbus_addr_decode is
-
- function ipbus_addr_sel(signal addr : in std_logic_vector(31 downto 0)) return integer;
-
-end ipbus_addr_decode;
-
-package body ipbus_addr_decode is
-
- function ipbus_addr_sel(signal addr : in std_logic_vector(31 downto 0)) return integer is
- variable sel : integer;
- begin
- if std_match(addr, "-----------------------0001-----") then
- sel := 0; -- DUTInterfaces / base 00000020 / mask 0000001f
- elsif std_match(addr, "-----------------------0010-----") then
- sel := 1; -- triggerInputs / base 00000040 / mask 0000001f
- elsif std_match(addr, "-----------------------0011-----") then
- sel := 2; -- triggerLogic / base 00000060 / mask 0000001f
- elsif std_match(addr, "-----------------------0100-----") then
- sel := 3; -- eventBuffer / base 00000080 / mask 0000001f
- elsif std_match(addr, "-----------------------0101-----") then
- sel := 4; -- logic_clocks / base 000000a0 / mask 0000001f
- elsif std_match(addr, "-----------------------0110-----") then
- sel := 5; -- i2c_master / base 000000c0 / mask 00000007
- elsif std_match(addr, "-----------------------1010-----") then
- sel := 6; -- Event_Formatter / base 00000140 / mask 0000001f
- elsif std_match(addr, "-----------------------1011-----") then
- sel := 7; -- TPix3_iface / base 00000160 / mask 0000001f
- elsif std_match(addr, "-----------------------0000-----") then
- sel := 8; -- version / base 00000000 / mask 00000000
- else
- sel := 99;
- end if;
- return sel;
- end ipbus_addr_sel;
-
-end ipbus_addr_decode;
diff --git a/EUDETdummy/hdl/ipbus_decode_ipbus_example.vhd b/EUDETdummy/hdl/ipbus_decode_ipbus_example.vhd
deleted file mode 100644
index a315ed0..0000000
--- a/EUDETdummy/hdl/ipbus_decode_ipbus_example.vhd
+++ /dev/null
@@ -1,69 +0,0 @@
--- Address decode logic for ipbus fabric
---
---
--- We assume the synthesis tool is clever enough to recognise exclusive conditions
--- in the if statement.
---
--- Dave Newbold, February 2011
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use ieee.numeric_std.all;
-
-package ipbus_decode_ipbus_example is
-
- constant IPBUS_SEL_WIDTH: positive := 5; -- Should be enough for now?
- subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0);
- function ipbus_sel_ipbus_example(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t;
-
--- START automatically generated VHDL the Fri Oct 7 12:10:31 2016
- constant N_SLV_CTRL_REG: integer := 0; --for tests
- constant N_SLV_REG: integer := 1; -- for tests
- constant N_SLV_I2C_0: integer := 2; --I2C core for the TLU
- constant N_SLV_DUT: integer :=3;
- constant N_SLV_SHUT: integer :=4;
- constant N_SLV_EVBUF: integer :=5;
- constant N_SLV_EVFMT: integer :=6;
- constant N_SLV_TRGIN: integer :=7;
- constant N_SLV_TRGLGC: integer :=8;
- constant N_SLV_LGCCLK: integer :=9;
-
- constant N_SLAVES: integer := 10; --Total number of slaves
--- END automatically generated VHDL
- --constant N_I2C_CORES: integer := 3; --How many I2C cores
-
-end ipbus_decode_ipbus_example;
-
-package body ipbus_decode_ipbus_example is
-
- function ipbus_sel_ipbus_example(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t is
- variable sel: ipbus_sel_t;
- begin
-
--- START automatically generated VHDL the Fri Oct 7 12:10:31 2016
- if std_match(addr, "-----------------000----------0-") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_CTRL_REG, IPBUS_SEL_WIDTH)); -- ctrl_reg / base 0x00000000 / mask 0x00003002
- elsif std_match(addr, "-----------------000----------1-") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_REG, IPBUS_SEL_WIDTH)); -- reg / base 0x00000002 / mask 0x00003002
- --elsif std_match(addr, "-----------------001------------") then
- --sel := ipbus_sel_t(to_unsigned(N_SLV_RAM, IPBUS_SEL_WIDTH)); -- ram / base 0x00001000 / mask 0x00003000
- --elsif std_match(addr, "-----------------010----------0-") then
- -- sel := ipbus_sel_t(to_unsigned(N_SLV_PRAM, IPBUS_SEL_WIDTH)); -- pram / base 0x00002000 / mask 0x00003002
- elsif std_match(addr, "-----------------011------------") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_I2C_0, IPBUS_SEL_WIDTH)); -- i2c / base 0x00003000 / mask 0x00003002
- elsif std_match(addr, "-----------------100------------") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_DUT, IPBUS_SEL_WIDTH)); -- i2c / base 0x00004000 / mask 0x00003002
- elsif std_match(addr, "-----------------101------------") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_TRGIN, IPBUS_SEL_WIDTH)); -- i2c / base 0x00005000 / mask 0x00003002
--- END automatically generated VHDL
-
- else
- sel := ipbus_sel_t(to_unsigned(N_SLAVES, IPBUS_SEL_WIDTH));
- end if;
-
- return sel;
-
- end function ipbus_sel_ipbus_example;
-
-end ipbus_decode_ipbus_example;
-
diff --git a/EUDETdummy/hdl/ipbus_decode_tlu.vhd b/EUDETdummy/hdl/ipbus_decode_tlu.vhd
deleted file mode 100644
index 114da40..0000000
--- a/EUDETdummy/hdl/ipbus_decode_tlu.vhd
+++ /dev/null
@@ -1,73 +0,0 @@
--- Address decode logic for ipbus fabric
---
---
---
--- Paolo Baesso, February 2017
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use ieee.numeric_std.all;
-
-package ipbus_decode_tlu is
-
- constant IPBUS_SEL_WIDTH: positive := 5; -- Should be enough for now?
- subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0);
- function ipbus_sel_ipbus_example(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t;
-
--- START automatically generated VHDL the Fri Oct 7 12:10:31 2016
- constant N_SLV_CTRL_REG: integer := 0; --for tests
- constant N_SLV_REG: integer := 1; -- for tests
- constant N_SLV_I2C_0: integer := 2; --I2C core for the TLU
- constant N_SLV_DUT: integer :=3;
- constant N_SLV_SHUT: integer :=4;
- constant N_SLV_EVBUF: integer :=5;
- constant N_SLV_EVFMT: integer :=6;
- constant N_SLV_TRGIN: integer :=7;
- constant N_SLV_TRGLGC: integer :=8;
- constant N_SLV_LGCCLK: integer :=9;
-
- constant N_SLAVES: integer := 10; --Total number of IPBus slaves
--- END automatically generated VHDL
- --constant N_I2C_CORES: integer := 3; --How many I2C cores
-
-end ipbus_decode_tlu;
-
-package body ipbus_decode_tlu is
-
- function ipbus_sel_ipbus_example(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t is
- variable sel: ipbus_sel_t;
- begin
-
--- START automatically generated VHDL the Fri Oct 7 12:10:31 2016
- if std_match(addr, "----------------0000----------0-") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_CTRL_REG, IPBUS_SEL_WIDTH)); -- ctrl_reg / base 0x00000000 / mask 0x00003002
- elsif std_match(addr, "----------------0000----------1-") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_REG, IPBUS_SEL_WIDTH)); -- reg / base 0x00000002 / mask 0x00003002
- elsif std_match(addr, "----------------0001------------") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_DUT, IPBUS_SEL_WIDTH)); -- ram / base 0x00001000 / mask 0x00003000
- elsif std_match(addr, "----------------0010----------0-") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_SHUT, IPBUS_SEL_WIDTH)); -- shutter / base 0x00002000 / mask 0x00003002
- elsif std_match(addr, "----------------0011------------") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_I2C_0, IPBUS_SEL_WIDTH)); -- i2c / base 0x00003000 / mask 0x00003002
- elsif std_match(addr, "----------------0100------------") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_EVBUF, IPBUS_SEL_WIDTH)); -- event buffer / base 0x00004000 / mask 0x00003002
- elsif std_match(addr, "----------------0101------------") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_EVFMT, IPBUS_SEL_WIDTH)); -- event formatter / base 0x00005000 / mask 0x00003002
- elsif std_match(addr, "----------------0110------------") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_TRGIN, IPBUS_SEL_WIDTH)); -- trigger inputs / base 0x00006000 / mask 0x00003002
- elsif std_match(addr, "----------------0111------------") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_TRGLGC, IPBUS_SEL_WIDTH)); -- trigger logic / base 0x00007000 / mask 0x00003002
- elsif std_match(addr, "----------------1000------------") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_LGCCLK, IPBUS_SEL_WIDTH)); -- logic clocks / base 0x00008000 / mask 0x00003002
--- END automatically generated VHDL
-
- else
- sel := ipbus_sel_t(to_unsigned(N_SLAVES, IPBUS_SEL_WIDTH));
- end if;
-
- return sel;
-
- end function ipbus_sel_ipbus_example;
-
-end ipbus_decode_tlu;
-
diff --git a/EUDETdummy/hdl/ipbus_example.vhd b/EUDETdummy/hdl/ipbus_example.vhd
deleted file mode 100644
index 5cc5f12..0000000
--- a/EUDETdummy/hdl/ipbus_example.vhd
+++ /dev/null
@@ -1,174 +0,0 @@
--- ipbus_example
---
--- selection of different IPBus slaves without actual function,
--- just for performance evaluation of the IPbus/uhal system
---
--- Kristian Harder, March 2014
--- based on code by Dave Newbold, February 2011
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use work.ipbus.all;
-use work.ipbus_reg_types.all;
-use work.ipbus_decode_ipbus_example.all;
-
-entity ipbus_example is
- port(
- ipb_clk: in std_logic;
- ipb_rst: in std_logic;
- ipb_in: in ipb_wbus;
- ipb_out: out ipb_rbus;
- nuke: out std_logic;
- soft_rst: out std_logic;
- --i2c_scl_b: INOUT std_logic;
- --i2c_sda_b: INOUT std_logic;
-
- --i2c_sda_i: IN std_logic;
- --i2c_scl_i: IN std_logic;
- --i2c_scl_enb_o: OUT std_logic;
- --i2c_sda_enb_o: OUT std_logic;
-
- i2c_sda_i: IN std_logic_vector(N_I2C_CORES - 1 downto 0);
- i2c_scl_i: IN std_logic_vector(N_I2C_CORES - 1 downto 0);
- i2c_scl_enb_o: OUT std_logic_vector(N_I2C_CORES - 1 downto 0);
- i2c_sda_enb_o: OUT std_logic_vector(N_I2C_CORES - 1 downto 0);
- userled: out std_logic
- );
-
-end ipbus_example;
-
-architecture rtl of ipbus_example is
-
- signal ipbw: ipb_wbus_array(N_SLAVES - 1 downto 0);
- signal ipbr: ipb_rbus_array(N_SLAVES - 1 downto 0);
- signal ctrl, stat: ipb_reg_v(0 downto 0);
- --SIGNAL s_i2c_scl_enb : std_logic;
- --SIGNAL s_i2c_sda_enb : std_logic;
-
- -->P
- COMPONENT i2c_master
- PORT (
- i2c_scl_i : IN std_logic;
- i2c_sda_i : IN std_logic;
- ipbus_clk_i : IN std_logic;
- ipbus_i : IN ipb_wbus;
- ipbus_reset_i : IN std_logic;
- i2c_scl_enb_o : OUT std_logic;
- i2c_sda_enb_o : OUT std_logic;
- ipbus_o : OUT ipb_rbus
- );
- END COMPONENT i2c_master;
- FOR ALL : i2c_master USE ENTITY work.i2c_master;-- N_SLAVES,
- SEL_WIDTH => IPBUS_SEL_WIDTH)
- port map(
- ipb_in => ipb_in,
- ipb_out => ipb_out,
- sel => ipbus_sel_ipbus_example(ipb_in.ipb_addr),
- ipb_to_slaves => ipbw,
- ipb_from_slaves => ipbr
- );
-
--- Slave 0: id / rst reg
-
- slave0: entity work.ipbus_ctrlreg_v
- port map(
- clk => ipb_clk,
- reset => ipb_rst,
- ipbus_in => ipbw(N_SLV_CTRL_REG),
- ipbus_out => ipbr(N_SLV_CTRL_REG),
- d => stat,
- q => ctrl
- );
-
- stat(0) <= X"abcdfedc";
- soft_rst <= ctrl(0)(0);
- nuke <= ctrl(0)(1);
-
--- Slave 1: register
-
- slave1: entity work.ipbus_reg_v
- port map(
- clk => ipb_clk,
- reset => ipb_rst,
- ipbus_in => ipbw(N_SLV_REG),
- ipbus_out => ipbr(N_SLV_REG),
- q => open
- );
-
--- Slave 2: 1kword RAM
-
- slave4: entity work.ipbus_ram
- generic map(ADDR_WIDTH => 10)
- port map(
- clk => ipb_clk,
- reset => ipb_rst,
- ipbus_in => ipbw(N_SLV_RAM),
- ipbus_out => ipbr(N_SLV_RAM)
- );
-
--- Slave 3: peephole RAM
-
- slave5: entity work.ipbus_peephole_ram
- generic map(ADDR_WIDTH => 10)
- port map(
- clk => ipb_clk,
- reset => ipb_rst,
- ipbus_in => ipbw(N_SLV_PRAM),
- ipbus_out => ipbr(N_SLV_PRAM)
- );
--- slave6 : i2c_master
--- PORT MAP (
--- i2c_scl_i => i2c_scl_b,
--- i2c_sda_i => i2c_sda_b,
--- ipbus_clk_i => ipb_clk,
--- ipbus_i => ipbw(N_SLV_I2C),
--- ipbus_reset_i => ipb_rst,
--- i2c_scl_enb_o => s_i2c_scl_enb,
--- i2c_sda_enb_o => s_i2c_sda_enb,
--- ipbus_o => ipbr(N_SLV_I2C)
--- );
-
- -- Instantiate a I2C core for the EEPROM
- slave6 : i2c_master
- PORT MAP (
- i2c_scl_i => i2c_scl_i(0),
- i2c_sda_i => i2c_sda_i(0),
- ipbus_clk_i => ipb_clk,
- ipbus_i => ipbw(N_SLV_I2C_0),
- ipbus_reset_i => ipb_rst,
- i2c_scl_enb_o => i2c_scl_enb_o(0),
- i2c_sda_enb_o => i2c_sda_enb_o(0),
- ipbus_o => ipbr(N_SLV_I2C_0)
- );
- slave7 : i2c_master
- PORT MAP (
- i2c_scl_i => i2c_scl_i(1),
- i2c_sda_i => i2c_sda_i(1),
- ipbus_clk_i => ipb_clk,
- ipbus_i => ipbw(N_SLV_I2C_1),
- ipbus_reset_i => ipb_rst,
- i2c_scl_enb_o => i2c_scl_enb_o(1),
- i2c_sda_enb_o => i2c_sda_enb_o(1),
- ipbus_o => ipbr(N_SLV_I2C_1)
- );
- slave8 : i2c_master
- PORT MAP (
- i2c_scl_i => i2c_scl_i(2),
- i2c_sda_i => i2c_sda_i(2),
- ipbus_clk_i => ipb_clk,
- ipbus_i => ipbw(N_SLV_I2C_2),
- ipbus_reset_i => ipb_rst,
- i2c_scl_enb_o => i2c_scl_enb_o(2),
- i2c_sda_enb_o => i2c_sda_enb_o(2),
- ipbus_o => ipbr(N_SLV_I2C_2)
- );
-end rtl;
diff --git a/EUDETdummy/hdl/ipbus_fabric_sel.vhd b/EUDETdummy/hdl/ipbus_fabric_sel.vhd
deleted file mode 100644
index 86d2fa7..0000000
--- a/EUDETdummy/hdl/ipbus_fabric_sel.vhd
+++ /dev/null
@@ -1,61 +0,0 @@
--- The ipbus bus fabric, address select logic, data multiplexers
---
--- This version selects the addressed slave depending on the state
--- of incoming control lines
---
--- Dave Newbold, February 2011
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use ieee.numeric_std.all;
-use work.ipbus.ALL;
-
-entity ipbus_fabric_sel is
- generic(
- NSLV: positive;
- STROBE_GAP: boolean := false;
- SEL_WIDTH: positive
- );
- port(
- sel: in std_logic_vector(SEL_WIDTH - 1 downto 0);
- ipb_in: in ipb_wbus;
- ipb_out: out ipb_rbus;
- ipb_to_slaves: out ipb_wbus_array(NSLV - 1 downto 0);
- ipb_from_slaves: in ipb_rbus_array(NSLV - 1 downto 0) := (others => IPB_RBUS_NULL)
- );
-
-end ipbus_fabric_sel;
-
-architecture rtl of ipbus_fabric_sel is
-
- signal sel_i: integer range 0 to NSLV := 0;
- signal ored_ack, ored_err: std_logic_vector(NSLV downto 0);
- signal qstrobe: std_logic;
-
-begin
-
- sel_i <= to_integer(unsigned(sel));
-
- ored_ack(NSLV) <= '0';
- ored_err(NSLV) <= '0';
-
- qstrobe <= ipb_in.ipb_strobe when STROBE_GAP = false else
- ipb_in.ipb_strobe and not (ored_ack(0) or ored_err(0));
-
- busgen: for i in NSLV-1 downto 0 generate
- begin
-
- ipb_to_slaves(i).ipb_addr <= ipb_in.ipb_addr;
- ipb_to_slaves(i).ipb_wdata <= ipb_in.ipb_wdata;
- ipb_to_slaves(i).ipb_strobe <= qstrobe when sel_i = i else '0';
- ipb_to_slaves(i).ipb_write <= ipb_in.ipb_write;
- ored_ack(i) <= ored_ack(i+1) or ipb_from_slaves(i).ipb_ack;
- ored_err(i) <= ored_err(i+1) or ipb_from_slaves(i).ipb_err;
-
- end generate;
-
- ipb_out.ipb_rdata <= ipb_from_slaves(sel_i).ipb_rdata when sel_i /= NSLV else (others => '0');
- ipb_out.ipb_ack <= ored_ack(0);
- ipb_out.ipb_err <= ored_err(0);
-
-end rtl;
diff --git a/EUDETdummy/hdl/ipbus_slaves.vhd b/EUDETdummy/hdl/ipbus_slaves.vhd
deleted file mode 100644
index e0ee08f..0000000
--- a/EUDETdummy/hdl/ipbus_slaves.vhd
+++ /dev/null
@@ -1,170 +0,0 @@
--- ipbus_example
---
--- selection of different IPBus slaves without actual function,
--- just for performance evaluation of the IPbus/uhal system
---
--- Kristian Harder, March 2014
--- based on code by Dave Newbold, February 2011
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use work.ipbus.all;
-use work.ipbus_reg_types.all;
-use work.ipbus_decode_ipbus_example.all;
-
-entity ipbus_slaves is
- port(
- ipb_clk: in std_logic;
- ipb_rst: in std_logic;
- ipb_in: in ipb_wbus;
- ipb_out: out ipb_rbus;
- nuke: out std_logic;
- soft_rst: out std_logic;
- --i2c_scl_b: INOUT std_logic;
- --i2c_sda_b: INOUT std_logic;
-
- --i2c_sda_i: IN std_logic;
- --i2c_scl_i: IN std_logic;
- --i2c_scl_enb_o: OUT std_logic;
- --i2c_sda_enb_o: OUT std_logic;
-
- i2c_sda_i: IN std_logic_vector(N_I2C_CORES - 1 downto 0);
- i2c_scl_i: IN std_logic_vector(N_I2C_CORES - 1 downto 0);
- i2c_scl_enb_o: OUT std_logic_vector(N_I2C_CORES - 1 downto 0);
- i2c_sda_enb_o: OUT std_logic_vector(N_I2C_CORES - 1 downto 0);
- userled: out std_logic
- );
-
-end ipbus_slaves;
-
-architecture rtl of ipbus_slaves is
-
- signal ipbw: ipb_wbus_array(N_SLAVES - 1 downto 0);
- signal ipbr: ipb_rbus_array(N_SLAVES - 1 downto 0);
- signal ctrl, stat: ipb_reg_v(0 downto 0);
- --SIGNAL s_i2c_scl_enb : std_logic;
- --SIGNAL s_i2c_sda_enb : std_logic;
-
- -->P
- COMPONENT i2c_master
- PORT (
- i2c_scl_i : IN std_logic;
- i2c_sda_i : IN std_logic;
- ipbus_clk_i : IN std_logic;
- ipbus_i : IN ipb_wbus;
- ipbus_reset_i : IN std_logic;
- i2c_scl_enb_o : OUT std_logic;
- i2c_sda_enb_o : OUT std_logic;
- ipbus_o : OUT ipb_rbus
- );
- END COMPONENT i2c_master;
- FOR ALL : i2c_master USE ENTITY work.i2c_master;--
N_SLAVES,
- SEL_WIDTH => IPBUS_SEL_WIDTH)
- port map(
- ipb_in => ipb_in,
- ipb_out => ipb_out,
- sel => ipbus_sel_ipbus_example(ipb_in.ipb_addr),
- ipb_to_slaves => ipbw,
- ipb_from_slaves => ipbr
- );
-
--- Slave 0: id / rst reg
-
- slave0: entity work.ipbus_ctrlreg_v
- port map(
- clk => ipb_clk,
- reset => ipb_rst,
- ipbus_in => ipbw(N_SLV_CTRL_REG),
- ipbus_out => ipbr(N_SLV_CTRL_REG),
- d => stat,
- q => ctrl
- );
- stat(0) <= X"abcdfedc";
- soft_rst <= ctrl(0)(0);
- nuke <= ctrl(0)(1);
-
--- Slave 1: register
- slave1: entity work.ipbus_reg_v
- port map(
- clk => ipb_clk,
- reset => ipb_rst,
- ipbus_in => ipbw(N_SLV_REG),
- ipbus_out => ipbr(N_SLV_REG),
- q => open
- );
-
--- Slave 2: 1kword RAM
--- slave4: entity work.ipbus_ram
--- generic map(ADDR_WIDTH => 10)
--- port map(
--- clk => ipb_clk,
--- reset => ipb_rst,
--- ipbus_in => ipbw(N_SLV_RAM),
--- ipbus_out => ipbr(N_SLV_RAM)
--- );
-
--- Slave 3: peephole RAM
--- slave5: entity work.ipbus_peephole_ram
--- generic map(ADDR_WIDTH => 10)
--- port map(
--- clk => ipb_clk,
--- reset => ipb_rst,
--- ipbus_in => ipbw(N_SLV_PRAM),
--- ipbus_out => ipbr(N_SLV_PRAM)
--- );
--- slave6 : i2c_master
--- PORT MAP (
--- i2c_scl_i => i2c_scl_b,
--- i2c_sda_i => i2c_sda_b,
--- ipbus_clk_i => ipb_clk,
--- ipbus_i => ipbw(N_SLV_I2C),
--- ipbus_reset_i => ipb_rst,
--- i2c_scl_enb_o => s_i2c_scl_enb,
--- i2c_sda_enb_o => s_i2c_sda_enb,
--- ipbus_o => ipbr(N_SLV_I2C)
--- );
-
- -- Instantiate a I2C core for the EEPROM
- slave6 : i2c_master
- PORT MAP (
- i2c_scl_i => i2c_scl_i(0),
- i2c_sda_i => i2c_sda_i(0),
- ipbus_clk_i => ipb_clk,
- ipbus_i => ipbw(N_SLV_I2C_0),
- ipbus_reset_i => ipb_rst,
- i2c_scl_enb_o => i2c_scl_enb_o(0),
- i2c_sda_enb_o => i2c_sda_enb_o(0),
- ipbus_o => ipbr(N_SLV_I2C_0)
- );
- slave7 : i2c_master
- PORT MAP (
- i2c_scl_i => i2c_scl_i(1),
- i2c_sda_i => i2c_sda_i(1),
- ipbus_clk_i => ipb_clk,
- ipbus_i => ipbw(N_SLV_I2C_1),
- ipbus_reset_i => ipb_rst,
- i2c_scl_enb_o => i2c_scl_enb_o(1),
- i2c_sda_enb_o => i2c_sda_enb_o(1),
- ipbus_o => ipbr(N_SLV_I2C_1)
- );
- slave8 : i2c_master
- PORT MAP (
- i2c_scl_i => i2c_scl_i(2),
- i2c_sda_i => i2c_sda_i(2),
- ipbus_clk_i => ipb_clk,
- ipbus_i => ipbw(N_SLV_I2C_2),
- ipbus_reset_i => ipb_rst,
- i2c_scl_enb_o => i2c_scl_enb_o(2),
- i2c_sda_enb_o => i2c_sda_enb_o(2),
- ipbus_o => ipbr(N_SLV_I2C_2)
- );
-end rtl;
diff --git a/EUDETdummy/hdl/ipbus_ver.vhd b/EUDETdummy/hdl/ipbus_ver.vhd
deleted file mode 100644
index 068f126..0000000
--- a/EUDETdummy/hdl/ipbus_ver.vhd
+++ /dev/null
@@ -1,46 +0,0 @@
---=============================================================================
---! @file ipbus_ver.vhd
---=============================================================================
-
--- Version register, returns a fixed value
---
--- To be replaced by a more coherent versioning mechanism later
---
--- Dave Newbold, August 2011
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use work.ipbus.all;
-
---! @brief IPBus fixed register returning Firmware version number
-entity ipbus_ver is
- port(
- ipbus_in: in ipb_wbus;
- ipbus_out: out ipb_rbus
- );
-
-end ipbus_ver;
-
-architecture rtl of ipbus_ver is
-
-begin
-
- ipbus_out.ipb_rdata <= X"a622" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
- ipbus_out.ipb_ack <= ipbus_in.ipb_strobe;
- ipbus_out.ipb_err <= '0';
-
-end rtl;
-
--- Build log
---
--- build 0x1000 : 22/08/11 : Starting build ID
--- build 0x1001 : 29/08/11 : Version for SPI testing
--- build 0x1002 : 27/09/11 : Bug fixes, new transactor code; v1.3 candidate
--- build 0x1003 : buggy
--- build 0x1004 : 18/10/11 : New mini-t top level, bug fixes, 1.3 codebase
--- build 0x1005 : 20/10/11 : ipbus address config testing in mini-t
--- build 0x1006 : 26/10/11 : trying with jumbo frames
--- build 0x1007 : 27/10/11 : new slaves / address map + rhino frames
--- build 0x1008 : 31/10/11 : rhino frames + multibus demo
-
-
diff --git a/EUDETdummy/hdl/led_stretcher.vhd b/EUDETdummy/hdl/led_stretcher.vhd
deleted file mode 100644
index c8af6c6..0000000
--- a/EUDETdummy/hdl/led_stretcher.vhd
+++ /dev/null
@@ -1,74 +0,0 @@
--- stretcher
---
--- Stretches a single clock pulse so it's visible on an LED
---
--- Dave Newbold, January 2013
---
--- $Id$
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity led_stretcher is
- generic(
- WIDTH: positive := 1
- );
- port(
- clk: in std_logic; -- Assumed to be 125MHz ipbus clock
- d: in std_logic_vector(WIDTH - 1 downto 0); -- Input (edge detected)
- q: out std_logic_vector(WIDTH - 1 downto 0) -- LED output, ~250ms pulse
- );
-
-end led_stretcher;
-
-architecture rtl of led_stretcher is
-
- signal d17, d17_d: std_logic;
-
-begin
-
- clkdiv: entity work.ipbus_clock_div
- port map(
- clk => clk,
- d17 => d17
- );
-
- process(clk)
- begin
- if rising_edge(clk) then
- d17_d <= d17;
- end if;
- end process;
-
- lgen: for i in WIDTH - 1 downto 0 generate
-
- signal s, sd, e, e_d, sl: std_logic;
- signal scnt: unsigned(6 downto 0);
-
- begin
-
- process(clk)
- begin
- if rising_edge(clk) then
- s <= d(i); -- Possible clock domain crossing from slower clock (sync not important)
- sd <= s;
- e <= (e or (s and not sd)) and not e_d;
- if d17 = '1' and d17_d = '0' then
- e_d <= e;
- if e = '1' then
- scnt <= "0000001";
- elsif sl = '0' then
- scnt <= scnt + 1;
- end if;
- end if;
- end if;
- end process;
-
- sl <= '1' when scnt = "0000000" else '0';
-
- q(i) <= not sl;
-
- end generate;
-
-end rtl;
diff --git a/EUDETdummy/hdl/logic_clocks_rtl.vhd b/EUDETdummy/hdl/logic_clocks_rtl.vhd
deleted file mode 100644
index 631007a..0000000
--- a/EUDETdummy/hdl/logic_clocks_rtl.vhd
+++ /dev/null
@@ -1,344 +0,0 @@
---=============================================================================
---! @file logic_clocks_rtl.vhd
---=============================================================================
---
--------------------------------------------------------------------------------
--- --
--- University of Bristol, High Energy Physics Group.
--- --
-------------------------------------------------------------------------------- --
--- VHDL Architecture fmc_mTLU_lib.logic_clocks.rtl
---
---------------------------------------------------------------------------------
---
--- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
---
--- Based on output of Xilinx Coregen and Alvro Dosil TLU code.
-------------------------------------------------------------------------------
--- "Output Output Phase Duty Pk-to-Pk Phase"
--- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
-------------------------------------------------------------------------------
--- CLK_OUT1___640.000______0.000______50.0______175.916____213.982
--- CLK_OUT2___160.000______0.000______50.0______223.480____213.982
--- CLK_OUT3____40.000______0.000______50.0______306.416____213.982
---
-------------------------------------------------------------------------------
--- "Input Clock Freq (MHz) Input Jitter (UI)"
-------------------------------------------------------------------------------
--- __primary__________40.000____________0.010
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-USE ieee.numeric_std.all;
-
-USE work.ipbus.all;
-
-library unisim;
-use unisim.vcomponents.all;
-
---! @brief Generates 160MHz , 640MHz clocks from an incoming 40MHz clock.
---! Can switch between clock generated from on-board Xtal ( clk_logic_xtal ) and external clock.
---! Can also output clock to external clock pins.
---!
---! @author David Cussans , David.Cussans@bristol.ac.uk
---
---! @date 14:20:26 11/14/12
---
---! @version v0.1
---
---! @details
---! \br IPBus Address map:
---! \br (decode 2 bits)
---! \li 0x00000000 - control/status register:
---! \li bit-0 - PLL locked ( 1 = locked )
---! \li bit-1 - buff-PLL locked ( 1 = locked )
---! \li bit-2 - use xtal for logic ( 1 = xtal , 0= external)
---! \li bit-3 - clock connector is an input ( 1=input , 0 = output)
---! \li 0x00000001 - reset logic. Write to bit-zero to send reset.
---!
---!
-ENTITY logic_clocks IS
- GENERIC(
- g_USE_EXTERNAL_CLK : integer := 1
- );
- PORT(
- ipbus_clk_i : IN std_logic;
- ipbus_i : IN ipb_wbus;
- ipbus_reset_i : IN std_logic;
- Reset_i : IN std_logic;
- clk_logic_xtal_i : IN std_logic; --! 40MHz clock derived from onboard xtal
- clk_8x_logic_o : OUT std_logic; --! 640MHz clock
- clk_4x_logic_o : OUT std_logic; --! 160MHz clock
- ipbus_o : OUT ipb_rbus;
- strobe_8x_logic_o : OUT std_logic; --! strobes once every 4 cycles of clk_16x
- strobe_4x_logic_o : OUT std_logic; --! one pulse every 4 cycles of clk_4x
- DUT_clk_o : OUT std_logic; --! 40MHz to DUTs
- logic_clocks_locked_o : OUT std_logic; --! Goes high if clocks locked.
- logic_reset_o : OUT std_logic --! Goes high to reset counters etc. Sync with clk_4x_logic
- );
-
--- Declarations
-END ENTITY logic_clocks ;
-
---
-ARCHITECTURE rtl OF logic_clocks IS
- signal s_clk40 , s_clk40_internal : std_logic;
- signal s_clk160 ,s_clk160_internal : std_logic;
- signal ryanclock : std_logic;
- signal s_clk320 , s_clk320_internal : std_logic;
- signal s_clk40_out : std_logic; -- Clock generated by DDR register to feed out of chip.
- signal s_clk_is_xtal, s_clk_is_ext_buf : std_logic := '0'; -- default to
- -- input from ext
- -- signal s_logic_clk_rst : std_logic := '0';
- signal s_locked_pll, s_locked_bufpll : std_logic;
-
- signal s_clk : std_logic;
- signal s_DUT_Clk, s_DUT_Clk_o, s_DUT_ClkG : std_logic;
- signal s_extclk, s_extclkG : std_logic;
- -- signal s_clk_d1 , s_strobe_4x_p1 , s_strobe_4x_logic : std_logic;
- signal s_clkfbout_buf , s_clkfbout : std_logic;
-
- signal s_strobe_generator : std_logic_vector(3 downto 0) := "1000"; -- ! Store state of ring buffer to generate strobe
- signal s_logic_clk_generator : std_logic_vector(3 downto 0) := "1100"; --! Stores state of 40MHz "clock"
- --signal s_strobe_generator : std_logic_vector(15 downto 0) := "1111000000000000"; -- ! Store state of ring buffer to generate strobe
- --signal s_logic_clk_generator : std_logic_vector(15 downto 0) := "1111111100000000"; --! Stores state of 40MHz "clock"
- signal s_strobe160 :std_logic_vector(15 downto 0) := "1000000000000000"; -- 160 strobe ring
- signal s_strobe_fb : std_logic := '0';
-
- signal s_logic_reset_ipb, s_logic_reset_ipb_d1 : std_logic := '0';
- -- ! Reset signal in IPBus clock domain
- signal s_logic_reset , s_logic_reset_d1 , s_logic_reset_d2 , s_logic_reset_d3 , s_logic_reset_d4 : std_logic := '0';
- -- ! reset signal clocked onto logic-clock domain.
- attribute SHREG_EXTRACT: string;
- attribute SHREG_EXTRACT of s_logic_reset_d1: signal is "no"; -- Synchroniser not to be optimised into shre
- attribute SHREG_EXTRACT of s_logic_reset_d2: signal is "no"; -- Synchroniser not to be optimised into shreg
- attribute SHREG_EXTRACT of s_logic_reset_d3: signal is "no"; -- Synchroniser not to be optimised into shreg
- attribute SHREG_EXTRACT of s_logic_reset_d4: signal is "no"; -- Synchroniser not to be optimised into shreg
- signal s_ipbus_ack : std_logic := '0';
- signal s_reset_pll : std_logic := '0';
-
-
- -- ! Global Reset signal
- signal s_extclk_internal : std_logic := '0';
- signal s_clock_status_ipb : std_logic_vector( ipbus_o.ipb_rdata'range ); --! Hold status of clocks
-
-BEGIN
- -----------------------------------------------------------------------------
- -- IPBus write
- -----------------------------------------------------------------------------
- ipbus_write: process (ipbus_clk_i)
- begin -- process ipb_clk_i
- if rising_edge(ipbus_clk_i) then
- s_logic_reset_ipb <= '0';
- if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1') then
- case ipbus_i.ipb_addr(1 downto 0) is
- when "00" =>
- s_clk_is_xtal <= ipbus_i.ipb_wdata(2) ; -- select clock source
-
- when "01" =>
- s_logic_reset_ipb <= ipbus_i.ipb_wdata(0) ; -- write to reset
- when others => null;
- end case;
- end if;
-
- -- register reset signal to aid timing.
- s_logic_reset_ipb_d1 <= s_logic_reset_ipb;
- s_ipbus_ack <= ipbus_i.ipb_strobe and not s_ipbus_ack;
- -- register the clock status signals onto IPBus domain.
- --s_clock_status_ipb <= x"0000000" & '0' & s_clk_is_xtal & s_locked_bufpll & s_locked_pll;
- s_clock_status_ipb <= x"0000000" & '0' & '0' & '0' & s_locked_pll; -- The only useful bit is not the PLL lock status.
- end if;
- end process ipbus_write;
-
- ipbus_o.ipb_ack <= s_ipbus_ack;
- ipbus_o.ipb_err <= '0';
-
- -----------------------------------------------------------------------------
- -- IPBUS read
- -----------------------------------------------------------------------------
- with ipbus_i.ipb_addr(1 downto 0) select
- ipbus_o.ipb_rdata <=
- s_clock_status_ipb when "00",
- (others => '1') when others;
-
-
- -----------------------------------------------------------------------------
- -- Generate reset signal on logic-clock domain
- -- This relies on the IPBus clock being much slower than the 4x logic clock.
- -----------------------------------------------------------------------------
- p_reset: process (s_clk160_internal)
- begin -- process p_reset
- if rising_edge(s_clk160_internal) then
- s_logic_reset_d1 <= s_logic_reset_ipb_d1;
- s_logic_reset_d2 <= s_logic_reset_d1;
- s_logic_reset_d3 <= s_logic_reset_d2;
- s_logic_reset_d4 <= s_logic_reset_d2 and ( not s_logic_reset_d3);
- s_logic_reset <= s_logic_reset_d4;
- end if;
- end process p_reset;
-
- logic_reset_o <= s_logic_reset;
- logic_clocks_locked_o <= s_locked_bufpll and s_locked_pll;
-
-
- -- Use Generate, since can't figure out how BUFGMUX works
- -- gen_extclk_input: if ( g_USE_EXTERNAL_CLK = 1) generate
- -- s_DUT_Clk <= s_extclkG; -- Hard wire for now.
- -- end generate gen_extclk_input;
- -- gen_intclk_input: if ( g_USE_EXTERNAL_CLK = 0) generate
- s_DUT_Clk <= clk_logic_xtal_i;
- -- end generate gen_intclk_input;
-
-
-
- --! Clocking primitive
- -------------------------------------
- --! Instantiation of the PLL primitive
- pll_base_inst : PLL_BASE
- generic map
- (BANDWIDTH => "OPTIMIZED",
- --CLK_FEEDBACK => "CLKOUT0", --"CLKFBOUT",
- CLK_FEEDBACK => "CLKFBOUT",
- COMPENSATION => "SYSTEM_SYNCHRONOUS",
- DIVCLK_DIVIDE => 1,
- CLKFBOUT_MULT => 16,
- CLKFBOUT_PHASE => 0.000,
- CLKOUT0_DIVIDE => 2, -- 1-->2 move from 640 to 320
- CLKOUT0_PHASE => 0.000,
- CLKOUT0_DUTY_CYCLE => 0.500,
- CLKOUT1_DIVIDE => 4, -- 4-->8 move from 160 to 80
- CLKOUT1_PHASE => 0.000,
- CLKOUT1_DUTY_CYCLE => 0.500,
- CLKOUT2_DIVIDE => 16, -- 16--> 32 move from 40 to 20
- CLKOUT2_PHASE => 0.000,
- CLKOUT2_DUTY_CYCLE => 0.500,
- CLKIN_PERIOD => 25.000,
- REF_JITTER => 0.010)
- port map(
- -- Output clocks
- CLKFBOUT => s_clkfbout,
- CLKOUT0 => s_clk320,
- CLKOUT1 => s_clk160,
- CLKOUT2 => s_clk40,
- CLKOUT3 => open,
- CLKOUT4 => open,
- CLKOUT5 => open,
- -- Status and control signals
- LOCKED => s_locked_pll,
- -- RST => s_logic_clk_rst,
- RST => s_reset_pll,
- -- Input clock control
- -- CLKFBIN => s_clkfbout_buf,
- CLKFBIN => s_clkfbout,
- CLKIN => s_DUT_clk);
- -- CLKIN => clk_logic_xtal_i);
-
- s_reset_pll <= Reset_i or s_logic_reset;
-
------------------------------------------------
---BUFPLL not supported by 7 Series. We need to replace it with BUFIO+BUFR
- -- Buffer the 16x clock and generate the ISERDES strobe signal
--- BUFPLL_inst : BUFPLL
--- generic map (
--- DIVIDE => 4)
--- port map (
--- IOCLK => s_clk640_internal, -- 1-bit output: Output I/O clock
--- LOCK => s_locked_bufpll, -- 1-bit output: Synchronized LOCK output
--- SERDESSTROBE => strobe_16x_logic_O, -- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
--- GCLK => s_clk160_internal, -- 1-bit input: BUFG clock input
--- LOCKED => s_locked_pll, -- 1-bit input: LOCKED input from PLL
--- PLLIN => s_clk640 -- 1-bit input: Clock input from PLL
--- );
-
- BUFG_inst: BUFG
- port map (
- I => s_clk320,
- O => s_clk320_internal
- );
-
--- BUFR_inst: BUFR
--- generic map (
--- BUFR_DIVIDE => "4"
--- )
--- port map (
--- I => s_clk160_internal,
--- CE => '1',
--- CLR => '0',
--- O => ryanclock
--- );
-
--- BUFG_inst2: BUFG
--- port map (
--- I => ryanclock,
--- O => strobe_16x_logic_O -- Not sure this is actually a strobe... Check
--- );
------------------------------------------------
-
- clk_8x_logic_o <= s_clk320_internal;
- DUT_clk_o <= s_DUT_clk;
-
-
-
- -- Generate a strobe signal every 4 clocks.
- -- Can't use a clock signal as a combinatorial signal. Hence the baroque
- -- method of generating a strobe. Add a mechanism to restart if the '1' gets
- -- lost ....
-
- ------------------
- generate_4x_strobe: process (s_clk160_internal)-- , s_clk40_out)
- begin -- process generate_4x_strobe
- if rising_edge(s_clk160_internal) then
- if s_logic_reset = '1' then
- s_strobe_generator <= "1000";
- s_logic_clk_generator <= "1100";
- --s_strobe160 <= "1000000000000000";
- elsif (s_locked_pll ='1') then
- s_strobe_generator <= s_strobe_generator(2 downto 0) & s_strobe_generator(3); -- <- bit shift left
- s_logic_clk_generator <= s_logic_clk_generator(2 downto 0) & s_logic_clk_generator(3); -- <- bit shift left
- --s_strobe160 <= s_strobe160(14 downto 0) & s_strobe160(15);
- end if;
- end if;
- end process generate_4x_strobe;
- strobe_4x_logic_o <= s_strobe_generator(3); -- Every 4 clocks this gets to 1 for one pulse
- s_clk40_out <= s_logic_clk_generator(3); -- Every 4 clocks this gets to 1 for two pulses (so half F of the original clock? But then it is a clk80 not clk40.) Not used it seems.
- ---------------
-
- generate_8x_strobe: process (s_clk320_internal)
- begin
- if rising_edge(s_clk320_internal) then
- if s_logic_reset = '1' then
- s_strobe160 <= "1000000000000000";
- --s_strobe_generator <= "1111000000000000";--
- --s_logic_clk_generator <= "1111111100000000";--
- elsif (s_locked_pll ='1') then
- s_strobe160 <= s_strobe160(14 downto 0) & s_strobe160(15);
- --s_strobe_generator <= s_strobe_generator(14 downto 0) & s_strobe_generator(15); --
- --s_logic_clk_generator <= s_logic_clk_generator(14 downto 0) & s_logic_clk_generator(15); -- <- bit shift left
- end if;
- end if;
- end process generate_8x_strobe;
- strobe_8x_logic_O <= s_strobe160(15);
- --strobe_4x_logic_o <= s_strobe_generator(15); --
- --s_clk40_out <= s_logic_clk_generator(15); --
-
-
- -- buffer 160MHz (4x) clock
- --------------------------------------
- clk160_o_buf : BUFG
- port map(
- O => s_clk160_internal,
- I => s_clk160);
-
- clk_4x_logic_o <= s_clk160_internal;
-
--- -- buffer 40MHz (1x) clock
--- --------------------------------------
--- clk40_o_buf : BUFG
--- port map(
--- O => s_clk40_internal,
--- I => s_clk40);
-
--- clk_logic_o <= s_clk40_out;
-
-END ARCHITECTURE rtl;
-
diff --git a/EUDETdummy/hdl/top_EUDET_dummy.vhd b/EUDETdummy/hdl/top_EUDET_dummy.vhd
deleted file mode 100644
index 66b0ab9..0000000
--- a/EUDETdummy/hdl/top_EUDET_dummy.vhd
+++ /dev/null
@@ -1,646 +0,0 @@
--- Top-level design for TLU v1E
---
--- This version is for Enclustra AX3 module, using the RGMII PHY on the PM3 baseboard
---
--- You must edit this file to set the IP and MAC addresses
---
--- Dave Newbold, 4/10/16--
-
-library IEEE;
-library UNISIM;
-use IEEE.STD_LOGIC_1164.ALL;
-use ieee.numeric_std.all;
-use work.fmcTLU.all;
-use work.ipbus_decode_tlu.all;
-use work.ipbus.all;
-use work.ipbus_reg_types.all;
-use UNISIM.vcomponents.all;
-
---Library UNISIM;
---use UNISIM.vcomponents.all;
-
-use work.ipbus.ALL;
-
-entity top_EUDET_dummy is
- generic(
- constant FW_VERSION : unsigned(31 downto 0):= X"ffff0006"; -- Firmware revision. Remember to change this as needed.
- g_NUM_DUTS : positive := 4; -- <- was 3
- g_NUM_TRIG_INPUTS :positive := 6;-- <- was 4
- g_NUM_EDGE_INPUTS :positive := 6;-- <-- was 4
- g_NUM_EXT_SLAVES :positive :=8;-- <-- ??
- g_EVENT_DATA_WIDTH :positive := 32;-- <-- ??
- g_IPBUS_WIDTH :positive := 32;-- <-- was 32
- g_SPILL_COUNTER_WIDTH :positive := 12;-- <-- ??
- g_BUILD_SIMULATED_MAC :integer := 0
- );
- port(
- --Clock
- --sysclk: in std_logic; --50 MHz clock input from FPGA
- clk_enclustra: in std_logic; --Enclustra onboard oscillator 40 MHz. Used for the IPBus block
- sysclk_50_o_p : out std_logic; --50 MHz clock output to FMC pins
- sysclk_50_o_n : out std_logic; --50 MHz clock output to FMC pins
- sysclk_40_i_p: in std_logic;
- sysclk_40_i_n: in std_logic;
- --Misc
- leds: out std_logic_vector(3 downto 0); -- status LEDs
- dip_sw: in std_logic_vector(3 downto 0); -- switches
- gpio: out std_logic; -- gpio pin on J1 (eventually make it inout)
- --RGMII interface signals
- rgmii_txd: out std_logic_vector(3 downto 0);
- rgmii_tx_ctl: out std_logic;
- rgmii_txc: out std_logic;
- rgmii_rxd: in std_logic_vector(3 downto 0);
- rgmii_rx_ctl: in std_logic;
- rgmii_rxc: in std_logic;
- phy_rstn: out std_logic;
- --I2C bus
- i2c_scl_b: inout std_logic;
- i2c_sda_b: inout std_logic;
- i2c_reset: out std_logic; --Reset line for the expander serial lines
- --Clock generator controls
- clk_gen_rst: out std_logic; --Reset line for the Si5345 clock generator (active low)
- --clk_gen_lol: in std_logic; --LOL signal. Do not use for now as it is connected to CONT_FROM_FPGA<0>
- --TLU signals for DUTs
- busy_i: in std_logic_vector(g_NUM_DUTS-1 downto 0);-- Busy lines from DUTs (active high) (busy to FPGA)
- busy_o: out std_logic_vector(g_NUM_DUTS-1 downto 0);-- Busy lines to DUTs (active high) (busy from FPGA)
- cont_i: in std_logic_vector(g_NUM_DUTS-1 downto 0); --Control lines from DUTs
- cont_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --Control lines to DUTs
- spare_i: in std_logic_vector(g_NUM_DUTS-1 downto 0); --Spare lines from DUTs
- spare_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --Spare lines to DUTs
- triggers_i: in std_logic_vector(g_NUM_DUTS-1 downto 0); --Trigger lines from DUTs
- triggers_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --Trigger lines to DUTs
- dut_clk_i: in std_logic_vector(g_NUM_DUTS-1 downto 0); --Clock from DUTs
- dut_clk_o: out std_logic_vector(g_NUM_DUTS-1 downto 0) --Clock to DUTs
-
-
- --reset_or_clk_n_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --T0 synchronization signal
- --reset_or_clk_p_o: out std_logic_vector(g_NUM_DUTS-1 downto 0);
- --shutter_to_dut_n_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --Shutter output
- --shutter_to_dut_p_o: out std_logic_vector(g_NUM_DUTS-1 downto 0);
-
- );
-
-end top_EUDET_dummy;
-
-architecture rtl of top_EUDET_dummy is
-
- signal clk_ipb, rst_ipb, nuke, soft_rst, phy_rst_e, clk_200, sysclk_40, clk_encl_buf, userled: std_logic;
- signal mac_addr: std_logic_vector(47 downto 0);
- signal ip_addr: std_logic_vector(31 downto 0);
- signal ipb_out: ipb_wbus;
- signal ipb_in: ipb_rbus;
- signal inf_leds: std_logic_vector(1 downto 0);
- signal s_i2c_scl_enb : std_logic;
- signal s_i2c_sda_enb : std_logic;
- signal encl_clock50: std_logic; -- This is a 50 MHz clock generated from the Enclustra onboard oscillator (rather than the clock input)
-
- --signal s_i2c_sda_i : std_logic;
- --signal s_i2c_scl_i : std_logic;
- ------------------------------------------
- -- Internal signal declarations
- SIGNAL T0_o : std_logic;
- SIGNAL buffer_full_o : std_logic; --! Goes high when event buffer almost full
- SIGNAL clk_8x_logic : std_logic; -- 320MHz clock
- SIGNAL clk_4x_logic : std_logic; --! normally 160MHz
- SIGNAL clk_logic_xtal : std_logic; -- ! 40MHz clock from onboard xtal
- SIGNAL data_strobe : std_logic; -- goes high when data ready to load into event buffer
- SIGNAL dout : std_logic;
- SIGNAL dout1 : std_logic;
- SIGNAL event_data : std_logic_vector(g_EVENT_DATA_WIDTH-1 DOWNTO 0);
- signal ipbww: ipb_wbus_array(N_SLAVES - 1 downto 0);
- signal ipbrr: ipb_rbus_array(N_SLAVES - 1 downto 0);
- SIGNAL logic_clocks_reset : std_logic; -- Goes high to reset counters etc. Sync with clk_4x_logic
- SIGNAL logic_reset : std_logic;
- SIGNAL overall_trigger : std_logic; --! goes high to load trigger data
- SIGNAL overall_veto : std_logic; --! Halts triggers when high
- SIGNAL postVetoTrigger_times : t_triggerTimeArray(g_NUM_TRIG_INPUTS-1 DOWNTO 0); -- ! trigger arrival time ( w.r.t. logic_strobe)
- SIGNAL postVetotrigger : std_logic_vector(g_NUM_TRIG_INPUTS-1 DOWNTO 0); -- ! High when trigger from input connector active and enabled
- --trigger_count_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Not used yet.
- SIGNAL rst_fifo_o : std_logic; --! rst signal to first level fifos
- SIGNAL s_edge_fall_times : t_triggerTimeArray(g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- Array of edge times ( w.r.t. logic_strobe)
- SIGNAL s_edge_falling : std_logic_vector(g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- ! High when falling edge
- SIGNAL s_edge_rise_times : t_triggerTimeArray(g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- Array of edge times ( w.r.t. logic_strobe)
- SIGNAL s_edge_rising : std_logic_vector(g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- ! High when rising edge
- --SIGNAL s_i2c_scl_enb : std_logic;
- --SIGNAL s_i2c_sda_enb : std_logic;
- SIGNAL s_shutter : std_logic; --! shutter signal from TimePix, retimed onto local clock
- SIGNAL s_triggerLogic_reset : std_logic;
- SIGNAL shutter_cnt_i : std_logic_vector(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0);
- SIGNAL shutter_i : std_logic;
- SIGNAL spill_cnt_i : std_logic_vector(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0);
- SIGNAL spill_i : std_logic;
- SIGNAL strobe_8x_logic : std_logic; --! Pulses one cycle every 4 of 16x clock.
- SIGNAL strobe_4x_logic : std_logic; -- one pulse every 4 cycles of clk_4x
- SIGNAL trigger_count : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0);
- type myTrigArray is array (g_NUM_DUTS-1 downto 0) of std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0);
- signal TrigNArray : myTrigArray;
- SIGNAL TriggerNumber : std_logic_vector(g_EVENT_DATA_WIDTH-1 DOWNTO 0);
- SIGNAL TriggerNumberStrobe : std_logic_vector(g_NUM_DUTS-1 downto 0);
- SIGNAL stretchFlags : std_logic_vector(g_NUM_DUTS-1 downto 0) := "0011"; -- ! define which dummyDUT have their busy line stretched
-
- SIGNAL trigger_times : t_triggerTimeArray(g_NUM_TRIG_INPUTS-1 DOWNTO 0); -- ! trigger arrival time ( w.r.t. logic_strobe)
- SIGNAL triggers : std_logic_vector(g_NUM_TRIG_INPUTS-1 DOWNTO 0);
- SIGNAL veto_o : std_logic; --! goes high when one or more DUT are busy
- signal ctrl, stat: ipb_reg_v(0 downto 0);
- --My signals
- --SIGNAL busy_toggle_o : std_logic_vector(g_NUM_DUTS-1 downto 0);
-
-----------------------------------------------
-----------------------------------------------
- component DUTInterfaces
- generic(
- g_NUM_DUTS : positive := 4;-- <- was 3
- g_IPBUS_WIDTH : positive := 32
- );
- port (
- clk_4x_logic_i : IN std_logic ;
- strobe_4x_logic_i : IN std_logic ; --! goes high every 4th clock cycle
- trigger_counter_i : IN std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0); --! Number of trigger events since last reset
- trigger_i : IN std_logic ; --! goes high when trigger logic issues a trigger
- reset_or_clk_to_dut_i : IN std_logic ; --! Synchronization signal. Passed TO DUT pins
- shutter_to_dut_i : IN std_logic ; --! Goes high TO indicate data-taking active. DUTs report busy unless ignoreShutterVeto IPBus flag is set high
- -- IPBus signals.
- ipbus_clk_i : IN std_logic ;
- ipbus_i : IN ipb_wbus ; --! Signals from IPBus core TO slave
- ipbus_reset_i : IN std_logic ;
- ipbus_o : OUT ipb_rbus ; --! signals from slave TO IPBus core
- -- Signals to/from DUT
- busy_from_dut : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! BUSY input from DUTs
- busy_to_dut : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! BUSY input to DUTs (single ended)
- clk_from_dut : IN std_logic_vector(g_NUM_DUTS-1 DOWNTO 0); --new signal for TLU, replace differential I/O
- clk_to_dut : OUT std_logic_vector(g_NUM_DUTS-1 DOWNTO 0); --new signal for TLU, replace differential I/O
- reset_to_dut: OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Replaces reset_or_clk_to_dut
- trigger_to_dut : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Trigger output
- shutter_to_dut : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Shutter output
- veto_o : OUT std_logic
- );
- end component DUTInterfaces;
-----------------------------------------------
-----------------------------------------------
- component Dummy_DUT
- Port (
- CLK : in STD_LOGIC; --! this is the USB clock.
- RST : in STD_LOGIC; --! Synchronous clock
- Trigger : in STD_LOGIC; --! Trigger from TLU
- stretchBusy: in STD_LOGIC; --! flag: if 1 extend the BUSY signal
- Busy : out STD_LOGIC; --! Busy to TLU
- DUTClk : out STD_LOGIC; --! clock from DUT
- TriggerNumber : out STD_LOGIC_VECTOR(31 downto 0);
- TriggerNumberStrobe : out STD_LOGIC;
- FSM_Error : out STD_LOGIC
- );
-end component;
-----------------------------------------------
-----------------------------------------------
-
- COMPONENT eventBuffer
- GENERIC (
- g_EVENT_DATA_WIDTH : positive := 32;
- g_IPBUS_WIDTH : positive := 32;
- g_READ_COUNTER_WIDTH : positive := 16
- );
- PORT (
- clk_4x_logic_i : IN std_logic ;
- data_strobe_i : IN std_logic ; -- Indicates data TO transfer
- event_data_i : IN std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
- ipbus_clk_i : IN std_logic ;
- ipbus_i : IN ipb_wbus ;
- ipbus_reset_i : IN std_logic ;
- strobe_4x_logic_i : IN std_logic ;
- --trigger_count_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Not used yet.
- rst_fifo_o : OUT std_logic ; --! rst signal TO first level fifos
- buffer_full_o : OUT std_logic ; --! Goes high when event buffer almost full
- ipbus_o : OUT ipb_rbus ;
- logic_reset_i : IN std_logic -- reset buffers when high. Synch withclk_4x_logic
- );
- END COMPONENT eventBuffer;
-----------------------------------------------
-----------------------------------------------
--- COMPONENT eventFormatter
--- GENERIC (
--- g_EVENT_DATA_WIDTH : positive := 64;
--- g_IPBUS_WIDTH : positive := 32;
--- g_COUNTER_TRIG_WIDTH : positive := 32;
--- g_COUNTER_WIDTH : positive := 12;
--- g_EVTTYPE_WIDTH : positive := 4; --! Width of the event type word
--- --g_NUM_INPUT_TYPES : positive := 4; -- Number of different input types (trigger, shutter, edge...)
--- g_NUM_EDGE_INPUTS : positive := 4; --! Number of edge inputs
--- g_NUM_TRIG_INPUTS : positive := 6 --! Number of trigger inputs (POSSIBLY WRONG!)
--- );
--- PORT (
--- clk_4x_logic_i : IN std_logic ; --! Rising edge active
--- ipbus_clk_i : IN std_logic ;
--- logic_strobe_i : IN std_logic ; --! Pulses high once every 4 cycles of clk_4x_logic
--- logic_reset_i : IN std_logic ; --! goes high TO reset counters. Synchronous with clk_4x_logic
--- rst_fifo_i : IN std_logic ; --! Goes high TO reset FIFOs
--- buffer_full_i : IN std_logic ; --! Goes high when output fifo full
--- trigger_i : IN std_logic ; --! goes high TO load trigger data. One cycle of clk_4x_logic
--- trigger_times_i : IN t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0); --! Array of trigger times ( w.r.t. logic_strobe)
--- trigger_inputs_fired_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0); --! high for each input that "fired"
--- trigger_cnt_i : IN std_logic_vector (g_COUNTER_TRIG_WIDTH-1 DOWNTO 0); --! Trigger count
--- shutter_i : IN std_logic ;
--- shutter_cnt_i : IN std_logic_vector (g_COUNTER_WIDTH-1 DOWNTO 0);
--- spill_i : IN std_logic ;
--- spill_cnt_i : IN std_logic_vector (g_COUNTER_WIDTH-1 DOWNTO 0);
--- edge_rise_i : IN std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0); --! High when rising edge
--- edge_fall_i : IN std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0); --! High when falling edge
--- edge_rise_time_i : IN t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0); --! Array of edge times ( w.r.t. logic_strobe)
--- edge_fall_time_i : IN t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0); --! Array of edge times ( w.r.t. logic_strobe)
--- ipbus_i : IN ipb_wbus ;
--- ipbus_o : OUT ipb_rbus ;
--- data_strobe_o : OUT std_logic ; --! goes high when data ready TO load into event buffer
--- event_data_o : OUT std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
--- reset_timestamp_i : IN std_logic ; --! Taking high causes timestamp TO be reset. Combined with internal timestmap reset and written to reset_timestamp_o
--- reset_timestamp_o : OUT std_logic --! Goes high for one clock cycle of clk_4x_logic when timestamp reset
--- );
--- END COMPONENT eventFormatter;
-----------------------------------------------
-----------------------------------------------
- COMPONENT logic_clocks
- GENERIC (
- g_USE_EXTERNAL_CLK : integer := 1
- );
- PORT (
- ipbus_clk_i : IN std_logic ;
- ipbus_i : IN ipb_wbus ;
- ipbus_reset_i : IN std_logic ;
- Reset_i : IN std_logic ;
- clk_logic_xtal_i : IN std_logic ; -- ! 40MHz clock from onboard xtal
- clk_8x_logic_o : OUT std_logic ; -- 640MHz clock
- clk_4x_logic_o : OUT std_logic ; -- 160MHz clock
- ipbus_o : OUT ipb_rbus ;
- strobe_8x_logic_o : OUT std_logic ; -- strobes once every 4 cycles of clk_16x
- strobe_4x_logic_o : OUT std_logic ; -- one pulse every 4 cycles of clk_4x
- --extclk_p_b : INOUT std_logic ; -- either external clock in, or a clock being driven out
- --extclk_n_b : INOUT std_logic ;
- DUT_clk_o : OUT std_logic ;
- logic_clocks_locked_o : OUT std_logic ;
- logic_reset_o : OUT std_logic -- Goes high TO reset counters etc. Sync with clk_4x_logic
- );
- END COMPONENT logic_clocks;
-----------------------------------------------
-
-
- COMPONENT i2c_master
- PORT (
- i2c_scl_i : IN std_logic;
- i2c_sda_i : IN std_logic;
- ipbus_clk_i : IN std_logic;
- ipbus_i : IN ipb_wbus;
- ipbus_reset_i : IN std_logic;
- i2c_scl_enb_o : OUT std_logic;
- i2c_sda_enb_o : OUT std_logic;
- ipbus_o : OUT ipb_rbus
- );
- END COMPONENT i2c_master;
-
--- component clk_wiz_0
--- port
--- (-- Clock in ports
--- clk_in1 : in std_logic;
--- -- Clock out ports
--- clk_out1 : out std_logic;
--- -- Status and control signals
--- reset : in std_logic;
--- locked : out std_logic
--- );
--- end component;
-
-
- -- Optional embedded configurations
- -- pragma synthesis_off
- FOR ALL : DUTInterfaces USE ENTITY work.DUTInterfaces;
- --FOR ALL : IPBusInterface USE ENTITY work.IPBusInterface;
- FOR ALL : T0_Shutter_Iface USE ENTITY work.T0_Shutter_Iface;
- FOR ALL : eventBuffer USE ENTITY work.eventBuffer;
- FOR ALL : eventFormatter USE ENTITY work.eventFormatter;
- FOR ALL : i2c_master USE ENTITY work.i2c_master;--
'0');
- -- ModuleWare code(v1.12) for instance 'I13' of 'gnd'
- shutter_i <= '0';
- -- ModuleWare code(v1.12) for instance 'I14' of 'gnd'
- shutter_cnt_i <= (OTHERS => '0');
- -- ModuleWare code(v1.12) for instance 'I17' of 'gnd'
- dout1 <= '0';
- -- ModuleWare code(v1.12) for instance 'I18' of 'gnd'
- dout <= '0';
- -- ModuleWare code(v1.12) for instance 'I19' of 'merge'
- --gpio_hdr <= dout1 & dout & s_shutter & T0_o;
- -- ModuleWare code(v1.12) for instance 'I8' of 'sor'
- overall_veto <= buffer_full_o OR veto_o;
- -- ModuleWare code(v1.12) for instance 'I16' of 'sor'
- s_triggerLogic_reset <= logic_reset OR T0_o;
-
- i2c_reset <= '1';
- clk_gen_rst <= '1';
- gpio <= strobe_8x_logic;
- sysclk_50_o_p <= '0';
- sysclk_50_o_n <= '0';
- --busy_o <= std_logic_vector(to_unsigned(0, busy_o'length));
- --busy_o <= '000000';
- --sysclk_40_o_p <= sysclk;
-
-------------------------------------------
- infra: entity work.enclustra_ax3_pm3_infra
- port map(
- sysclk => clk_encl_buf,
- clk_ipb_o => clk_ipb,
- rst_ipb_o => rst_ipb,
- rst_125_o => phy_rst_e,
- clk_200_o => clk_200,
- nuke => nuke,
- soft_rst => soft_rst,
- leds => inf_leds,
- rgmii_txd => rgmii_txd,
- rgmii_tx_ctl => rgmii_tx_ctl,
- rgmii_txc => rgmii_txc,
- rgmii_rxd => rgmii_rxd,
- rgmii_rx_ctl => rgmii_rx_ctl,
- rgmii_rxc => rgmii_rxc,
- mac_addr => mac_addr,
- ip_addr => ip_addr,
- ipb_in => ipb_in,
- ipb_out => ipb_out
- );
-
- --leds <= not ('0' & userled & inf_leds); -- Check this.
- phy_rstn <= not phy_rst_e;
-
--- mac_addr <= X"020ddba1151" & dip_sw; -- Careful here, arbitrary addresses do not always work
--- ip_addr <= X"c0a8c81" & dip_sw; -- 192.168.200.16+n
- mac_addr <= X"020ddba1151d"; -- Careful here, arbitrary addresses do not always work
- ip_addr <= X"c0a8c81d"; -- 192.168.200.29
-
-------------------------------------------
- I1 : entity work.ipbus_ctrlreg_v
- port map(
- clk => clk_ipb,
- reset => rst_ipb,
- ipbus_in => ipbww(N_SLV_CTRL_REG),
- ipbus_out => ipbrr(N_SLV_CTRL_REG),
- d => stat,
- q => ctrl
- );
- stat(0) <= std_logic_vector(FW_VERSION);-- <-Let's use this as firmware revision number
- soft_rst <= ctrl(0)(0);
- nuke <= ctrl(0)(1);
-
-------------------------------------------
- I2 : entity work.ipbus_fabric_sel
- generic map(
- NSLV => N_SLAVES,
- SEL_WIDTH => IPBUS_SEL_WIDTH)
- port map(
- ipb_in => ipb_out,
- ipb_out => ipb_in,
- sel => ipbus_sel_ipbus_example(ipb_out.ipb_addr),
- ipb_to_slaves => ipbww,
- ipb_from_slaves => ipbrr
- );
-
-------------------------------------------
- I3 : i2c_master
- PORT MAP (
- i2c_scl_i => i2c_scl_b,
- i2c_sda_i => i2c_sda_b,
- ipbus_clk_i => clk_ipb,
- ipbus_i => ipbww(N_SLV_I2C_0),
- ipbus_reset_i => rst_ipb,
- i2c_scl_enb_o => s_i2c_scl_enb,
- i2c_sda_enb_o => s_i2c_sda_enb,
- ipbus_o => ipbrr(N_SLV_I2C_0)
- );
-
-----------------------------------------------
- I4 : logic_clocks
- GENERIC MAP (
- g_USE_EXTERNAL_CLK => 0
- )
- PORT MAP (
- ipbus_clk_i => clk_ipb,
- ipbus_i => ipbww(N_SLV_LGCCLK),
- ipbus_reset_i => rst_ipb,
- Reset_i => logic_clocks_reset,
- clk_logic_xtal_i => sysclk_40, -- Not sure this is correct
- clk_8x_logic_o => clk_8x_logic,
- clk_4x_logic_o => clk_4x_logic,
- ipbus_o => ipbrr(N_SLV_LGCCLK),
- strobe_8x_logic_o => strobe_8x_logic,
- strobe_4x_logic_o => strobe_4x_logic,
- DUT_clk_o => open,
- logic_clocks_locked_o => leds(3),
- logic_reset_o => logic_reset
- );
-
-
-
-------------------------------------------
--- I6 : eventFormatter
--- GENERIC MAP (
--- g_EVENT_DATA_WIDTH => g_EVENT_DATA_WIDTH,
--- g_IPBUS_WIDTH => g_IPBUS_WIDTH,
--- g_COUNTER_TRIG_WIDTH => g_IPBUS_WIDTH,
--- g_COUNTER_WIDTH => 12,
--- g_EVTTYPE_WIDTH => 4, --! Width of the event type word
--- --g_NUM_INPUT_TYPES : positive := 4; -- Number of different input types (trigger, shutter, edge...)
--- g_NUM_EDGE_INPUTS => g_NUM_EDGE_INPUTS, --! Number of edge inputs
--- g_NUM_TRIG_INPUTS => g_NUM_TRIG_INPUTS --! Number of trigger inputs
--- )
--- PORT MAP (
--- clk_4x_logic_i => clk_4x_logic,
--- ipbus_clk_i => clk_ipb,
--- logic_strobe_i => strobe_4x_logic,
--- logic_reset_i => logic_reset,
--- rst_fifo_i => rst_fifo_o,
--- buffer_full_i => buffer_full_o,
--- trigger_i => overall_trigger,
--- trigger_times_i => postVetoTrigger_times,
--- trigger_inputs_fired_i => postVetotrigger,
--- trigger_cnt_i => trigger_count,
--- shutter_i => shutter_i,
--- shutter_cnt_i => shutter_cnt_i,
--- spill_i => spill_i,
--- spill_cnt_i => spill_cnt_i,
--- edge_rise_i => s_edge_rising,
--- edge_fall_i => s_edge_falling,
--- edge_rise_time_i => s_edge_rise_times,
--- edge_fall_time_i => s_edge_fall_times,
--- ipbus_i => ipbww(N_SLV_EVFMT),
--- ipbus_o => ipbrr(N_SLV_EVFMT),
--- data_strobe_o => data_strobe,
--- event_data_o => event_data,
--- reset_timestamp_i => T0_o,
--- reset_timestamp_o => OPEN
--- );
-
-------------------------------------------
- I7 : eventBuffer
- GENERIC MAP (
- g_EVENT_DATA_WIDTH => 32,
- g_IPBUS_WIDTH => g_IPBUS_WIDTH,
- g_READ_COUNTER_WIDTH => 13
-
- )
- PORT MAP (
- clk_4x_logic_i => clk_4x_logic,
- --clk_4x_logic_i => sysclk_40,
- data_strobe_i => TriggerNumberStrobe(0),
- event_data_i => TrigNArray(0),
- ipbus_clk_i => clk_ipb,
- ipbus_i => ipbww(N_SLV_EVBUF),
- ipbus_reset_i => rst_ipb,
- strobe_4x_logic_i => strobe_4x_logic,
- rst_fifo_o => rst_fifo_o,
- buffer_full_o => buffer_full_o,
- ipbus_o => ipbrr(N_SLV_EVBUF),
- logic_reset_i => logic_reset
- );
-
-
-------------------------------------------
--- I9 : DUTInterfaces
--- GENERIC MAP (
--- g_NUM_DUTS => g_NUM_DUTS,
--- g_IPBUS_WIDTH => g_IPBUS_WIDTH
--- )
--- PORT MAP (
--- clk_4x_logic_i => clk_4x_logic,
--- strobe_4x_logic_i => strobe_4x_logic,
--- trigger_counter_i => trigger_count,
--- trigger_i => overall_trigger,
--- reset_or_clk_to_dut_i => T0_o,
--- shutter_to_dut_i => s_shutter,
--- ipbus_clk_i => clk_ipb,
--- ipbus_i => ipbww(N_SLV_DUT),
--- ipbus_reset_i => rst_ipb,
--- ipbus_o => ipbrr(N_SLV_DUT),
--- busy_from_dut => busy_i,
--- busy_to_dut => open,
--- clk_from_dut => dut_clk_i,
--- clk_to_dut => dut_clk_o,
--- --reset_or_clk_to_dut_n_o => reset_or_clk_n_o,
--- --reset_or_clk_to_dut_p_o => reset_or_clk_p_o,
--- reset_to_dut => spare_o,
--- trigger_to_dut => triggers_o,
--- --shutter_to_dut_n_o => shutter_to_dut_n_o,
--- --shutter_to_dut_p_o => shutter_to_dut_p_o,
--- shutter_to_dut => cont_o,
--- veto_o => veto_o
--- );
-
-
-
--------------TEST AREA------------
--- test0: entity work.test_inToOut
--- port map(
--- clk_in => clk_200,
--- busy_in=> busy_i,
--- control_in=> cont_i,
--- trig_in=> triggers_i,
--- clkDut_in=> dut_clk_i,
--- spare_in=> spare_i,
--- busy_out=> busy_o,
--- control_out=> cont_o,
--- trig_out=> triggers_o,
--- clkDut_out=> dut_clk_o,
--- spare_out=> spare_o
--- );
-
--- dutout0: entity work.DUTs_outputs
--- port map(
--- clk_in => encl_clock50,
--- d_clk_o => dut_clk_o,
--- d_trg_o => triggers_o,
--- d_busy_o => busy_o,
--- d_cont_o => cont_o,
--- d_spare_o => spare_o
--- );
-
--- clk50_o_fromEnclustra : clk_wiz_0
--- port map (
--- -- Clock in ports
--- clk_in1 => clk_encl_buf, --sysclk_40,
--- -- Clock out ports
--- clk_out1 => encl_clock50,
--- -- Status and control signals
--- reset => '0',
--- locked => open
--- );
-
-
-----------------------------------------------
- OutBlocks:
- for iDUT in 0 to g_NUM_DUTS-1 generate
- begin
-
-
--- generate an instance of the Dummy DUT behind connector 0
- DUT_Instance: Dummy_DUT
- Port map (
- --CLK => clk_4x_logic,--160 Mhz clock
- CLK => sysclk_40,
- RST => cont_i(iDUT),-- coming from HDMI pin
- Trigger => triggers_i(iDUT), --coming from HDMI pin
- stretchBusy => stretchFlags(iDUT),
- Busy => busy_o(iDUT), --going out on HDMI pin
- DUTClk => dut_clk_o(iDUT), --going out on HDMI pin
- TriggerNumber => TrigNArray(iDUT),
- TriggerNumberStrobe => TriggerNumberStrobe(iDUT),
- FSM_Error => open
- );
-
-
-
- end generate;
-
-
-
-
-------------------------------------------
-
-
-------------------------------------------
- IBUFGDS_inst: IBUFGDS
- generic map (
- IBUF_LOW_PWR=> false
- )
- port map (
- O => sysclk_40,
- I => sysclk_40_i_p,
- IB => sysclk_40_i_n
- );
-
-------------------------------------------
- IBUFG_inst: IBUFG
- port map (
- O => clk_encl_buf,
- I => clk_enclustra--sysclk
- );
-
-
-
-
-
-
-end rtl;
diff --git a/EUDETdummy/scripts/EUDETdummy.py b/EUDETdummy/scripts/EUDETdummy.py
deleted file mode 100644
index ff9d2d9..0000000
--- a/EUDETdummy/scripts/EUDETdummy.py
+++ /dev/null
@@ -1,588 +0,0 @@
-# -*- coding: utf-8 -*-
-import uhal;
-import pprint;
-#from FmcTluI2c import *
-import time
-from I2CuHal import I2CCore
-from si5345 import si5345 # Library for clock chip
-from AD5665R import AD5665R # Library for DAC
-from PCA9539PW import PCA9539PW # Library for serial line expander
-
-class EUDETdummy:
- """docstring for TLU"""
- def __init__(self, dev_name, man_file):
- self.dev_name = dev_name
- self.manager= uhal.ConnectionManager(man_file)
- self.hw = self.manager.getDevice(self.dev_name)
- self.nDUTs= 4 #Number of DUT connectors
- self.nChannels= 6 #Number of trigger inputs
- self.VrefInt= 2.5 #Internal DAC voltage reference
- self.VrefExt= 1.3 #External DAC voltage reference
- self.intRefOn= False #Internal reference is OFF by default
-
- self.fwVersion = self.hw.getNode("version").read()
- self.hw.dispatch()
- print "EUDUMMY FIRMWARE VERSION= " , hex(self.fwVersion)
-
- # Instantiate a I2C core to configure components
- self.TLU_I2C= I2CCore(self.hw, 10, 5, "i2c_master", None)
- #self.TLU_I2C.state()
-
- enableCore= True #Only need to run this once, after power-up
- self.enableCore()
-
- # Instantiate clock chip
- self.zeClock=si5345(self.TLU_I2C, 0x68)
- res= self.zeClock.getDeviceVersion()
- self.zeClock.checkDesignID()
-
- # Instantiate DACs and configure them to use reference based on TLU setting
- self.zeDAC1=AD5665R(self.TLU_I2C, 0x13)
- self.zeDAC2=AD5665R(self.TLU_I2C, 0x1F)
- self.zeDAC1.setIntRef(self.intRefOn)
- self.zeDAC2.setIntRef(self.intRefOn)
-
- # Instantiate the serial line expanders and configure them to default values
- self.IC6=PCA9539PW(self.TLU_I2C, 0x74)
- self.IC6.setInvertReg(0, 0x00)# 0= normal, 1= inverted
- self.IC6.setIOReg(0, 0x00)# 0= output, 1= input
- self.IC6.setOutputs(0, 0x88)# If output, set to XX
-
- self.IC6.setInvertReg(1, 0x00)# 0= normal, 1= inverted
- self.IC6.setIOReg(1, 0x00)# 0= output, 1= input
- self.IC6.setOutputs(1, 0x88)# If output, set to XX
-
- self.IC7=PCA9539PW(self.TLU_I2C, 0x75)
- self.IC7.setInvertReg(0, 0x00)# 0= normal, 1= inverted
- self.IC7.setIOReg(0, 0x00)# 0= output, 1= input
- self.IC7.setOutputs(0, 0x0F)# If output, set to XX
-
- self.IC7.setInvertReg(1, 0x00)# 0= normal, 1= inverted
- self.IC7.setIOReg(1, 0x00)# 0= output, 1= input
- self.IC7.setOutputs(1, 0x50)# If output, set to XX
-
-
-##################################################################################################################################
-##################################################################################################################################
- def DUTOutputs(self, dutN, enable=False, verbose=False):
- ## Set the status of the transceivers for a specific HDMI connector. When enable= False the transceivers are disabled and the
- ## connector cannot send signals from FPGA to the outside world. When enable= True then signals from the FPGA will be sent out to the HDMI.
- ## NOTE: the other direction is always enabled, i.e. signals from the DUTs are always sent to the FPGA.
- ## NOTE: CLK direction must be defined separately using DUTClkSrc
-
- if (dutN < 0) | (dutN> (self.nDUTs-1)):
- print "\tERROR: DUTOutputs. The DUT number must be comprised between 0 and ", self.nDUTs-1
- return -1
- bank= dutN//2 # DUT0 and DUT1 are on bank 0. DUT2 and DUT3 on bank 1
- nibble= dutN%2 # DUT0 and DUT2 are on nibble 0. DUT1 and DUT3 are on nibble 1
- print " Setting DUT:", dutN, "to", enable
- if verbose:
- print "\tBank", bank, "Nibble", nibble
- res= self.IC6.getIOReg(bank)
- oldStatus= res[0]
- mask= 0xF << 4*nibble
- newStatus= oldStatus & (~mask)
- if (not enable): # we want to write 0 to activate the outputs so check opposite of "enable"
- newStatus |= mask
- if verbose:
- print "\tOldStatus= ", "{0:#0{1}x}".format(oldStatus,4), "Mask=" , hex(mask), "newStatus=", "{0:#0{1}x}".format(newStatus,4)
- self.IC6.setIOReg(bank, newStatus)
- return newStatus
-
- def DUTClkSrc(self, dutN, clkSrc=0, verbose= False):
- ## Allows to choose the source of the clock signal sent to the DUTs over HDMI
- ## clkSrc= 0: clock disabled
- ## clkSrc= 1: clock from Si5345
- ## clkSrc=2: clock from FPGA
- if (dutN < 0) | (dutN> (self.nDUTs-1)):
- print "\tERROR: DUTClkSrc. The DUT number must be comprised between 0 and ", self.nDUTs-1
- return -1
- if (clkSrc < 0) | (clkSrc> 2):
- print "\tERROR: DUTClkSrc. clkSrc can only be 0 (disabled), 1 (Si5345) or 2 (FPGA)"
- return -1
- bank=0
- maskLow= 1 << (1* dutN) #CLK FROM FPGA
- maskHigh= 1<< (1* dutN +4) #CLK FROM Si5345
- mask= maskLow | maskHigh
- res= self.IC7.getIOReg(bank)
- oldStatus= res[0]
- newStatus= oldStatus & ~mask #set both bits to zero
- outStat= ""
- if clkSrc==0:
- newStatus = newStatus | mask
- outStat= "disabled"
- elif clkSrc==1:
- newStatus = newStatus | maskLow
- outStat= "Si5435"
- elif clkSrc==2:
- newStatus= newStatus | maskHigh
- outStat= "FPGA"
- print " Setting DUT:", dutN, "clock source to", outStat
- if verbose:
- print "\tOldStatus= ", "{0:#0{1}x}".format(oldStatus,4), "Mask=" , hex(mask), "newStatus=", "{0:#0{1}x}".format(newStatus,4)
- self.IC7.setIOReg(bank, newStatus)
- return newStatus
-
- def enableClkLEMO(self, enable= False, verbose= False):
- ## Enable or disable the output clock to the differential LEMO output
- bank=1
- mask= 0x10
- res= self.IC7.getIOReg(bank)
- oldStatus= res[0]
- newStatus= oldStatus & ~mask
- outStat= "enabled"
- if (not enable): #A 0 activates the output. A 1 disables it.
- newStatus= newStatus | mask
- outStat= "disabled"
- print " Clk LEMO", outStat
- if verbose:
- print "\tOldStatus= ", "{0:#0{1}x}".format(oldStatus,4), "Mask=" , hex(mask), "newStatus=", "{0:#0{1}x}".format(newStatus,4)
- self.IC7.setIOReg(bank, newStatus)
- return newStatus
-
- def enableCore(self):
- ## At power up the Enclustra I2C lines are disabled (tristate buffer is off).
- ## This function enables the lines. It is only required once.
- mystop=True
- print " Enabling I2C bus (expect 127):"
- myslave= 0x21
- mycmd= [0x01, 0x7F]
- nwords= 1
- self.TLU_I2C.write(myslave, mycmd, mystop)
-
- mystop=False
- mycmd= [0x01]
- self.TLU_I2C.write(myslave, mycmd, mystop)
- res= self.TLU_I2C.read( myslave, nwords)
- print "\tPost RegDir: ", res
-
- def getAllChannelsCounts(self):
- chCounts=[]
- for ch in range (0,self.nChannels):
- chCounts.append(int(self.getChCount(ch)))
- return chCounts
-
- def getChStatus(self):
- inputStatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
- self.hw.dispatch()
- print "\tInput status= " , hex(inputStatus)
- return inputStatus
-
- def getChCount(self, channel):
- regString= "triggerInputs.ThrCount"+ str(channel)+"R"
- count = self.hw.getNode(regString).read()
- self.hw.dispatch()
- print "\tCh", channel, "Count:" , count
- return count
-
- def getClockStatus(self):
- clockStatus = self.hw.getNode("logic_clocks.LogicClocksCSR").read()
- self.hw.dispatch()
- print " CLOCK STATUS [expected 1]"
- print "\t", hex(clockStatus)
- if ( clockStatus == 0 ):
- "ERROR: Clocks in EUDUMMY FPGA are not locked."
- return clockStatus
-
- def getDUTmask(self):
- DUTMaskR = self.hw.getNode("DUTInterfaces.DutMaskR").read()
- self.hw.dispatch()
- print "\tDUTMask read back as:" , hex(DUTMaskR)
- return DUTMaskR
-
- def getExternalVeto(self):
- extVeto= self.hw.getNode("triggerLogic.ExternalTriggerVetoR").read()
- self.hw.dispatch()
- print "\tEXTERNAL Veto read back as:", hex(extVeto)
- return extVeto
-
- def getFifoData(self, nWords):
- #fifoData= self.hw.getNode("eventBuffer.EventFifoData").read()
- fifoData= self.hw.getNode("eventBuffer.EventFifoData").readBlock (nWords);
- self.hw.dispatch()
- #print "\tFIFO Data:", hex(fifoData)
- return fifoData
-
- def getFifoLevel(self):
- FifoFill= self.hw.getNode("eventBuffer.EventFifoFillLevel").read()
- self.hw.dispatch()
- print "\tFIFO level read back as:", hex(FifoFill)
- return FifoFill
-
- def getFifoCSR(self):
- FifoCSR= self.hw.getNode("eventBuffer.EventFifoCSR").read()
- self.hw.dispatch()
- print "\tFIFO CSR read back as:", hex(FifoCSR)
- return FifoCSR
-
- def getInternalTrg(self):
- trigIntervalR = self.hw.getNode("triggerLogic.InternalTriggerIntervalR").read()
- self.hw.dispatch()
- print "\tTrigger frequency read back as:", trigIntervalR, "Hz"
- return trigIntervalR
-
- def getMode(self):
- DUTInterfaceModeR = self.hw.getNode("DUTInterfaces.DUTInterfaceModeR").read()
- self.hw.dispatch()
- print "\tDUT mode read back as:" , hex(DUTInterfaceModeR)
- return DUTInterfaceModeR
-
- def getModeModifier(self):
- DUTInterfaceModeModifierR = self.hw.getNode("DUTInterfaces.DUTInterfaceModeModifierR").read()
- self.hw.dispatch()
- print "\tDUT mode modifier read back as:" , hex(DUTInterfaceModeModifierR)
- return DUTInterfaceModeModifierR
-
- def getSN(self):
- epromcontent=self.readEEPROM(0xfa, 6)
- print " EUDET dummy serial number (EEPROM):"
- result="\t"
- for iaddr in epromcontent:
- result+="%02x "%(iaddr)
- print result
- return epromcontent
-
- def getPostVetoTrg(self):
- triggerN = self.hw.getNode("triggerLogic.PostVetoTriggersR").read()
- self.hw.dispatch()
- print "\tPOST VETO TRIGGER NUMBER:", (triggerN)
- return triggerN
-
- def getPulseDelay(self):
- pulseDelayR = self.hw.getNode("triggerLogic.PulseDelayR").read()
- self.hw.dispatch()
- print "\tPulse delay read back as:", hex(pulseDelayR)
- return pulseDelayR
-
- def getPulseStretch(self):
- pulseStretchR = self.hw.getNode("triggerLogic.PulseStretchR").read()
- self.hw.dispatch()
- print "\tPulse stretch read back as:", hex(pulseStretchR)
- return pulseStretchR
-
- def getRecordDataStatus(self):
- RecordStatus= self.hw.getNode("Event_Formatter.Enable_Record_Data").read()
- self.hw.dispatch()
- print "\tData recording:", RecordStatus
- return RecordStatus
-
- def getTriggerVetoStatus(self):
- trgVetoStatus= self.hw.getNode("triggerLogic.TriggerVetoR").read()
- self.hw.dispatch()
- print "\tTrigger veto status read back as:", trgVetoStatus
- return trgVetoStatus
-
- def getTrgPattern(self):
- triggerPattern_low = self.hw.getNode("triggerLogic.TriggerPattern_lowR").read()
- triggerPattern_high = self.hw.getNode("triggerLogic.TriggerPattern_highR").read()
- self.hw.dispatch()
- print "\tTrigger pattern read back as: 0x%08X 0x%08X" %(triggerPattern_high, triggerPattern_low)
- return triggerPattern_low, triggerPattern_high
-
- def getVetoDUT(self):
- IgnoreDUTBusyR = self.hw.getNode("DUTInterfaces.IgnoreDUTBusyR").read()
- self.hw.dispatch()
- print "\tIgnoreDUTBusy read back as:" , hex(IgnoreDUTBusyR)
- return IgnoreDUTBusyR
-
- def getVetoShutters(self):
- IgnoreShutterVeto = self.hw.getNode("DUTInterfaces.IgnoreShutterVetoR").read()
- self.hw.dispatch()
- print "\tIgnoreShutterVeto read back as:" , IgnoreShutterVeto
- return IgnoreShutterVeto
-
- def pulseT0(self):
- cmd = int("0x1",16)
- self.hw.getNode("Shutter.PulseT0").write(cmd)
- self.hw.dispatch()
- print "\tPulsing T0"
-
- def readEEPROM(self, startadd, bytes):
- mystop= 1
- time.sleep(0.1)
- myaddr= [startadd]#0xfa
- self.TLU_I2C.write( 0x50, [startadd], mystop)
- res= self.TLU_I2C.read( 0x50, bytes)
- return res
-
- def resetClock(self):
- # Set the RST pin from the PLL to 1
- print " Clocks reset"
- cmd = int("0x1",16)
- self.hw.getNode("logic_clocks.LogicRst").write(cmd)
- self.hw.dispatch()
-
- def resetClocks(self):
- #Reset clock PLL
- self.resetClock()
- #Get clock status after reset
- self.getClockStatus()
- #Restore clock PLL
- self.restoreClock()
- #Get clock status after restore
- self.getClockStatus()
- #Get serdes status
- self.getChStatus()
-
- def resetCounters(self):
- cmd = int("0x2", 16) #write 0x2 to reset
- self.hw.getNode("triggerInputs.SerdesRstW").write(cmd)
- restatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
- self.hw.dispatch()
- cmd = int("0x0", 16) #write 0x2 to reset
- self.hw.getNode("triggerInputs.SerdesRstW").write(cmd)
- restatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
- self.hw.dispatch()
- #print "Trigger Reset: 0x%X" % restatus
- print "\tTrigger counters reset"
-
- def resetSerdes(self):
- cmd = int("0x3",16)
- self.setChStatus(cmd)
- inputStatus= self.getChStatus()
- print "\t Input status during reset = " , hex(inputStatus)
-
- cmd = int("0x0",16)
- self.setChStatus(cmd)
- inputStatus= self.getChStatus()
- print "\t Input status after reset = " , hex(inputStatus)
-
- cmd = int("0x4",16)
- self.setChStatus(cmd)
- inputStatus= self.getChStatus()
- print "\t Input status during calibration = " , hex(inputStatus)
-
- cmd = int("0x0",16)
- self.setChStatus(cmd)
- inputStatus= self.getChStatus()
- print "\t Input status after calibration = " , hex(inputStatus)
-
- def restoreClock(self):
- # Set the RST pin from the PLL to 0
- print " Clocks restore"
- cmd = int("0x0",16)
- self.hw.getNode("logic_clocks.LogicRst").write(cmd)
- self.hw.dispatch()
-
- def setChStatus(self, cmd):
- self.hw.getNode("triggerInputs.SerdesRstW").write(cmd)
- inputStatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
- self.hw.dispatch()
- print " INPUT STATUS SET TO= " , hex(inputStatus)
-
- def setClockStatus(self, cmd):
- # Only use this for testing. The clock source is actually selected in the Si5345.
- self.hw.getNode("logic_clocks.LogicClocksCSR").write(cmd)
- self.hw.dispatch()
-
- def setDUTmask(self, DUTMask):
- print " DUT MASK ENABLING: Mask= " , hex(DUTMask)
- self.hw.getNode("DUTInterfaces.DutMaskW").write(DUTMask)
- self.hw.dispatch()
- self.getDUTmask()
-
- def setFifoCSR(self, cmd):
- self.hw.getNode("eventBuffer.EventFifoCSR").write(cmd)
- self.hw.dispatch()
- self.getFifoCSR()
-
- def setInternalTrg(self, triggerInterval):
- print " TRIGGERS INTERNAL:"
- if triggerInterval == 0:
- internalTriggerFreq = 0
- print "\tdisabled"
- else:
- internalTriggerFreq = 160000.0/triggerInterval
- print "\t Setting:", internalTriggerFreq, "Hz"
- self.hw.getNode("triggerLogic.InternalTriggerIntervalW").write(int(internalTriggerFreq))
- self.hw.dispatch()
- self.getInternalTrg()
-
- def setMode(self, mode):
- print " DUT MODE SET TO: ", hex(mode)
- self.hw.getNode("DUTInterfaces.DUTInterfaceModeW").write(mode)
- self.hw.dispatch()
- self.getMode()
-
- def setModeModifier(self, modifier):
- print " DUT MODE MODIFIER:", hex(modifier)
- self.hw.getNode("DUTInterfaces.DUTInterfaceModeModifierW").write(modifier)
- self.hw.dispatch()
- self.getModeModifier()
-
- def setPulseDelay(self, pulseDelay):
- print " TRIGGER DELAY SET TO", hex(pulseDelay), "[Units= 160MHz clock, 5-bit values (one per input) packed in to 32-bit word]"
- self.hw.getNode("triggerLogic.PulseDelayW").write(pulseDelay)
- self.hw.dispatch()
- self.getPulseDelay()
-
- def setPulseStretch(self, pulseStretch):
- print " INPUT COINCIDENCE WINDOW SET TO", hex(pulseStretch) ,"[Units= 160MHz clock cycles, 5-bit values (one per input) packed in to 32-bit word]"
- self.hw.getNode("triggerLogic.PulseStretchW").write(pulseStretch)
- self.hw.dispatch()
- self.getPulseStretch()
-
- def setRecordDataStatus(self, status=False):
- print " Data recording set:"
- self.hw.getNode("Event_Formatter.Enable_Record_Data").write(status)
- self.hw.dispatch()
- self.getRecordDataStatus()
-
- def setTriggerVetoStatus(self, status=False):
- self.hw.getNode("triggerLogic.TriggerVetoW").write(status)
- self.hw.dispatch()
- self.getTriggerVetoStatus()
-
- def setTrgPattern(self, triggerPatternH, triggerPatternL):
- triggerPatternL &= 0xffffffff
- triggerPatternH &= 0xffffffff
- print " TRIGGER PATTERN (for external triggers) SET TO 0x%08X 0x%08X. Two 32-bit words." %(triggerPatternH, triggerPatternL)
- self.hw.getNode("triggerLogic.TriggerPattern_lowW").write(triggerPatternL)
- self.hw.getNode("triggerLogic.TriggerPattern_highW").write(triggerPatternH)
- self.hw.dispatch()
- self.getTrgPattern()
-
- def setVetoDUT(self, ignoreDUTBusy):
- print " VETO IGNORE BY DUT BUSY MASK SET TO" , hex(ignoreDUTBusy)
- self.hw.getNode("DUTInterfaces.IgnoreDUTBusyW").write(ignoreDUTBusy)
- self.hw.dispatch()
- self.getVetoDUT()
-
- def setVetoShutters(self, newState):
- if newState:
- print " IgnoreShutterVetoW SET TO LISTEN FOR VETO FROM SHUTTER"
- cmd= int("0x0",16)
- else:
- print " IgnoreShutterVetoW SET TO IGNORE VETO FROM SHUTTER"
- cmd= int("0x1",16)
- self.hw.getNode("DUTInterfaces.IgnoreShutterVetoW").write(cmd)
- self.hw.dispatch()
- self.getVetoShutters()
-
- def writeThreshold(self, DACtarget, Vtarget, channel):
- #Writes the threshold. The DAC voltage differs from the threshold voltage because
- #the range is shifted to be symmetrical around 0V.
-
- #Check if the DACs are using the internal reference
- if (self.intRefOn):
- Vref= self.VrefInt
- else:
- Vref= self.VrefExt
-
- #Calculate offset voltage (because of the following shifter)
- Vdac= ( Vtarget + Vref ) / 2
- print" THRESHOLD setting:"
- if channel==7:
- print "\tCH: ALL"
- else:
- print "\tCH:", channel
- print "\tTarget V:", Vtarget
- dacValue = 0xFFFF * (Vdac / Vref)
- DACtarget.writeDAC(int(dacValue), channel, True)
-
- def parseFifoData(self, fifoData, nEvents, verbose):
- #for index in range(0, len(fifoData)-1, 6):
- outList= []
- for index in range(0, (nEvents)*6, 6):
- word0= (fifoData[index] << 32) + fifoData[index + 1]
- word1= (fifoData[index + 2] << 32) + fifoData[index + 3]
- word2= (fifoData[index + 4] << 32) + fifoData[index + 5]
- evType= (fifoData[index] & 0xF0000000) >> 28
- inTrig= (fifoData[index] & 0x0FFF0000) >> 16
- tStamp= ((fifoData[index] & 0x0000FFFF) << 32) + fifoData[index + 1]
- fineTs= fifoData[index + 2]
- evNum= fifoData[index + 3]
- fineTsList=[-1]*12
- fineTsList[3]= (fineTs & 0x000000FF)
- fineTsList[2]= (fineTs & 0x0000FF00) >> 8
- fineTsList[1]= (fineTs & 0x00FF0000) >> 16
- fineTsList[0]= (fineTs & 0xFF000000) >> 24
- fineTsList[7]= (fifoData[index + 4] & 0x000000FF)
- fineTsList[6]= (fifoData[index + 4] & 0x0000FF00) >> 8
- fineTsList[5]= (fifoData[index + 4] & 0x00FF0000) >> 16
- fineTsList[4]= (fifoData[index + 4] & 0xFF000000) >> 24
- fineTsList[11]= (fifoData[index + 5] & 0x000000FF)
- fineTsList[10]= (fifoData[index + 5] & 0x0000FF00) >> 8
- fineTsList[9]= (fifoData[index + 5] & 0x00FF0000) >> 16
- fineTsList[8]= (fifoData[index + 5] & 0xFF000000) >> 24
- if verbose:
- print "====== EVENT", evNum, "================================================="
- print "[", hex(word0), "]", "\t TYPE", hex(evType), "\t TRIGGER", hex(inTrig), "\t TIMESTAMP", (tStamp)
- print "[",hex(word1), "]", "\tEV NUM", evNum, "\tFINETS[0,3]", hex(fineTs)
- print "[",hex(word2), "]", "\tFINETS[4,11]", hex(word2)
- print fineTsList
- fineTsList.insert(0, tStamp)
- fineTsList.insert(0, evNum)
- #print fineTsList
- outList.insert(len(outList), fineTsList)
- printdata= False
- if (printdata):
- print "=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-="
- print "EN#\tCOARSE_TS\tFINE_TS0...FINE_TS11"
- pprint.pprint(outList)
- return outList
-
-
-
-
-##################################################################################################################################
-##################################################################################################################################
-
- def initialize(self):
- print "\nEUDUMMY INITIALIZING..."
-
- # We need to pass it listenForTelescopeShutter , pulseDelay , pulseStretch , triggerPattern , DUTMask , ignoreDUTBusy , triggerInterval , thresholdVoltage
-
- #READ CONTENT OF EPROM VIA I2C
- self.getSN()
-
-
- #
- # #SET DACs
- targetV= -0.12
- DACchannel= 7
- self.writeThreshold(self.zeDAC1, targetV, DACchannel, )
- self.writeThreshold(self.zeDAC2, targetV, DACchannel, )
-
- #
- # #ENABLE/DISABLE HDMI OUTPUTS
- #self.DUTOutputs(0, True, False)
- #self.DUTOutputs(1, True, False)
- #self.DUTOutputs(2, True, False)
- #self.DUTOutputs(3, True, False)
-
- ## ENABLE/DISABLE LEMO CLOCK OUTPUT
- #self.enableClkLEMO(True, False)
-
- #
- # #Check clock status
- self.getClockStatus()
-
- resetClocks = 0
- resetSerdes = 0
- resetCounters= 0
- if resetClocks:
- self.resetClocks()
- self.getClockStatus()
- if resetSerdes:
- self.resetSerdes()
- if resetCounters:
- self.resetCounters()
-
-
-
- print "EUDUMMY INITIALIZED"
-
-##################################################################################################################################
-##################################################################################################################################
- def start(self, logtimestamps=False):
- print "EUDUMMY STARTING..."
-
- print " EUDUMMY RUNNING"
-
-##################################################################################################################################
-##################################################################################################################################
- def stop(self):
- print "EUDUMMY STOPPING..."
-
- print " EUDUMMY STOPPED"
diff --git a/EUDETdummy/scripts/EUDETdummyconnection.xml b/EUDETdummy/scripts/EUDETdummyconnection.xml
deleted file mode 100644
index 6084306..0000000
--- a/EUDETdummy/scripts/EUDETdummyconnection.xml
+++ /dev/null
@@ -1,6 +0,0 @@
-
-
-
-
-
diff --git a/EUDETdummy/scripts/EUDummy_testscript.py b/EUDETdummy/scripts/EUDummy_testscript.py
deleted file mode 100644
index 5c7d7e3..0000000
--- a/EUDETdummy/scripts/EUDummy_testscript.py
+++ /dev/null
@@ -1,155 +0,0 @@
-# -*- coding: utf-8 -*-
-import uhal
-from I2CuHal import I2CCore
-import time
-#import miniTLU
-from si5345 import si5345
-from AD5665R import AD5665R
-from PCA9539PW import PCA9539PW
-from E24AA025E48T import E24AA025E48T
-
-manager = uhal.ConnectionManager("file://./EUDETdummyconnection.xml")
-hw = manager.getDevice("eudummy")
-
-# hw.getNode("A").write(255)
-reg = hw.getNode("version").read()
-hw.dispatch()
-print "CHECK REG= ", hex(reg)
-
-
-# #First I2C core
-print ("Instantiating master I2C core:")
-master_I2C= I2CCore(hw, 10, 5, "i2c_master", None)
-master_I2C.state()
-
-
-
-
-#
-# #######################################
-enableCore= True #Only need to run this once, after power-up
-if (enableCore):
- mystop=True
- print " Write RegDir to set I/O[7] to output:"
- myslave= 0x21
- mycmd= [0x01, 0x7F]
- nwords= 1
- master_I2C.write(myslave, mycmd, mystop)
-
-
- mystop=False
- mycmd= [0x01]
- master_I2C.write(myslave, mycmd, mystop)
- res= master_I2C.read( myslave, nwords)
- print "\tPost RegDir: ", res
-# #######################################
-#
-# time.sleep(0.1)
-# #Read the EPROM
-# mystop=False
-# nwords=6
-# myslave= 0x53 #DUNE EPROM 0x53 (Possibly)
-# myaddr= [0xfa]#0xfa
-# master_I2C.write( myslave, myaddr, mystop)
-# #res= master_I2C.read( 0x50, 6)
-# res= master_I2C.read( myslave, nwords)
-# print " PCB EPROM: "
-# result="\t "
-# for iaddr in res:
-# result+="%02x "%(iaddr)
-# print result
-# #######################################
-
-
-#CLOCK CONFIGURATION BEGIN
-zeClock=si5345(master_I2C, 0x68)
-res= zeClock.getDeviceVersion()
-zeClock.checkDesignID()
-#zeClock.setPage(0, True)
-#zeClock.getPage(True)
-clkRegList= zeClock.parse_clk("./../../bitFiles/TLU_CLK_Config.txt")
-zeClock.writeConfiguration(clkRegList)######
-zeClock.writeRegister(0x0536, [0x0B]) #Configures manual switch of inputs
-zeClock.writeRegister(0x0949, [0x0F]) #Enable all inputs
-zeClock.writeRegister(0x052A, [0x05]) #Configures source of input
-iopower= zeClock.readRegister(0x0949, 1)
-print " Clock IO power: 0x%X" % iopower[0]
-lol= zeClock.readRegister(0x000E, 1)
-print " Clock LOL: 0x%X" % lol[0]
-los= zeClock.readRegister(0x000D, 1)
-print " Clock LOS: 0x%X" % los[0]
-#CLOCK CONFIGURATION END
-
-#DAC CONFIGURATION BEGIN
-zeDAC1=AD5665R(master_I2C, 0x13)
-zeDAC1.setIntRef(intRef= False, verbose= True)
-zeDAC1.writeDAC(0x0, 7, verbose= True)#7626
-
-zeDAC2=AD5665R(master_I2C, 0x1F)
-zeDAC2.setIntRef(intRef= False, verbose= True)
-zeDAC2.writeDAC(0x2fff, 3, verbose= True)
-#DAC CONFIGURATION END
-
-#EEPROM BEGIN
-zeEEPROM= E24AA025E48T(master_I2C, 0x50)
-res=zeEEPROM.readEEPROM(0xfa, 6)
-result=" EEPROM ID:\n\t"
-for iaddr in res:
- result+="%02x "%(iaddr)
-print result
-#EEPROM END
-
-# #I2C EXPANDER CONFIGURATION BEGIN
-IC6=PCA9539PW(master_I2C, 0x74)
-#BANK 0
-IC6.setInvertReg(0, 0x00)# 0= normal
-IC6.setIOReg(0, 0xF7)# 0= output <<<<<<<<<<<<<<<<<<<
-IC6.setOutputs(0, 0xFF)
-res= IC6.getInputs(0)
-print "IC6 read back bank 0: 0x%X" % res[0]
-#
-#BANK 1
-IC6.setInvertReg(1, 0x00)# 0= normal
-IC6.setIOReg(1, 0xFF)# 0= output <<<<<<<<<<<<<<<<<<<
-IC6.setOutputs(1, 0xFF)
-res= IC6.getInputs(1)
-print "IC6 read back bank 1: 0x%X" % res[0]
-
-# # #
-IC7=PCA9539PW(master_I2C, 0x75)
-#BANK 0
-IC7.setInvertReg(0, 0xFF)# 0= normal
-IC7.setIOReg(0, 0xFA)# 0= output <<<<<<<<<<<<<<<<<<<
-IC7.setOutputs(0, 0xFF)
-res= IC7.getInputs(0)
-print "IC7 read back bank 0: 0x%X" % res[0]
-#
-#BANK 1
-IC7.setInvertReg(1, 0x00)# 0= normal
-IC7.setIOReg(1, 0x0F)# 0= output <<<<<<<<<<<<<<<<<<<
-IC7.setOutputs(1, 0xFF)
-res= IC7.getInputs(1)
-print "IC7 read back bank 1: 0x%X" % res[0]
-# #I2C EXPANDER CONFIGURATION END
-
-
-# #Reset counters
-#cmd = int("0x0", 16) #write 0x2 to reset
-#hw.getNode("triggerInputs.SerdesRstW").write(cmd)
-#restatus= hw.getNode("triggerInputs.SerdesRstR").read()
-#hw.dispatch()
-#print "Trigger Reset: 0x%X" % restatus
-## #Read trigger inputs
-#myreg= [-1, -1, -1, -1, -1, -1]
-#for inputN in range(0, 6):
-# regString= "triggerInputs.ThrCount%dR" % inputN
-# myreg[inputN]= hw.getNode(regString).read()
-# hw.dispatch()
-# print regString, myreg[inputN]
-
-## Read ev formatter
-#cmd = int("0x0", 16) #
-##hw.getNode("Event_Formatter.Enable_Record_Data").write(cmd)
-#efstatus= hw.getNode("Event_Formatter.CurrentTimestampLR").read()
-#hw.dispatch()
-#print "Event Formatter Record: 0x%X" % efstatus
diff --git a/EUDETdummy/scripts/initTLU.py b/EUDETdummy/scripts/initTLU.py
deleted file mode 100644
index eb1ae65..0000000
--- a/EUDETdummy/scripts/initTLU.py
+++ /dev/null
@@ -1,184 +0,0 @@
-#
-# Function to initialize TLU
-#
-# David Cussans, October 2015
-#
-# Nasty hack - use both PyChips and uHAL ( for block read ... )
-
-from PyChipsUser import *
-from FmcTluI2c import *
-
-import uhal
-
-import sys
-import time
-
-def startTLU( uhalDevice , pychipsBoard , writeTimestamps):
-
- print "RESETTING FIFO"
- pychipsBoard.write("EventFifoCSR",0x2)
- eventFifoFillLevel = pychipsBoard.read("EventFifoFillLevel")
- print "FIFO FILL LEVEL AFTER RESET= " , eventFifoFillLevel
-
-
- if writeTimestamps:
- print "ENABLING DATA RECORDING"
- pychipsBoard.write("Enable_Record_Data",1)
- else:
- print "Disabling data recording"
- pychipsBoard.write("Enable_Record_Data",0)
-
- print "Pulsing T0"
- pychipsBoard.write("PulseT0",1)
-
- print "Turning off software trigger veto"
- pychipsBoard.write("TriggerVetoW",0)
-
- print "TLU is running"
-
-
-def stopTLU( uhalDevice , pychipsBoard ):
-
- print "Turning on software trigger veto"
- pychipsBoard.write("TriggerVetoW",1)
-
- print "TLU triggers are stopped"
-
-def initTLU( uhalDevice , pychipsBoard , listenForTelescopeShutter , pulseDelay , pulseStretch , triggerPattern , DUTMask , ignoreDUTBusy , triggerInterval , thresholdVoltage ):
-
- print "SETTING UP AIDA TLU"
-
- fwVersion = uhalDevice.getNode("version").read()
- uhalDevice.dispatch()
- print "\tVersion (uHAL)= " , hex(fwVersion)
-
- print "\tTurning on software trigger veto"
- pychipsBoard.write("TriggerVetoW",1)
-
- # Check the bus for I2C devices
- pychipsBoardi2c = FmcTluI2c(pychipsBoard)
-
- print "\tScanning I2C bus:"
- scanResults = pychipsBoardi2c.i2c_scan()
- #print scanResults
- print '\t', ', '.join(scanResults), '\n'
-
- boardId = pychipsBoardi2c.get_serial_number()
- print "\tFMC-TLU serial number= " , boardId
-
- resetClocks = 0
- resetSerdes = 0
-
-# set DACs to -200mV
- print "\tSETTING ALL DAC THRESHOLDS TO" , thresholdVoltage , "V"
- pychipsBoardi2c.set_threshold_voltage(7, thresholdVoltage)
-
- clockStatus = pychipsBoard.read("LogicClocksCSR")
- print "\tCLOCK STATUS (should be 3 if all clocks locked)= " , hex(clockStatus)
- assert ( clockStatus == 3 ) , "Clocks in TLU FPGA are not locked. No point in continuing. Re-prgramme or power cycle board"
-
- if resetClocks:
- print "Resetting clocks"
- pychipsBoard.write("LogicRst", 1 )
-
- clockStatus = pychipsBoard.read("LogicClocksCSR")
- print "Clock status after reset = " , hex(clockStatus)
-
- inputStatus = pychipsBoard.read("SerdesRstR")
- print "Input status = " , hex(inputStatus)
-
- if resetSerdes:
- pychipsBoard.write("SerdesRstW", 0x00000003 )
- inputStatus = pychipsBoard.read("SerdesRstR")
- print "Input status during reset = " , hex(inputStatus)
-
- pychipsBoard.write("SerdesRstW", 0x00000000 )
- inputStatus = pychipsBoard.read("SerdesRstR")
- print "Input status after reset = " , hex(inputStatus)
-
- pychipsBoard.write("SerdesRstW", 0x00000004 )
- inputStatus = pychipsBoard.read("SerdesRstR")
- print "Input status during calibration = " , hex(inputStatus)
-
- pychipsBoard.write("SerdesRstW", 0x00000000 )
- inputStatus = pychipsBoard.read("SerdesRstR")
- print "Input status after calibration = " , hex(inputStatus)
-
-
- inputStatus = pychipsBoard.read("SerdesRstR")
- print "\tINPUT STATUS= " , hex(inputStatus)
-
- count0 = pychipsBoard.read("ThrCount0R")
- print "\t Count 0= " , count0
-
- count1 = pychipsBoard.read("ThrCount1R")
- print "\t Count 1= " , count1
-
- count2 = pychipsBoard.read("ThrCount2R")
- print "\t Count 2= " , count2
-
- count3 = pychipsBoard.read("ThrCount3R")
- print "\t Count 3= " , count3
-
-# Stop internal triggers until setup complete
- pychipsBoard.write("InternalTriggerIntervalW",0)
-
- print "\tSETTING INPUT COINCIDENCE WINDOW TO",pulseStretch,"[Units= 160MHz clock cycles, Four 5-bit values (one per input) packed in to 32-bit word]"
- pychipsBoard.write("PulseStretchW",int(pulseStretch))
- pulseStretchR = pychipsBoard.read("PulseStretchR")
- print "\t Pulse stretch read back as:", hex(pulseStretchR)
- # assert (int(pulseStretch) == pulseStretchR) , "Pulse stretch read-back doesn't equal written value"
-
- print "\tSETTING INPUT TRIGGER DELAY TO",pulseDelay , "[Units= 160MHz clock cycles, Four 5-bit values (one per input) packed in to 32-bit word]"
- pychipsBoard.write("PulseDelayW",int(pulseDelay))
- pulseDelayR = pychipsBoard.read("PulseDelayR")
- print "\t Pulse delay read back as:", hex(pulseDelayR)
-
- print "\tSETTING TRIGGER PATTERN (for external triggers) TO 0x%08X. Two 16-bit patterns packed into 32 bit word " %(triggerPattern)
- pychipsBoard.write("TriggerPatternW",int(triggerPattern))
- triggerPatternR = pychipsBoard.read("TriggerPatternR")
- print "\t Trigger pattern read back as: 0x%08X " % (triggerPatternR)
-
- print "\tENABLING DUT(s): Mask= " , hex(DUTMask)
- pychipsBoard.write("DUTMaskW",int(DUTMask))
- DUTMaskR = pychipsBoard.read("DUTMaskR")
- print "\t DUTMask read back as:" , hex(DUTMaskR)
-
- print "\tSETTING ALL DUTs IN AIDA MODE"
- pychipsBoard.write("DUTInterfaceModeW", 0xFF)
- DUTInterfaceModeR = pychipsBoard.read("DUTInterfaceModeR")
- print "\t DUT mode read back as:" , DUTInterfaceModeR
-
- print "\tSET DUT MODE MODIFIER"
- pychipsBoard.write("DUTInterfaceModeModifierW", 0xFF)
- DUTInterfaceModeModifierR = pychipsBoard.read("DUTInterfaceModeModifierR")
- print "\t DUT mode modifier read back as:" , DUTInterfaceModeModifierR
-
- if listenForTelescopeShutter:
- print "\tSET IgnoreShutterVetoW TO LISTEN FOR VETO FROM SHUTTER"
- pychipsBoard.write("IgnoreShutterVetoW",0)
- else:
- print "\tSET IgnoreShutterVetoW TO IGNORE VETO FROM SHUTTER"
- pychipsBoard.write("IgnoreShutterVetoW",1)
- IgnoreShutterVeto = pychipsBoard.read("IgnoreShutterVetoR")
- print "\t IgnoreShutterVeto read back as:" , IgnoreShutterVeto
-
- print "\tSETTING IGNORE VETO BY DUT BUSY MASK TO" , hex(ignoreDUTBusy)
- pychipsBoard.write("IgnoreDUTBusyW",int(ignoreDUTBusy))
- IgnoreDUTBusy = pychipsBoard.read("IgnoreDUTBusyR")
- print "\t IgnoreDUTBusy read back as:" , hex(IgnoreDUTBusy)
-
-#print "Enabling handshake: No-handshake"
-#board.write("HandshakeTypeW",1)
-
-
- print "\tSETTING INTERNAL TRIGGER INTERVAL TO" , triggerInterval , "(zero= no internal triggers)"
- if triggerInterval == 0:
- internalTriggerFreq = 0
- else:
- internalTriggerFreq = 160000.0/triggerInterval
- print "\tINTERNAL TRIGGER FREQUENCY= " , internalTriggerFreq , " kHz"
- pychipsBoard.write("InternalTriggerIntervalW",triggerInterval) #0->Internal pulse generator disabled. Any other value will generate pulses with a frequency of n*6.25ns
- trigIntervalR = pychipsBoard.read("InternalTriggerIntervalR")
- print "\t Trigger interval read back as:", trigIntervalR
- print "AIDA TLU SETUP COMPLETED"
diff --git a/EUDETdummy/scripts/startDUMMY.sh b/EUDETdummy/scripts/startDUMMY.sh
deleted file mode 100644
index 03f6c55..0000000
--- a/EUDETdummy/scripts/startDUMMY.sh
+++ /dev/null
@@ -1,24 +0,0 @@
-#!/bin/bash
-
-echo "=========================="
-CURRENT_DIR=${0%/*}
-echo "CURRENT DIRECTORY: " $CURRENT_DIR
-
-echo "============"
-echo "SETTING PATHS"
-export PYTHONPATH=$CURRENT_DIR/../../../../Python_Scripts/PyChips_1_5_0_pre2A/src:$PYTHONPATH
-export PYTHONPATH=~/Python_Scripts/PyChips_1_5_0_preexport PYTHONPATH=../../packages:$PYTHONPATH2A/src:$PYTHONPATH
-echo "PYTHON PATH= " $PYTHONPATH
-export LD_LIBRARY_PATH=/opt/cactus/lib:$LD_LIBRARY_PATH
-echo "LD_LIBRARY_PATH= " $LD_LIBRARY_PATH
-export PATH=/usr/bin/:/opt/cactus/bin:$PATH
-echo "PATH= " $PATH
-
-cd $CURRENT_DIR
-
-echo "============"
-echo "STARTING PYTHON SCRIPT FOR TLU"
-#python $CURRENT_DIR/startTLU_v8.py $@
-
-python startEUDETdummy.py $@
-#python testTLU_script.py
diff --git a/EUDETdummy/scripts/startEUDETdummy.py b/EUDETdummy/scripts/startEUDETdummy.py
deleted file mode 100644
index e253e82..0000000
--- a/EUDETdummy/scripts/startEUDETdummy.py
+++ /dev/null
@@ -1,78 +0,0 @@
-# -*- coding: utf-8 -*-
-# miniTLU test script
-
-#from PyChipsUser import *
-#from FmcTluI2c import *
-import uhal
-import sys
-import time
-# from ROOT import TFile, TTree
-# from ROOT import gROOT
-from datetime import datetime
-
-from EUDETdummy import EUDETdummy
-# Use to have interactive shell
-import cmd
-
-class MyPrompt(cmd.Cmd):
-
-
- def do_startRun(self, args):
- """Starts the TLU run"""
- print "COMMAND RECEIVED: STARTING TLU RUN"
- startTLU( uhalDevice = self.hw, pychipsBoard = self.board, writeTimestamps = ( options.writeTimestamps == "True" ) )
- #print self.hw
-
- def do_stopRun(self, args):
- """Stops the TLU run"""
- print "COMMAND RECEIVED: STOP TLU RUN"
- #stopTLU( uhalDevice = hw, pychipsBoard = board )
-
- def do_quit(self, args):
- """Quits the program."""
- print "COMMAND RECEIVED: QUITTING SCRIPT."
- #raise SystemExit
- return True
-
-# # Override methods in Cmd object ##
-# def preloop(self):
-# """Initialization before prompting user for commands.
-# Despite the claims in the Cmd documentaion, Cmd.preloop() is not a stub.
-# """
-# cmd.Cmd.preloop(self) # # sets up command completion
-# self._hist = [] # # No history yet
-# self._locals = {} # # Initialize execution namespace for user
-# self._globals = {}
-# print "\nINITIALIZING"
-# now = datetime.now().strftime('%Y-%m-%dT%H_%M_%S')
-# default_filename = './rootfiles/tluData_' + now + '.root'
-# print "SETTING UP AIDA TLU TO SUPPLY CLOCK AND TRIGGER TO TORCH READOUT\n"
-# self.manager = uhal.ConnectionManager("file://./connection.xml")
-# self.hw = self.manager.getDevice("minitlu")
-# self.device_id = self.hw.id()
-#
-# # Point to TLU in Pychips
-# self.bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
-#
-# # Assume DIP-switch controlled address. Switches at 2
-# self.board = ChipsBusUdp(self.bAddrTab,"192.168.200.32",50001)
-
-
-#################################################
-if __name__ == "__main__":
- EUDummy= EUDETdummy("eudummy", "file://./EUDETdummyconnection.xml")
- EUDummy.initialize()
-
- logdata= True
- EUDummy.start(logdata)
- time.sleep(0.2)
- nwords= int( EUDummy.getFifoLevel() )
- print nwords
- myarray= EUDummy.getFifoData(nwords)
- for iel in myarray:
- print iel >> 16
-
- EUDummy.stop()
- # prompt = MyPrompt()
- # prompt.prompt = '>> '
- # prompt.cmdloop("Welcome to miniTLU test console.\nType HELP for a list of commands.")
diff --git a/EUDETdummy/scripts/testTLU_script.py b/EUDETdummy/scripts/testTLU_script.py
deleted file mode 100644
index 9d8b334..0000000
--- a/EUDETdummy/scripts/testTLU_script.py
+++ /dev/null
@@ -1,79 +0,0 @@
-# miniTLU test script
-
-from FmcTluI2c import *
-import uhal
-import sys
-import time
-from I2CuHal import I2CCore
-from miniTLU import MiniTLU
-from datetime import datetime
-
-if __name__ == "__main__":
- print "\tTEST TLU SCRIPT"
- miniTLU= MiniTLU("minitlu", "file://./connection.xml")
- #(self, target, wclk, i2cclk, name="i2c", delay=None)
- TLU_I2C= I2CCore(miniTLU.hw, 10, 5, "i2c_master", None)
- TLU_I2C.state()
-
-
- #READ CONTENT OF EEPROM ON 24AA02E48 (0xFA - 0XFF)
- mystop= 1
- time.sleep(0.1)
- myaddr= [0xfa]
- TLU_I2C.write( 0x50, myaddr, mystop)
- res=TLU_I2C.read( 0x50, 6)
- print "Checkin EEPROM:"
- result="\t"
- for iaddr in res:
- result+="%02x "%(iaddr)
- print result
-
- #SCAN I2C ADDRESSES
- #WRITE PROM
- #WRITE DAC
-
-
- #Convert required threshold voltage to DAC code
- #def convert_voltage_to_dac(self, desiredVoltage, Vref=1.300):
- print("Writing DAC setting:")
- Vref= 1.300
- desiredVoltage= 3.3
- channel= 0
- i2cSlaveAddrDac = 0x1F
- vrefOn= 0
- Vdaq = ( desiredVoltage + Vref ) / 2
- dacCode = 0xFFFF * Vdaq / Vref
- dacCode= 0x391d
- print "\tVreq:", desiredVoltage
- print "\tDAC code:" , dacCode
- print "\tCH:", channel
- print "\tIntRef:", vrefOn
-
- #Set DAC value
- #def set_dac(self,channel,value , vrefOn = 0 , i2cSlaveAddrDac = 0x1F):
- if channel<0 or channel>7:
- print "set_dac ERROR: channel",channel,"not in range 0-7 (bit mask)"
- ##return -1
- if dacCode<0 or dacCode>0xFFFF:
- print "set_dac ERROR: value",dacCode ,"not in range 0-0xFFFF"
- ##return -1
- # AD5665R chip with A0,A1 tied to ground
- #i2cSlaveAddrDac = 0x1F # seven bit address, binary 00011111
-
- # print "I2C address of DAC = " , hex(i2cSlaveAddrDac)
- # dac = RawI2cAccess(self.i2cBusProps, i2cSlaveAddrDac)
- # # if we want to enable internal voltage reference:
-
- if vrefOn:
- # enter vref-on mode:
- print "\tTurning internal reference ON"
- #dac.write([0x38,0x00,0x01])
- TLU_I2C.write( i2cSlaveAddrDac, [0x38,0x00,0x01], 0)
- else:
- print "\tTurning internal reference OFF"
- #dac.write([0x38,0x00,0x00])
- TLU_I2C.write( i2cSlaveAddrDac, [0x38,0x00,0x00], 0)
- # Now set the actual value
- sequence=[( 0x18 + ( channel &0x7 ) ) , int(dacCode/256)&0xff , int(dacCode)&0xff]
- print "\tWriting byte sequence:", sequence
- TLU_I2C.write( i2cSlaveAddrDac, sequence, 0)
diff --git a/README.md b/README.md
index c70d7f2..07a1b95 100644
--- a/README.md
+++ b/README.md
@@ -1,23 +1,81 @@
-# aidatlu
+# AIDA-TLU
[](https://github.com/psf/black)
-Repository for controlling the AIDA-2020 TLU with python using uHAL bindings from [IPbus](https://ipbus.web.cern.ch/).
-
+Repository for controlling the AIDA-2020 Trigger Logic Unit (TLU) with Python using uHAL bindings from [IPbus](https://ipbus.web.cern.ch/).
+The Python control software is based on [EUDAQ2](https://github.com/eudaq/eudaq/tree/master/user/tlu).
+The software is a lightweight version written in Python with a focus on readability and user-friendliness.
+Most user cases can be set with a .yaml configuration file and started by executing a single Python script.
+For a more in-depth look at the hardware components please take a look at the official [AIDA-2020 TLU project](https://ohwr.org/project/fmc-mtlu).
# Installation
## IPbus
-You need to install [IPbus](https://ipbus.web.cern.ch/doc/user/html/software/install/compile.html) and its python bindings to the desired interpreter.
-Follow the linked tutorial for pre-requisites and general installation.
-The following commands have been proven useful for custom installation and building against current (non-system) python within an environment:
+You need to install [IPbus](https://ipbus.web.cern.ch/doc/user/html/software/install/compile.html) and its Python bindings to the desired interpreter.
+Follow the linked tutorial for prerequisites and general installation.
+Install prerequisites.
+```bash
+sudo apt-get install -y make erlang g++ libboost-all-dev libpugixml-dev python-all-dev rsyslog
+sudo touch /usr/lib/erlang/man/man1/x86_64-linux-gnu-gcov-tool.1.gz
+sudo touch /usr/lib/erlang/man/man1/gcov-tool.1.gz
+```
+Checkout from git and compile the repository.
+```bash
+git clone --depth=1 -b v2.8.12 --recurse-submodules https://github.com/ipbus/ipbus-software.git
+cd ipbus-software
+make
+```
+Next install against the current Python environment.
```bash
-make -j $((`nproc`-1))
# Pass current PATH to su shell to build against current environment python
-sudo env PATH=$PATH make install prefix=
+sudo env PATH=$PATH make install
+```
+Afterwards you should be able to import uhal in your specific Python environment.
+When using a custom installation path for IPbus you need to import the library path.
+```bash
+export LD_LIBRARY_PATH=/lib
+```
+The default install location is located in /opt/cactus/.
+Then start the controlhub from ipbus-software/controlhub/scripts.
+```bash
+./controlhub_start
+```
+The contolhub needs to run for the working of the AIDA TLU, so needs to be started again each time the controlhub is stopped.
+The default IP address of the TLU is:
+```
+192.168.200.30
```
-## Python package
-Install the python package as usual
+## Python packages
+Install the Python package as usual.
```
pip install -e .
```
# Usage
-TODO
\ No newline at end of file
+There are multiple ways to use the control software of the AIDA 2020 TLU.
+If one executes tlu.py in the main directory, the TLU is initialized, configured and starts a run automatically.
+```bash
+ python tlu.py
+```
+The TLU is configured with the standard tlu_configuration file. To stop the run use ctrl+c.
+
+
+While configuring the TLU outputs are powered on and off.
+This leads to problems in AIDA mode where the clock is powered off shortly during configuration.
+To avoid this at the start of runs in AIDA mode the best way is to use the aidatlu_run.py script.
+This is started and controlled with the terminal input:
+```bash
+ python -i aidatlu_run.py
+```
+This initializes the main tlu.py script. One is now able to control the TLU through the Python terminal interface,
+with the following commands:
+```bash
+ tlu.configure()
+ tlu.run()
+ tlu.help()
+```
+Naturally, this also works for any EUDET mode runs.
+Runs are stopped with the keyboard interrupt ctr+c.
+For more commands take a look at the python script aidatlu.py.
+
+All configurations are done by the use of a yaml file (tlu_configuration.yaml).
+
+
+Additionally, take a look at the [documentation](https://silab-bonn.github.io/aidatlu/).
\ No newline at end of file
diff --git a/TLU_v1c/scripts/500ns_23ns.txt b/TLU_v1c/scripts/500ns_23ns.txt
deleted file mode 100644
index 7d050b4..0000000
--- a/TLU_v1c/scripts/500ns_23ns.txt
+++ /dev/null
@@ -1,8048 +0,0 @@
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diff --git a/TLU_v1c/scripts/500ns_24ns.txt b/TLU_v1c/scripts/500ns_24ns.txt
deleted file mode 100644
index c6f9734..0000000
--- a/TLU_v1c/scripts/500ns_24ns.txt
+++ /dev/null
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diff --git a/TLU_v1c/scripts/AIDA_testScript.py b/TLU_v1c/scripts/AIDA_testScript.py
deleted file mode 100644
index 4b8f505..0000000
--- a/TLU_v1c/scripts/AIDA_testScript.py
+++ /dev/null
@@ -1,183 +0,0 @@
-# -*- coding: utf-8 -*-
-import uhal
-from I2CuHal import I2CCore
-import time
-#import miniTLU
-from si5345 import si5345
-from AD5665R import AD5665R
-from PCA9539PW import PCA9539PW
-from E24AA025E48T import E24AA025E48T
-
-manager = uhal.ConnectionManager("file://./TLUconnection.xml")
-hw = manager.getDevice("tlu")
-
-# hw.getNode("A").write(255)
-reg = hw.getNode("version").read()
-hw.dispatch()
-print "CHECK REG= ", hex(reg)
-
-
-# #First I2C core
-print ("Instantiating master I2C core:")
-master_I2C= I2CCore(hw, 10, 5, "i2c_master", None)
-master_I2C.state()
-
-
-
-
-#
-# #######################################
-enableCore= True #Only need to run this once, after power-up
-if (enableCore):
- mystop=True
- print " Write RegDir to set I/O[7] to output:"
- myslave= 0x21
- mycmd= [0x01, 0x7F]
- nwords= 1
- master_I2C.write(myslave, mycmd, mystop)
-
-
- mystop=False
- mycmd= [0x01]
- master_I2C.write(myslave, mycmd, mystop)
- res= master_I2C.read( myslave, nwords)
- print "\tPost RegDir: ", res
-# #######################################
-#
-# time.sleep(0.1)
-# #Read the EPROM
-# mystop=False
-# nwords=6
-# myslave= 0x53 #DUNE EPROM 0x53 (Possibly)
-# myaddr= [0xfa]#0xfa
-# master_I2C.write( myslave, myaddr, mystop)
-# #res= master_I2C.read( 0x50, 6)
-# res= master_I2C.read( myslave, nwords)
-# print " PCB EPROM: "
-# result="\t "
-# for iaddr in res:
-# result+="%02x "%(iaddr)
-# print result
-# #######################################
-
-
-#Second I2C core
-#print ("Instantiating SFP I2C core:")
-#clock_I2C= I2CCore(hw, 10, 5, "i2c_sfp", None)
-#clock_I2C.state()
-
-# #Third I2C core
-# print ("Instantiating clock I2C core:")
-# clock_I2C= I2CCore(hw, 10, 5, "i2c_clk", None)
-# clock_I2C.state()
-
-
-# #time.sleep(0.01)
-# #Read the EPROM
-# mystop=False
-# nwords=2
-# myslave= 0x68 #DUNE CLOCK CHIP 0x68
-# myaddr= [0x02 ]#0xfa
-# clock_I2C.write( myslave, myaddr, mystop)
-# #time.sleep(0.1)
-# res= clock_I2C.read( myslave, nwords)
-# print " CLOCK EPROM: "
-# result="\t "
-# for iaddr in res:
-# result+="%02x "%(iaddr)
-# print result
-
-#
-
-#CLOCK CONFIGURATION BEGIN
-zeClock=si5345(master_I2C, 0x68)
-res= zeClock.getDeviceVersion()
-zeClock.checkDesignID()
-#zeClock.setPage(0, True)
-#zeClock.getPage(True)
-clkRegList= zeClock.parse_clk("./../../bitFiles/TLU_CLK_Config.txt")
-zeClock.writeConfiguration(clkRegList)######
-zeClock.writeRegister(0x0536, [0x0B]) #Configures manual switch of inputs
-zeClock.writeRegister(0x0949, [0x0F]) #Enable all inputs
-zeClock.writeRegister(0x052A, [0x05]) #Configures source of input
-iopower= zeClock.readRegister(0x0949, 1)
-print " Clock IO power: 0x%X" % iopower[0]
-lol= zeClock.readRegister(0x000E, 1)
-print " Clock LOL: 0x%X" % lol[0]
-los= zeClock.readRegister(0x000D, 1)
-print " Clock LOS: 0x%X" % los[0]
-#CLOCK CONFIGURATION END
-
-#DAC CONFIGURATION BEGIN
-zeDAC1=AD5665R(master_I2C, 0x13)
-zeDAC1.setIntRef(intRef= False, verbose= True)
-zeDAC1.writeDAC(0x0, 7, verbose= True)#7626
-
-zeDAC2=AD5665R(master_I2C, 0x1F)
-zeDAC2.setIntRef(intRef= False, verbose= True)
-zeDAC2.writeDAC(0x2fff, 3, verbose= True)
-#DAC CONFIGURATION END
-
-#EEPROM BEGIN
-zeEEPROM= E24AA025E48T(master_I2C, 0x50)
-res=zeEEPROM.readEEPROM(0xfa, 6)
-result=" EEPROM ID:\n\t"
-for iaddr in res:
- result+="%02x "%(iaddr)
-print result
-#EEPROM END
-
-# #I2C EXPANDER CONFIGURATION BEGIN
-IC6=PCA9539PW(master_I2C, 0x74)
-#BANK 0
-IC6.setInvertReg(0, 0x00)# 0= normal
-IC6.setIOReg(0, 0xFF)# 0= output <<<<<<<<<<<<<<<<<<<
-IC6.setOutputs(0, 0xFF)
-res= IC6.getInputs(0)
-print "IC6 read back bank 0: 0x%X" % res[0]
-#
-#BANK 1
-IC6.setInvertReg(1, 0x00)# 0= normal
-IC6.setIOReg(1, 0xFF)# 0= output <<<<<<<<<<<<<<<<<<<
-IC6.setOutputs(1, 0xFF)
-res= IC6.getInputs(1)
-print "IC6 read back bank 1: 0x%X" % res[0]
-
-# # #
-IC7=PCA9539PW(master_I2C, 0x75)
-#BANK 0
-IC7.setInvertReg(0, 0xFF)# 0= normal
-IC7.setIOReg(0, 0xFA)# 0= output <<<<<<<<<<<<<<<<<<<
-IC7.setOutputs(0, 0xFF)
-res= IC7.getInputs(0)
-print "IC7 read back bank 0: 0x%X" % res[0]
-#
-#BANK 1
-IC7.setInvertReg(1, 0x00)# 0= normal
-IC7.setIOReg(1, 0x0F)# 0= output <<<<<<<<<<<<<<<<<<<
-IC7.setOutputs(1, 0xFF)
-res= IC7.getInputs(1)
-print "IC7 read back bank 1: 0x%X" % res[0]
-# #I2C EXPANDER CONFIGURATION END
-
-
-# #Reset counters
-#cmd = int("0x0", 16) #write 0x2 to reset
-#hw.getNode("triggerInputs.SerdesRstW").write(cmd)
-#restatus= hw.getNode("triggerInputs.SerdesRstR").read()
-#hw.dispatch()
-#print "Trigger Reset: 0x%X" % restatus
-## #Read trigger inputs
-#myreg= [-1, -1, -1, -1, -1, -1]
-#for inputN in range(0, 6):
-# regString= "triggerInputs.ThrCount%dR" % inputN
-# myreg[inputN]= hw.getNode(regString).read()
-# hw.dispatch()
-# print regString, myreg[inputN]
-
-## Read ev formatter
-#cmd = int("0x0", 16) #
-##hw.getNode("Event_Formatter.Enable_Record_Data").write(cmd)
-#efstatus= hw.getNode("Event_Formatter.CurrentTimestampLR").read()
-#hw.dispatch()
-#print "Event Formatter Record: 0x%X" % efstatus
diff --git a/TLU_v1c/scripts/TLU.py b/TLU_v1c/scripts/TLU.py
deleted file mode 100644
index c340cfe..0000000
--- a/TLU_v1c/scripts/TLU.py
+++ /dev/null
@@ -1,749 +0,0 @@
-# -*- coding: utf-8 -*-
-import uhal;
-import pprint;
-#from FmcTluI2c import *
-from I2CuHal import I2CCore
-from si5345 import si5345 # Library for clock chip
-from AD5665R import AD5665R # Library for DAC
-from PCA9539PW import PCA9539PW # Library for serial line expander
-import time
-
-class TLU:
- """docstring for TLU"""
- def __init__(self, dev_name, man_file):
- self.dev_name = dev_name
- self.manager= uhal.ConnectionManager(man_file)
- self.hw = self.manager.getDevice(self.dev_name)
- self.nDUTs= 4 #Number of DUT connectors
- self.nChannels= 6 #Number of trigger inputs
- self.VrefInt= 2.5 #Internal DAC voltage reference
- self.VrefExt= 1.3 #External DAC voltage reference
- self.intRefOn= False #Internal reference is OFF by default
-
- self.fwVersion = self.hw.getNode("version").read()
- self.hw.dispatch()
- print "TLU FIRMWARE VERSION= " , hex(self.fwVersion)
-
- # Instantiate a I2C core to configure components
- self.TLU_I2C= I2CCore(self.hw, 10, 5, "i2c_master", None)
- #self.TLU_I2C.state()
-
- enableCore= True #Only need to run this once, after power-up
- self.enableCore()
-
- # Instantiate clock chip
- self.zeClock=si5345(self.TLU_I2C, 0x68)
- res= self.zeClock.getDeviceVersion()
- self.zeClock.checkDesignID()
-
- # Instantiate DACs and configure them to use reference based on TLU setting
- self.zeDAC1=AD5665R(self.TLU_I2C, 0x13)
- self.zeDAC2=AD5665R(self.TLU_I2C, 0x1F)
- self.zeDAC1.setIntRef(self.intRefOn)
- self.zeDAC2.setIntRef(self.intRefOn)
-
- # Instantiate the serial line expanders and configure them to default values
- self.IC6=PCA9539PW(self.TLU_I2C, 0x74)
- self.IC6.setInvertReg(0, 0x00)# 0= normal, 1= inverted
- self.IC6.setIOReg(0, 0xFF)# 0= output, 1= input
- self.IC6.setOutputs(0, 0xFF)# If output, set to 1
- self.IC6.setInvertReg(1, 0x00)# 0= normal, 1= inverted
- self.IC6.setIOReg(1, 0xFF)# 0= output, 1= input
- self.IC6.setOutputs(1, 0xFF)# If output, set to 1
-
- self.IC7=PCA9539PW(self.TLU_I2C, 0x75)
- self.IC7.setInvertReg(0, 0x00)# 0= normal, 1= inverted
- self.IC7.setIOReg(0, 0xFF)# 0= output, 1= input
- self.IC7.setOutputs(0, 0xFF)# If output, set to 1
- self.IC7.setInvertReg(1, 0x00)# 0= normal, 1= inverted
- self.IC7.setIOReg(1, 0xFF)# 0= output, 1= input
- self.IC7.setOutputs(1, 0xFF)# If output, set to 1
-
-
-##################################################################################################################################
-##################################################################################################################################
- def DUTOutputs(self, dutN, enable=False, verbose=False):
- ## Set the status of the transceivers for a specific HDMI connector. When enable= False the transceivers are disabled and the
- ## connector cannot send signals from FPGA to the outside world. When enable= True then signals from the FPGA will be sent out to the HDMI.
- ## NOTE: the other direction is always enabled, i.e. signals from the DUTs are always sent to the FPGA.
- ## NOTE: CLK direction must be defined separately using DUTClkSrc
-
- if (dutN < 0) | (dutN> (self.nDUTs-1)):
- print "\tERROR: DUTOutputs. The DUT number must be comprised between 0 and ", self.nDUTs-1
- return -1
- bank= dutN//2 # DUT0 and DUT1 are on bank 0. DUT2 and DUT3 on bank 1
- nibble= dutN%2 # DUT0 and DUT2 are on nibble 0. DUT1 and DUT3 are on nibble 1
- print " Setting DUT:", dutN, "to", enable
- if verbose:
- print "\tBank", bank, "Nibble", nibble
- res= self.IC6.getIOReg(bank)
- oldStatus= res[0]
- mask= 0xF << 4*nibble
- newStatus= oldStatus & (~mask)
- if (not enable): # we want to write 0 to activate the outputs so check opposite of "enable"
- newStatus |= mask
- if verbose:
- print "\tOldStatus= ", "{0:#0{1}x}".format(oldStatus,4), "Mask=" , hex(mask), "newStatus=", "{0:#0{1}x}".format(newStatus,4)
- self.IC6.setIOReg(bank, newStatus)
- return newStatus
-
- def DUTClkSrc(self, dutN, clkSrc=0, verbose= False):
- ## Allows to choose the source of the clock signal sent to the DUTs over HDMI
- ## clkSrc= 0: clock disabled
- ## clkSrc= 1: clock from Si5345
- ## clkSrc=2: clock from FPGA
- if (dutN < 0) | (dutN> (self.nDUTs-1)):
- print "\tERROR: DUTClkSrc. The DUT number must be comprised between 0 and ", self.nDUTs-1
- return -1
- if (clkSrc < 0) | (clkSrc> 2):
- print "\tERROR: DUTClkSrc. clkSrc can only be 0 (disabled), 1 (Si5345) or 2 (FPGA)"
- return -1
- bank=0
- maskLow= 1 << (1* dutN) #CLK FROM FPGA
- maskHigh= 1<< (1* dutN +4) #CLK FROM Si5345
- mask= maskLow | maskHigh
- res= self.IC7.getIOReg(bank)
- oldStatus= res[0]
- newStatus= oldStatus & ~mask #set both bits to zero
- outStat= ""
- if clkSrc==0:
- newStatus = newStatus | mask
- outStat= "disabled"
- elif clkSrc==1:
- newStatus = newStatus | maskLow
- outStat= "Si5435"
- elif clkSrc==2:
- newStatus= newStatus | maskHigh
- outStat= "FPGA"
- print " Setting DUT:", dutN, "clock source to", outStat
- if verbose:
- print "\tOldStatus= ", "{0:#0{1}x}".format(oldStatus,4), "Mask=" , hex(mask), "newStatus=", "{0:#0{1}x}".format(newStatus,4)
- self.IC7.setIOReg(bank, newStatus)
- return newStatus
-
- def enableClkLEMO(self, enable= False, verbose= False):
- ## Enable or disable the output clock to the differential LEMO output
- bank=1
- mask= 0x10
- res= self.IC7.getIOReg(bank)
- oldStatus= res[0]
- newStatus= oldStatus & ~mask
- outStat= "enabled"
- if (not enable): #A 0 activates the output. A 1 disables it.
- newStatus= newStatus | mask
- outStat= "disabled"
- print " Clk LEMO", outStat
- if verbose:
- print "\tOldStatus= ", "{0:#0{1}x}".format(oldStatus,4), "Mask=" , hex(mask), "newStatus=", "{0:#0{1}x}".format(newStatus,4)
- self.IC7.setIOReg(bank, newStatus)
- return newStatus
-
- def enableCore(self):
- ## At power up the Enclustra I2C lines are disabled (tristate buffer is off).
- ## This function enables the lines. It is only required once.
- mystop=True
- print " Enabling I2C bus (expect 127):"
- myslave= 0x21
- mycmd= [0x01, 0x7F]
- nwords= 1
- self.TLU_I2C.write(myslave, mycmd, mystop)
-
- mystop=False
- mycmd= [0x01]
- self.TLU_I2C.write(myslave, mycmd, mystop)
- res= self.TLU_I2C.read( myslave, nwords)
- print "\tPost RegDir: ", res
-
- def getAllChannelsCounts(self):
- chCounts=[]
- for ch in range (0,self.nChannels):
- chCounts.append(int(self.getChCount(ch)))
- return chCounts
-
- def getChStatus(self):
- inputStatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
- self.hw.dispatch()
- print "\tInput status= " , hex(inputStatus)
- return inputStatus
-
- def getChCount(self, channel):
- regString= "triggerInputs.ThrCount"+ str(channel)+"R"
- count = self.hw.getNode(regString).read()
- self.hw.dispatch()
- print "\tCh", channel, "Count:" , count
- return count
-
- def getClockStatus(self):
- clockStatus = self.hw.getNode("logic_clocks.LogicClocksCSR").read()
- self.hw.dispatch()
- print " CLOCK STATUS [expected 1]"
- print "\t", hex(clockStatus)
- if ( clockStatus == 0 ):
- "ERROR: Clocks in TLU FPGA are not locked."
- return clockStatus
-
- def getDUTmask(self):
- DUTMaskR = self.hw.getNode("DUTInterfaces.DutMaskR").read()
- self.hw.dispatch()
- print "\tDUTMask read back as:" , hex(DUTMaskR)
- return DUTMaskR
-
- def getExternalVeto(self):
- extVeto= self.hw.getNode("triggerLogic.ExternalTriggerVetoR").read()
- self.hw.dispatch()
- print "\tEXTERNAL Veto read back as:", hex(extVeto)
- return extVeto
-
- def getFifoData(self, nWords):
- #fifoData= self.hw.getNode("eventBuffer.EventFifoData").read()
- fifoData= self.hw.getNode("eventBuffer.EventFifoData").readBlock (nWords);
- self.hw.dispatch()
- #print "\tFIFO Data:", hex(fifoData)
- return fifoData
-
- def getFifoLevel(self):
- FifoFill= self.hw.getNode("eventBuffer.EventFifoFillLevel").read()
- self.hw.dispatch()
- print "\tFIFO level read back as:", hex(FifoFill)
- return FifoFill
-
- def getFifoCSR(self):
- FifoCSR= self.hw.getNode("eventBuffer.EventFifoCSR").read()
- self.hw.dispatch()
- print "\tFIFO CSR read back as:", hex(FifoCSR)
- return FifoCSR
-
- def getInternalTrg(self):
- trigIntervalR = self.hw.getNode("triggerLogic.InternalTriggerIntervalR").read()
- self.hw.dispatch()
- print "\tTrigger frequency read back as:", trigIntervalR, "Hz"
- return trigIntervalR
-
- def getMode(self):
- DUTInterfaceModeR = self.hw.getNode("DUTInterfaces.DUTInterfaceModeR").read()
- self.hw.dispatch()
- print "\tDUT mode read back as:" , hex(DUTInterfaceModeR)
- return DUTInterfaceModeR
-
- def getModeModifier(self):
- DUTInterfaceModeModifierR = self.hw.getNode("DUTInterfaces.DUTInterfaceModeModifierR").read()
- self.hw.dispatch()
- print "\tDUT mode modifier read back as:" , hex(DUTInterfaceModeModifierR)
- return DUTInterfaceModeModifierR
-
- def getSN(self):
- epromcontent=self.readEEPROM(0xfa, 6)
- print " FMC-TLU serial number (EEPROM):"
- result="\t"
- for iaddr in epromcontent:
- result+="%02x "%(iaddr)
- print result
- return epromcontent
-
- def getPostVetoTrg(self):
- triggerN = self.hw.getNode("triggerLogic.PostVetoTriggersR").read()
- self.hw.dispatch()
- print "\tPOST VETO TRIGGER NUMBER:", (triggerN)
- return triggerN
-
- def getPulseDelay(self):
- pulseDelayR = self.hw.getNode("triggerLogic.PulseDelayR").read()
- self.hw.dispatch()
- print "\tPulse delay read back as:", hex(pulseDelayR)
- return pulseDelayR
-
- def getPulseStretch(self):
- pulseStretchR = self.hw.getNode("triggerLogic.PulseStretchR").read()
- self.hw.dispatch()
- print "\tPulse stretch read back as:", hex(pulseStretchR)
- return pulseStretchR
-
- def getRecordDataStatus(self):
- RecordStatus= self.hw.getNode("Event_Formatter.Enable_Record_Data").read()
- self.hw.dispatch()
- print "\tData recording:", RecordStatus
- return RecordStatus
-
- def getTriggerVetoStatus(self):
- trgVetoStatus= self.hw.getNode("triggerLogic.TriggerVetoR").read()
- self.hw.dispatch()
- print "\tTrigger veto status read back as:", trgVetoStatus
- return trgVetoStatus
-
- def getTrgPattern(self):
- triggerPattern_low = self.hw.getNode("triggerLogic.TriggerPattern_lowR").read()
- triggerPattern_high = self.hw.getNode("triggerLogic.TriggerPattern_highR").read()
- self.hw.dispatch()
- print "\tTrigger pattern read back as: 0x%08X 0x%08X" %(triggerPattern_high, triggerPattern_low)
- return triggerPattern_low, triggerPattern_high
-
- def getVetoDUT(self):
- IgnoreDUTBusyR = self.hw.getNode("DUTInterfaces.IgnoreDUTBusyR").read()
- self.hw.dispatch()
- print "\tIgnoreDUTBusy read back as:" , hex(IgnoreDUTBusyR)
- return IgnoreDUTBusyR
-
- def getVetoShutters(self):
- IgnoreShutterVeto = self.hw.getNode("DUTInterfaces.IgnoreShutterVetoR").read()
- self.hw.dispatch()
- print "\tIgnoreShutterVeto read back as:" , IgnoreShutterVeto
- return IgnoreShutterVeto
-
- def pulseT0(self):
- cmd = int("0x1",16)
- self.hw.getNode("Shutter.PulseT0").write(cmd)
- self.hw.dispatch()
- print "\tPulsing T0"
-
- def readEEPROM(self, startadd, bytes):
- mystop= 1
- time.sleep(0.1)
- myaddr= [startadd]#0xfa
- self.TLU_I2C.write( 0x50, [startadd], mystop)
- res= self.TLU_I2C.read( 0x50, bytes)
- return res
-
- def resetClock(self):
- # Set the RST pin from the PLL to 1
- print " Clocks reset"
- cmd = int("0x1",16)
- self.hw.getNode("logic_clocks.LogicRst").write(cmd)
- self.hw.dispatch()
-
- def resetClocks(self):
- #Reset clock PLL
- self.resetClock()
- #Get clock status after reset
- self.getClockStatus()
- #Restore clock PLL
- self.restoreClock()
- #Get clock status after restore
- self.getClockStatus()
- #Get serdes status
- self.getChStatus()
-
- def resetCounters(self):
- cmd = int("0x2", 16) #write 0x2 to reset
- self.hw.getNode("triggerInputs.SerdesRstW").write(cmd)
- restatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
- self.hw.dispatch()
- cmd = int("0x0", 16) #write 0x2 to reset
- self.hw.getNode("triggerInputs.SerdesRstW").write(cmd)
- restatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
- self.hw.dispatch()
- #print "Trigger Reset: 0x%X" % restatus
- print "\tTrigger counters reset"
-
- def resetSerdes(self):
- cmd = int("0x3",16)
- self.setChStatus(cmd)
- inputStatus= self.getChStatus()
- print "\t Input status during reset = " , hex(inputStatus)
-
- cmd = int("0x0",16)
- self.setChStatus(cmd)
- inputStatus= self.getChStatus()
- print "\t Input status after reset = " , hex(inputStatus)
-
- cmd = int("0x4",16)
- self.setChStatus(cmd)
- inputStatus= self.getChStatus()
- print "\t Input status during calibration = " , hex(inputStatus)
-
- cmd = int("0x0",16)
- self.setChStatus(cmd)
- inputStatus= self.getChStatus()
- print "\t Input status after calibration = " , hex(inputStatus)
-
- def restoreClock(self):
- # Set the RST pin from the PLL to 0
- print " Clocks restore"
- cmd = int("0x0",16)
- self.hw.getNode("logic_clocks.LogicRst").write(cmd)
- self.hw.dispatch()
-
- def setChStatus(self, cmd):
- self.hw.getNode("triggerInputs.SerdesRstW").write(cmd)
- inputStatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
- self.hw.dispatch()
- print " INPUT STATUS SET TO= " , hex(inputStatus)
-
- def setClockStatus(self, cmd):
- # Only use this for testing. The clock source is actually selected in the Si5345.
- self.hw.getNode("logic_clocks.LogicClocksCSR").write(cmd)
- self.hw.dispatch()
-
- def setDUTmask(self, DUTMask):
- print " DUT MASK ENABLING: Mask= " , hex(DUTMask)
- self.hw.getNode("DUTInterfaces.DutMaskW").write(DUTMask)
- self.hw.dispatch()
- self.getDUTmask()
-
- def setFifoCSR(self, cmd):
- self.hw.getNode("eventBuffer.EventFifoCSR").write(cmd)
- self.hw.dispatch()
- self.getFifoCSR()
-
- def setInternalTrg(self, triggerInterval):
- print " TRIGGERS INTERNAL:"
- if triggerInterval == 0:
- internalTriggerFreq = 0
- print "\tdisabled"
- else:
- internalTriggerFreq = 160000.0/triggerInterval
- print "\t Setting:", internalTriggerFreq, "Hz"
- self.hw.getNode("triggerLogic.InternalTriggerIntervalW").write(int(internalTriggerFreq))
- self.hw.dispatch()
- self.getInternalTrg()
-
- def setMode(self, mode):
- print " DUT MODE SET TO: ", hex(mode)
- self.hw.getNode("DUTInterfaces.DUTInterfaceModeW").write(mode)
- self.hw.dispatch()
- self.getMode()
-
- def setModeModifier(self, modifier):
- print " DUT MODE MODIFIER:", hex(modifier)
- self.hw.getNode("DUTInterfaces.DUTInterfaceModeModifierW").write(modifier)
- self.hw.dispatch()
- self.getModeModifier()
-
- def setPulseDelay(self, pulseDelay):
- print " TRIGGER DELAY SET TO", hex(pulseDelay), "[Units= 160MHz clock, 5-bit values (one per input) packed in to 32-bit word]"
- self.hw.getNode("triggerLogic.PulseDelayW").write(pulseDelay)
- self.hw.dispatch()
- self.getPulseDelay()
-
- def setPulseStretch(self, pulseStretch):
- print " INPUT COINCIDENCE WINDOW SET TO", hex(pulseStretch) ,"[Units= 160MHz clock cycles, 5-bit values (one per input) packed in to 32-bit word]"
- self.hw.getNode("triggerLogic.PulseStretchW").write(pulseStretch)
- self.hw.dispatch()
- self.getPulseStretch()
-
- def setRecordDataStatus(self, status=False):
- print " Data recording set:"
- self.hw.getNode("Event_Formatter.Enable_Record_Data").write(status)
- self.hw.dispatch()
- self.getRecordDataStatus()
-
- def setTriggerVetoStatus(self, status=False):
- self.hw.getNode("triggerLogic.TriggerVetoW").write(status)
- self.hw.dispatch()
- self.getTriggerVetoStatus()
-
- def setTrgPattern(self, triggerPatternH, triggerPatternL):
- triggerPatternL &= 0xffffffff
- triggerPatternH &= 0xffffffff
- print " TRIGGER PATTERN (for external triggers) SET TO 0x%08X 0x%08X. Two 32-bit words." %(triggerPatternH, triggerPatternL)
- self.hw.getNode("triggerLogic.TriggerPattern_lowW").write(triggerPatternL)
- self.hw.getNode("triggerLogic.TriggerPattern_highW").write(triggerPatternH)
- self.hw.dispatch()
- self.getTrgPattern()
-
- def setVetoDUT(self, ignoreDUTBusy):
- print " VETO IGNORE BY DUT BUSY MASK SET TO" , hex(ignoreDUTBusy)
- self.hw.getNode("DUTInterfaces.IgnoreDUTBusyW").write(ignoreDUTBusy)
- self.hw.dispatch()
- self.getVetoDUT()
-
- def setVetoShutters(self, newState):
- if newState:
- print " IgnoreShutterVetoW SET TO LISTEN FOR VETO FROM SHUTTER"
- cmd= int("0x0",16)
- else:
- print " IgnoreShutterVetoW SET TO IGNORE VETO FROM SHUTTER"
- cmd= int("0x1",16)
- self.hw.getNode("DUTInterfaces.IgnoreShutterVetoW").write(cmd)
- self.hw.dispatch()
- self.getVetoShutters()
-
- def writeThreshold(self, DACtarget, Vtarget, channel):
- #Writes the threshold. The DAC voltage differs from the threshold voltage because
- #the range is shifted to be symmetrical around 0V.
-
- #Check if the DACs are using the internal reference
- if (self.intRefOn):
- Vref= self.VrefInt
- else:
- Vref= self.VrefExt
-
- #Calculate offset voltage (because of the following shifter)
- Vdac= ( Vtarget + Vref ) / 2
- print" THRESHOLD setting:"
- if channel==7:
- print "\tCH: ALL"
- else:
- print "\tCH:", channel
- print "\tTarget V:", Vtarget
- dacValue = 0xFFFF * (Vdac / Vref)
- DACtarget.writeDAC(int(dacValue), channel, True)
-
- def parseFifoData(self, fifoData, nEvents, verbose):
- #for index in range(0, len(fifoData)-1, 6):
- outList= []
- for index in range(0, (nEvents)*6, 6):
- word0= (fifoData[index] << 32) + fifoData[index + 1]
- word1= (fifoData[index + 2] << 32) + fifoData[index + 3]
- word2= (fifoData[index + 4] << 32) + fifoData[index + 5]
- evType= (fifoData[index] & 0xF0000000) >> 28
- inTrig= (fifoData[index] & 0x0FFF0000) >> 16
- tStamp= ((fifoData[index] & 0x0000FFFF) << 32) + fifoData[index + 1]
- fineTs= fifoData[index + 2]
- evNum= fifoData[index + 3]
- fineTsList=[-1]*12
- fineTsList[3]= (fineTs & 0x000000FF)
- fineTsList[2]= (fineTs & 0x0000FF00) >> 8
- fineTsList[1]= (fineTs & 0x00FF0000) >> 16
- fineTsList[0]= (fineTs & 0xFF000000) >> 24
- fineTsList[7]= (fifoData[index + 4] & 0x000000FF)
- fineTsList[6]= (fifoData[index + 4] & 0x0000FF00) >> 8
- fineTsList[5]= (fifoData[index + 4] & 0x00FF0000) >> 16
- fineTsList[4]= (fifoData[index + 4] & 0xFF000000) >> 24
- fineTsList[11]= (fifoData[index + 5] & 0x000000FF)
- fineTsList[10]= (fifoData[index + 5] & 0x0000FF00) >> 8
- fineTsList[9]= (fifoData[index + 5] & 0x00FF0000) >> 16
- fineTsList[8]= (fifoData[index + 5] & 0xFF000000) >> 24
- if verbose:
- print "====== EVENT", evNum, "================================================="
- print "[", hex(word0), "]", "\t TYPE", hex(evType), "\t TRIGGER", hex(inTrig), "\t TIMESTAMP", (tStamp)
- print "[",hex(word1), "]", "\tEV NUM", evNum, "\tFINETS[0,3]", hex(fineTs)
- print "[",hex(word2), "]", "\tFINETS[4,11]", hex(word2)
- print fineTsList
- fineTsList.insert(0, tStamp)
- fineTsList.insert(0, evNum)
- #print fineTsList
- outList.insert(len(outList), fineTsList)
- printdata= False
- if (printdata):
- print "=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-="
- print "EN#\tCOARSE_TS\tFINE_TS0...FINE_TS11"
- pprint.pprint(outList)
- return outList
-
- def plotFifoData(self, outList):
- import matplotlib.pyplot as plt
- import numpy as np
- import matplotlib.mlab as mlab
-
- coarseColumn= [row[1] for row in outList]
- fineColumn= [row[2] for row in outList]
- timeStamp= [sum(x) for x in zip(coarseColumn, fineColumn)]
- correctTs= [-1]*len(coarseColumn)
- coarseVal= 0.000000025 #coarse time value (40 Mhz, 25 ns)
- fineVal= 0.00000000078125 #fine time value (1280 MHz, 0.78125 ns)
- for iTs in range(0, len(coarseColumn)):
- correctTs[iTs]= coarseColumn[iTs]*coarseVal + fineColumn[iTs]*fineVal
- #if iTs:
- #print correctTs[iTs]-correctTs[iTs-1], "\t ", correctTs[iTs], "\t", coarseColumn[iTs], "\t", fineColumn[iTs]
-
- xdiff = np.diff(correctTs)
- np.all(xdiff[0] == xdiff)
- P= 1000000000 #display in ns
- nsDeltas = [x * P for x in xdiff]
- #centerRange= np.mean(nsDeltas)
- centerRange= 476
- windowsns= 30
- minRange= centerRange-windowsns
- maxRange= centerRange+windowsns
-
- #Divide figure in two axes
- plt.subplot(311)
-
- #Create first histogram
- plt.hist(nsDeltas, 60, range=[minRange, maxRange], facecolor='blue', align='mid', alpha= 0.75)
- #plt.hist(nsDeltas, 100, normed=True, facecolor='blue', align='mid', alpha=0.75)
- #plt.xlim((min(nsDeltas), max(nsDeltas)))
- plt.xlabel('Time (ns)')
- plt.ylabel('Entries')
- plt.title('Histogram DeltaTime')
- plt.grid(True)
-
- #Superimpose Gauss to first plot
- mean = np.mean(nsDeltas)
- variance = np.var(nsDeltas)
- sigma = np.sqrt(variance)
- x = np.linspace(min(nsDeltas), max(nsDeltas), 100)
- plt.plot(x, mlab.normpdf(x, mean, sigma))
-
- MSBTs= [-1]*len(fineColumn)
- LSBTs= [-1]*len(fineColumn)
- for iTs in range(0, len(fineColumn)):
- MSBTs[iTs]= fineColumn[iTs] & 0b11000
- LSBTs[iTs]= fineColumn[iTs] & 0b00111
- #if iTs:
- #print correctTs[iTs]-correctTs[iTs-1], "\t ", correctTs[iTs], "\t", coarseColumn[iTs], "\t", fineColumn[iTs]
-
- #Second plot
- plt.subplot(312)
- plt.xlabel('Clock sample')
- plt.ylabel('Entries')
- plt.title('Histogram Fine Time Stamp (2 MSB)')
- plt.grid(True)
- plt.hist(MSBTs, 100, normed=False, facecolor='blue', align='mid', alpha=0.75)
-
- #Third plot
- plt.subplot(313)
- plt.xlabel('Clock sample')
- plt.ylabel('Entries')
- plt.title('Histogram Fine Time Stamp (3 LSB)')
- plt.grid(True)
- plt.hist(LSBTs, 100, normed=False, facecolor='blue', align='mid', alpha=0.75)
-
- #Display plot
- plt.show()
-
-
- def saveFifoData(self, outList):
- import csv
- with open("output.csv", "wb") as f:
- writer = csv.writer(f)
- writer.writerows(outList)
-
-
-##################################################################################################################################
-##################################################################################################################################
-
- def initialize(self):
- print "\nTLU INITIALIZING..."
-
- # We need to pass it listenForTelescopeShutter , pulseDelay , pulseStretch , triggerPattern , DUTMask , ignoreDUTBusy , triggerInterval , thresholdVoltage
-
- #READ CONTENT OF EPROM VIA I2C
- self.getSN()
-
- print " Turning on software trigger veto"
- cmd = int("0x1",16)
- self.setTriggerVetoStatus(cmd)
-
- #
- # #SET DACs
- targetV= -0.12
- DACchannel= 7
- self.writeThreshold(self.zeDAC1, targetV, DACchannel, )
- self.writeThreshold(self.zeDAC2, targetV, DACchannel, )
-
- #
- # #ENABLE/DISABLE HDMI OUTPUTS
- self.DUTOutputs(0, True, False)
- self.DUTOutputs(1, True, False)
- self.DUTOutputs(2, True, False)
- self.DUTOutputs(3, True, False)
-
- ## ENABLE/DISABLE LEMO CLOCK OUTPUT
- self.enableClkLEMO(True, False)
-
- #
- # #Check clock status
- self.getClockStatus()
-
- resetClocks = 0
- resetSerdes = 0
- resetCounters= 0
- if resetClocks:
- self.resetClocks()
- self.getClockStatus()
- if resetSerdes:
- self.resetSerdes()
- if resetCounters:
- self.resetCounters()
-
- # # Get inputs status and counters
- self.getChStatus()
- self.getAllChannelsCounts()
- #
- # # Stop internal triggers until setup complete
- cmd = int("0x0",16)
- self.setInternalTrg(cmd)
- #
- # # Set pulse stretch
- pulseStretch= 0x00000000
- self.setPulseStretch(pulseStretch)
- #
- # # Set pulse delay
- pulseDelay= 0x00
- self.setPulseDelay(pulseDelay)
-
- # # Set trigger pattern
- #triggerPattern_low= 0xFFFEFFFE
- #triggerPattern_high= 0xFFFFFFFF
- triggerPattern_low= 0x00010102
- triggerPattern_low= 0x00000002
- triggerPattern_high= 0x00000000
- self.setTrgPattern(triggerPattern_high, triggerPattern_low)
-
- # # Set DUTs
- DUTMask= 0xF
- self.setDUTmask(DUTMask)
- #
- # # # Set mode
- DUTMode= 0xFFFFFFFF
- self.setMode(DUTMode)
-
- # # # Set modifier
- modifier = int("0xFF",16)
- self.setModeModifier(modifier)
- #
- # # Set veto shutter
- setVetoShutters=0
- self.setVetoShutters(setVetoShutters)
-
- # # Set veto by DUT
- ignoreDUTBusy=0x0
- self.setVetoDUT(ignoreDUTBusy)
- self.getExternalVeto()
- #
- # # Set trigger interval (use 0 to disable internal triggers)
- triggerInterval= 0000
- self.setInternalTrg(triggerInterval)
-
- print "TLU INITIALIZED"
-
-##################################################################################################################################
-##################################################################################################################################
- def start(self, logtimestamps=False):
- print "TLU STARTING..."
-
- print " FIFO RESET:"
- FIFOcmd= 0x2
- self.setFifoCSR(FIFOcmd)
-
- eventFifoFillLevel= self.getFifoLevel()
- cmd = int("0x000",16)
- self.setInternalTrg(cmd)
-
- if logtimestamps:
- self.setRecordDataStatus(True)
- else:
- self.setRecordDataStatus(False)
-
- # Pulse T0
- self.pulseT0()
-
- print " Turning off software trigger veto"
- cmd = int("0x0",16)
- self.setTriggerVetoStatus(cmd)
-
- print "TLU RUNNING"
-
-##################################################################################################################################
-##################################################################################################################################
- def stop(self):
- print "TLU STOPPING..."
-
- self.getPostVetoTrg()
- eventFifoFillLevel= self.getFifoLevel()
- print " Turning on software trigger veto"
- cmd = int("0x1",16)
- self.setTriggerVetoStatus(cmd)
-
- nFifoWords= int(eventFifoFillLevel)
- fifoData= self.getFifoData(nFifoWords)
-
- outList= self.parseFifoData(fifoData, nFifoWords/6, False)
- self.saveFifoData(outList)
- self.plotFifoData(outList)
- #outFile = open('./test.txt', 'w')
- #for iData in range (0, 30):
- # outFile.write("%s\n" % fifoData[iData])
- # print hex(fifoData[iData])
- print "TLU STOPPED"
diff --git a/TLU_v1c/scripts/TLUconnection.xml b/TLU_v1c/scripts/TLUconnection.xml
deleted file mode 100644
index fca67f5..0000000
--- a/TLU_v1c/scripts/TLUconnection.xml
+++ /dev/null
@@ -1,6 +0,0 @@
-
-
-
-
-
diff --git a/TLU_v1c/scripts/initTLU.py b/TLU_v1c/scripts/initTLU.py
deleted file mode 100644
index eb1ae65..0000000
--- a/TLU_v1c/scripts/initTLU.py
+++ /dev/null
@@ -1,184 +0,0 @@
-#
-# Function to initialize TLU
-#
-# David Cussans, October 2015
-#
-# Nasty hack - use both PyChips and uHAL ( for block read ... )
-
-from PyChipsUser import *
-from FmcTluI2c import *
-
-import uhal
-
-import sys
-import time
-
-def startTLU( uhalDevice , pychipsBoard , writeTimestamps):
-
- print "RESETTING FIFO"
- pychipsBoard.write("EventFifoCSR",0x2)
- eventFifoFillLevel = pychipsBoard.read("EventFifoFillLevel")
- print "FIFO FILL LEVEL AFTER RESET= " , eventFifoFillLevel
-
-
- if writeTimestamps:
- print "ENABLING DATA RECORDING"
- pychipsBoard.write("Enable_Record_Data",1)
- else:
- print "Disabling data recording"
- pychipsBoard.write("Enable_Record_Data",0)
-
- print "Pulsing T0"
- pychipsBoard.write("PulseT0",1)
-
- print "Turning off software trigger veto"
- pychipsBoard.write("TriggerVetoW",0)
-
- print "TLU is running"
-
-
-def stopTLU( uhalDevice , pychipsBoard ):
-
- print "Turning on software trigger veto"
- pychipsBoard.write("TriggerVetoW",1)
-
- print "TLU triggers are stopped"
-
-def initTLU( uhalDevice , pychipsBoard , listenForTelescopeShutter , pulseDelay , pulseStretch , triggerPattern , DUTMask , ignoreDUTBusy , triggerInterval , thresholdVoltage ):
-
- print "SETTING UP AIDA TLU"
-
- fwVersion = uhalDevice.getNode("version").read()
- uhalDevice.dispatch()
- print "\tVersion (uHAL)= " , hex(fwVersion)
-
- print "\tTurning on software trigger veto"
- pychipsBoard.write("TriggerVetoW",1)
-
- # Check the bus for I2C devices
- pychipsBoardi2c = FmcTluI2c(pychipsBoard)
-
- print "\tScanning I2C bus:"
- scanResults = pychipsBoardi2c.i2c_scan()
- #print scanResults
- print '\t', ', '.join(scanResults), '\n'
-
- boardId = pychipsBoardi2c.get_serial_number()
- print "\tFMC-TLU serial number= " , boardId
-
- resetClocks = 0
- resetSerdes = 0
-
-# set DACs to -200mV
- print "\tSETTING ALL DAC THRESHOLDS TO" , thresholdVoltage , "V"
- pychipsBoardi2c.set_threshold_voltage(7, thresholdVoltage)
-
- clockStatus = pychipsBoard.read("LogicClocksCSR")
- print "\tCLOCK STATUS (should be 3 if all clocks locked)= " , hex(clockStatus)
- assert ( clockStatus == 3 ) , "Clocks in TLU FPGA are not locked. No point in continuing. Re-prgramme or power cycle board"
-
- if resetClocks:
- print "Resetting clocks"
- pychipsBoard.write("LogicRst", 1 )
-
- clockStatus = pychipsBoard.read("LogicClocksCSR")
- print "Clock status after reset = " , hex(clockStatus)
-
- inputStatus = pychipsBoard.read("SerdesRstR")
- print "Input status = " , hex(inputStatus)
-
- if resetSerdes:
- pychipsBoard.write("SerdesRstW", 0x00000003 )
- inputStatus = pychipsBoard.read("SerdesRstR")
- print "Input status during reset = " , hex(inputStatus)
-
- pychipsBoard.write("SerdesRstW", 0x00000000 )
- inputStatus = pychipsBoard.read("SerdesRstR")
- print "Input status after reset = " , hex(inputStatus)
-
- pychipsBoard.write("SerdesRstW", 0x00000004 )
- inputStatus = pychipsBoard.read("SerdesRstR")
- print "Input status during calibration = " , hex(inputStatus)
-
- pychipsBoard.write("SerdesRstW", 0x00000000 )
- inputStatus = pychipsBoard.read("SerdesRstR")
- print "Input status after calibration = " , hex(inputStatus)
-
-
- inputStatus = pychipsBoard.read("SerdesRstR")
- print "\tINPUT STATUS= " , hex(inputStatus)
-
- count0 = pychipsBoard.read("ThrCount0R")
- print "\t Count 0= " , count0
-
- count1 = pychipsBoard.read("ThrCount1R")
- print "\t Count 1= " , count1
-
- count2 = pychipsBoard.read("ThrCount2R")
- print "\t Count 2= " , count2
-
- count3 = pychipsBoard.read("ThrCount3R")
- print "\t Count 3= " , count3
-
-# Stop internal triggers until setup complete
- pychipsBoard.write("InternalTriggerIntervalW",0)
-
- print "\tSETTING INPUT COINCIDENCE WINDOW TO",pulseStretch,"[Units= 160MHz clock cycles, Four 5-bit values (one per input) packed in to 32-bit word]"
- pychipsBoard.write("PulseStretchW",int(pulseStretch))
- pulseStretchR = pychipsBoard.read("PulseStretchR")
- print "\t Pulse stretch read back as:", hex(pulseStretchR)
- # assert (int(pulseStretch) == pulseStretchR) , "Pulse stretch read-back doesn't equal written value"
-
- print "\tSETTING INPUT TRIGGER DELAY TO",pulseDelay , "[Units= 160MHz clock cycles, Four 5-bit values (one per input) packed in to 32-bit word]"
- pychipsBoard.write("PulseDelayW",int(pulseDelay))
- pulseDelayR = pychipsBoard.read("PulseDelayR")
- print "\t Pulse delay read back as:", hex(pulseDelayR)
-
- print "\tSETTING TRIGGER PATTERN (for external triggers) TO 0x%08X. Two 16-bit patterns packed into 32 bit word " %(triggerPattern)
- pychipsBoard.write("TriggerPatternW",int(triggerPattern))
- triggerPatternR = pychipsBoard.read("TriggerPatternR")
- print "\t Trigger pattern read back as: 0x%08X " % (triggerPatternR)
-
- print "\tENABLING DUT(s): Mask= " , hex(DUTMask)
- pychipsBoard.write("DUTMaskW",int(DUTMask))
- DUTMaskR = pychipsBoard.read("DUTMaskR")
- print "\t DUTMask read back as:" , hex(DUTMaskR)
-
- print "\tSETTING ALL DUTs IN AIDA MODE"
- pychipsBoard.write("DUTInterfaceModeW", 0xFF)
- DUTInterfaceModeR = pychipsBoard.read("DUTInterfaceModeR")
- print "\t DUT mode read back as:" , DUTInterfaceModeR
-
- print "\tSET DUT MODE MODIFIER"
- pychipsBoard.write("DUTInterfaceModeModifierW", 0xFF)
- DUTInterfaceModeModifierR = pychipsBoard.read("DUTInterfaceModeModifierR")
- print "\t DUT mode modifier read back as:" , DUTInterfaceModeModifierR
-
- if listenForTelescopeShutter:
- print "\tSET IgnoreShutterVetoW TO LISTEN FOR VETO FROM SHUTTER"
- pychipsBoard.write("IgnoreShutterVetoW",0)
- else:
- print "\tSET IgnoreShutterVetoW TO IGNORE VETO FROM SHUTTER"
- pychipsBoard.write("IgnoreShutterVetoW",1)
- IgnoreShutterVeto = pychipsBoard.read("IgnoreShutterVetoR")
- print "\t IgnoreShutterVeto read back as:" , IgnoreShutterVeto
-
- print "\tSETTING IGNORE VETO BY DUT BUSY MASK TO" , hex(ignoreDUTBusy)
- pychipsBoard.write("IgnoreDUTBusyW",int(ignoreDUTBusy))
- IgnoreDUTBusy = pychipsBoard.read("IgnoreDUTBusyR")
- print "\t IgnoreDUTBusy read back as:" , hex(IgnoreDUTBusy)
-
-#print "Enabling handshake: No-handshake"
-#board.write("HandshakeTypeW",1)
-
-
- print "\tSETTING INTERNAL TRIGGER INTERVAL TO" , triggerInterval , "(zero= no internal triggers)"
- if triggerInterval == 0:
- internalTriggerFreq = 0
- else:
- internalTriggerFreq = 160000.0/triggerInterval
- print "\tINTERNAL TRIGGER FREQUENCY= " , internalTriggerFreq , " kHz"
- pychipsBoard.write("InternalTriggerIntervalW",triggerInterval) #0->Internal pulse generator disabled. Any other value will generate pulses with a frequency of n*6.25ns
- trigIntervalR = pychipsBoard.read("InternalTriggerIntervalR")
- print "\t Trigger interval read back as:", trigIntervalR
- print "AIDA TLU SETUP COMPLETED"
diff --git a/TLU_v1c/scripts/output_check.csv b/TLU_v1c/scripts/output_check.csv
deleted file mode 100644
index 7932e23..0000000
--- a/TLU_v1c/scripts/output_check.csv
+++ /dev/null
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diff --git a/TLU_v1c/scripts/startTLU.sh b/TLU_v1c/scripts/startTLU.sh
deleted file mode 100644
index 311d785..0000000
--- a/TLU_v1c/scripts/startTLU.sh
+++ /dev/null
@@ -1,25 +0,0 @@
-#!/bin/bash
-
-echo "=========================="
-CURRENT_DIR=${0%/*}
-echo "CURRENT DIRECTORY: " $CURRENT_DIR
-
-echo "============"
-echo "SETTING PATHS"
-#export PYTHONPATH=$CURRENT_DIR/../../../../Python_Scripts/PyChips_1_5_0_pre2A/src:$PYTHONPATH
-#export PYTHONPATH=~/Python_Scripts/PyChips_1_5_0_pre2A/src:$PYTHONPATH
-export PYTHONPATH=../../packages:$PYTHONPATH
-echo "PYTHON PATH= " $PYTHONPATH
-export LD_LIBRARY_PATH=/opt/cactus/lib:$LD_LIBRARY_PATH
-echo "LD_LIBRARY_PATH= " $LD_LIBRARY_PATH
-export PATH=/usr/bin/:/opt/cactus/bin:$PATH
-echo "PATH= " $PATH
-
-cd $CURRENT_DIR
-
-echo "============"
-echo "STARTING PYTHON SCRIPT FOR TLU"
-#python $CURRENT_DIR/startTLU_v8.py $@
-
-python startTLU_v8.py $@
-#python testTLU_script.py
diff --git a/TLU_v1c/scripts/startTLU_v6.py b/TLU_v1c/scripts/startTLU_v6.py
deleted file mode 100644
index b7948f2..0000000
--- a/TLU_v1c/scripts/startTLU_v6.py
+++ /dev/null
@@ -1,232 +0,0 @@
-#
-# Script to setup AIDA TLU for TPix3 telescope <--> TORCH synchronization
-#
-# David Cussans, December 2012
-#
-# Nasty hack - use both PyChips and uHAL ( for block read ... )
-
-from PyChipsUser import *
-from FmcTluI2c import *
-
-import uhal
-
-import sys
-
-import time
-
-from datetime import datetime
-
-from optparse import OptionParser
-
-# For single character non-blocking input:
-import select
-import tty
-import termios
-
-from initTLU import *
-
-def isData():
- return select.select([sys.stdin], [], [], 0) == ([sys.stdin], [], [])
-
-now = datetime.now().strftime('%Y-%m-%dT%H_%M_%S')
-default_filename = 'tluData_' + now + '.root'
-parser = OptionParser()
-
-parser.add_option('-r','--rootFname',dest='rootFname',
- default=default_filename,help='Path of output file')
-parser.add_option('-o','--writeTimestamps',dest='writeTimestamps',
- default="True",help='Set True to write timestamps to ROOT file')
-parser.add_option('-p','--printTimestamps',dest='printTimestamps',
- default="True",help='Set True to print timestamps to screen (nothing printed unless also output to file) ')
-parser.add_option('-s','--listenForTelescopeShutter',dest='listenForTelescopeShutter',
- default=False,help='Set True to veto triggers when shutter goes high')
-parser.add_option('-d','--pulseDelay',dest='pulseDelay', type=int,
- default=0x00,help='Delay added to input triggers. Four 5-bit numbers packed into 32-bt word, Units of 6.125ns')
-parser.add_option('-w','--pulseStretch',dest='pulseStretch',type=int,
- default=0x00,help='Width added to input triggers. Four 5-bit numbers packed into 32-bt word. Units of 6.125ns')
-parser.add_option('-t','--triggerPattern',dest='triggerPattern',type=int,
- default=0xFFFEFFFE,help='Pattern match to generate trigger. Two 16-bit words packed into 32-bit word.')
-parser.add_option('-m','--DUTMask',dest='DUTMask',type=int,
- default=0x01,help='Three-bit mask selecting which DUTs are active.')
-parser.add_option('-y','--ignoreDUTBusy',dest='ignoreDUTBusy',type=int,
- default=0x0F,help='Three-bit mask selecting which DUTs can veto triggers by setting BUSY high. Low = can veto, high = ignore busy.')
-parser.add_option('-i','--triggerInterval',dest='triggerInterval',type=int,
- default=0,help='Interval between internal trigers ( in units of 6.125ns ). Set to zero to turn off internal triggers')
-parser.add_option('-v','--thresholdVoltage',dest='thresholdVoltage',type=float,
- default=-0.2,help='Threshold voltage for TLU inputs ( units of volts)')
-
-(options, args) = parser.parse_args(sys.argv[1:])
-
-from ROOT import TFile, TTree
-from ROOT import gROOT
-
-print "SETTING UP AIDA TLU TO SUPPLY CLOCK AND TRIGGER TO TORCH READOUT\n"
-
-# Point to board in uHAL
-manager = uhal.ConnectionManager("file://./connection.xml")
-hw = manager.getDevice("minitlu")
-device_id = hw.id()
-
-# Point to TLU in Pychips
-bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
-
-# Assume DIP-switch controlled address. Switches at 2
-board = ChipsBusUdp(bAddrTab,"192.168.200.32",50001)
-
-# Open Root file
-print "OPENING ROOT FILE:", options.rootFname
-f = TFile( options.rootFname, 'RECREATE' )
-
-# Create a root "tree"
-tree = TTree( 'T', 'TLU Data' )
-highWord =0
-lowWord =0
-evtNumber=0
-timeStamp=0
-evtType=0
-trigsFired=0
-bufPos = 0
-
-# Create a branch for each piece of data
-tree.Branch( 'tluHighWord' , highWord , "HighWord/l")
-tree.Branch( 'tluLowWord' , lowWord , "LowWord/l")
-tree.Branch( 'tluTimeStamp' , timeStamp , "TimeStamp/l")
-tree.Branch( 'tluBufPos' , bufPos , "Bufpos/s")
-tree.Branch( 'tluEvtNumber' , evtNumber , "EvtNumber/i")
-tree.Branch( 'tluEvtType' , evtType , "EvtType/b")
-tree.Branch( 'tluTrigFired' , trigsFired, "TrigsFired/b")
-
-# Initialize TLU registers
-initTLU( uhalDevice = hw, pychipsBoard = board, listenForTelescopeShutter = options.listenForTelescopeShutter, pulseDelay = options.pulseDelay, pulseStretch = options.pulseStretch, triggerPattern = options.triggerPattern , DUTMask = options.DUTMask, ignoreDUTBusy = options.ignoreDUTBusy , triggerInterval = options.triggerInterval, thresholdVoltage = options.thresholdVoltage )
-
-loopWait = 0.1
-oldEvtNumber = 0
-
-oldPreVetotriggerCount = board.read("PreVetoTriggersR")
-oldPostVetotriggerCount = board.read("PostVetoTriggersR")
-
-oldThresholdCounter0 =0
-oldThresholdCounter1 =0
-oldThresholdCounter2 =0
-oldThresholdCounter3 =0
-
-print "STARTING POLLING LOOP"
-
-eventFifoFillLevel = 0
-loopRunning = True
-runStarted = False
-
-oldTime = time.time()
-
-# Save old terminal settings
-oldTermSettings = termios.tcgetattr(sys.stdin)
-tty.setcbreak(sys.stdin.fileno())
-
-while loopRunning:
-
- if isData():
- c = sys.stdin.read(1)
- print "\tGOT INPUT:", c
- if c == 't':
- loopRunning = False
- print "\tTERMINATING LOOP"
- elif c == 'c':
- runStarted = True
- print "\tSTARTING RUN"
- startTLU( uhalDevice = hw, pychipsBoard = board, writeTimestamps = ( options.writeTimestamps == "True" ) )
- elif c == 'f':
- # runStarted = True
- print "\tSTOPPING TRIGGERS"
- stopTLU( uhalDevice = hw, pychipsBoard = board )
-
-
- if runStarted:
-
- eventFifoFillLevel = hw.getNode("eventBuffer.EventFifoFillLevel").read()
-
- preVetotriggerCount = hw.getNode("triggerLogic.PreVetoTriggersR").read()
- postVetotriggerCount = hw.getNode("triggerLogic.PostVetoTriggersR").read()
-
- timestampHigh = hw.getNode("Event_Formatter.CurrentTimestampHR").read()
- timestampLow = hw.getNode("Event_Formatter.CurrentTimestampLR").read()
-
- thresholdCounter0 = hw.getNode("triggerInputs.ThrCount0R").read()
- thresholdCounter1 = hw.getNode("triggerInputs.ThrCount1R").read()
- thresholdCounter2 = hw.getNode("triggerInputs.ThrCount2R").read()
- thresholdCounter3 = hw.getNode("triggerInputs.ThrCount3R").read()
-
- hw.dispatch()
-
- newTime = time.time()
- timeDelta = newTime - oldTime
- oldTime = newTime
- #print "time delta = " , timeDelta
- preVetoFreq = (preVetotriggerCount-oldPreVetotriggerCount)/timeDelta
- postVetoFreq = (postVetotriggerCount-oldPostVetotriggerCount)/timeDelta
- oldPreVetotriggerCount = preVetotriggerCount
- oldPostVetotriggerCount = postVetotriggerCount
-
- deltaCounts0 = thresholdCounter0 - oldThresholdCounter0
- oldThresholdCounter0 = thresholdCounter0
- deltaCounts1 = thresholdCounter1 - oldThresholdCounter1
- oldThresholdCounter1 = thresholdCounter1
- deltaCounts2 = thresholdCounter2 - oldThresholdCounter2
- oldThresholdCounter2 = thresholdCounter2
- deltaCounts3 = thresholdCounter3 - oldThresholdCounter3
- oldThresholdCounter3 = thresholdCounter3
-
- print "pre , post veto triggers , pre , post frequency = " , preVetotriggerCount , postVetotriggerCount , preVetoFreq , postVetoFreq
-
- print "CURRENT TIMESTAMP HIGH, LOW (hex) = " , hex(timestampHigh) , hex(timestampLow)
-
- print "Input counts 0,1,2,3 = " , thresholdCounter0 , thresholdCounter1 , thresholdCounter2 , thresholdCounter3
- print "Input freq (Hz) 0,1,2,3 = " , deltaCounts0/timeDelta , deltaCounts1/timeDelta , deltaCounts2/timeDelta , deltaCounts3/timeDelta
-
- nEvents = int(eventFifoFillLevel)//4 # only read out whole events ( 4 x 32-bit words )
- wordsToRead = nEvents*4
-
- print "FIFO FILL LEVEL= " , eventFifoFillLevel
-
- print "# EVENTS IN FIFO = ",nEvents
- print "WORDS TO READ FROM FIFO = ",wordsToRead
-
- # get timestamp data and fifo fill in same outgoing packet.
- timestampData = hw.getNode("eventBuffer.EventFifoData").readBlock(wordsToRead)
-
- hw.dispatch()
-
- # print timestampData
- for bufPos in range (0, nEvents ):
- lowWord = timestampData[bufPos*4 + 1] + 0x100000000* timestampData[ (bufPos*4) + 0] # timestamp
-
- highWord = timestampData[bufPos*4 + 3] + 0x100000000* timestampData[ (bufPos*4) + 2] # evt number
- evtNumber = timestampData[bufPos*4 + 3]
-
- if evtNumber != ( oldEvtNumber + 1 ):
- print "***WARNING *** Non sqeuential event numbers *** , evt,oldEvt = ", evtNumber , oldEvtNumber
-
- oldEvtNumber = evtNumber
-
- timeStamp = lowWord & 0xFFFFFFFFFFFF
-
- evtType = timestampData[ (bufPos*4) + 0] >> 28
-
- trigsFired = (timestampData[ (bufPos*4) + 0] >> 16) & 0xFFF
-
- if (options.printTimestamps == "True" ):
- print "bufferPos, highWord , lowWord , event-number , timestamp , evtType = %x %016x %016x %08x %012x %01x %03x" % ( bufPos , highWord , lowWord, evtNumber , timeStamp , evtType , trigsFired)
-
- # Fill root branch - see example in http://wlav.web.cern.ch/wlav/pyroot/tpytree.html : write raw data and decoded data for now.
- tree.Fill()
-
- time.sleep( loopWait)
-
-# Fixme - at the moment infinite loop.
-preVetotriggerCount = board.read("PreVetoTriggersR")
-postVetotriggerCount = board.read("PostVetoTriggersR")
-print "EXIT POLLING LOOP"
-print "\nTRIGGER COUNT AT THE END OF RUN [pre, post]:" , preVetotriggerCount , postVetotriggerCount
-
-termios.tcsetattr(sys.stdin, termios.TCSADRAIN, oldTermSettings)
-f.Write()
-f.Close()
diff --git a/TLU_v1c/scripts/startTLU_v8.py b/TLU_v1c/scripts/startTLU_v8.py
deleted file mode 100644
index 470d173..0000000
--- a/TLU_v1c/scripts/startTLU_v8.py
+++ /dev/null
@@ -1,72 +0,0 @@
-# -*- coding: utf-8 -*-
-# miniTLU test script
-
-#from PyChipsUser import *
-#from FmcTluI2c import *
-import uhal
-import sys
-import time
-# from ROOT import TFile, TTree
-# from ROOT import gROOT
-from datetime import datetime
-
-from TLU import TLU
-# Use to have interactive shell
-import cmd
-
-class MyPrompt(cmd.Cmd):
-
-
- def do_startRun(self, args):
- """Starts the TLU run"""
- print "COMMAND RECEIVED: STARTING TLU RUN"
- startTLU( uhalDevice = self.hw, pychipsBoard = self.board, writeTimestamps = ( options.writeTimestamps == "True" ) )
- #print self.hw
-
- def do_stopRun(self, args):
- """Stops the TLU run"""
- print "COMMAND RECEIVED: STOP TLU RUN"
- #stopTLU( uhalDevice = hw, pychipsBoard = board )
-
- def do_quit(self, args):
- """Quits the program."""
- print "COMMAND RECEIVED: QUITTING SCRIPT."
- #raise SystemExit
- return True
-
-# # Override methods in Cmd object ##
-# def preloop(self):
-# """Initialization before prompting user for commands.
-# Despite the claims in the Cmd documentaion, Cmd.preloop() is not a stub.
-# """
-# cmd.Cmd.preloop(self) # # sets up command completion
-# self._hist = [] # # No history yet
-# self._locals = {} # # Initialize execution namespace for user
-# self._globals = {}
-# print "\nINITIALIZING"
-# now = datetime.now().strftime('%Y-%m-%dT%H_%M_%S')
-# default_filename = './rootfiles/tluData_' + now + '.root'
-# print "SETTING UP AIDA TLU TO SUPPLY CLOCK AND TRIGGER TO TORCH READOUT\n"
-# self.manager = uhal.ConnectionManager("file://./connection.xml")
-# self.hw = self.manager.getDevice("minitlu")
-# self.device_id = self.hw.id()
-#
-# # Point to TLU in Pychips
-# self.bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
-#
-# # Assume DIP-switch controlled address. Switches at 2
-# self.board = ChipsBusUdp(self.bAddrTab,"192.168.200.32",50001)
-
-
-#################################################
-if __name__ == "__main__":
- TLU= TLU("tlu", "file://./TLUconnection.xml")
- TLU.initialize()
-
- logdata= True
- TLU.start(logdata)
- time.sleep(0.2)
- TLU.stop()
- # prompt = MyPrompt()
- # prompt.prompt = '>> '
- # prompt.cmdloop("Welcome to miniTLU test console.\nType HELP for a list of commands.")
diff --git a/TLU_v1c/scripts/test.py b/TLU_v1c/scripts/test.py
deleted file mode 100644
index ac68201..0000000
--- a/TLU_v1c/scripts/test.py
+++ /dev/null
@@ -1,34 +0,0 @@
-import matplotlib.pyplot as plt
-import numpy as np
-import matplotlib.mlab as mlab
-
-print "TEST.py"
-myFile= "./500ns_23ns.txt"
-
-with open(myFile) as f:
- nsDeltas = map(float, f)
-
-P= 1000000000 #display in ns
-nsDeltas = [x * P for x in nsDeltas]
-centerRange= 25
-windowsns= 5
-minRange= centerRange-windowsns
-maxRange= centerRange+windowsns
-plt.hist(nsDeltas, 60, range=[minRange, maxRange], facecolor='blue', align='mid', alpha= 0.75)
-#plt.hist(nsDeltas, 100, normed=True, facecolor='blue', align='mid', alpha=0.75)
-#plt.xlim((min(nsDeltas), max(nsDeltas)))
-plt.xlabel('Time (ns)')
-plt.ylabel('Entries')
-plt.title('Histogram DeltaTime')
-plt.grid(True)
-
-#Superimpose Gauss
-mean = np.mean(nsDeltas)
-variance = np.var(nsDeltas)
-sigma = np.sqrt(variance)
-x = np.linspace(min(nsDeltas), max(nsDeltas), 100)
-plt.plot(x, mlab.normpdf(x, mean, sigma))
-print (mean, sigma)
-
-#Display plot
-plt.show()
diff --git a/TLU_v1c/scripts/testTLU_script.py b/TLU_v1c/scripts/testTLU_script.py
deleted file mode 100644
index 9d8b334..0000000
--- a/TLU_v1c/scripts/testTLU_script.py
+++ /dev/null
@@ -1,79 +0,0 @@
-# miniTLU test script
-
-from FmcTluI2c import *
-import uhal
-import sys
-import time
-from I2CuHal import I2CCore
-from miniTLU import MiniTLU
-from datetime import datetime
-
-if __name__ == "__main__":
- print "\tTEST TLU SCRIPT"
- miniTLU= MiniTLU("minitlu", "file://./connection.xml")
- #(self, target, wclk, i2cclk, name="i2c", delay=None)
- TLU_I2C= I2CCore(miniTLU.hw, 10, 5, "i2c_master", None)
- TLU_I2C.state()
-
-
- #READ CONTENT OF EEPROM ON 24AA02E48 (0xFA - 0XFF)
- mystop= 1
- time.sleep(0.1)
- myaddr= [0xfa]
- TLU_I2C.write( 0x50, myaddr, mystop)
- res=TLU_I2C.read( 0x50, 6)
- print "Checkin EEPROM:"
- result="\t"
- for iaddr in res:
- result+="%02x "%(iaddr)
- print result
-
- #SCAN I2C ADDRESSES
- #WRITE PROM
- #WRITE DAC
-
-
- #Convert required threshold voltage to DAC code
- #def convert_voltage_to_dac(self, desiredVoltage, Vref=1.300):
- print("Writing DAC setting:")
- Vref= 1.300
- desiredVoltage= 3.3
- channel= 0
- i2cSlaveAddrDac = 0x1F
- vrefOn= 0
- Vdaq = ( desiredVoltage + Vref ) / 2
- dacCode = 0xFFFF * Vdaq / Vref
- dacCode= 0x391d
- print "\tVreq:", desiredVoltage
- print "\tDAC code:" , dacCode
- print "\tCH:", channel
- print "\tIntRef:", vrefOn
-
- #Set DAC value
- #def set_dac(self,channel,value , vrefOn = 0 , i2cSlaveAddrDac = 0x1F):
- if channel<0 or channel>7:
- print "set_dac ERROR: channel",channel,"not in range 0-7 (bit mask)"
- ##return -1
- if dacCode<0 or dacCode>0xFFFF:
- print "set_dac ERROR: value",dacCode ,"not in range 0-0xFFFF"
- ##return -1
- # AD5665R chip with A0,A1 tied to ground
- #i2cSlaveAddrDac = 0x1F # seven bit address, binary 00011111
-
- # print "I2C address of DAC = " , hex(i2cSlaveAddrDac)
- # dac = RawI2cAccess(self.i2cBusProps, i2cSlaveAddrDac)
- # # if we want to enable internal voltage reference:
-
- if vrefOn:
- # enter vref-on mode:
- print "\tTurning internal reference ON"
- #dac.write([0x38,0x00,0x01])
- TLU_I2C.write( i2cSlaveAddrDac, [0x38,0x00,0x01], 0)
- else:
- print "\tTurning internal reference OFF"
- #dac.write([0x38,0x00,0x00])
- TLU_I2C.write( i2cSlaveAddrDac, [0x38,0x00,0x00], 0)
- # Now set the actual value
- sequence=[( 0x18 + ( channel &0x7 ) ) , int(dacCode/256)&0xff , int(dacCode)&0xff]
- print "\tWriting byte sequence:", sequence
- TLU_I2C.write( i2cSlaveAddrDac, sequence, 0)
diff --git a/TLU_v1c/scripts/test_T0.py b/TLU_v1c/scripts/test_T0.py
deleted file mode 100644
index cf81b33..0000000
--- a/TLU_v1c/scripts/test_T0.py
+++ /dev/null
@@ -1,92 +0,0 @@
-#
-# Script to exercise AIDA mini-TLU
-#
-# David Cussans, December 2012
-#
-# Nasty hack - use both PyChips and uHAL ( for block read ... )
-
-from PyChipsUser import *
-from FmcTluI2c import *
-
-import sys
-import time
-
-
-# Point to TLU in Pychips
-bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
-# Assume DIP-switch controlled address. Switches at 2
-board = ChipsBusUdp(bAddrTab,"192.168.200.32",50001)
-
-# Check the bus for I2C devices
-boardi2c = FmcTluI2c(board)
-
-firmwareID=board.read("FirmwareId")
-
-print "Firmware (from PyChips) = " , hex(firmwareID)
-
-print "Scanning I2C bus:"
-scanResults = boardi2c.i2c_scan()
-print scanResults
-
-boardId = boardi2c.get_serial_number()
-print "FMC-TLU serial number = " , boardId
-
-resetClocks = 0
-
-
-
-clockStatus = board.read("LogicClocksCSR")
-print "Clock status = " , hex(clockStatus)
-
-if resetClocks:
- print "Resetting clocks"
- board.write("LogicRst", 1 )
-
- clockStatus = board.read("LogicClocksCSR")
- print "Clock status after reset = " , hex(clockStatus)
-
-
-board.write("InternalTriggerIntervalW",0)
-
-print "Enabling DUT 0 and 1"
-board.write("DUTMaskW",3)
-DUTMask = board.read("DUTMaskR")
-print "DUTMaskR = " , DUTMask
-
-print "Ignore veto on DUT 0 and 1"
-board.write("IgnoreDUTBusyW",3)
-IgnoreDUTBusy = board.read("IgnoreDUTBusyR")
-print "IgnoreDUTBusyR = " , IgnoreDUTBusy
-
-print "Turning off software trigger veto"
-board.write("TriggerVetoW",0)
-
-print "Reseting FIFO"
-board.write("EventFifoCSR",0x2)
-eventFifoFillLevel = board.read("EventFifoFillLevel")
-print "FIFO fill level after resetting FIFO = " , eventFifoFillLevel
-
-print "Enabling data recording"
-board.write("Enable_Record_Data",1)
-
-#print "Enabling handshake: No-handshake"
-#board.write("HandshakeTypeW",1)
-
-#TriggerInterval = 400000
-TriggerInterval = 0
-print "Setting internal trigger interval to " , TriggerInterval
-board.write("InternalTriggerIntervalW",TriggerInterval) #0->Internal pulse generator disabled. Any other value will generate pulses with a frequency of n*6.25ns
-trigInterval = board.read("InternalTriggerIntervalR")
-print "Trigger interval read back as ", trigInterval
-
-print "Setting TPix_maskexternal to ignore external shutter and T0"
-board.write("TPix_maskexternal",0x0003)
-
-numLoops = 500000
-oldEvtNumber = 0
-
-for iLoop in range(0,numLoops):
-
- board.write("TPix_T0", 0x0001)
-
-# time.sleep( 1.0)
diff --git a/TLU_v1e/.svn/entries b/TLU_v1e/.svn/entries
deleted file mode 100644
index b806c37..0000000
--- a/TLU_v1e/.svn/entries
+++ /dev/null
@@ -1,28 +0,0 @@
-10
-
-dir
-0
-https://app.deveo.com/universityofbristol/projects/fmc_tlu/repositories/subversion/AIDA/TLU_v1e
-https://app.deveo.com/universityofbristol/projects/fmc_tlu/repositories/subversion/AIDA
-add
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-a80b426a-c11e-11e6-a987-c3d832fc0b90
-
diff --git a/TLU_v1e/documents/FMC_TLU_TOPLEVEL_E.SCH.1.pdf b/TLU_v1e/documents/FMC_TLU_TOPLEVEL_E.SCH.1.pdf
deleted file mode 100644
index e1c970a..0000000
Binary files a/TLU_v1e/documents/FMC_TLU_TOPLEVEL_E.SCH.1.pdf and /dev/null differ
diff --git a/TLU_v1e/documents/TLU_v1E_TestPoints.pdf b/TLU_v1e/documents/TLU_v1E_TestPoints.pdf
deleted file mode 100644
index 4e7a2b4..0000000
Binary files a/TLU_v1e/documents/TLU_v1E_TestPoints.pdf and /dev/null differ
diff --git a/TLU_v1e/scripts/AIDA_testPower.py b/TLU_v1e/scripts/AIDA_testPower.py
deleted file mode 100644
index 9c13ba6..0000000
--- a/TLU_v1e/scripts/AIDA_testPower.py
+++ /dev/null
@@ -1,85 +0,0 @@
-# -*- coding: utf-8 -*-
-import uhal
-from I2CuHal import I2CCore
-import time
-#import miniTLU
-from si5345 import si5345
-from AD5665R import AD5665R
-from PCA9539PW import PCA9539PW
-from E24AA025E48T import E24AA025E48T
-
-manager = uhal.ConnectionManager("file://./TLUconnection.xml")
-hw = manager.getDevice("tlu")
-
-# hw.getNode("A").write(255)
-reg = hw.getNode("version").read()
-hw.dispatch()
-print "CHECK REG= ", hex(reg)
-
-
-# #First I2C core
-print ("Instantiating master I2C core:")
-master_I2C= I2CCore(hw, 10, 5, "i2c_master", None)
-master_I2C.state()
-
-
-
-
-#
-# #######################################
-enableCore= False #Only need to run this once, after power-up
-if (enableCore):
- mystop=True
- print " Write RegDir to set I/O[7] to output:"
- myslave= 0x21
- mycmd= [0x01, 0x7F]
- nwords= 1
- master_I2C.write(myslave, mycmd, mystop)
-
- mystop=False
- mycmd= [0x01]
- master_I2C.write(myslave, mycmd, mystop)
- res= master_I2C.read( myslave, nwords)
- print "\tPost RegDir: ", res
-
-
-#DAC CONFIGURATION BEGIN
-if (False):
- zeDAC1=AD5665R(master_I2C, 0x1C)
- zeDAC1.setIntRef(intRef= False, verbose= True)
- zeDAC1.writeDAC(0x0, 7, verbose= True)#7626
-
-if (True):
- # #I2C EXPANDER CONFIGURATION BEGIN
- IC6=PCA9539PW(master_I2C, 0x76)
- #BANK 0
- IC6.setInvertReg(0, 0x00)# 0= normal
- IC6.setIOReg(0, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
- IC6.setOutputs(0, 0x00)
- res= IC6.getInputs(0)
- print "IC6 read back bank 0: 0x%X" % res[0]
- #
- #BANK 1
- IC6.setInvertReg(1, 0x00)# 0= normal
- IC6.setIOReg(1, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
- IC6.setOutputs(1, 0x00)
- res= IC6.getInputs(1)
- print "IC6 read back bank 1: 0x%X" % res[0]
-
- # # #
- IC7=PCA9539PW(master_I2C, 0x77)
- #BANK 0
- IC7.setInvertReg(0, 0x00)# 0= normal
- IC7.setIOReg(0, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
- IC7.setOutputs(0, 0x00)
- res= IC7.getInputs(0)
- print "IC7 read back bank 0: 0x%X" % res[0]
- #
- #BANK 1
- IC7.setInvertReg(1, 0x00)# 0= normal
- IC7.setIOReg(1, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
- IC7.setOutputs(1, 0x00)
- res= IC7.getInputs(1)
- print "IC7 read back bank 1: 0x%X" % res[0]
- # #I2C EXPANDER CONFIGURATION END
-
diff --git a/TLU_v1e/scripts/AIDA_testScript.py b/TLU_v1e/scripts/AIDA_testScript.py
deleted file mode 100644
index de7316b..0000000
--- a/TLU_v1e/scripts/AIDA_testScript.py
+++ /dev/null
@@ -1,193 +0,0 @@
-# -*- coding: utf-8 -*-
-import uhal
-from I2CuHal import I2CCore
-import time
-#import miniTLU
-from si5345 import si5345
-from AD5665R import AD5665R
-from PCA9539PW import PCA9539PW
-from E24AA025E48T import E24AA025E48T
-from I2CDISP import LCD_ada #Library for display
-
-manager = uhal.ConnectionManager("file://./TLUconnection.xml")
-hw = manager.getDevice("tlu")
-
-# hw.getNode("A").write(255)
-reg = hw.getNode("version").read()
-hw.dispatch()
-print "CHECK REG= ", hex(reg)
-
-
-# #First I2C core
-print ("Instantiating master I2C core:")
-master_I2C= I2CCore(hw, 10, 5, "i2c_master", None)
-master_I2C.state()
-
-
-
-
-#
-# #######################################
-enableCore= True #Only need to run this once, after power-up
-if (enableCore):
- mystop=True
- print " Write RegDir to set I/O[7] to output:"
- myslave= 0x21
- mycmd= [0x01, 0x7F]
- nwords= 1
- master_I2C.write(myslave, mycmd, mystop)
-
-
- mystop=False
- mycmd= [0x01]
- master_I2C.write(myslave, mycmd, mystop)
- res= master_I2C.read( myslave, nwords)
- print "\tPost RegDir: ", res
-# #######################################
-#
-# time.sleep(0.1)
-# #Read the EPROM
-# mystop=False
-# nwords=6
-# myslave= 0x53 #DUNE EPROM 0x53 (Possibly)
-# myaddr= [0xfa]#0xfa
-# master_I2C.write( myslave, myaddr, mystop)
-# #res= master_I2C.read( 0x50, 6)
-# res= master_I2C.read( myslave, nwords)
-# print " PCB EPROM: "
-# result="\t "
-# for iaddr in res:
-# result+="%02x "%(iaddr)
-# print result
-# #######################################
-
-
-#Second I2C core
-#print ("Instantiating SFP I2C core:")
-#clock_I2C= I2CCore(hw, 10, 5, "i2c_sfp", None)
-#clock_I2C.state()
-
-# #Third I2C core
-# print ("Instantiating clock I2C core:")
-# clock_I2C= I2CCore(hw, 10, 5, "i2c_clk", None)
-# clock_I2C.state()
-
-
-# #time.sleep(0.01)
-# #Read the EPROM
-# mystop=False
-# nwords=2
-# myslave= 0x68 #DUNE CLOCK CHIP 0x68
-# myaddr= [0x02 ]#0xfa
-# clock_I2C.write( myslave, myaddr, mystop)
-# #time.sleep(0.1)
-# res= clock_I2C.read( myslave, nwords)
-# print " CLOCK EPROM: "
-# result="\t "
-# for iaddr in res:
-# result+="%02x "%(iaddr)
-# print result
-
-#
-
-#CLOCK CONFIGURATION BEGIN
-zeClock=si5345(master_I2C, 0x68)
-res= zeClock.getDeviceVersion()
-zeClock.checkDesignID()
-#zeClock.setPage(0, True)
-#zeClock.getPage(True)
-doClock= False
-if (doClock):
- clkRegList= zeClock.parse_clk("./../../bitFiles/TLU_CLK_Config_v1e.txt")
- zeClock.writeConfiguration(clkRegList)######
- zeClock.writeRegister(0x0536, [0x0A]) #Configures manual switch of inputs
- zeClock.writeRegister(0x0949, [0x0F]) #Enable all inputs
- zeClock.writeRegister(0x052A, [0x05]) #Configures source of input
-iopower= zeClock.readRegister(0x0949, 1)
-print " Clock IO power: 0x%X" % iopower[0]
-lol= zeClock.readRegister(0x000E, 1)
-print " Clock LOL (0x000E): 0x%X" % lol[0]
-los= zeClock.readRegister(0x000D, 1)
-print " Clock LOS (0x000D): 0x%X" % los[0]
-#CLOCK CONFIGURATION END
-
-#DAC CONFIGURATION BEGIN
-zeDAC1=AD5665R(master_I2C, 0x13)
-zeDAC1.setIntRef(intRef= False, verbose= True)
-zeDAC1.writeDAC(0x0, 7, verbose= True)#7626
-
-zeDAC2=AD5665R(master_I2C, 0x1F)
-zeDAC2.setIntRef(intRef= False, verbose= True)
-zeDAC2.writeDAC(0x2fff, 3, verbose= True)
-#DAC CONFIGURATION END
-
-#EEPROM BEGIN
-zeEEPROM= E24AA025E48T(master_I2C, 0x50)
-res=zeEEPROM.readEEPROM(0xfa, 6)
-result=" EEPROM ID:\n\t"
-for iaddr in res:
- result+="%02x "%(iaddr)
-print result
-#EEPROM END
-
-# #I2C EXPANDER CONFIGURATION BEGIN
-IC6=PCA9539PW(master_I2C, 0x74)
-#BANK 0
-IC6.setInvertReg(0, 0x00)# 0= normal
-IC6.setIOReg(0, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
-IC6.setOutputs(0, 0x77)#77
-res= IC6.getInputs(0)
-print "\tIC6 read back bank 0: 0x%X" % res[0]
-#
-#BANK 1
-IC6.setInvertReg(1, 0x00)# 0= normal
-IC6.setIOReg(1, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
-IC6.setOutputs(1, 0x77)#77
-res= IC6.getInputs(1)
-print "\tIC6 read back bank 1: 0x%X" % res[0]
-
-# # #
-IC7=PCA9539PW(master_I2C, 0x75)
-#BANK 0
-IC7.setInvertReg(0, 0x00)# 0= normal
-IC7.setIOReg(0, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
-IC7.setOutputs(0, 0xF0)
-res= IC7.getInputs(0)
-print "\tIC7 read back bank 0: 0x%X" % res[0]
-#
-#BANK 1
-IC7.setInvertReg(1, 0x00)# 0= normal
-IC7.setIOReg(1, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
-IC7.setOutputs(1, 0xAF)
-res= IC7.getInputs(1)
-print "\tIC7 read back bank 1: 0x%X" % res[0]
-# #I2C EXPANDER CONFIGURATION END
-
-
-#Instantiate Display
-doDisplaytest= False
-if doDisplaytest:
- DISP=LCD_ada(master_I2C, 0x20) #3A
- #self.DISP.clear()
- DISP.test()
-
-# #Reset counters
-#cmd = int("0x0", 16) #write 0x2 to reset
-#hw.getNode("triggerInputs.SerdesRstW").write(cmd)
-#restatus= hw.getNode("triggerInputs.SerdesRstR").read()
-#hw.dispatch()
-#print "Trigger Reset: 0x%X" % restatus
-## #Read trigger inputs
-#myreg= [-1, -1, -1, -1, -1, -1]
-#for inputN in range(0, 6):
-# regString= "triggerInputs.ThrCount%dR" % inputN
-# myreg[inputN]= hw.getNode(regString).read()
-# hw.dispatch()
-# print regString, myreg[inputN]
-
-## Read ev formatter
-#cmd = int("0x0", 16) #
-##hw.getNode("Event_Formatter.Enable_Record_Data").write(cmd)
-#efstatus= hw.getNode("Event_Formatter.CurrentTimestampLR").read()
-#hw.dispatch()
-#print "Event Formatter Record: 0x%X" % efstatus
diff --git a/TLU_v1e/scripts/TLU_v1e.py b/TLU_v1e/scripts/TLU_v1e.py
deleted file mode 100644
index 82e2e8a..0000000
--- a/TLU_v1e/scripts/TLU_v1e.py
+++ /dev/null
@@ -1,993 +0,0 @@
-# -*- coding: utf-8 -*-
-import uhal;
-# import pprint;
-# import ConfigParser
-#from FmcTluI2c import *
-# from ROOT import TFile, TTree, gROOT, AddressOf
-# from ROOT import *
-import time
-
-from packages.I2CuHal import I2CCore
-from packages.si5345 import si5345 # Library for clock chip
-from packages.AD5665R import AD5665R # Library for DAC
-from packages.PCA9539PW import PCA9539PW # Library for serial line expander
-from packages.I2CDISP import LCD_ada # Library for Adafruit display
-from packages.I2CDISP import LCD09052 # Library for SparkFun display
-from packages.TLU_powermodule import PWRLED
-from packages.ATSHA204A import ATSHA204A
-
-
-class TLU:
- """docstring for TLU"""
- def __init__(self, dev_name, man_file, parsed_cfg):
-
- uhal.setLogLevelTo(uhal.LogLevel.NOTICE) ## Get rid of initial flood of IPBUS messages
- self.isRunning= False
-
- section_name= "Producer.fmctlu"
- self.dev_name = dev_name
-
- #man_file= parsed_cfg.get(section_name, "ConnectionFile")
- self.manager= uhal.ConnectionManager(man_file)
- self.hw = self.manager.getDevice(self.dev_name)
-
- # #Get Verbose setting
- self.verbose= parsed_cfg.getint(section_name, "verbose")
-
- #self.nDUTs= 4 #Number of DUT connectors
- self.nDUTs= parsed_cfg.getint(section_name, "nDUTs")
-
- #self.nChannels= 6 #Number of trigger inputs
- self.nChannels= parsed_cfg.getint(section_name, "nTrgIn")
-
- #self.VrefInt= 2.5 #Internal DAC voltage reference
- self.VrefInt= parsed_cfg.getfloat(section_name, "VRefInt")
-
- #self.VrefExt= 1.3 #External DAC voltage reference
- self.VrefExt= parsed_cfg.getfloat(section_name, "VRefExt")
-
- #self.intRefOn= False #Internal reference is OFF by default
- self.intRefOn= int(parsed_cfg.get(section_name, "intRefOn"))
-
- self.fwVersion = self.hw.getNode("version").read()
- self.hw.dispatch()
- print("TLU V1E FIRMWARE VERSION= " , hex(self.fwVersion))
-
- # Instantiate a I2C core to configure components
- self.TLU_I2C= I2CCore(self.hw, 10, 5, "i2c_master", None)
- #self.TLU_I2C.state()
-
- enableCore= True #Only need to run this once, after power-up
- self.enableCore()
- ####### EEPROM AX3 testing
- doAtmel= False
- if doAtmel:
- self.ax3eeprom= ATSHA204A(self.TLU_I2C, 0x64)
- print("shiftR\tdatBit\tcrcBit\tcrcReg \n", self.ax3eeprom._CalculateCrc([255, 12, 54, 28, 134, 89], 3))
- self.ax3eeprom._wake(True, True)
- print(self.ax3eeprom._GetCommandPacketSize(8))
- #self.eepromAX3read()
- ####### EEPROM AX3 testing end
-
- # Instantiate clock chip and configure it (if necessary)
- #self.zeClock=si5345(self.TLU_I2C, 0x68)
- clk_addr= int(parsed_cfg.get(section_name, "I2C_CLK_Addr"), 16)
- self.zeClock=si5345(self.TLU_I2C, clk_addr)
- res= self.zeClock.getDeviceVersion()
- if (int(parsed_cfg.get(section_name, "CONFCLOCK"), 16)):
- #clkRegList= self.zeClock.parse_clk("./../../bitFiles/TLU_CLK_Config_v1e.txt")
- clkRegList= self.zeClock.parse_clk(parsed_cfg.get(section_name, "CLOCK_CFG_FILE"))
- self.zeClock.writeConfiguration(clkRegList, self.verbose)######
-
- self.zeClock.checkDesignID()
-
- # Instantiate DACs and configure them to use reference based on TLU setting
- #self.zeDAC1=AD5665R(self.TLU_I2C, 0x13)
- #self.zeDAC2=AD5665R(self.TLU_I2C, 0x1F)
- dac_addr1= int(parsed_cfg.get(section_name, "I2C_DAC1_Addr"), 16)
- self.zeDAC1=AD5665R(self.TLU_I2C, dac_addr1)
- dac_addr2= int(parsed_cfg.get(section_name, "I2C_DAC2_Addr"), 16)
- self.zeDAC2=AD5665R(self.TLU_I2C, dac_addr2)
- self.zeDAC1.setIntRef(self.intRefOn, self.verbose)
- self.zeDAC2.setIntRef(self.intRefOn, self.verbose)
-
- # Instantiate the serial line expanders and configure them to default values
- #self.IC6=PCA9539PW(self.TLU_I2C, 0x74)
- exp1_addr= int(parsed_cfg.get(section_name, "I2C_EXP1_Addr"), 16)
- self.IC6=PCA9539PW(self.TLU_I2C, exp1_addr)
- self.IC6.setInvertReg(0, 0x00)# 0= normal, 1= inverted
- self.IC6.setIOReg(0, 0x00)# 0= output, 1= input
- self.IC6.setOutputs(0, 0xFF)# If output, set to XX
-
- self.IC6.setInvertReg(1, 0x00)# 0= normal, 1= inverted
- self.IC6.setIOReg(1, 0x00)# 0= output, 1= input
- self.IC6.setOutputs(1, 0xFF)# If output, set to XX
-
- #self.IC7=PCA9539PW(self.TLU_I2C, 0x75)
- exp2_addr= int(parsed_cfg.get(section_name, "I2C_EXP2_Addr"), 16)
- self.IC7=PCA9539PW(self.TLU_I2C, exp2_addr)
- self.IC7.setInvertReg(0, 0x00)# 0= normal, 1= inverted
- self.IC7.setIOReg(0, 0x00)# 0= output, 1= input
- self.IC7.setOutputs(0, 0x00)# If output, set to XX
-
- self.IC7.setInvertReg(1, 0x00)# 0= normal, 1= inverted
- self.IC7.setIOReg(1, 0x00)# 0= output, 1= input
- self.IC7.setOutputs(1, 0xB0)# If output, set to XX
-
- #Attempt to instantiate Display
- self.displayPresent= True
- i2ccmd= [7, 150]
- mystop= True
- print(" Attempting to detect TLU display")
- # res= self.TLU_I2C.write( 0x3A, i2ccmd, mystop)
- res= self.TLU_I2C.write( 0x20, i2ccmd, mystop)
- if (res== -1): # if this fails, likely no display installed
- self.displayPresent= False
- print("\tNo TLU display detected")
- if self.displayPresent:
- self.DISP = LCD_ada(self.TLU_I2C, 0x20)
- self.DISP.test()
- # self.DISP=LCD09052(self.TLU_I2C, 0x3A) #0x3A for Sparkfun, 0x20 for Adafruit
- # self.DISP.test2("192.168.200.30", "AIDA TLU")
- #self.DISP=CFA632(self.TLU_I2C, 0x2A) #
-
- #Instantiate Power/Led Module
- dac_addr_module= int(parsed_cfg.get(section_name, "I2C_DACModule_Addr"), 16)
- exp1_addr= int(parsed_cfg.get(section_name, "I2C_EXP1Module_Addr"), 16)
- exp2_addr= int(parsed_cfg.get(section_name, "I2C_EXP2Module_Addr"), 16)
- pmtCtrVMax= parsed_cfg.getfloat(section_name, "PMT_vCtrlMax")
-
- self.pwdled= PWRLED(self.TLU_I2C, dac_addr_module, pmtCtrVMax, exp1_addr, exp2_addr)
-
- self.pwdled.allGreen()
- time.sleep(0.1)
- self.pwdled.allBlue()
- time.sleep(0.1)
- self.pwdled.allBlack()
- time.sleep(0.1)
- self.pwdled.kitt()
- time.sleep(0.1)
- self.pwdled.allWhite()
- #self.pwdled.test()
-
-
-
-##################################################################################################################################
-##################################################################################################################################
- def DUTOutputs_old(self, dutN, enable=False, verbose=False):
- ## Set the status of the transceivers for a specific HDMI connector. When enable= False the transceivers are disabled and the
- ## connector cannot send signals from FPGA to the outside world. When enable= True then signals from the FPGA will be sent out to the HDMI.
- ## NOTE: the other direction is always enabled, i.e. signals from the DUTs are always sent to the FPGA.
- ## NOTE: CLK direction must be defined separately using DUTClkSrc
- ## NOTE: This version changes all the pins together. Use DUTOutputs to control individual pins.
-
- if (dutN < 0) | (dutN> (self.nDUTs-1)):
- print("\tERROR: DUTOutputs. The DUT number must be comprised between 0 and ", self.nDUTs-1)
- return -1
- bank= dutN//2 # DUT0 and DUT1 are on bank 0. DUT2 and DUT3 on bank 1
- nibble= dutN%2 # DUT0 and DUT2 are on nibble 0. DUT1 and DUT3 are on nibble 1
- print(" Setting DUT:", dutN, "to", enable)
- if (verbose > 1):
- print("\tBank", bank, "Nibble", nibble)
- res= self.IC6.getOutputs(bank)
- oldStatus= res[0]
- mask= 0xF << 4*nibble
- newStatus= oldStatus & (~mask)
- if (not enable): # we want to write 0 to activate the outputs so check opposite of "enable"
- newStatus |= mask
- self.IC6.setOutputs(bank, newStatus)
-
- if verbose:
- print("\tOldStatus= ", "{0:#0{1}x}".format(oldStatus,4), "Mask=" , hex(mask), "newStatus=", "{0:#0{1}x}".format(newStatus,4))
- return newStatus
-
- def DUTOutputs(self, dutN, enable=0x7, verbose=False):
- ## Set the status of the transceivers for a specific HDMI connector. When enable= False the transceivers are disabled and the
- ## connector cannot send signals from FPGA to the outside world. When enable= True then signals from the FPGA will be sent out to the HDMI.
- ## NOTE: the other direction is always enabled, i.e. signals from the DUTs are always sent to the FPGA.
- ## NOTE: CLK direction must be defined separately using DUTClkSrc
-
- if (dutN < 0) | (dutN> (self.nDUTs-1)):
- print("\tERROR: DUTOutputs. The DUT number must be comprised between 0 and ", self.nDUTs-1)
- return -1
- bank= dutN//2 # DUT0 and DUT1 are on bank 0. DUT2 and DUT3 on bank 1
- nibble= dutN%2 # DUT0 and DUT2 are on nibble 0. DUT1 and DUT3 are on nibble 1
- print(" Setting DUT:", dutN, "pins status to", hex(enable))
- if (verbose > 1):
- print("\tBank", bank, "Nibble", nibble)
- res= self.IC6.getOutputs(bank)
- oldStatus= res[0]
- mask= 0xF << 4*nibble
- newnibble= (enable & 0xF) << 4*nibble # bits we want to change are marked with 1
- newStatus= (oldStatus & (~mask)) | (newnibble & mask)
-
- self.IC6.setOutputs(bank, newStatus)
-
- if (verbose > 0):
- self.getDUTOutpus(dutN, verbose)
- if (verbose > 1):
- print("\tOldStatus= ", "{0:#0{1}x}".format(oldStatus,4), "Mask=" , hex(mask), "newStatus=", "{0:#0{1}x}".format(newStatus,4))
-
- return newStatus
-
- def DUTClkSrc(self, dutN, clkSrc=0, verbose= False):
- ## Allows to choose the source of the clock signal sent to the DUTs over HDMI
- ## clkSrc= 0: clock disabled
- ## clkSrc= 1: clock from Si5345
- ## clkSrc=2: clock from FPGA
- if (dutN < 0) | (dutN> (self.nDUTs-1)):
- print("\tERROR: DUTClkSrc. The DUT number must be comprised between 0 and ", self.nDUTs-1)
- return -1
- if (clkSrc < 0) | (clkSrc> 2):
- print("\tERROR: DUTClkSrc. clkSrc can only be 0 (disabled), 1 (Si5345) or 2 (FPGA)")
- return -1
- bank=0
- maskLow= 1 << (1* dutN) #CLK FROM FPGA
- maskHigh= 1<< (1* dutN +4) #CLK FROM Si5345
- mask= maskLow | maskHigh
- res= self.IC7.getOutputs(bank)
- oldStatus= res[0]
- newStatus= oldStatus & ~mask #set both bits to zero
- outStat= ""
- if clkSrc==0:
- newStatus = newStatus
- outStat= "disabled"
- elif clkSrc==1:
- newStatus = newStatus | maskLow
- outStat= "Si5435"
- elif clkSrc==2:
- newStatus= newStatus | maskHigh
- outStat= "FPGA"
- print(" Setting DUT:", dutN, "clock source to", outStat)
- if (verbose > 1):
- print("\tOldStatus= ", "{0:#0{1}x}".format(oldStatus,4), "Mask=" , hex(mask), "newStatus=", "{0:#0{1}x}".format(newStatus,4))
- self.IC7.setOutputs(bank, newStatus)
- return newStatus
-
- def eepromAX3read(self):
- mystop=True
- print(" Reading AX3 eeprom (not working 100% yet):")
- myslave= 0x64
- self.TLU_I2C.write(myslave, [0x02, 0x00])
- nwords= 5
- res= self.TLU_I2C.read( myslave, nwords)
- print("\tAX3 awake: ", res)
- mystop=True
- nwords= 7
- #mycmd= [0x03, 0x07, 0x02, 0x00, 0x00, 0x00, 0x1e, 0x2d]#conf 0?
- mycmd= [0x03, 0x07, 0x02, 0x00, 0x01, 0x00, 0x17, 0xad]#conf 1 <<< seems to reply with correct error code (0)
- #mycmd= [0x03, 0x07, 0x02, 0x02, 0x00, 0x00, 0x1d, 0xa8]#data 0?
- self.TLU_I2C.write(myslave, mycmd, mystop)
- res= self.TLU_I2C.read( myslave, nwords)
- print("\tAX3 EEPROM: ", res)
-
- def enableClkLEMO(self, enable= False, verbose= False):
- ## Enable or disable the output clock to the differential LEMO output
- bank=1
- mask= 0x10
- res= self.IC7.getOutputs(bank)
- oldStatus= res[0]
- newStatus= oldStatus & ~mask
- outStat= "enabled"
- if (not enable): #A 0 activates the output. A 1 disables it.
- newStatus= newStatus | mask
- outStat= "disabled"
- print(" Clk LEMO", outStat)
- if verbose:
- print("\tOldStatus= ", "{0:#0{1}x}".format(oldStatus,4), "Mask=" , hex(mask), "newStatus=", "{0:#0{1}x}".format(newStatus,4))
- self.IC7.setOutputs(bank, newStatus)
- return newStatus
-
- def enableCore(self):
- ## At power up the Enclustra I2C lines are disabled (tristate buffer is off).
- ## This function enables the lines. It is only required once.
- mystop=True
- print(" Enabling I2C bus (expect 127):")
- myslave= 0x21
- mycmd= [0x01, 0x7F]
- nwords= 1
- self.TLU_I2C.write(myslave, mycmd, mystop)
-
- mystop=False
- mycmd= [0x01]
- self.TLU_I2C.write(myslave, mycmd, mystop)
- res= self.TLU_I2C.read( myslave, nwords)
- print("\tPost RegDir: ", res)
-
- def getDUTOutpus(self, dutN, verbose=0):
- if (dutN < 0) | (dutN> (self.nDUTs-1)):
- print("\tERROR: DUTOutputs. The DUT number must be comprised between 0 and ", self.nDUTs-1)
- return -1
- bank= dutN//2 # DUT0 and DUT1 are on bank 0. DUT2 and DUT3 on bank 1
- nibble= dutN%2 # DUT0 and DUT2 are on nibble 0. DUT1 and DUT3 are on nibble 1
- res= self.IC6.getOutputs(bank)
- dut_status= res[0]
- dut_lines= ["CONT", "SPARE", "TRIG", "BUSY"]
- dut_status= 0x0F & (dut_status >> (4*nibble))
-
- if verbose > 0:
- for idx, iLine in enumerate(dut_lines):
- this_bit= 0x1 & (dut_status >> idx)
- if this_bit:
- this_status= "ENABLED"
- else:
- this_status= "DISABLED"
- print("\t", iLine, "output is", this_status)
-
- if verbose > 1:
- print("\tDUT CURRENT:", hex(dut_status), "Nibble:", nibble, "Bank:", bank)
-
- return dut_status
-
- def getAllChannelsCounts(self):
- chCounts=[]
- for ch in range (0,self.nChannels):
- chCounts.append(int(self.getChCount(ch)))
- return chCounts
-
- def getChStatus(self):
- inputStatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
- self.hw.dispatch()
- print("\tTRIGGER COUNTERS status= " , hex(inputStatus))
- return inputStatus
-
- def getChCount(self, channel):
- regString= "triggerInputs.ThrCount"+ str(channel)+"R"
- count = self.hw.getNode(regString).read()
- self.hw.dispatch()
- print("\tCh", channel, "Count:" , count)
- return count
-
- def getClockStatus(self):
- clockStatus = self.hw.getNode("logic_clocks.LogicClocksCSR").read()
- self.hw.dispatch()
- print(" CLOCK STATUS [expected 1]")
- print("\t", hex(clockStatus))
- if ( clockStatus == 0 ):
- "ERROR: Clocks in TLU FPGA are not locked."
- return clockStatus
-
- def getDUTmask(self):
- DUTMaskR = self.hw.getNode("DUTInterfaces.DUTMaskR").read()
- self.hw.dispatch()
- print("\tDUTMask read back as:" , hex(DUTMaskR))
- return DUTMaskR
-
- def getExternalVeto(self):
- extVeto= self.hw.getNode("triggerLogic.ExternalTriggerVetoR").read()
- self.hw.dispatch()
- print("\tEXTERNAL Veto read back as:", hex(extVeto))
- return extVeto
-
- def getFifoData(self, nWords):
- #fifoData= self.hw.getNode("eventBuffer.EventFifoData").read()
- fifoData= self.hw.getNode("eventBuffer.EventFifoData").readBlock(nWords)
- self.hw.dispatch()
- #print "\tFIFO Data:", hex(fifoData)
- return fifoData
-
- def getFifoLevel(self, verbose= 0):
- FifoFill= self.hw.getNode("eventBuffer.EventFifoFillLevel").read()
- self.hw.dispatch()
- if (verbose > 0):
- print("\tFIFO level read back as:", hex(FifoFill))
- return FifoFill
-
- def getFifoCSR(self):
- FifoCSR= self.hw.getNode("eventBuffer.EventFifoCSR").read()
- self.hw.dispatch()
- print("\tFIFO CSR read back as:", hex(FifoCSR))
- return FifoCSR
-
- def getFifoFlags(self):
- # Useless?
- FifoFLAG= self.hw.getNode("eventBuffer.EventFifoFillLevelFlags").read()
- self.hw.dispatch()
- print("\tFIFO FLAGS read back as:", hex(FifoFLAG))
- return FifoFLAG
-
- def getInternalTrg(self):
- trigIntervalR = self.hw.getNode("triggerLogic.InternalTriggerIntervalR").read()
- self.hw.dispatch()
- print("\tInternal interval read back as:", trigIntervalR)
- return trigIntervalR
-
- def getMode(self):
- DUTInterfaceModeR = self.hw.getNode("DUTInterfaces.DUTInterfaceModeR").read()
- self.hw.dispatch()
- print("\tDUT mode read back as:" , hex(DUTInterfaceModeR))
- return DUTInterfaceModeR
-
- def getModeModifier(self):
- DUTInterfaceModeModifierR = self.hw.getNode("DUTInterfaces.DUTInterfaceModeModifierR").read()
- self.hw.dispatch()
- print("\tDUT mode modifier read back as:" , hex(DUTInterfaceModeModifierR))
- return DUTInterfaceModeModifierR
-
- def getSN(self):
- epromcontent=self.readEEPROM(0xfa, 6)
- print(" FMC-TLU serial number (EEPROM):")
- result="\t"
- for iaddr in epromcontent:
- result+="%02x "%(iaddr)
- print(result)
- return epromcontent
-
- def getPostVetoTrg(self):
- triggerN = self.hw.getNode("triggerLogic.PostVetoTriggersR").read()
- self.hw.dispatch()
- print("\tPOST VETO TRIGGER NUMBER:", (triggerN))
- return triggerN
-
- def getPulseDelay(self):
- pulseDelayR = self.hw.getNode("triggerLogic.PulseDelayR").read()
- self.hw.dispatch()
- print("\tPulse delay read back as:", hex(pulseDelayR))
- return pulseDelayR
-
- def getPulseStretch(self):
- pulseStretchR = self.hw.getNode("triggerLogic.PulseStretchR").read()
- self.hw.dispatch()
- print("\tPulse stretch read back as:", hex(pulseStretchR))
- return pulseStretchR
-
- def getRecordDataStatus(self):
- RecordStatus= self.hw.getNode("Event_Formatter.Enable_Record_Data").read()
- self.hw.dispatch()
- print("\tData recording:", RecordStatus)
- return RecordStatus
-
- def getTriggerVetoStatus(self):
- trgVetoStatus= self.hw.getNode("triggerLogic.TriggerVetoR").read()
- self.hw.dispatch()
- print("\tTrigger veto status read back as:", trgVetoStatus)
- return trgVetoStatus
-
- def getTrgPattern(self):
- triggerPattern_low = self.hw.getNode("triggerLogic.TriggerPattern_lowR").read()
- triggerPattern_high = self.hw.getNode("triggerLogic.TriggerPattern_highR").read()
- self.hw.dispatch()
- print("\tTrigger pattern read back as: 0x%08X 0x%08X" %(triggerPattern_high, triggerPattern_low))
- return triggerPattern_low, triggerPattern_high
-
- def getVetoDUT(self):
- IgnoreDUTBusyR = self.hw.getNode("DUTInterfaces.IgnoreDUTBusyR").read()
- self.hw.dispatch()
- print("\tIgnoreDUTBusy read back as:" , hex(IgnoreDUTBusyR))
- return IgnoreDUTBusyR
-
- def getVetoShutters(self):
- IgnoreShutterVeto = self.hw.getNode("DUTInterfaces.IgnoreShutterVetoR").read()
- self.hw.dispatch()
- print("\tIgnoreShutterVeto read back as:" , IgnoreShutterVeto)
- return IgnoreShutterVeto
-
-# def pulseT0(self):
-# cmd = int("0x1",16)
-# self.hw.getNode("Shutter.PulseT0").write(cmd)
-# self.hw.dispatch()
-# print "\tPulsing T0"
-
-
- def setRunActive(self):
- cmd = int("0x1",16)
- self.hw.getNode("Shutter.RunActiveRW").write(cmd)
- self.hw.dispatch()
- print("\tSet run active (pulses T0)")
-
- def setRunInactive(self):
- cmd = int("0x0",16)
- self.hw.getNode("Shutter.RunActiveRW").write(cmd)
- self.hw.dispatch()
- print("\tSet run inactive")
-
- def readEEPROM(self, startadd, bytes):
- mystop= 1
- time.sleep(0.1)
- myaddr= [startadd]#0xfa
- self.TLU_I2C.write( 0x50, [startadd], mystop)
- res= self.TLU_I2C.read( 0x50, bytes)
- return res
-
- def resetClock(self):
- # Set the RST pin from the PLL to 1
- print(" Clocks reset")
- cmd = int("0x1",16)
- self.hw.getNode("logic_clocks.LogicRst").write(cmd)
- self.hw.dispatch()
-
- def resetClocks(self):
- #Reset clock PLL
- self.resetClock()
- #Get clock status after reset
- self.getClockStatus()
- #Restore clock PLL
- self.restoreClock()
- #Get clock status after restore
- self.getClockStatus()
- #Get serdes status
- self.getChStatus()
-
- def resetCounters(self):
- cmd = int("0x2", 16) #write 0x2 to reset
- self.hw.getNode("triggerInputs.SerdesRstW").write(cmd)
- restatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
- self.hw.dispatch()
- cmd = int("0x0", 16) #write 0x2 to reset
- self.hw.getNode("triggerInputs.SerdesRstW").write(cmd)
- restatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
- self.hw.dispatch()
- #print "Trigger Reset: 0x%X" % restatus
- print("\tTrigger counters reset")
-
- def resetSerdes(self):
- cmd = int("0x3",16)
- self.setChStatus(cmd)
- inputStatus= self.getChStatus()
- print("\t Input status during reset = " , hex(inputStatus))
-
- cmd = int("0x0",16)
- self.setChStatus(cmd)
- inputStatus= self.getChStatus()
- print("\t Input status after reset = " , hex(inputStatus))
-
- cmd = int("0x4",16)
- self.setChStatus(cmd)
- inputStatus= self.getChStatus()
- print("\t Input status during calibration = " , hex(inputStatus))
-
- cmd = int("0x0",16)
- self.setChStatus(cmd)
- inputStatus= self.getChStatus()
- print("\t Input status after calibration = " , hex(inputStatus))
-
- def restoreClock(self):
- # Set the RST pin from the PLL to 0
- print(" Clocks restore")
- cmd = int("0x0",16)
- self.hw.getNode("logic_clocks.LogicRst").write(cmd)
- self.hw.dispatch()
-
- def setChStatus(self, cmd):
- self.hw.getNode("triggerInputs.SerdesRstW").write(cmd)
- inputStatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
- self.hw.dispatch()
- print(" INPUT STATUS SET TO= " , hex(inputStatus))
-
- def setClockStatus(self, cmd):
- # Only use this for testing. The clock source is actually selected in the Si5345.
- self.hw.getNode("logic_clocks.LogicClocksCSR").write(cmd)
- self.hw.dispatch()
-
- def setDUTmask(self, DUTMask):
- print(" DUT MASK ENABLING: Mask= " , hex(DUTMask))
- self.hw.getNode("DUTInterfaces.DUTMaskW").write(DUTMask)
- self.hw.dispatch()
- self.getDUTmask()
-
- def setFifoCSR(self, cmd):
- self.hw.getNode("eventBuffer.EventFifoCSR").write(cmd)
- self.hw.dispatch()
- self.getFifoCSR()
-
- def setInternalTrg(self, triggerInterval):
- print(" TRIGGERS INTERNAL:")
- if triggerInterval == 0:
- internalTriggerFreq = 0
- print("\tdisabled")
- else:
- internalTriggerFreq = 160000000.0/triggerInterval
- print("\tRequired internal trigger frequency:", triggerInterval, "Hz")
- print("\tSetting internal interval to:", internalTriggerFreq)
- self.hw.getNode("triggerLogic.InternalTriggerIntervalW").write(int(internalTriggerFreq))
- self.hw.dispatch()
- self.getInternalTrg()
-
- def setMode(self, mode):
- print(" DUT MODE SET TO: ", hex(mode))
- self.hw.getNode("DUTInterfaces.DUTInterfaceModeW").write(mode)
- self.hw.dispatch()
- self.getMode()
-
- def setModeModifier(self, modifier):
- print(" DUT MODE MODIFIER:", hex(modifier))
- self.hw.getNode("DUTInterfaces.DUTInterfaceModeModifierW").write(modifier)
- self.hw.dispatch()
- self.getModeModifier()
-
- def setPulseDelay(self, inArray):
- print(" TRIGGER DELAY SET TO", inArray, "[Units= 160MHz clock, 5-bit values (one per input) packed in to 32-bit word]")
- pulseDelay= self.packBits(inArray)
- self.hw.getNode("triggerLogic.PulseDelayW").write(pulseDelay)
- self.hw.dispatch()
- self.getPulseDelay()
-
- def setPulseStretch(self, inArray):
- print(" INPUT COINCIDENCE WINDOW SET TO", inArray ,"[Units= 160MHz clock cycles, 5-bit values (one per input) packed in to 32-bit word]")
- pulseStretch= self.packBits(inArray)
- self.hw.getNode("triggerLogic.PulseStretchW").write(pulseStretch)
- self.hw.dispatch()
- self.getPulseStretch()
-
- def setRecordDataStatus(self, status=False):
- print(" Data recording set:")
- self.hw.getNode("Event_Formatter.Enable_Record_Data").write(status)
- self.hw.dispatch()
- self.getRecordDataStatus()
-
- def setTriggerVetoStatus(self, status=False):
- self.hw.getNode("triggerLogic.TriggerVetoW").write(status)
- self.hw.dispatch()
- self.getTriggerVetoStatus()
-
- def setTrgPattern(self, triggerPatternH, triggerPatternL):
- triggerPatternL &= 0xffffffff
- triggerPatternH &= 0xffffffff
- print(" TRIGGER PATTERN (for external triggers) SET TO 0x%08X 0x%08X. Two 32-bit words." %(triggerPatternH, triggerPatternL))
- self.hw.getNode("triggerLogic.TriggerPattern_lowW").write(triggerPatternL)
- self.hw.getNode("triggerLogic.TriggerPattern_highW").write(triggerPatternH)
- self.hw.dispatch()
- self.getTrgPattern()
-
- def setVetoDUT(self, ignoreDUTBusy):
- print(" VETO IGNORE BY DUT BUSY MASK SET TO" , hex(ignoreDUTBusy))
- self.hw.getNode("DUTInterfaces.IgnoreDUTBusyW").write(ignoreDUTBusy)
- self.hw.dispatch()
- self.getVetoDUT()
-
- def setVetoShutters(self, newState):
- if newState:
- print(" IgnoreShutterVetoW SET TO LISTEN FOR VETO FROM SHUTTER")
- cmd= int("0x0",16)
- else:
- print(" IgnoreShutterVetoW SET TO IGNORE VETO FROM SHUTTER")
- cmd= int("0x1",16)
- self.hw.getNode("DUTInterfaces.IgnoreShutterVetoW").write(cmd)
- self.hw.dispatch()
- self.getVetoShutters()
-
- def writeThreshold(self, DACtarget, Vtarget, channel, verbose=False):
- #Writes the threshold. The DAC voltage differs from the threshold voltage because
- #the range is shifted to be symmetrical around 0V.
-
- #Check if the DACs are using the internal reference
- if (self.intRefOn):
- Vref= self.VrefInt
- else:
- Vref= self.VrefExt
-
- #Calculate offset voltage (because of the following shifter)
- Vdac= ( Vtarget + Vref ) / 2
- print(" THRESHOLD setting:")
- if channel==7:
- print("\tCH: ALL")
- else:
- print("\tCH:", channel)
- print("\tTarget V:", Vtarget)
- dacValue = 0xFFFF * (Vdac / Vref)
- DACtarget.writeDAC(int(dacValue), channel, verbose)
-
- def packBits(self, raw_values):
- packed_bits= 0
- if (len(raw_values) != self.nChannels):
- print("Error (packBits): wrong number of elements in array")
- else:
- for idx, iCh in enumerate(raw_values):
- tmpint= iCh << idx*5
- packed_bits= packed_bits | tmpint
- print("\tPacked =", hex(packed_bits))
- return packed_bits
-
- def parseFifoData(self, fifoData, nEvents, mystruct, root_tree, verbose):
- #for index in range(0, len(fifoData)-1, 6):
- outList= []
- for index in range(0, (nEvents)*6, 6):
- word0= (fifoData[index] << 32) + fifoData[index + 1]
- word1= (fifoData[index + 2] << 32) + fifoData[index + 3]
- word2= (fifoData[index + 4] << 32) + fifoData[index + 5]
- evType= (fifoData[index] & 0xF0000000) >> 28
- inTrig= (fifoData[index] & 0x0FFF0000) >> 16
- tStamp= ((fifoData[index] & 0x0000FFFF) << 32) + fifoData[index + 1]
- fineTs= fifoData[index + 2]
- evNum= fifoData[index + 3]
- fineTsList=[-1]*12
- fineTsList[3]= (fineTs & 0x000000FF)
- fineTsList[2]= (fineTs & 0x0000FF00) >> 8
- fineTsList[1]= (fineTs & 0x00FF0000) >> 16
- fineTsList[0]= (fineTs & 0xFF000000) >> 24
- fineTsList[7]= (fifoData[index + 4] & 0x000000FF)
- fineTsList[6]= (fifoData[index + 4] & 0x0000FF00) >> 8
- fineTsList[5]= (fifoData[index + 4] & 0x00FF0000) >> 16
- fineTsList[4]= (fifoData[index + 4] & 0xFF000000) >> 24
- fineTsList[11]= (fifoData[index + 5] & 0x000000FF)
- fineTsList[10]= (fifoData[index + 5] & 0x0000FF00) >> 8
- fineTsList[9]= (fifoData[index + 5] & 0x00FF0000) >> 16
- fineTsList[8]= (fifoData[index + 5] & 0xFF000000) >> 24
- if verbose:
- print("====== EVENT", evNum, "=================================================")
- print("[", hex(word0), "]", "\t TYPE", hex(evType), "\t TRIGGER", hex(inTrig), "\t TIMESTAMP", (tStamp))
- print("[",hex(word1), "]", "\tEV NUM", evNum, "\tFINETS[0,3]", hex(fineTs))
- print("[",hex(word2), "]", "\tFINETS[4,11]", hex(word2))
- print(fineTsList)
- fineTsList.insert(0, tStamp)
- fineTsList.insert(0, evNum)
- if (root_tree != None):
- highWord= word0
- lowWord= word1
- extWord= word2
- timeStamp= tStamp
- bufPos= 0
- evtNumber= evNum
- evtType= evType
- trigsFired= inTrig
- mystruct.raw0= fifoData[index]
- mystruct.raw1= fifoData[index+1]
- mystruct.raw2= fifoData[index+2]
- mystruct.raw3= fifoData[index+3]
- mystruct.raw4= fifoData[index+4]
- mystruct.raw5= fifoData[index+5]
- mystruct.evtNumber= evNum
- mystruct.tluTimeStamp= tStamp
- mystruct.tluEvtType= evType
- mystruct.tluTrigFired= inTrig
- root_tree.Fill()
-
- outList.insert(len(outList), fineTsList)
- #print "=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-="
- #print "EN#\tCOARSE_TS\tFINE_TS0...FINE_TS11"
- #pprint.pprint(outList)
- return outList
-
- def plotFifoData(self, outList):
- import matplotlib.pyplot as plt
- import numpy as np
- import matplotlib.mlab as mlab
-
- coarseColumn= [row[1] for row in outList]
- fineColumn= [row[2] for row in outList]
- timeStamp= [sum(x) for x in zip(coarseColumn, fineColumn)]
- correctTs= [-1]*len(coarseColumn)
- coarseVal= 0.000000025 #coarse time value (40 Mhz, 25 ns)
- fineVal= 0.00000000078125 #fine time value (1280 MHz, 0.78125 ns)
- for iTs in range(0, len(coarseColumn)):
- correctTs[iTs]= coarseColumn[iTs]*coarseVal + fineColumn[iTs]*fineVal
- #if iTs:
- #print correctTs[iTs]-correctTs[iTs-1], "\t ", correctTs[iTs], "\t", coarseColumn[iTs], "\t", fineColumn[iTs]
-
- xdiff = np.diff(correctTs)
- np.all(xdiff[0] == xdiff)
- P= 1000000000 #display in ns
- nsDeltas = [x * P for x in xdiff]
- #centerRange= np.mean(nsDeltas)
- centerRange= 476
- windowsns= 30
- minRange= centerRange-windowsns
- maxRange= centerRange+windowsns
- plt.hist(nsDeltas, 60, range=[minRange, maxRange], facecolor='blue', align='mid', alpha= 0.75)
- #plt.hist(nsDeltas, 100, normed=True, facecolor='blue', align='mid', alpha=0.75)
- #plt.xlim((min(nsDeltas), max(nsDeltas)))
- plt.xlabel('Time (ns)')
- plt.ylabel('Entries')
- plt.title('Histogram DeltaTime')
- plt.grid(True)
-
- #Superimpose Gauss
- mean = np.mean(nsDeltas)
- variance = np.var(nsDeltas)
- sigma = np.sqrt(variance)
- x = np.linspace(min(nsDeltas), max(nsDeltas), 100)
- plt.plot(x, mlab.normpdf(x, mean, sigma))
-
- #Display plot
- plt.show()
-
- def saveFifoData(self, outList):
- import csv
- with open("output.csv", "wb") as f:
- writer = csv.writer(f)
- writer.writerows(outList)
-
-##################################################################################################################################
-##################################################################################################################################
- def acquire(self, mystruct, root_tree= None):
- print("STARTING ACQUIRE LOOP")
- print("Run#" , self.runN, "\n")
- self.isRunning= True
- index=0
- while (self.isRunning == True):
- eventFifoFillLevel= self.getFifoLevel(0)
- nFifoWords= int(eventFifoFillLevel)
- if (nFifoWords > 0):
- fifoData= self.getFifoData(nFifoWords)
- outList= self.parseFifoData(fifoData, nFifoWords/6, mystruct, root_tree, False)
-
- time.sleep(0.1)
- index= index + nFifoWords/6
- print("STOPPING ACQUIRE LOOP:", index, "events collected")
- return index
-
- def configure(self, parsed_cfg):
- print("\nTLU INITIALIZING...")
- section_name= "Producer.fmctlu"
-
- #READ CONTENT OF EPROM VIA I2C
- self.getSN()
-
- print(" Turning on software trigger veto")
- cmd = int("0x1",16)
- self.setTriggerVetoStatus(cmd)
-
- # #Get Verbose setting
- self.verbose= parsed_cfg.getint(section_name, "verbose")
-
-
- # #SET DACs
- self.writeThreshold(self.zeDAC1, parsed_cfg.getfloat(section_name, "DACThreshold0"), 1, self.verbose)
- self.writeThreshold(self.zeDAC1, parsed_cfg.getfloat(section_name, "DACThreshold1"), 0, self.verbose)
- self.writeThreshold(self.zeDAC2, parsed_cfg.getfloat(section_name, "DACThreshold2"), 3, self.verbose)
- self.writeThreshold(self.zeDAC2, parsed_cfg.getfloat(section_name, "DACThreshold3"), 2, self.verbose)
- self.writeThreshold(self.zeDAC2, parsed_cfg.getfloat(section_name, "DACThreshold4"), 1, self.verbose)
- self.writeThreshold(self.zeDAC2, parsed_cfg.getfloat(section_name, "DACThreshold5"), 0, self.verbose)
-
- #
- # #ENABLE/DISABLE HDMI OUTPUTS
- self.DUTOutputs(0, int(parsed_cfg.get(section_name, "HDMI1_set"), 16) , self.verbose)
- self.DUTOutputs(1, int(parsed_cfg.get(section_name, "HDMI2_set"), 16) , self.verbose)
- self.DUTOutputs(2, int(parsed_cfg.get(section_name, "HDMI3_set"), 16) , self.verbose)
- self.DUTOutputs(3, int(parsed_cfg.get(section_name, "HDMI4_set"), 16) , self.verbose)
-
- # #SELECT CLOCK SOURCE TO HDMI
- self.DUTClkSrc(0, int(parsed_cfg.get(section_name, "HDMI1_clk"), 16) , self.verbose)
- self.DUTClkSrc(1, int(parsed_cfg.get(section_name, "HDMI2_clk"), 16) , self.verbose)
- self.DUTClkSrc(2, int(parsed_cfg.get(section_name, "HDMI3_clk"), 16) , self.verbose)
- self.DUTClkSrc(3, int(parsed_cfg.get(section_name, "HDMI4_clk"), 16) , self.verbose)
-
- # #ENABLE/DISABLE LEMO CLOCK OUTPUT
- self.enableClkLEMO(parsed_cfg.getint(section_name, "LEMOclk"), False)
-
- #
- # #Check clock status
- self.getClockStatus()
-
- resetClocks = 0
- resetSerdes = 0
- resetCounters= 0
- if resetClocks:
- self.resetClocks()
- self.getClockStatus()
- if resetSerdes:
- self.resetSerdes()
- if resetCounters:
- self.resetCounters()
-
- # # Get inputs status and counters
- self.getChStatus()
- self.getAllChannelsCounts()
-
- # # Stop internal triggers until setup complete
- cmd = int("0x0",16)
- self.setInternalTrg(cmd)
-
- # # Set the control voltages for the PMTs
- PMT1_V= parsed_cfg.getfloat(section_name, "PMT1_V")
- PMT2_V= parsed_cfg.getfloat(section_name, "PMT2_V")
- PMT3_V= parsed_cfg.getfloat(section_name, "PMT3_V")
- PMT4_V= parsed_cfg.getfloat(section_name, "PMT4_V")
- self.pwdled.setVch(0, PMT1_V, True)
- self.pwdled.setVch(1, PMT2_V, True)
- self.pwdled.setVch(2, PMT3_V, True)
- self.pwdled.setVch(3, PMT4_V, True)
-
- # # Set pulse stretches
- str0= parsed_cfg.getint(section_name, "in0_STR")
- str1= parsed_cfg.getint(section_name, "in1_STR")
- str2= parsed_cfg.getint(section_name, "in2_STR")
- str3= parsed_cfg.getint(section_name, "in3_STR")
- str4= parsed_cfg.getint(section_name, "in4_STR")
- str5= parsed_cfg.getint(section_name, "in5_STR")
- self.setPulseStretch([str0, str1, str2, str3, str4, str5])
-
- # # Set pulse delays
- del0= parsed_cfg.getint(section_name, "in0_DEL")
- del1= parsed_cfg.getint(section_name, "in1_DEL")
- del2= parsed_cfg.getint(section_name, "in2_DEL")
- del3= parsed_cfg.getint(section_name, "in3_DEL")
- del4= parsed_cfg.getint(section_name, "in4_DEL")
- del5= parsed_cfg.getint(section_name, "in5_DEL")
- self.setPulseDelay([del0, del1, del2, del3, del4, del5])
-
- # # Set trigger pattern
- triggerPattern_low= int(parsed_cfg.get(section_name, "trigMaskLo"), 16)
- triggerPattern_high= int(parsed_cfg.get(section_name, "trigMaskHi"), 16)
- self.setTrgPattern(triggerPattern_high, triggerPattern_low)
-
- # # Set active DUTs
- DUTMask= int(parsed_cfg.get(section_name, "DUTMask"), 16)
- self.setDUTmask(DUTMask)
-
- # # Set mode (AIDA, EUDET)
- DUTMode= int(parsed_cfg.get(section_name, "DUTMaskMode"), 16)
- self.setMode(DUTMode)
-
- # # Set modifier
- modifier = int(parsed_cfg.get(section_name, "DUTMaskModeModifier"), 16)
- self.setModeModifier(modifier)
-
- # # Set veto shutter
- setVetoShutters = int(parsed_cfg.get(section_name, "DUTIgnoreShutterVeto"), 16)
- self.setVetoShutters(setVetoShutters)
-
- # # Set veto by DUT
- ignoreDUTBusy = int(parsed_cfg.get(section_name, "DUTIgnoreBusy"), 16)
- self.setVetoDUT(ignoreDUTBusy)
-
- print(" Check external veto:")
- self.getExternalVeto()
-
- # # Set trigger interval (use 0 to disable internal triggers)
- triggerInterval= parsed_cfg.getint(section_name, "InternalTriggerFreq")
- self.setInternalTrg(triggerInterval)
-
- print("TLU INITIALIZED")
-
-##################################################################################################################################
-##################################################################################################################################
- def start(self, logtimestamps=False, runN=0, mystruct= None, root_tree= None):
- print("TLU STARTING...")
- self.runN= runN
-
- print(" FIFO RESET:")
- FIFOcmd= 0x2
- self.setFifoCSR(FIFOcmd)
- eventFifoFillLevel= self.getFifoLevel()
- #cmd = int("0x000",16)
- #self.setInternalTrg(cmd)
-
- if logtimestamps:
- self.setRecordDataStatus(True)
- else:
- self.setRecordDataStatus(False)
-
- # Pulse T0
- #self.pulseT0()
- # Set run active
- self.setRunActive()
-
- print(" Turning off software trigger veto")
- self.setTriggerVetoStatus( int("0x0",16) )
-
- print("TLU STARTED")
-
- # nEvents= self.acquire(mystruct, root_tree)
- return
-
-
-##################################################################################################################################
-##################################################################################################################################
- def stop(self, saveD= False, plotD= False):
- print("TLU STOPPING...")
-
- self.getPostVetoTrg()
- eventFifoFillLevel= self.getFifoLevel()
- self.getFifoFlags()
- self.getFifoCSR()
- print(" Turning on software trigger veto")
- self.setTriggerVetoStatus( int("0x1",16) )
-
- print("Turning off shutter (setting run inactive)")
- self.setRunInactive()
-
- nFifoWords= int(eventFifoFillLevel)
- fifoData= self.getFifoData(nFifoWords)
-
- #outList= self.parseFifoData(fifoData, nFifoWords/6, None, None, True)
- #if saveD:
- # self.saveFifoData(outList)
- #if plotD:
- # self.plotFifoData(outList)
- #outFile = open('./test.txt', 'w')
- #for iData in range (0, 30):
- # outFile.write("%s\n" % fifoData[iData])
- # print hex(fifoData[iData])
- print("TLU STOPPED")
- return
diff --git a/TLU_v1e/scripts/TLUconnection.xml b/TLU_v1e/scripts/TLUconnection.xml
deleted file mode 100644
index fca67f5..0000000
--- a/TLU_v1e/scripts/TLUconnection.xml
+++ /dev/null
@@ -1,6 +0,0 @@
-
-
-
-
-
diff --git a/TLU_v1e/scripts/config_parser.py b/TLU_v1e/scripts/config_parser.py
deleted file mode 100644
index d05c5c4..0000000
--- a/TLU_v1e/scripts/config_parser.py
+++ /dev/null
@@ -1,29 +0,0 @@
-# Parse *.ini file and provide some methods to access data
-
-class ConfigParser(object):
- def __init__(self, filename):
- with open(filename, "r") as in_file:
- parsed_cfg = {}
- for line in in_file.readlines():
- line = line.strip()
- if len(line) == 0:
- continue
-
- if line[0] == "[":
- section = line[1:-1]
- parsed_cfg[section] = {}
- elif line[0] != "#":
- key = line.split("=")[0].strip()
- value = line.split("=")[1].strip()
- parsed_cfg[section][key] = value
-
- self.conf = parsed_cfg
-
- def get(self, section, key):
- return self.conf[section][key]
-
- def getint(self, section, key):
- return int(self.get(section, key))
-
- def getfloat(self, section, key):
- return float(self.get(section, key))
diff --git a/TLU_v1e/scripts/initTLU.py b/TLU_v1e/scripts/initTLU.py
deleted file mode 100644
index eb1ae65..0000000
--- a/TLU_v1e/scripts/initTLU.py
+++ /dev/null
@@ -1,184 +0,0 @@
-#
-# Function to initialize TLU
-#
-# David Cussans, October 2015
-#
-# Nasty hack - use both PyChips and uHAL ( for block read ... )
-
-from PyChipsUser import *
-from FmcTluI2c import *
-
-import uhal
-
-import sys
-import time
-
-def startTLU( uhalDevice , pychipsBoard , writeTimestamps):
-
- print "RESETTING FIFO"
- pychipsBoard.write("EventFifoCSR",0x2)
- eventFifoFillLevel = pychipsBoard.read("EventFifoFillLevel")
- print "FIFO FILL LEVEL AFTER RESET= " , eventFifoFillLevel
-
-
- if writeTimestamps:
- print "ENABLING DATA RECORDING"
- pychipsBoard.write("Enable_Record_Data",1)
- else:
- print "Disabling data recording"
- pychipsBoard.write("Enable_Record_Data",0)
-
- print "Pulsing T0"
- pychipsBoard.write("PulseT0",1)
-
- print "Turning off software trigger veto"
- pychipsBoard.write("TriggerVetoW",0)
-
- print "TLU is running"
-
-
-def stopTLU( uhalDevice , pychipsBoard ):
-
- print "Turning on software trigger veto"
- pychipsBoard.write("TriggerVetoW",1)
-
- print "TLU triggers are stopped"
-
-def initTLU( uhalDevice , pychipsBoard , listenForTelescopeShutter , pulseDelay , pulseStretch , triggerPattern , DUTMask , ignoreDUTBusy , triggerInterval , thresholdVoltage ):
-
- print "SETTING UP AIDA TLU"
-
- fwVersion = uhalDevice.getNode("version").read()
- uhalDevice.dispatch()
- print "\tVersion (uHAL)= " , hex(fwVersion)
-
- print "\tTurning on software trigger veto"
- pychipsBoard.write("TriggerVetoW",1)
-
- # Check the bus for I2C devices
- pychipsBoardi2c = FmcTluI2c(pychipsBoard)
-
- print "\tScanning I2C bus:"
- scanResults = pychipsBoardi2c.i2c_scan()
- #print scanResults
- print '\t', ', '.join(scanResults), '\n'
-
- boardId = pychipsBoardi2c.get_serial_number()
- print "\tFMC-TLU serial number= " , boardId
-
- resetClocks = 0
- resetSerdes = 0
-
-# set DACs to -200mV
- print "\tSETTING ALL DAC THRESHOLDS TO" , thresholdVoltage , "V"
- pychipsBoardi2c.set_threshold_voltage(7, thresholdVoltage)
-
- clockStatus = pychipsBoard.read("LogicClocksCSR")
- print "\tCLOCK STATUS (should be 3 if all clocks locked)= " , hex(clockStatus)
- assert ( clockStatus == 3 ) , "Clocks in TLU FPGA are not locked. No point in continuing. Re-prgramme or power cycle board"
-
- if resetClocks:
- print "Resetting clocks"
- pychipsBoard.write("LogicRst", 1 )
-
- clockStatus = pychipsBoard.read("LogicClocksCSR")
- print "Clock status after reset = " , hex(clockStatus)
-
- inputStatus = pychipsBoard.read("SerdesRstR")
- print "Input status = " , hex(inputStatus)
-
- if resetSerdes:
- pychipsBoard.write("SerdesRstW", 0x00000003 )
- inputStatus = pychipsBoard.read("SerdesRstR")
- print "Input status during reset = " , hex(inputStatus)
-
- pychipsBoard.write("SerdesRstW", 0x00000000 )
- inputStatus = pychipsBoard.read("SerdesRstR")
- print "Input status after reset = " , hex(inputStatus)
-
- pychipsBoard.write("SerdesRstW", 0x00000004 )
- inputStatus = pychipsBoard.read("SerdesRstR")
- print "Input status during calibration = " , hex(inputStatus)
-
- pychipsBoard.write("SerdesRstW", 0x00000000 )
- inputStatus = pychipsBoard.read("SerdesRstR")
- print "Input status after calibration = " , hex(inputStatus)
-
-
- inputStatus = pychipsBoard.read("SerdesRstR")
- print "\tINPUT STATUS= " , hex(inputStatus)
-
- count0 = pychipsBoard.read("ThrCount0R")
- print "\t Count 0= " , count0
-
- count1 = pychipsBoard.read("ThrCount1R")
- print "\t Count 1= " , count1
-
- count2 = pychipsBoard.read("ThrCount2R")
- print "\t Count 2= " , count2
-
- count3 = pychipsBoard.read("ThrCount3R")
- print "\t Count 3= " , count3
-
-# Stop internal triggers until setup complete
- pychipsBoard.write("InternalTriggerIntervalW",0)
-
- print "\tSETTING INPUT COINCIDENCE WINDOW TO",pulseStretch,"[Units= 160MHz clock cycles, Four 5-bit values (one per input) packed in to 32-bit word]"
- pychipsBoard.write("PulseStretchW",int(pulseStretch))
- pulseStretchR = pychipsBoard.read("PulseStretchR")
- print "\t Pulse stretch read back as:", hex(pulseStretchR)
- # assert (int(pulseStretch) == pulseStretchR) , "Pulse stretch read-back doesn't equal written value"
-
- print "\tSETTING INPUT TRIGGER DELAY TO",pulseDelay , "[Units= 160MHz clock cycles, Four 5-bit values (one per input) packed in to 32-bit word]"
- pychipsBoard.write("PulseDelayW",int(pulseDelay))
- pulseDelayR = pychipsBoard.read("PulseDelayR")
- print "\t Pulse delay read back as:", hex(pulseDelayR)
-
- print "\tSETTING TRIGGER PATTERN (for external triggers) TO 0x%08X. Two 16-bit patterns packed into 32 bit word " %(triggerPattern)
- pychipsBoard.write("TriggerPatternW",int(triggerPattern))
- triggerPatternR = pychipsBoard.read("TriggerPatternR")
- print "\t Trigger pattern read back as: 0x%08X " % (triggerPatternR)
-
- print "\tENABLING DUT(s): Mask= " , hex(DUTMask)
- pychipsBoard.write("DUTMaskW",int(DUTMask))
- DUTMaskR = pychipsBoard.read("DUTMaskR")
- print "\t DUTMask read back as:" , hex(DUTMaskR)
-
- print "\tSETTING ALL DUTs IN AIDA MODE"
- pychipsBoard.write("DUTInterfaceModeW", 0xFF)
- DUTInterfaceModeR = pychipsBoard.read("DUTInterfaceModeR")
- print "\t DUT mode read back as:" , DUTInterfaceModeR
-
- print "\tSET DUT MODE MODIFIER"
- pychipsBoard.write("DUTInterfaceModeModifierW", 0xFF)
- DUTInterfaceModeModifierR = pychipsBoard.read("DUTInterfaceModeModifierR")
- print "\t DUT mode modifier read back as:" , DUTInterfaceModeModifierR
-
- if listenForTelescopeShutter:
- print "\tSET IgnoreShutterVetoW TO LISTEN FOR VETO FROM SHUTTER"
- pychipsBoard.write("IgnoreShutterVetoW",0)
- else:
- print "\tSET IgnoreShutterVetoW TO IGNORE VETO FROM SHUTTER"
- pychipsBoard.write("IgnoreShutterVetoW",1)
- IgnoreShutterVeto = pychipsBoard.read("IgnoreShutterVetoR")
- print "\t IgnoreShutterVeto read back as:" , IgnoreShutterVeto
-
- print "\tSETTING IGNORE VETO BY DUT BUSY MASK TO" , hex(ignoreDUTBusy)
- pychipsBoard.write("IgnoreDUTBusyW",int(ignoreDUTBusy))
- IgnoreDUTBusy = pychipsBoard.read("IgnoreDUTBusyR")
- print "\t IgnoreDUTBusy read back as:" , hex(IgnoreDUTBusy)
-
-#print "Enabling handshake: No-handshake"
-#board.write("HandshakeTypeW",1)
-
-
- print "\tSETTING INTERNAL TRIGGER INTERVAL TO" , triggerInterval , "(zero= no internal triggers)"
- if triggerInterval == 0:
- internalTriggerFreq = 0
- else:
- internalTriggerFreq = 160000.0/triggerInterval
- print "\tINTERNAL TRIGGER FREQUENCY= " , internalTriggerFreq , " kHz"
- pychipsBoard.write("InternalTriggerIntervalW",triggerInterval) #0->Internal pulse generator disabled. Any other value will generate pulses with a frequency of n*6.25ns
- trigIntervalR = pychipsBoard.read("InternalTriggerIntervalR")
- print "\t Trigger interval read back as:", trigIntervalR
- print "AIDA TLU SETUP COMPLETED"
diff --git a/TLU_v1e/scripts/localConf.conf b/TLU_v1e/scripts/localConf.conf
deleted file mode 100644
index 2892d29..0000000
--- a/TLU_v1e/scripts/localConf.conf
+++ /dev/null
@@ -1,93 +0,0 @@
-[Producer.fmctlu]
-verbose= 2
-confid= 20170626
-delayStart= 1000
-nDUTs = 1
-
-# HDMI pin direction:
-# 4-bits to determine direction of HDMI pins
-# 1-bit for the clock pair
-# 0= pins are not driving signals, 1 pins drive signals (outputs)
-HDMI1_set= 0x7
-HDMI2_set= 0x7
-HDMI3_set= 0x7
-HDMI4_set= 0x7
-HDMI1_clk = 0
-HDMI2_clk = 0
-HDMI3_clk = 0
-HDMI4_clk = 0
-
-# Control voltages for the PMTs
-PMT1_V= 0.5
-PMT2_V= 0.7
-PMT3_V= 0.9
-PMT4_V= 1
-
-# Enable/disable differential LEMO CLOCK
-LEMOclk = 1
-
-# Set delay and stretch for trigger pulses
-in0_STR = 1
-in0_DEL = 0
-in1_STR = 1
-in1_DEL = 0
-in2_STR = 1
-in2_DEL = 0
-in3_STR = 1
-in3_DEL = 0
-in4_STR = 1
-in4_DEL = 0
-in5_STR = 1
-in5_DEL = 0
-#
-trigMaskHi = 0x00000000
-trigMaskLo = 0x00000002
-#
-#### DAC THRESHOLD
-DACThreshold0 = -0.12
-DACThreshold1 = -0.12
-DACThreshold2 = -0.12
-DACThreshold3 = -0.12
-DACThreshold4 = -0.12
-DACThreshold5 = -0.12
-
-# Define which DUTs are ON
-DUTMask = 0x1
-
-# Define mode of DUT (00 EUDET, 11 AIDA)
-DUTMaskMode= 0x00
-
-# Allow asynchronous veto
-DUTMaskModeModifier= 0x0
-
-# Ignore busy from a specific DUT
-DUTIgnoreBusy = 0x0
-
-# Ignore the SHUTTER veto on a specific DUT
-DUTIgnoreShutterVeto = 0x0
-
-# Generate internal triggers (in Hz, 0= no triggers)
-InternalTriggerFreq = 1000
-
-
-
-[LogCollector.log]
-# Currently, all LogCollectors have a hardcoded runtime name: log
-# nothing
-
-
-[DataCollector.my_dc]
-EUDAQ_MON=my_mon
-# send assambled event to the monitor with runtime name my_mon;
-EUDAQ_FW=native
-# the format of data file
-EUDAQ_FW_PATTERN=$12D_run$6R$X
-# the name pattern of data file
-# the $12D will be converted a data/time string with 12 digits.
-# the $6R will be converted a run number string with 6 digits.
-# the $X will be converted the suffix name of data file.
-
-[Monitor.my_mon]
-EX0_ENABLE_PRINT=0
-EX0_ENABLE_STD_PRINT=0
-EX0_ENABLE_STD_CONVERTER=1
diff --git a/TLU_v1e/scripts/run_tlu.py b/TLU_v1e/scripts/run_tlu.py
deleted file mode 100644
index 652de3a..0000000
--- a/TLU_v1e/scripts/run_tlu.py
+++ /dev/null
@@ -1,22 +0,0 @@
-import time
-
-from config_parser import ConfigParser
-from TLU_v1e import TLU
-
-conf = ConfigParser(filename="/home/silab/git/aida-tlu/TLU_v1e/scripts/localIni.ini")
-configure_conf = ConfigParser(filename="/home/silab/git/aida-tlu/TLU_v1e/scripts/localConf.conf")
-t = TLU(dev_name='tlu', man_file='file:///home/silab/git/aida-tlu/TLU_v1e/scripts/TLUconnection.xml', parsed_cfg=conf)
-t.configure(configure_conf)
-t.start()
-t.isRunning = True
-try:
- while (t.isRunning == True):
- eventFifoFillLevel= t.getFifoLevel(0)
- nFifoWords= int(eventFifoFillLevel)
- if (nFifoWords > 0):
- fifoData= t.getFifoData(nFifoWords)
- print(fifoData)
- time.sleep(1)
-except KeyboardInterrupt:
- t.isRunning = False
-t.stop()
diff --git a/TLU_v1e/scripts/startTLU_v1e.py b/TLU_v1e/scripts/startTLU_v1e.py
deleted file mode 100644
index d4a42b7..0000000
--- a/TLU_v1e/scripts/startTLU_v1e.py
+++ /dev/null
@@ -1,246 +0,0 @@
-# -*- coding: utf-8 -*-
-# miniTLU test script
-
-#from PyChipsUser import *
-#from FmcTluI2c import *
-import uhal
-import sys
-import time
-from datetime import datetime
-import threading
-# from ROOT import TFile, TTree
-# from ROOT import gROOT
-from datetime import datetime
-
-from TLU_v1e import TLU
-# Use to have interactive shell
-import cmd
-
-# Use to have config file parser
-import ConfigParser
-
-# Use root
-from ROOT import TFile, TTree, gROOT, AddressOf
-from ROOT import *
-import numpy as numpy
-
-
-## Define class that creates the command user inteface
-class MyPrompt(cmd.Cmd):
-
- # def do_initialise(self, args):
- # """Processes the INI file and writes its values to the TLU. To use a specific file type:\n
- # parseIni path/to/filename.ini\n
- # (without quotation marks)"""
- # print "COMMAND RECEIVED: PARSE INI"
- # parsed_cfg= self.open_cfg_file(args, "/users/phpgb/workspace/myFirmware/AIDA/TLU_v1e/scripts/localIni.ini")
- # try:
- # theID = parsed_cfg.getint("Producer.fmctlu", "initid")
- # print theID
- # theSTRING= parsed_cfg.get("Producer.fmctlu", "ConnectionFile")
- # print theSTRING
- # #TLU= TLU("tlu", theSTRING, parsed_cfg)
- # except IOError:
- # print "\t Could not retrieve INI data."
- # return
-
-
- def do_configure(self, args):
- """Processes the CONF file and writes its values to the TLU. To use a specific file type:\n
- parseIni path/to/filename.conf\n
- (without quotation marks)"""
- print "==== COMMAND RECEIVED: PARSE CONFIG"
- #self.testme()
- parsed_cfg= self.open_cfg_file(args, "./localConf.conf")
- try:
- theID = parsed_cfg.getint("Producer.fmctlu", "confid")
- print "\t", theID
- TLU.configure(parsed_cfg)
- except IOError:
- print "\t Could not retrieve CONF data."
- return
-
- def do_i2c(self, args):
- arglist = args.split()
- if len(arglist) == 0:
- print "\tno command specified"
- else:
- i2ccmd= arglist[0]
- results = list(map(int, arglist))
- TLU.DISP.writeSomething(results)
- print "Sending i2c command to display"
- return
-
- def do_id(self, args):
- """Interrogates the TLU and prints it unique ID on screen"""
- TLU.getSN()
- return
-
- def do_triggers(self, args):
- """Interrogates the TLU and prints the number of triggers seen by the input discriminators"""
- TLU.getChStatus()
- TLU.getAllChannelsCounts()
- TLU.getPostVetoTrg()
- return
-
- def do_startRun(self, args):
- """Starts the TLU run. If a number is specified, this number will be appended to the file name as Run_#"""
- print "==== COMMAND RECEIVED: STARTING TLU RUN"
- #startTLU( uhalDevice = self.hw, pychipsBoard = self.board, writeTimestamps = ( options.writeTimestamps == "True" ) )
- arglist = args.split()
- if len(arglist) == 0:
- print "\tno run# specified, using 1"
- runN= 1
- else:
- runN= arglist[0]
-
- logdata= True
-
- #TLU.start(logdata)
- if (TLU.isRunning): #Prevent double start
- print " Run already in progress"
- return
- else:
- now = datetime.now().strftime('%Y%m%d_%H%M%S')
- default_filename = "./datafiles/"+ now + "_tluData_" + str(runN) + ".root"
- rootFname= default_filename
- print "OPENING ROOT FILE:", rootFname
- self.root_file = TFile( rootFname, 'RECREATE' )
- # Create a root "tree"
- root_tree = TTree( 'T', 'TLU Data' )
- #highWord =0
- #lowWord =0
- #evtNumber=0
- #timeStamp=0
- #evtType=0
- #trigsFired=0
- #bufPos = 0
-
- #https://root-forum.cern.ch/t/long-integer/1961/2
- gROOT.ProcessLine(
- "struct MyStruct {\
- UInt_t raw0;\
- UInt_t raw1;\
- UInt_t raw2;\
- UInt_t raw3;\
- UInt_t raw4;\
- UInt_t raw5;\
- UInt_t evtNumber;\
- ULong64_t tluTimeStamp;\
- UChar_t tluEvtType;\
- UChar_t tluTrigFired;\
- };" );
-
- mystruct= MyStruct()
-
-
- # Create a branch for each piece of data
- root_tree.Branch('EVENTS', mystruct, 'raw0/i:raw1/i:raw2/i:raw3/i:raw4/i:raw5/i:evtNumber/i:tluTimeStamp/l:tluEvtType/b:tluTrigFired/b' )
- # root_tree.Branch( 'tluHighWord' , highWord , "HighWord/l")
- # root_tree.Branch( 'tluLowWord' , lowWord , "LowWord/l")
- # root_tree.Branch( 'tluExtWord' , extWord , "ExtWord/l")
- # root_tree.Branch( 'tluTimeStamp' , timeStamp , "TimeStamp/l")
- # root_tree.Branch( 'tluBufPos' , bufPos , "Bufpos/s")
- # root_tree.Branch( 'tluEvtNumber' , evtNumber , "EvtNumber/i")
- # root_tree.Branch( 'tluEvtType' , evtType , "EvtType/b")
- # root_tree.Branch( 'tluTrigFired' , trigsFired, "TrigsFired/b")
- #self.root_file.Write()
-
- daq_thread= threading.Thread(target = TLU.start, args=(logdata, runN, mystruct, root_tree))
- daq_thread.start()
-
- def do_endRun(self, args):
- """Stops the TLU run"""
- print "==== COMMAND RECEIVED: STOP TLU RUN"
- if TLU.isRunning:
- TLU.isRunning= False
- TLU.stop(False, False)
- self.root_file.Write()
- self.root_file.Close()
- else:
- print " No run to stop"
-
-
- def do_quit(self, args):
- """Quits the program."""
- print "==== COMMAND RECEIVED: QUITTING TLU CONSOLE"
- if TLU.isRunning:
- TLU.isRunning= False
- TLU.stop(False, False)
- self.root_file.Write()
- self.root_file.Close()
- print "Terminating run"
- return True
-
- def testme(self):
- print "This is a test"
-
- def open_cfg_file(self, args, default_file):
- # Parse the user arguments, attempts to opent the file and performs a (minimal)
- # check to verify the file exists (but not that its content is correct)
-
- arglist = args.split()
- if len(arglist) == 0:
- print "\tno file specified, using default"
- fileName= default_file
- print "\t", fileName
- else:
- fileName= arglist[0]
- if len(arglist) > 1:
- print "\tinvalid: too many arguments. Max 1."
- return
-
- parsed_file = ConfigParser.RawConfigParser()
- try:
- with open(fileName) as f:
- parsed_file.readfp(f)
- print "\t", parsed_file.sections()
- except IOError:
- print "\t Error while parsing the specified file."
- return
- return parsed_file
-
-# # Override methods in Cmd object ##
-# def preloop(self):
-# """Initialization before prompting user for commands.
-# Despite the claims in the Cmd documentaion, Cmd.preloop() is not a stub.
-# """
-# cmd.Cmd.preloop(self) # # sets up command completion
-# self._hist = [] # # No history yet
-# self._locals = {} # # Initialize execution namespace for user
-# self._globals = {}
-# print "\nINITIALIZING"
-# now = datetime.now().strftime('%Y-%m-%dT%H_%M_%S')
-# default_filename = './rootfiles/tluData_' + now + '.root'
-# print "SETTING UP AIDA TLU TO SUPPLY CLOCK AND TRIGGER TO TORCH READOUT\n"
-# self.manager = uhal.ConnectionManager("file://./connection.xml")
-# self.hw = self.manager.getDevice("minitlu")
-# self.device_id = self.hw.id()
-#
-# # Point to TLU in Pychips
-# self.bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
-#
-# # Assume DIP-switch controlled address. Switches at 2
-# self.board = ChipsBusUdp(self.bAddrTab,"192.168.200.32",50001)
-
-
-#################################################
-if __name__ == "__main__":
- print "TLU v1E MAIN"
- prompt = MyPrompt()
- prompt.prompt = '>> '
-
- parsed_ini= prompt.open_cfg_file("", "./localIni.ini")
- TLU= TLU("tlu", "file://./TLUconnection.xml", parsed_ini)
-
- ###TLU.configure(parsed_cfg)
- ###logdata= True
- ###TLU.start(logdata)
- ###time.sleep(5)
- ###TLU.stop(False, False)
-
- # Start interactive prompt
- print "===================================================================="
- print "==========================TLU TEST CONSOLE=========================="
- print "===================================================================="
- prompt.cmdloop("Type 'help' for a list of commands.")
diff --git a/TLU_v1e/scripts/startTLU_v1e.sh b/TLU_v1e/scripts/startTLU_v1e.sh
deleted file mode 100644
index f0bb387..0000000
--- a/TLU_v1e/scripts/startTLU_v1e.sh
+++ /dev/null
@@ -1,25 +0,0 @@
-#!/bin/bash
-
-echo "=========================="
-CURRENT_DIR=${0%/*}
-echo "CURRENT DIRECTORY: " $CURRENT_DIR
-
-echo "============"
-echo "SETTING PATHS"
-#export PYTHONPATH=$CURRENT_DIR/../../../../../Python_Scripts/PyChips_1_5_0_pre2A/src:$PYTHONPATH
-#export PYTHONPATH=~/Python_Scripts/PyChips_1_5_0_pre2A/src:$PYTHONPATH
-export PYTHONPATH=../../packages:$PYTHONPATH
-echo "PYTHON PATH= " $PYTHONPATH
-export LD_LIBRARY_PATH=/opt/cactus/lib:$LD_LIBRARY_PATH
-echo "LD_LIBRARY_PATH= " $LD_LIBRARY_PATH
-export PATH=/usr/bin/:/opt/cactus/bin:$PATH
-echo "PATH= " $PATH
-
-cd $CURRENT_DIR
-
-echo "============"
-echo "STARTING PYTHON SCRIPT FOR TLU"
-#python $CURRENT_DIR/startTLU_v8.py $@
-
-python startTLU_v1e.py $@
-#python testTLU_script.py
diff --git a/TLU_v1e/scripts/startTLU_v6.py b/TLU_v1e/scripts/startTLU_v6.py
deleted file mode 100644
index b7948f2..0000000
--- a/TLU_v1e/scripts/startTLU_v6.py
+++ /dev/null
@@ -1,232 +0,0 @@
-#
-# Script to setup AIDA TLU for TPix3 telescope <--> TORCH synchronization
-#
-# David Cussans, December 2012
-#
-# Nasty hack - use both PyChips and uHAL ( for block read ... )
-
-from PyChipsUser import *
-from FmcTluI2c import *
-
-import uhal
-
-import sys
-
-import time
-
-from datetime import datetime
-
-from optparse import OptionParser
-
-# For single character non-blocking input:
-import select
-import tty
-import termios
-
-from initTLU import *
-
-def isData():
- return select.select([sys.stdin], [], [], 0) == ([sys.stdin], [], [])
-
-now = datetime.now().strftime('%Y-%m-%dT%H_%M_%S')
-default_filename = 'tluData_' + now + '.root'
-parser = OptionParser()
-
-parser.add_option('-r','--rootFname',dest='rootFname',
- default=default_filename,help='Path of output file')
-parser.add_option('-o','--writeTimestamps',dest='writeTimestamps',
- default="True",help='Set True to write timestamps to ROOT file')
-parser.add_option('-p','--printTimestamps',dest='printTimestamps',
- default="True",help='Set True to print timestamps to screen (nothing printed unless also output to file) ')
-parser.add_option('-s','--listenForTelescopeShutter',dest='listenForTelescopeShutter',
- default=False,help='Set True to veto triggers when shutter goes high')
-parser.add_option('-d','--pulseDelay',dest='pulseDelay', type=int,
- default=0x00,help='Delay added to input triggers. Four 5-bit numbers packed into 32-bt word, Units of 6.125ns')
-parser.add_option('-w','--pulseStretch',dest='pulseStretch',type=int,
- default=0x00,help='Width added to input triggers. Four 5-bit numbers packed into 32-bt word. Units of 6.125ns')
-parser.add_option('-t','--triggerPattern',dest='triggerPattern',type=int,
- default=0xFFFEFFFE,help='Pattern match to generate trigger. Two 16-bit words packed into 32-bit word.')
-parser.add_option('-m','--DUTMask',dest='DUTMask',type=int,
- default=0x01,help='Three-bit mask selecting which DUTs are active.')
-parser.add_option('-y','--ignoreDUTBusy',dest='ignoreDUTBusy',type=int,
- default=0x0F,help='Three-bit mask selecting which DUTs can veto triggers by setting BUSY high. Low = can veto, high = ignore busy.')
-parser.add_option('-i','--triggerInterval',dest='triggerInterval',type=int,
- default=0,help='Interval between internal trigers ( in units of 6.125ns ). Set to zero to turn off internal triggers')
-parser.add_option('-v','--thresholdVoltage',dest='thresholdVoltage',type=float,
- default=-0.2,help='Threshold voltage for TLU inputs ( units of volts)')
-
-(options, args) = parser.parse_args(sys.argv[1:])
-
-from ROOT import TFile, TTree
-from ROOT import gROOT
-
-print "SETTING UP AIDA TLU TO SUPPLY CLOCK AND TRIGGER TO TORCH READOUT\n"
-
-# Point to board in uHAL
-manager = uhal.ConnectionManager("file://./connection.xml")
-hw = manager.getDevice("minitlu")
-device_id = hw.id()
-
-# Point to TLU in Pychips
-bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
-
-# Assume DIP-switch controlled address. Switches at 2
-board = ChipsBusUdp(bAddrTab,"192.168.200.32",50001)
-
-# Open Root file
-print "OPENING ROOT FILE:", options.rootFname
-f = TFile( options.rootFname, 'RECREATE' )
-
-# Create a root "tree"
-tree = TTree( 'T', 'TLU Data' )
-highWord =0
-lowWord =0
-evtNumber=0
-timeStamp=0
-evtType=0
-trigsFired=0
-bufPos = 0
-
-# Create a branch for each piece of data
-tree.Branch( 'tluHighWord' , highWord , "HighWord/l")
-tree.Branch( 'tluLowWord' , lowWord , "LowWord/l")
-tree.Branch( 'tluTimeStamp' , timeStamp , "TimeStamp/l")
-tree.Branch( 'tluBufPos' , bufPos , "Bufpos/s")
-tree.Branch( 'tluEvtNumber' , evtNumber , "EvtNumber/i")
-tree.Branch( 'tluEvtType' , evtType , "EvtType/b")
-tree.Branch( 'tluTrigFired' , trigsFired, "TrigsFired/b")
-
-# Initialize TLU registers
-initTLU( uhalDevice = hw, pychipsBoard = board, listenForTelescopeShutter = options.listenForTelescopeShutter, pulseDelay = options.pulseDelay, pulseStretch = options.pulseStretch, triggerPattern = options.triggerPattern , DUTMask = options.DUTMask, ignoreDUTBusy = options.ignoreDUTBusy , triggerInterval = options.triggerInterval, thresholdVoltage = options.thresholdVoltage )
-
-loopWait = 0.1
-oldEvtNumber = 0
-
-oldPreVetotriggerCount = board.read("PreVetoTriggersR")
-oldPostVetotriggerCount = board.read("PostVetoTriggersR")
-
-oldThresholdCounter0 =0
-oldThresholdCounter1 =0
-oldThresholdCounter2 =0
-oldThresholdCounter3 =0
-
-print "STARTING POLLING LOOP"
-
-eventFifoFillLevel = 0
-loopRunning = True
-runStarted = False
-
-oldTime = time.time()
-
-# Save old terminal settings
-oldTermSettings = termios.tcgetattr(sys.stdin)
-tty.setcbreak(sys.stdin.fileno())
-
-while loopRunning:
-
- if isData():
- c = sys.stdin.read(1)
- print "\tGOT INPUT:", c
- if c == 't':
- loopRunning = False
- print "\tTERMINATING LOOP"
- elif c == 'c':
- runStarted = True
- print "\tSTARTING RUN"
- startTLU( uhalDevice = hw, pychipsBoard = board, writeTimestamps = ( options.writeTimestamps == "True" ) )
- elif c == 'f':
- # runStarted = True
- print "\tSTOPPING TRIGGERS"
- stopTLU( uhalDevice = hw, pychipsBoard = board )
-
-
- if runStarted:
-
- eventFifoFillLevel = hw.getNode("eventBuffer.EventFifoFillLevel").read()
-
- preVetotriggerCount = hw.getNode("triggerLogic.PreVetoTriggersR").read()
- postVetotriggerCount = hw.getNode("triggerLogic.PostVetoTriggersR").read()
-
- timestampHigh = hw.getNode("Event_Formatter.CurrentTimestampHR").read()
- timestampLow = hw.getNode("Event_Formatter.CurrentTimestampLR").read()
-
- thresholdCounter0 = hw.getNode("triggerInputs.ThrCount0R").read()
- thresholdCounter1 = hw.getNode("triggerInputs.ThrCount1R").read()
- thresholdCounter2 = hw.getNode("triggerInputs.ThrCount2R").read()
- thresholdCounter3 = hw.getNode("triggerInputs.ThrCount3R").read()
-
- hw.dispatch()
-
- newTime = time.time()
- timeDelta = newTime - oldTime
- oldTime = newTime
- #print "time delta = " , timeDelta
- preVetoFreq = (preVetotriggerCount-oldPreVetotriggerCount)/timeDelta
- postVetoFreq = (postVetotriggerCount-oldPostVetotriggerCount)/timeDelta
- oldPreVetotriggerCount = preVetotriggerCount
- oldPostVetotriggerCount = postVetotriggerCount
-
- deltaCounts0 = thresholdCounter0 - oldThresholdCounter0
- oldThresholdCounter0 = thresholdCounter0
- deltaCounts1 = thresholdCounter1 - oldThresholdCounter1
- oldThresholdCounter1 = thresholdCounter1
- deltaCounts2 = thresholdCounter2 - oldThresholdCounter2
- oldThresholdCounter2 = thresholdCounter2
- deltaCounts3 = thresholdCounter3 - oldThresholdCounter3
- oldThresholdCounter3 = thresholdCounter3
-
- print "pre , post veto triggers , pre , post frequency = " , preVetotriggerCount , postVetotriggerCount , preVetoFreq , postVetoFreq
-
- print "CURRENT TIMESTAMP HIGH, LOW (hex) = " , hex(timestampHigh) , hex(timestampLow)
-
- print "Input counts 0,1,2,3 = " , thresholdCounter0 , thresholdCounter1 , thresholdCounter2 , thresholdCounter3
- print "Input freq (Hz) 0,1,2,3 = " , deltaCounts0/timeDelta , deltaCounts1/timeDelta , deltaCounts2/timeDelta , deltaCounts3/timeDelta
-
- nEvents = int(eventFifoFillLevel)//4 # only read out whole events ( 4 x 32-bit words )
- wordsToRead = nEvents*4
-
- print "FIFO FILL LEVEL= " , eventFifoFillLevel
-
- print "# EVENTS IN FIFO = ",nEvents
- print "WORDS TO READ FROM FIFO = ",wordsToRead
-
- # get timestamp data and fifo fill in same outgoing packet.
- timestampData = hw.getNode("eventBuffer.EventFifoData").readBlock(wordsToRead)
-
- hw.dispatch()
-
- # print timestampData
- for bufPos in range (0, nEvents ):
- lowWord = timestampData[bufPos*4 + 1] + 0x100000000* timestampData[ (bufPos*4) + 0] # timestamp
-
- highWord = timestampData[bufPos*4 + 3] + 0x100000000* timestampData[ (bufPos*4) + 2] # evt number
- evtNumber = timestampData[bufPos*4 + 3]
-
- if evtNumber != ( oldEvtNumber + 1 ):
- print "***WARNING *** Non sqeuential event numbers *** , evt,oldEvt = ", evtNumber , oldEvtNumber
-
- oldEvtNumber = evtNumber
-
- timeStamp = lowWord & 0xFFFFFFFFFFFF
-
- evtType = timestampData[ (bufPos*4) + 0] >> 28
-
- trigsFired = (timestampData[ (bufPos*4) + 0] >> 16) & 0xFFF
-
- if (options.printTimestamps == "True" ):
- print "bufferPos, highWord , lowWord , event-number , timestamp , evtType = %x %016x %016x %08x %012x %01x %03x" % ( bufPos , highWord , lowWord, evtNumber , timeStamp , evtType , trigsFired)
-
- # Fill root branch - see example in http://wlav.web.cern.ch/wlav/pyroot/tpytree.html : write raw data and decoded data for now.
- tree.Fill()
-
- time.sleep( loopWait)
-
-# Fixme - at the moment infinite loop.
-preVetotriggerCount = board.read("PreVetoTriggersR")
-postVetotriggerCount = board.read("PostVetoTriggersR")
-print "EXIT POLLING LOOP"
-print "\nTRIGGER COUNT AT THE END OF RUN [pre, post]:" , preVetotriggerCount , postVetotriggerCount
-
-termios.tcsetattr(sys.stdin, termios.TCSADRAIN, oldTermSettings)
-f.Write()
-f.Close()
diff --git a/TLU_v1e/scripts/test.py b/TLU_v1e/scripts/test.py
deleted file mode 100644
index ac68201..0000000
--- a/TLU_v1e/scripts/test.py
+++ /dev/null
@@ -1,34 +0,0 @@
-import matplotlib.pyplot as plt
-import numpy as np
-import matplotlib.mlab as mlab
-
-print "TEST.py"
-myFile= "./500ns_23ns.txt"
-
-with open(myFile) as f:
- nsDeltas = map(float, f)
-
-P= 1000000000 #display in ns
-nsDeltas = [x * P for x in nsDeltas]
-centerRange= 25
-windowsns= 5
-minRange= centerRange-windowsns
-maxRange= centerRange+windowsns
-plt.hist(nsDeltas, 60, range=[minRange, maxRange], facecolor='blue', align='mid', alpha= 0.75)
-#plt.hist(nsDeltas, 100, normed=True, facecolor='blue', align='mid', alpha=0.75)
-#plt.xlim((min(nsDeltas), max(nsDeltas)))
-plt.xlabel('Time (ns)')
-plt.ylabel('Entries')
-plt.title('Histogram DeltaTime')
-plt.grid(True)
-
-#Superimpose Gauss
-mean = np.mean(nsDeltas)
-variance = np.var(nsDeltas)
-sigma = np.sqrt(variance)
-x = np.linspace(min(nsDeltas), max(nsDeltas), 100)
-plt.plot(x, mlab.normpdf(x, mean, sigma))
-print (mean, sigma)
-
-#Display plot
-plt.show()
diff --git a/TLU_v1e/scripts/testTLU_script.py b/TLU_v1e/scripts/testTLU_script.py
deleted file mode 100644
index 9d8b334..0000000
--- a/TLU_v1e/scripts/testTLU_script.py
+++ /dev/null
@@ -1,79 +0,0 @@
-# miniTLU test script
-
-from FmcTluI2c import *
-import uhal
-import sys
-import time
-from I2CuHal import I2CCore
-from miniTLU import MiniTLU
-from datetime import datetime
-
-if __name__ == "__main__":
- print "\tTEST TLU SCRIPT"
- miniTLU= MiniTLU("minitlu", "file://./connection.xml")
- #(self, target, wclk, i2cclk, name="i2c", delay=None)
- TLU_I2C= I2CCore(miniTLU.hw, 10, 5, "i2c_master", None)
- TLU_I2C.state()
-
-
- #READ CONTENT OF EEPROM ON 24AA02E48 (0xFA - 0XFF)
- mystop= 1
- time.sleep(0.1)
- myaddr= [0xfa]
- TLU_I2C.write( 0x50, myaddr, mystop)
- res=TLU_I2C.read( 0x50, 6)
- print "Checkin EEPROM:"
- result="\t"
- for iaddr in res:
- result+="%02x "%(iaddr)
- print result
-
- #SCAN I2C ADDRESSES
- #WRITE PROM
- #WRITE DAC
-
-
- #Convert required threshold voltage to DAC code
- #def convert_voltage_to_dac(self, desiredVoltage, Vref=1.300):
- print("Writing DAC setting:")
- Vref= 1.300
- desiredVoltage= 3.3
- channel= 0
- i2cSlaveAddrDac = 0x1F
- vrefOn= 0
- Vdaq = ( desiredVoltage + Vref ) / 2
- dacCode = 0xFFFF * Vdaq / Vref
- dacCode= 0x391d
- print "\tVreq:", desiredVoltage
- print "\tDAC code:" , dacCode
- print "\tCH:", channel
- print "\tIntRef:", vrefOn
-
- #Set DAC value
- #def set_dac(self,channel,value , vrefOn = 0 , i2cSlaveAddrDac = 0x1F):
- if channel<0 or channel>7:
- print "set_dac ERROR: channel",channel,"not in range 0-7 (bit mask)"
- ##return -1
- if dacCode<0 or dacCode>0xFFFF:
- print "set_dac ERROR: value",dacCode ,"not in range 0-0xFFFF"
- ##return -1
- # AD5665R chip with A0,A1 tied to ground
- #i2cSlaveAddrDac = 0x1F # seven bit address, binary 00011111
-
- # print "I2C address of DAC = " , hex(i2cSlaveAddrDac)
- # dac = RawI2cAccess(self.i2cBusProps, i2cSlaveAddrDac)
- # # if we want to enable internal voltage reference:
-
- if vrefOn:
- # enter vref-on mode:
- print "\tTurning internal reference ON"
- #dac.write([0x38,0x00,0x01])
- TLU_I2C.write( i2cSlaveAddrDac, [0x38,0x00,0x01], 0)
- else:
- print "\tTurning internal reference OFF"
- #dac.write([0x38,0x00,0x00])
- TLU_I2C.write( i2cSlaveAddrDac, [0x38,0x00,0x00], 0)
- # Now set the actual value
- sequence=[( 0x18 + ( channel &0x7 ) ) , int(dacCode/256)&0xff , int(dacCode)&0xff]
- print "\tWriting byte sequence:", sequence
- TLU_I2C.write( i2cSlaveAddrDac, sequence, 0)
diff --git a/TLU_v1e/scripts/test_T0.py b/TLU_v1e/scripts/test_T0.py
deleted file mode 100644
index cf81b33..0000000
--- a/TLU_v1e/scripts/test_T0.py
+++ /dev/null
@@ -1,92 +0,0 @@
-#
-# Script to exercise AIDA mini-TLU
-#
-# David Cussans, December 2012
-#
-# Nasty hack - use both PyChips and uHAL ( for block read ... )
-
-from PyChipsUser import *
-from FmcTluI2c import *
-
-import sys
-import time
-
-
-# Point to TLU in Pychips
-bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
-# Assume DIP-switch controlled address. Switches at 2
-board = ChipsBusUdp(bAddrTab,"192.168.200.32",50001)
-
-# Check the bus for I2C devices
-boardi2c = FmcTluI2c(board)
-
-firmwareID=board.read("FirmwareId")
-
-print "Firmware (from PyChips) = " , hex(firmwareID)
-
-print "Scanning I2C bus:"
-scanResults = boardi2c.i2c_scan()
-print scanResults
-
-boardId = boardi2c.get_serial_number()
-print "FMC-TLU serial number = " , boardId
-
-resetClocks = 0
-
-
-
-clockStatus = board.read("LogicClocksCSR")
-print "Clock status = " , hex(clockStatus)
-
-if resetClocks:
- print "Resetting clocks"
- board.write("LogicRst", 1 )
-
- clockStatus = board.read("LogicClocksCSR")
- print "Clock status after reset = " , hex(clockStatus)
-
-
-board.write("InternalTriggerIntervalW",0)
-
-print "Enabling DUT 0 and 1"
-board.write("DUTMaskW",3)
-DUTMask = board.read("DUTMaskR")
-print "DUTMaskR = " , DUTMask
-
-print "Ignore veto on DUT 0 and 1"
-board.write("IgnoreDUTBusyW",3)
-IgnoreDUTBusy = board.read("IgnoreDUTBusyR")
-print "IgnoreDUTBusyR = " , IgnoreDUTBusy
-
-print "Turning off software trigger veto"
-board.write("TriggerVetoW",0)
-
-print "Reseting FIFO"
-board.write("EventFifoCSR",0x2)
-eventFifoFillLevel = board.read("EventFifoFillLevel")
-print "FIFO fill level after resetting FIFO = " , eventFifoFillLevel
-
-print "Enabling data recording"
-board.write("Enable_Record_Data",1)
-
-#print "Enabling handshake: No-handshake"
-#board.write("HandshakeTypeW",1)
-
-#TriggerInterval = 400000
-TriggerInterval = 0
-print "Setting internal trigger interval to " , TriggerInterval
-board.write("InternalTriggerIntervalW",TriggerInterval) #0->Internal pulse generator disabled. Any other value will generate pulses with a frequency of n*6.25ns
-trigInterval = board.read("InternalTriggerIntervalR")
-print "Trigger interval read back as ", trigInterval
-
-print "Setting TPix_maskexternal to ignore external shutter and T0"
-board.write("TPix_maskexternal",0x0003)
-
-numLoops = 500000
-oldEvtNumber = 0
-
-for iLoop in range(0,numLoops):
-
- board.write("TPix_T0", 0x0001)
-
-# time.sleep( 1.0)
diff --git a/VERSION b/VERSION
new file mode 100644
index 0000000..9f8e9b6
--- /dev/null
+++ b/VERSION
@@ -0,0 +1 @@
+1.0
\ No newline at end of file
diff --git a/aidatlu.egg-info/PKG-INFO b/aidatlu.egg-info/PKG-INFO
deleted file mode 100644
index 5ab1187..0000000
--- a/aidatlu.egg-info/PKG-INFO
+++ /dev/null
@@ -1,16 +0,0 @@
-Metadata-Version: 2.1
-Name: aidatlu
-Version: 0.1.0
-Summary: UNKNOWN
-Home-page: UNKNOWN
-Author:
-Author-email:
-Maintainer:
-Maintainer-email:
-License: UNKNOWN
-Platform: any
-Requires-Python: >=3.0
-License-File: LICENSE
-
-UNKNOWN
-
diff --git a/aidatlu.egg-info/SOURCES.txt b/aidatlu.egg-info/SOURCES.txt
deleted file mode 100644
index d91eb47..0000000
--- a/aidatlu.egg-info/SOURCES.txt
+++ /dev/null
@@ -1,38 +0,0 @@
-LICENSE
-README.md
-setup.py
-TLU_v1e/__init__.py
-TLU_v1e/scripts/AIDA_testPower.py
-TLU_v1e/scripts/AIDA_testScript.py
-TLU_v1e/scripts/TLU_v1e.py
-TLU_v1e/scripts/__init__.py
-TLU_v1e/scripts/config_parser.py
-TLU_v1e/scripts/initTLU.py
-TLU_v1e/scripts/make_it_work.py
-TLU_v1e/scripts/startTLU_v1e.py
-TLU_v1e/scripts/startTLU_v6.py
-TLU_v1e/scripts/test.py
-TLU_v1e/scripts/testTLU_script.py
-TLU_v1e/scripts/test_T0.py
-aidatlu.egg-info/PKG-INFO
-aidatlu.egg-info/SOURCES.txt
-aidatlu.egg-info/dependency_links.txt
-aidatlu.egg-info/top_level.txt
-packages/AD5665R.py
-packages/ADN2814ACPZ.py
-packages/ATSHA204A.py
-packages/E24AA025E48T.py
-packages/FmcTluI2c.py
-packages/I2CDISP.py
-packages/I2CuHal.py
-packages/I2CuHal2.py
-packages/I2cBusProperties.py
-packages/NHDC0220Biz.py
-packages/PCA9539PW.py
-packages/PCA9548ADW.py
-packages/RawI2cAccess.py
-packages/SFPI2C.py
-packages/TLU_powermodule.py
-packages/__init__.py
-packages/si5345.py
-packages/TLU_v1e/__init__.py
\ No newline at end of file
diff --git a/aidatlu.egg-info/dependency_links.txt b/aidatlu.egg-info/dependency_links.txt
deleted file mode 100644
index 8b13789..0000000
--- a/aidatlu.egg-info/dependency_links.txt
+++ /dev/null
@@ -1 +0,0 @@
-
diff --git a/aidatlu.egg-info/top_level.txt b/aidatlu.egg-info/top_level.txt
deleted file mode 100644
index c31d529..0000000
--- a/aidatlu.egg-info/top_level.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-TLU_v1e
-packages
diff --git a/aidatlu/README.md b/aidatlu/README.md
new file mode 100644
index 0000000..74a91db
--- /dev/null
+++ b/aidatlu/README.md
@@ -0,0 +1,54 @@
+# Configuration
+The AIDA-2020 TLU is configured using a yaml file (tlu_configuration.yaml).
+In the following, the possible configuration parameters and settings are briefly explained.
+
+### Internal Trigger Generation (internal_trigger)
+The setting internal trigger allows the TLU to generate a trigger internally with a given frequency.
+To disable the generation of internal triggers set this frequency to zero.
+
+### DUT Module (dut_module)
+The DUT module configures the individual DUT interfaces.
+Where each interface can be set to one operating mode.
+The possible modes are 'aida', 'aidatrig' and 'eudet'.
+With 'aidatrig' the AIDA mode with additional trigger number.
+And 'aida' or 'eudet' the AIDA or EUDET operating modes.
+It is important to note that only working DUT devices should be enabled.
+One not properly working DUT can block the TLU from sending out triggers (especially in EUDET mode).
+
+### Trigger Inputs (trigger_inputs)
+Multiple settings of the trigger inputs are configurable.
+This includes trigger input thresholds, trigger logic, trigger polarity and trigger signal shaping.
+
+The threshold for each trigger input can be tuned individually between [-1.3; 1.3] V.
+
+Another setting controls the trigger input logic.
+Each trigger input can have one of three settings. The input can act as 'active', 'veto' or 'do not care'.
+Between each trigger input, there is also the possibility to set 'AND' or 'OR'.
+A desired trigger configuration is set with the use of the [Python bitwise operators](https://wiki.python.org/moin/BitwiseOperators).
+These operators are used in conjunction with the input channels CH1-CH6 and interpreted as a literal logic expression.
+For example "(CH1 & ~CH2) & (CH3 | CH4 | CH5 | CH6)" produces a valid trigger, when CH1 and not CH2 triggers and when one of CH3, CH4, CH5 or CH6 triggers.
+An input channel that is not explicitly set to 'veto' or 'enabled' is automatically set to 'do not care'.
+
+Trigger polarity controls if the TLU should trigger on a rising (0) or falling (1) edge of an incoming trigger signal.
+
+Each trigger input signal can be delayed and stretched by a given number of clock cycles.
+This is set with a list containing the number of clock cycles for every different trigger input.
+This value is written in a 5-bit register so the maximum stretch or delay in clock cycles is 32.
+One should stretch each used trigger input signal at least by 1 to prevent the generation of incomplete triggers.
+
+### Clock LEMO (clock_lemo)
+The clock LEMO setting enables or disables the clock LEMO output.
+Set this to 'True' or 'False'.
+
+### PMT Power (pmt_control)
+Set the PMT control voltage. The possible range is between [0; 1] V.
+
+### Data Handling and Online Monitor
+Two settings concern the data handling. The creation of raw and interpreted data files.
+At last, the ZMQ connection can be configured.
+
+### Stop Conditions
+Two optional stop conditions can be set in tlu_configuration.yaml.
+The maximum number of trigger events (max_trigger_number, e.g. max_trigger_number: 1000000)
+and a timeout in seconds (timeout, e.g. timeout: 100) can be set.
+These configurations are not included by default in the tlu_configuration file, so add them manually if needed.
\ No newline at end of file
diff --git a/aidatlu/TLUPyProducer.py b/aidatlu/TLUPyProducer.py
new file mode 100644
index 0000000..a0e702d
--- /dev/null
+++ b/aidatlu/TLUPyProducer.py
@@ -0,0 +1,100 @@
+#! /usr/bin/env python3
+# load binary lib/pyeudaq.so
+import pyeudaq
+from pyeudaq import EUDAQ_INFO, EUDAQ_ERROR
+import time
+from main.tlu import AidaTLU
+import uhal
+
+"""
+Example Producer from EUDAQ
+This is not well tested. But something like this should work.
+Prob. one needs to work a bit on the run loop.
+
+"""
+
+
+def exception_handler(method):
+ def inner(*args, **kwargs):
+ try:
+ return method(*args, **kwargs)
+ except Exception as e:
+ EUDAQ_ERROR(str(e))
+ raise e
+
+ return inner
+
+
+class TLUPyProducer(pyeudaq.Producer):
+ def __init__(self, name, runctrl):
+ pyeudaq.Producer.__init__(self, name, runctrl)
+
+ self.is_running = 0
+ EUDAQ_INFO("New instance of TLUPyProducer")
+
+ @exception_handler
+ def DoInitialise(self):
+ EUDAQ_INFO("DoInitialise")
+ uhal.setLogLevelTo(uhal.LogLevel.NOTICE)
+ manager = uhal.ConnectionManager("file://./misc/aida_tlu_connection.xml")
+ hw = uhal.HwInterface(manager.getDevice("aida_tlu.controlhub"))
+
+ self.tlu = AidaTLU(hw)
+ # print 'key_a(init) = ', self.GetInitItem("key_a")
+
+ @exception_handler
+ def DoConfigure(self):
+ EUDAQ_INFO("DoConfigure")
+ self.tlu.configure()
+ # print 'key_b(conf) = ', self.GetConfigItem("key_b")
+
+ @exception_handler
+ def DoStartRun(self):
+ EUDAQ_INFO("DoStartRun")
+ self.tlu.run()
+ self.is_running = 1
+
+ @exception_handler
+ def DoStopRun(self):
+ EUDAQ_INFO("DoStopRun")
+ self.tlu.stop_run()
+ self.is_running = 0
+
+ @exception_handler
+ def DoReset(self):
+ EUDAQ_INFO("DoReset")
+ self.tlu.reset_configuration()
+ self.is_running = 0
+
+ @exception_handler
+ def RunLoop(self):
+ EUDAQ_INFO("Start of RunLoop in TLUPyProducer")
+ trigger_n = 0
+ # TODO here the Run loop from the tlu is probably needed
+ while self.is_running:
+ ev = pyeudaq.Event("RawEvent", "sub_name")
+ ev.SetTriggerN(trigger_n)
+ # block = bytes(r'raw_data_string')
+ # ev.AddBlock(0, block)
+ # print ev
+ # Mengqing:
+ datastr = "raw_data_string"
+ block = bytes(datastr, "utf-8")
+ ev.AddBlock(0, block)
+ # print(ev)
+
+ self.SendEvent(ev)
+ trigger_n += 1
+ time.sleep(1)
+ EUDAQ_INFO("End of RunLoop in TLUPyProducer")
+
+
+if __name__ == "__main__":
+ myproducer = TLUPyProducer("AIDA_TLU", "tcp://localhost:44000")
+ print(
+ "connecting to runcontrol in localhost:44000",
+ )
+ myproducer.Connect()
+ time.sleep(2)
+ while myproducer.IsConnected():
+ time.sleep(1)
diff --git a/TLU_v1e/__init__.py b/aidatlu/__init__.py
similarity index 100%
rename from TLU_v1e/__init__.py
rename to aidatlu/__init__.py
diff --git a/aidatlu/aidatlu_run.py b/aidatlu/aidatlu_run.py
new file mode 100644
index 0000000..97800f7
--- /dev/null
+++ b/aidatlu/aidatlu_run.py
@@ -0,0 +1,56 @@
+from main.tlu import AidaTLU
+import uhal
+
+
+class AIDATLU:
+ def __init__(self, config_path, clock_path):
+ print(" ---------------------------------------")
+ print(" _ ___ ___ _ _____ _ _ _ ")
+ print(" /_\ |_ _| \ /_\ |_ _| | | | | |")
+ print(" / _ \ | || |) / _ \ | | | |_| |_| |")
+ print(" /_/ \_\___|___/_/ \_\ |_| |____\___/ \n")
+ print(" ---------------------------------------")
+ print("tlu.help()\n")
+
+ self.config_file = config_path
+ self.clock_file = clock_path
+ self.ready = False
+
+ def run(self):
+ if not self.ready:
+ print("TLU not configured, Run aborted")
+ else:
+ self.aidatlu.run()
+
+ def stop(self):
+ self.aidatlu.stop_run()
+
+ def configure(self):
+ self.ready = True
+ self.init()
+ self.aidatlu.configure()
+
+ def init(self):
+ self.aidatlu = AidaTLU(hw, self.config_file, self.clock_file)
+
+ def help(self):
+ print("tlu.configure()")
+ print("start run: tlu.run()")
+ print("stop run: ctr+c")
+ print("exit: ctr+d/exit()\n")
+ print("for access to the main tlu functions: tlu.aidatlu....")
+
+
+if __name__ == "__main__":
+ uhal.setLogLevelTo(uhal.LogLevel.NOTICE)
+ manager = uhal.ConnectionManager("file://./misc/aida_tlu_connection.xml")
+ hw = uhal.HwInterface(manager.getDevice("aida_tlu.controlhub"))
+
+ config_path = "tlu_configuration.yaml"
+ clock_path = "misc/aida_tlu_clk_config.txt"
+
+ tlu = AIDATLU(config_path, clock_path)
+
+ # Uncomment if you just want to use EUDET mode and just plug and play TLU.
+ # tlu.configure
+ # tlu.run
diff --git a/TLU_v1e/scripts/__init__.py b/aidatlu/hardware/__init__.py
similarity index 100%
rename from TLU_v1e/scripts/__init__.py
rename to aidatlu/hardware/__init__.py
diff --git a/aidatlu/hardware/clock_controller.py b/aidatlu/hardware/clock_controller.py
new file mode 100644
index 0000000..a4efa52
--- /dev/null
+++ b/aidatlu/hardware/clock_controller.py
@@ -0,0 +1,129 @@
+from aidatlu.hardware.i2c import I2CCore
+from aidatlu.hardware.ioexpander_controller import IOControl
+from aidatlu import logger
+
+
+class ClockControl(object):
+ """The control class for the Si5344 clock chip.
+ Main purpose is to read/write the clock configuration file to the chip.
+ """
+
+ def __init__(self, i2c: I2CCore, io_control: IOControl) -> None:
+ self.log = logger.setup_derived_logger("Clock Controller")
+ self.log.info("Initializing Clock Chip")
+ self.i2c = i2c
+ self.io_control = io_control
+
+ def get_device_version(self) -> int:
+ """Get Chip information.
+
+ Returns:
+ int: The Chip ID.
+ """
+ my_adress = 0x02
+ chip_id = 0x0
+ self._set_page(0)
+ for i in range(2):
+ nibble = self.i2c.read(self.i2c.modules["clk"], my_adress + i)
+ chip_id = ((nibble & 0xFF) << (i * 8)) | chip_id
+ return chip_id
+
+ def check_design_id(self, hex_str: bool = False) -> list:
+ """Checks the Chip ID. If the chip is correctly configured the list corresponds
+ to the data in the clock configuration file between the addresses 0x026B and 0x0272.
+
+ Args:
+ hex_str (bool): Returns the design ID as a list of hex strings. Defaults to False.
+
+ Returns:
+ list: List of the design ID contains 8 integers or hex strings.
+ """
+ reg_address = 0x026B
+ n_words = 8
+ words = []
+ for _ in range(n_words):
+ words.append(self.read_clock_register(reg_address))
+ reg_address += 1
+ if hex_str:
+ words = [hex(words[i]) for i in range(n_words)]
+ return words
+
+ def read_clock_register(self, address: int) -> int:
+ """Reads register of the clock chip.
+
+ Args:
+ address (int): Address of the register.
+
+ Returns:
+ int: Integer from the register address.
+ """
+ address = address & 0xFFFF
+ current_page = self._get_page()
+ required_page = (address & 0xFF00) >> 8
+ if current_page != required_page:
+ self._set_page(required_page)
+ return self.i2c.read(self.i2c.modules["clk"], address)
+
+ def write_clock_register(self, address: int, data: int) -> None:
+ """Write data in specific Clock Chip register.
+
+ Args:
+ address (int): Destination register.
+ data (int): Data to be written in address.
+ """
+ address = address & 0xFFFF
+ current_page = self._get_page()
+ required_page = (address & 0xFF00) >> 8
+ if current_page != required_page:
+ self._set_page(required_page)
+
+ self.i2c.write(self.i2c.modules["clk"], address, data)
+
+ def parse_clock_conf(self, file_path: str) -> list:
+ """reads the clock config file and returns a panda dataframe with two rows Adress and Data
+ The configuration file is produced by Clockbuilder Pro (Silicon Labs).
+
+ Args:
+ file_path (str): File path to the configuration file.
+
+ Returns:
+ list: 2-dim. list, consisting of the address and data values.
+ """
+ with open(file_path, newline="") as clk_conf:
+ contents = clk_conf.read().splitlines()
+ contents = [row.split(",") for row in contents[10:]]
+ return contents
+
+ def write_clock_conf(self, file_path: str) -> None:
+ """Writes clock configuration consecutivly in register. This takes a few seconds.
+
+ Args:
+ file_path (str): File path to the clock configuration file.
+ """
+ clock_conf = self.parse_clock_conf(file_path)
+ self.log.info("Writing clock configuration")
+ self.io_control.all_on("r")
+ for index, row in enumerate(clock_conf):
+ self.write_clock_register(int(row[0], 16), int(row[1], 16))
+ # This is just fancy, show progress of clock configuration with LEDs.
+ if index % 10 == 0 and int((index / len(clock_conf) * 10 + 1)) != 5:
+ self.io_control.switch_led(int((index / len(clock_conf) * 10 + 1)), "b")
+
+ self.log.success("Done writing clock configuration ")
+ self.io_control.all_off()
+
+ def _set_page(self, page: int) -> None:
+ """Configures chip to perform operations on specific address page.
+
+ Args:
+ page (int): Address page.
+ """
+ self.i2c.write(self.i2c.modules["clk"], 0x01, page)
+
+ def _get_page(self) -> int:
+ """Get the current address page.
+
+ Returns:
+ int: Current address page
+ """
+ return self.i2c.read(self.i2c.modules["clk"], 0x01)
diff --git a/aidatlu/hardware/dac_controller.py b/aidatlu/hardware/dac_controller.py
new file mode 100644
index 0000000..ec4f6aa
--- /dev/null
+++ b/aidatlu/hardware/dac_controller.py
@@ -0,0 +1,172 @@
+from aidatlu.hardware.i2c import I2CCore
+from aidatlu import logger
+
+
+class DacControl(object):
+ """Control class for the three AD5665R. One controls the PMT control power (pwr_dac).
+ Two set the trigger input thresholds (dac_1, dac_2).
+ Each AD5665R has four parallel outputs.
+ """
+
+ def __init__(self, i2c: I2CCore, int_ref: bool = False) -> None:
+ self.log = logger.setup_derived_logger(__class__.__name__)
+
+ self.log.info("Initializing DAC Control")
+ self.i2c = i2c
+
+ self._set_dac_reference(int_ref, 0)
+ self._set_dac_reference(int_ref, 1)
+ self._set_dac_reference(int_ref, 2)
+
+ def set_threshold(
+ self, trigger_channel: int, threshold_voltage: float, ref_v: float = 1.3
+ ) -> None:
+ """Sets the Threshold voltage for the trigger input channel. Use channel = 7 to set threshold for all channels.
+
+ Args:
+ trigger_channel (int): Trigger input channel. From 1 to 7, where 7 controlls all input channels.
+ threshold_voltage (float): Threshold voltage in volt.
+ ref_v (float): Reference voltage of the DAC. Defaults to the external reference voltage 1.3 V.
+ """
+
+ if threshold_voltage > ref_v:
+ self.log.warning(
+ "Threshold larger than %s V is not supported, Threshold will default to %s V "
+ % (ref_v, ref_v)
+ )
+ threshold_voltage = ref_v
+ if threshold_voltage < -ref_v:
+ self.log.warning(
+ "Threshold smaller than %s V is not supported, Threshold will default to %s V "
+ % (-ref_v, -ref_v)
+ )
+ threshold_voltage = -ref_v
+ if trigger_channel < 1 or trigger_channel > 7:
+ raise ValueError(
+ "Invalid trigger input channel. Channel has to be between 1 and 6. Or use channel = 7 for all channels."
+ )
+
+ channel = trigger_channel - 1 # shift channel number by 1
+ # calculates the DAC value for the threshold DAC
+ v_dac = (threshold_voltage + ref_v) / 2
+ dac_value = int(0xFFFF * v_dac / ref_v)
+
+ # Sets threshold for the different channels. The different handling of the channels comes from the weird connections of the ADC.
+ if channel == 6:
+ self._set_dac_value(channel + 1, dac_value, 1)
+ self._set_dac_value(channel + 1, dac_value, 2)
+ # The DAC channels are connected in reverse order. The first two channels sit on DAC 1 in reverse order.
+ if channel < 2:
+ self._set_dac_value(1 - channel, dac_value, 1)
+ # The last 4 channels sit on DAC 2 in reverse order.
+ if channel > 1 and channel < 6:
+ self._set_dac_value(3 - (channel - 2), dac_value, 2)
+ self.log.info(
+ "Threshold of input %s set to %s V" % (trigger_channel, threshold_voltage)
+ )
+
+ def set_voltage(self, pmt_channel: int, voltage: float) -> None:
+ """Sets given PMT DAC to given output voltage.
+
+ Args:
+ pmt_channel (int): DAC channel for the PMT from 1 to 5, where channel 5 sets the voltage of all PMT channels.
+ voltage (float): DAC output voltage
+ """
+
+ if pmt_channel < 1 or pmt_channel > 5:
+ raise ValueError("PMT Channel has to be between 1 and 5")
+
+ if voltage < 0:
+ self.log.warning(
+ "A Voltage value smaller than 0 is not supported, Voltage will default to 0"
+ )
+ voltage = 0
+
+ if voltage > 1:
+ self.log.warning(
+ "A Voltage value higher than 1 is not supported, Voltage will default to 1"
+ )
+ voltage = 1
+
+ # Channel - PMT map [channel 2 -> PMT 4, channel 0 -> PMT 3, channel 1 -> PMT 2, channel 3 -> PMT 1]
+ if pmt_channel == 1:
+ channel_map = 3
+ if pmt_channel == 2:
+ channel_map = 1
+ if pmt_channel == 3:
+ channel_map = 0
+ if pmt_channel == 4:
+ channel_map = 2
+
+ if pmt_channel == 5:
+ self._set_all_voltage(voltage)
+ else:
+ # 0xFFFF is max DAC value
+ self._set_dac_value(channel_map, int(voltage * 0xFFFF))
+ self.log.info("PMT channel %s set to %s V" % (pmt_channel, voltage))
+
+ def _set_all_voltage(self, voltages: float) -> None:
+ """Sets the same Voltage for all PMT DACs.
+
+ Args:
+ voltages (float): DAC voltages in volts.
+ """
+ for channel in range(4):
+ self.set_voltage(channel + 1, voltages)
+
+ def _set_dac_reference(self, internal: bool = False, dac: int = 0) -> None:
+ """Choose internal or external DAC reference
+
+ Args:
+ internal (bool, optional): Defaults to False.
+ dac (int): 0 is the power dac, 1 and 2 are DAC 1 and DAC 2 for the thresholds. Defaults to 0.
+ """
+ # There is a factor 2 in the output voltage between internal and external DAC reference. In general internal reference is a factor of 2 larger!
+ if internal:
+ chr = [0x00, 0x01]
+ else:
+ chr = [0x00, 0x00]
+
+ if dac == 0:
+ self.i2c.write_array(self.i2c.modules["pwr_dac"], 0x38, chr)
+ if dac == 1:
+ self.i2c.write_array(self.i2c.modules["dac_1"], 0x38, chr)
+ if dac == 2:
+ self.i2c.write_array(self.i2c.modules["dac_2"], 0x38, chr)
+ self.log.info(
+ "Set %s DAC reference of DAC %s"
+ % (("internal" if internal else "external"), dac)
+ )
+
+ def _set_dac_value(self, channel: int, value: int, dac: int = 0) -> None:
+ """Set the output value of the power DAC
+
+ Args:
+ channel (int): DAC channel
+ value (int): DAC output value
+ dac (int): 0 is the power dac, 1 and 2 are DAC 1 and DAC 2 for the thresholds. Defaults to 0.
+ """
+ if channel < 0 or channel > 7:
+ raise ValueError("Channel has to be between 0 and 7")
+
+ if value < 0x0000:
+ self.log.warning(
+ "DAC value < 0x0000 not supported, value will default to 0x0000"
+ )
+ value = 0
+
+ if value > 0xFFFF:
+ self.log.warning(
+ "DAC value > 0xFFFF not supported, value will default to 0xFFFF"
+ )
+ value = 0xFFFF
+
+ chr = [(value >> 8) & 0xFF, value & 0xFF]
+ mem_addr = 0x18 + (channel & 0x7)
+
+ if dac == 0:
+ self.i2c.write_array(self.i2c.modules["pwr_dac"], mem_addr, chr)
+ if dac == 1:
+ self.i2c.write_array(self.i2c.modules["dac_1"], mem_addr, chr)
+ if dac == 2:
+ self.i2c.write_array(self.i2c.modules["dac_2"], mem_addr, chr)
diff --git a/aidatlu/hardware/dut_controller.py b/aidatlu/hardware/dut_controller.py
new file mode 100644
index 0000000..5105509
--- /dev/null
+++ b/aidatlu/hardware/dut_controller.py
@@ -0,0 +1,113 @@
+from aidatlu import logger
+from aidatlu.hardware.i2c import I2CCore
+
+
+class DUTLogic(object):
+ def __init__(self, i2c: I2CCore):
+ self.log = logger.setup_derived_logger(__class__.__name__)
+ self.i2c = i2c
+
+ def set_dut_mask(self, enable: int | str) -> None:
+ """Enables HDMI Outputs the enable is here an 4-bit WORD as integer or binary string to enable each HDMI channel.
+ With HDMI channel 1 = bit 0, channel 2 = bit 2, channel 3 = bit 3 and channel 4 = bit 4.
+ E.q. 0b0001 or '0001' enables HDMI channel 1, '0011' enables channel 1 and 2 and so on.
+
+ Args:
+ value (int | str): 4-bit WORD to enable the the HDMI outputs. Can be an integer or binary string.
+ """
+ if type(enable) == str:
+ enable = int(enable, 2)
+
+ if enable > 0b1111 or enable < 0b0000:
+ raise ValueError("Enable has to be between 0 and 15 ('1111')")
+
+ self.i2c.write_register("DUTInterfaces.DUTMaskW", enable & 0xF)
+ self.log.debug("DUT mask set to %s" % self.get_dut_mask())
+
+ def set_dut_mask_mode(self, mode: int | str) -> None:
+ """Sets the DUT interface mode. Mode consits of one 8-bit WORD or more specific 4 2-bit WORDs.
+ Each 2-bit WORD corresponds to one HDMI output and its mode.
+ With HDMI channel 1 = bit 0 and 1, channel 2 = bit 2 and 3, channel 3 = bit 4 and 5 and channel 4 = bit 6 and 7.
+ The mode is set with X0 = EUDET and X1 = AIDA. #TODO They mention the leading bit X can be used for future modes. Is this still up to date?
+ E.q. 0b00000011 sets HDMI channel 1 to AIDA mode and channels 2,3 and 4 to EUDET.
+
+ Args:
+ mode (int | str): 8-bit WORD to set the mode for each DUT. Can be an integer or binary string.
+ """
+
+ if type(mode) == str:
+ mode = int(mode, 2)
+
+ if mode > 0b11111111 or mode < 0b00000000:
+ raise ValueError("Mode has to be between 0 and 256 ('100000000').")
+
+ self.i2c.write_register("DUTInterfaces.DUTInterfaceModeW", mode)
+ self.log.debug("DUT mask mode is set to %s" % self.get_dut_mask_mode())
+
+ def set_dut_mask_mode_modifier(self, value: int) -> None:
+ """#TODO Only affects the EUDET mode of operation, looks like some special EUDET configuration.
+
+ Args:
+ value (int): _description_ #TODO
+ """
+ self.i2c.write_register("DUTInterfaces.DUTInterfaceModeModifierW", value)
+ self.log.debug(
+ "DUT mask mode modifier is set to %s" % self.get_dut_mask_mode_modifier()
+ )
+
+ def set_dut_ignore_busy(self, channels: int | str) -> None:
+ """If set the TLU ignores the BUSY signal from a DUT in AIDA mode.
+ Channels consits of a 4-bit WORD describing the DUT interfaces.
+ With DUT interface 1 = bit 0, interface 2 = bit 1, interface 3 = bit 2 and interface 4 = bit 3.
+ #TODO not sure if this is true here. No answers in documentation.
+
+ Args:
+ channels (int | str): _description_#TODO
+ """
+ if type(channels) == str:
+ channels = int(channels, 2)
+
+ if channels > 0b1111 or channels < 0b0000:
+ raise ValueError("Channels has to be between 0 and 16 ('10000').")
+
+ self.i2c.write_register("DUTInterfaces.IgnoreDUTBusyW", channels)
+ self.log.debug("DUT ignore busy is set to %s" % self.get_dut_ignore_busy())
+
+ def get_dut_mask(self) -> int:
+ """Reads the contend in the register 'DUTMaskR'.
+
+ Returns:
+ int: Integer content of the register.
+ """
+ return self.i2c.read_register("DUTInterfaces.DUTMaskR")
+
+ def get_dut_mask_mode(self) -> int:
+ """Reads the contend in the register 'DUTInterfaceModeR'.
+
+ Returns:
+ int: Integer content of the register.
+ """
+ return self.i2c.read_register("DUTInterfaces.DUTInterfaceModeR")
+
+ def get_dut_mask_mode_modifier(self) -> int:
+ """Reads the content in the register 'DUTInterfaceModeModifierR'.
+
+ Returns:
+ int: Integer content of the register.
+ """
+ return self.i2c.read_register("DUTInterfaces.DUTInterfaceModeModifierR")
+
+ def get_dut_ignore_busy(self) -> int:
+ """Reads the content in the register 'IgnoreDUTBusyR'.
+
+ Returns:
+ int: Integer content of the register.
+ """
+ return self.i2c.read_register("DUTInterfaces.IgnoreDUTBusyR")
+
+ def set_dut_ignore_shutter(self, value: int) -> None:
+ self.i2c.write_register("DUTInterfaces.IgnoreShutterVetoW", value)
+ self.log.debug("DUT ignore shutter set to %s" % self.get_dut_ignore_shutter())
+
+ def get_dut_ignore_shutter(self):
+ return self.i2c.read_register("DUTInterfaces.IgnoreShutterVetoR")
diff --git a/aidatlu/i2c.py b/aidatlu/hardware/i2c.py
similarity index 73%
rename from aidatlu/i2c.py
rename to aidatlu/hardware/i2c.py
index 19008e7..29c3a0e 100644
--- a/aidatlu/i2c.py
+++ b/aidatlu/hardware/i2c.py
@@ -1,7 +1,6 @@
import time
from math import ceil
-
-import logger
+from aidatlu import logger
i2c_addr = {
"core": 0x21,
@@ -31,8 +30,8 @@ def init(self):
self.set_i2c_control(0x80)
self.write(i2c_addr["core"], 0x01, 0x7F)
- if self.read(i2c_addr["core"], 0x01) & 0x80 != 0:
- self.log.warn(
+ if self.read(i2c_addr["core"], 0x01) & 0x80 != 0x80:
+ self.log.warning(
"Enabling Enclustra I2C bus might have failed. This could prevent from talking to the I2C slaves on the TLU."
)
@@ -63,8 +62,8 @@ def init(self):
def write_register(self, register: str, value: int) -> None:
"""
- register: str Name of node in address file
- value: int Value to be written
+ register: str Name of node in address file
+ value: int Value to be written
"""
if type(value) != int:
raise TypeError("Value must be integer")
@@ -76,7 +75,7 @@ def write_register(self, register: str, value: int) -> None:
def read_register(self, register: str) -> int:
"""
- register: str Name of node in address file
+ register: str Name of node in address file
"""
try:
ret = self.i2c_hw.getNode(register).read()
@@ -102,8 +101,8 @@ def set_i2c_command(self, value: int):
def set_i2c_tx(self, value: int):
self.write_register("i2c_master.i2c_rxtx", value & 0xFF)
- def is_done(self):
- return (self.get_i2c_status() >> 1) & 0x1
+ def is_done(self) -> bool:
+ return bool((self.get_i2c_status() >> 1) & 0x1)
def set_i2c_clock_prescale(self, value: int):
self.write_register("i2c_master.i2c_pre_lo", value & 0xFF)
@@ -126,6 +125,9 @@ def write(self, device_addr: int, mem_addr: int, value: int) -> None:
self.set_i2c_command(0x10)
self.set_i2c_tx(value & 0xFF)
self.set_i2c_command(0x50)
+ self._compare_value_read_write(
+ value, self.read(device_addr, mem_addr), device_addr
+ )
def read(self, device_addr: int, mem_addr: int) -> int:
self.set_i2c_tx((device_addr << 1) | 0x0)
@@ -140,3 +142,33 @@ def read(self, device_addr: int, mem_addr: int) -> int:
return self.read_register("i2c_master.i2c_rxtx")
+ def write_array(self, device_addr: int, mem_addr: int, values: list) -> None:
+ self.set_i2c_tx((device_addr << 1) | 0x0)
+ self.set_i2c_command(0x90)
+
+ self.set_i2c_tx(mem_addr)
+ self.set_i2c_command(0x10)
+
+ for i in range(len(values) - 1):
+ if i > 0xFF:
+ n_bytes_to_write = ceil(len(hex(i)[2:] / 2))
+ for byte in range(
+ 8 * (n_bytes_to_write - 1), 0, -8
+ ): # funky magic to write byte by byte
+ to_write = (i & (0xFF << byte)) >> byte
+ self.set_i2c_tx(to_write)
+ self.set_i2c_command(0x10)
+ self.set_i2c_tx(values[i] & 0xFF)
+ self.set_i2c_command(0x10)
+
+ self.set_i2c_tx(values[-1] & 0xFF)
+ self.set_i2c_command(0x50)
+
+ def _compare_value_read_write(self, written: int, read: int, function: str) -> None:
+ if written != read:
+ self.log.warning(
+ "Mismatch in register function %s. written value %s, recieved value: %s."
+ % (function, written, read)
+ )
+ else:
+ pass
diff --git a/aidatlu/hardware/ioexpander_controller.py b/aidatlu/hardware/ioexpander_controller.py
new file mode 100644
index 0000000..4a8e042
--- /dev/null
+++ b/aidatlu/hardware/ioexpander_controller.py
@@ -0,0 +1,463 @@
+from aidatlu import logger
+from aidatlu.hardware.i2c import I2CCore
+from aidatlu.hardware.utils import _set_bit
+import time
+
+
+class IOControl(object):
+ """Main class for the control of the IO expander PCA9539PW.
+ Four I/O expanders are in use, two for the 11 front panel LEDs. and two
+ for the HDMI DUT interfaces.
+ """
+
+ def __init__(self, i2c: I2CCore) -> None:
+ self.log = logger.setup_derived_logger(__class__.__name__)
+
+ self.log.info("Initializing IO expander")
+ self.i2c = i2c
+
+ self.init_led_expander()
+ self.init_output_expander()
+
+ def init_led_expander(self) -> None:
+ """Initialize LED expanders"""
+ self._set_ioexpander_polarity(1, exp_id=1, cmd_byte=4, polarity=False)
+ self._set_ioexpander_direction(1, exp_id=1, cmd_byte=6, direction="output")
+ self._set_ioexpander_output(1, exp_id=1, cmd_byte=2, value=0xFF)
+
+ self._set_ioexpander_polarity(1, exp_id=1, cmd_byte=5, polarity=False)
+ self._set_ioexpander_direction(1, exp_id=1, cmd_byte=7, direction="output")
+ self._set_ioexpander_output(1, exp_id=1, cmd_byte=3, value=0xFF)
+
+ self._set_ioexpander_polarity(1, exp_id=2, cmd_byte=4, polarity=False)
+ self._set_ioexpander_direction(1, exp_id=2, cmd_byte=6, direction="output")
+ self._set_ioexpander_output(1, exp_id=2, cmd_byte=2, value=0xFF)
+
+ self._set_ioexpander_polarity(1, exp_id=2, cmd_byte=5, polarity=False)
+ self._set_ioexpander_direction(1, exp_id=2, cmd_byte=7, direction="output")
+ self._set_ioexpander_output(1, exp_id=2, cmd_byte=3, value=0xFF)
+
+ def init_output_expander(self) -> None:
+ """Initialize output expanders"""
+ self._set_ioexpander_polarity(2, exp_id=1, cmd_byte=4, polarity=False)
+ self._set_ioexpander_direction(2, exp_id=1, cmd_byte=6, direction="output")
+ self._set_ioexpander_output(2, exp_id=1, cmd_byte=2, value=0xFF)
+
+ self._set_ioexpander_polarity(2, exp_id=1, cmd_byte=5, polarity=False)
+ self._set_ioexpander_direction(2, exp_id=1, cmd_byte=7, direction="output")
+ self._set_ioexpander_output(2, exp_id=1, cmd_byte=3, value=0xFF)
+
+ self._set_ioexpander_polarity(2, exp_id=2, cmd_byte=4, polarity=False)
+ self._set_ioexpander_direction(2, exp_id=2, cmd_byte=6, direction="output")
+ self._set_ioexpander_output(2, exp_id=2, cmd_byte=2, value=0x00)
+
+ self._set_ioexpander_polarity(2, exp_id=2, cmd_byte=5, polarity=False)
+ self._set_ioexpander_direction(2, exp_id=2, cmd_byte=7, direction="output")
+ self._set_ioexpander_output(2, exp_id=2, cmd_byte=3, value=0xB0)
+
+ """ LED Control """
+
+ def test_leds(self, single=True) -> None:
+ """Test the 11 LEDs
+
+ Args:
+ single (bool, optional): Test all possible RGB combinations for all LEDs. Defaults to True.
+ """
+ self.log.info("Testing LEDs colors")
+ if single:
+ for color in [
+ [0, 1, 1],
+ [1, 0, 1],
+ [1, 1, 0],
+ [1, 0, 0],
+ [0, 1, 0],
+ [0, 0, 1],
+ [0, 0, 0],
+ ]:
+ for i in range(11):
+ if i + 1 == 5:
+ pass
+ else:
+ self._set_led(i + 1, color)
+ time.sleep(0.1)
+ self.all_off()
+ time.sleep(0.05)
+ for color in [[0, 0, 1], [0, 1, 1], [1, 0, 1]]:
+ self._set_led(5, color)
+ time.sleep(0.15)
+ self.all_off()
+ time.sleep(0.1)
+
+ else:
+ for color in ["w", "r", "g", "b"]:
+ self.log.info("Testing LEDs color: %s" % color)
+
+ self.all_on(color)
+ time.sleep(1)
+ self.all_off()
+ time.sleep(1)
+
+ def all_on(self, color: str = "w") -> None:
+ """Set all LEDs to same color
+
+ Args:
+ color (str, optional): Color code [white: "w", red: "r", green: "g", blue: "b"] Defaults to "w".
+ """
+ if color not in ["w", "r", "g", "b"]:
+ raise ValueError("%s color not supported" % color)
+
+ if color == "w":
+ self._set_ioexpander_output(io_exp=1, exp_id=1, cmd_byte=2, value=0x0)
+ self._set_ioexpander_output(io_exp=1, exp_id=1, cmd_byte=3, value=0x0)
+ self._set_ioexpander_output(io_exp=1, exp_id=2, cmd_byte=2, value=0x0)
+ self._set_ioexpander_output(io_exp=1, exp_id=2, cmd_byte=3, value=0x0)
+
+ if color == "r":
+ self._set_ioexpander_output(io_exp=1, exp_id=1, cmd_byte=2, value=0xB5)
+ self._set_ioexpander_output(io_exp=1, exp_id=1, cmd_byte=3, value=0x6D)
+ self._set_ioexpander_output(io_exp=1, exp_id=2, cmd_byte=2, value=0xDB)
+ self._set_ioexpander_output(io_exp=1, exp_id=2, cmd_byte=3, value=0xB6)
+
+ if color == "g":
+ self._set_ioexpander_output(io_exp=1, exp_id=1, cmd_byte=2, value=0xDA)
+ self._set_ioexpander_output(io_exp=1, exp_id=1, cmd_byte=3, value=0xB6)
+ self._set_ioexpander_output(io_exp=1, exp_id=2, cmd_byte=2, value=0x6D)
+ self._set_ioexpander_output(io_exp=1, exp_id=2, cmd_byte=3, value=0xDB)
+
+ if color == "b":
+ self._set_ioexpander_output(io_exp=1, exp_id=1, cmd_byte=2, value=0x6F)
+ self._set_ioexpander_output(io_exp=1, exp_id=1, cmd_byte=3, value=0xDB)
+ self._set_ioexpander_output(io_exp=1, exp_id=2, cmd_byte=2, value=0xB6)
+ self._set_ioexpander_output(io_exp=1, exp_id=2, cmd_byte=3, value=0x6D)
+
+ def all_off(self) -> None:
+ """Turn off all LEDs"""
+ self._set_ioexpander_output(io_exp=1, exp_id=1, cmd_byte=2, value=0xFF)
+ self._set_ioexpander_output(io_exp=1, exp_id=1, cmd_byte=3, value=0xFF)
+ self._set_ioexpander_output(io_exp=1, exp_id=2, cmd_byte=2, value=0xFF)
+ self._set_ioexpander_output(io_exp=1, exp_id=2, cmd_byte=3, value=0xFF)
+
+ def switch_led(self, led_id: int, color: str = "off") -> None:
+ """changes LED with led_id to specific color
+
+ Args:
+ led_id (int): ID for the 11 LEDs, led_id has to be between 1 and 11
+ color (str, optional): Color code [white: "w", red: "r", green: "g", blue: "b", off: "off"]
+ for Clock LED only [red: "r", green: "g", off: "off"].
+ Defaults to "off".
+ """
+
+ if led_id == 5 and color not in ["r", "g", "off"]:
+ raise ValueError("%s color not supported for Clock LED" % color)
+
+ elif color not in ["w", "r", "g", "b", "off"]:
+ raise ValueError("%s color not supported for LED" % color)
+
+ # Clock LED has only two LEDs
+ if led_id == 5:
+ if color == "r":
+ rgb = [0, 1, 1]
+ if color == "g":
+ rgb = [1, 0, 1]
+ if color == "off":
+ rgb = [1, 1, 1]
+
+ else:
+ if color == "w":
+ rgb = [0, 0, 0]
+ if color == "r":
+ rgb = [0, 1, 1]
+ if color == "g":
+ rgb = [1, 0, 1]
+ if color == "b":
+ rgb = [1, 0, 0]
+ if color == "off":
+ rgb = [1, 1, 1]
+
+ self._set_led(led_id, rgb)
+
+ def _set_led(self, led_id: int, rgb: list) -> None:
+ """sets led to a rgb value
+
+ Args:
+ led_id (int): Led id for the 11 LED, led_ id has to be between 1 and 11
+ rgb (list): rgb value for the LED e.q. [0,0,0]
+
+ """
+ if led_id < 1 or led_id > 11:
+ raise ValueError("LED ID has to be between 1 and 11")
+
+ # indicator map for LED positions notice the -1 for the clock led #TODO should this be global??
+ indicator = [
+ [30, 29, 31],
+ [27, 26, 28],
+ [24, 23, 25],
+ [21, 20, 22],
+ [18, 17, -1],
+ [15, 14, 16],
+ [12, 11, 13],
+ [9, 8, 10],
+ [6, 5, 7],
+ [3, 2, 4],
+ [1, 0, 19],
+ ]
+
+ status_now = [] # status of all ioexpander now
+ status_next = [] # status of all ioexpander next
+ status_now.append(0xFF & self._get_ioexpander_output(1, 1, 2))
+ status_now.append(0xFF & self._get_ioexpander_output(1, 1, 3))
+ status_now.append(0xFF & self._get_ioexpander_output(1, 2, 2))
+ status_now.append(0xFF & self._get_ioexpander_output(1, 2, 3))
+
+ word = 0x00000000
+ word = word | status_now[0]
+ word = word | (status_now[1] << 8)
+ word = word | (status_now[2] << 16)
+ word = word | (status_now[3] << 24)
+
+ for index in range(3):
+ if (
+ led_id == 5
+ ): # for clock led not all colors are allowed on clock [1,0,1] is green [0,1,1] is red the og eudaq indicator map produces here an error
+ # TODO some colors also switch on LED 11
+ word = _set_bit(word, [18, 17, 19][index], rgb[index])
+ else:
+ word = _set_bit(word, indicator[led_id - 1][index], rgb[index])
+
+ status_next.append(0xFF & word)
+ status_next.append(0xFF & (word >> 8))
+ status_next.append(0xFF & (word >> 16))
+ status_next.append(0xFF & (word >> 24))
+
+ if status_now[0] != status_next[0]:
+ self._set_ioexpander_output(1, 1, 2, status_next[0])
+
+ if status_now[1] != status_next[1]:
+ self._set_ioexpander_output(1, 1, 3, status_next[1])
+
+ if status_now[2] != status_next[2]:
+ self._set_ioexpander_output(1, 2, 2, status_next[2])
+
+ if status_now[3] != status_next[3]:
+ self._set_ioexpander_output(1, 2, 3, status_next[3])
+
+ """ Output Control """
+
+ def configure_hdmi(self, hdmi_channel: int, enable: int | str) -> None:
+ """This enables the pins of one HDMI channel as input (0) or output (1).
+ Enable is a 4-bit WORD for each pin as integer or binary string. With CONT = bit 0, SPARE = bit 1, TRIG = bit 2 and BUSY = bit 3.
+ E.q. 0b0111 or '0111' sets CONT, SPARE and TRIGGER as outputs and BUSY as input. '1100' sets CONT and SPARE as input and BUSY and TRIG as output.
+ The clock runs with the seperate function: clock_hdmi_output.
+
+ Args:
+ hdmi_num (int): HDMI channels from 1 to 4
+ enable (int | str, optional): 4-bit WORD to enable the 4 pins on the HDMI output. Can be an integer or binary string.
+
+ """
+ # TODO use DUT Interface or HDMI channel?
+ if hdmi_channel < 1 or hdmi_channel > 4:
+ raise ValueError("HDMI channel should be between 1 and 4")
+
+ if type(enable) == str:
+ enable = int(enable, 2)
+
+ if enable > 0b1111 or enable < 0b0000:
+ raise ValueError("Enable has to be between 0 and 16 ('10000').")
+
+ expander_id = 1
+
+ # TODO what is the difference between nibble and bank and address?
+ hdmi_channel = hdmi_channel - 1 # shift channel
+ bank = (
+ int(hdmi_channel / 2) + 2
+ ) # DUT0 and DUT1 are on bank0. DUT2 and DUT 3 are on bank 1. Shift of +2 due to the command bytes.
+ nibble = (
+ hdmi_channel % 2
+ ) # DUT0 and DUT2 are on nibble 0. DUT1 and DUT3 are on nibble 1.
+
+ # TODO what is happening here
+ old_status = self._get_ioexpander_output(2, expander_id, bank)
+ new_nibble = (enable & 0xF) << 4 * nibble
+ mask = 0xF << 4 * nibble
+ new_status = (old_status & (~mask)) | (new_nibble & mask)
+
+ self._set_ioexpander_output(2, expander_id, bank, new_status)
+ self.log.debug("HDMI Channel %i set to %s" % (hdmi_channel + 1, str(enable)))
+
+ def clock_hdmi_output(self, hdmi_channel: int, clock_source: str) -> None:
+ """Enables the Clock output for one HDMI channel.
+ Valid Clock sources are Si5453 clock chip 'chip' and FPGA 'fpga'.
+ #TODO does FPGA work?
+
+ Args:
+ hdmi_channel (int): HDMI channels from 1 to 4
+ clock_source (str): Clock source valid options are 'off', 'chip' and 'fpga'.
+ """
+ if clock_source not in ["off", "chip", "fpga"]:
+ raise ValueError("Clock source has to be 'off', 'chip' or 'fpga'")
+ if hdmi_channel < 1 or hdmi_channel > 4:
+ raise ValueError("HDMI channel should be between 1 and 4")
+
+ cmd_byte = 2
+ expander_id = 2
+
+ hdmi_channel = hdmi_channel - 1 # shift channel
+ mask_low = 1 << (hdmi_channel)
+ mask_high = 1 << (hdmi_channel + 4)
+ mask = mask_low | mask_high
+ old_status = self._get_ioexpander_output(2, expander_id, cmd_byte)
+
+ if clock_source == "off":
+ new_status = old_status & ~mask
+ elif clock_source == "chip":
+ new_status = (old_status | mask_high) & ~mask_low
+ elif clock_source == "fpga": # TODO nothing measurable here for now
+ new_status = (old_status | mask_low) & ~mask_high
+ else:
+ new_status = old_status
+ self._set_ioexpander_output(2, expander_id, cmd_byte, new_status)
+ self.log.info(
+ "Clock source of HDMI Channel %i set to %s."
+ % (hdmi_channel + 1, clock_source)
+ )
+
+ def clock_lemo_output(self, enable: bool = True) -> None:
+ """Enables the clock LEMO output. #TODO only with ~40MHz default clock
+
+ Args:
+ enable (bool, optional): Enable clock LEMO output. Defaults to True.
+ """
+
+ cmd_byte = 3 # this is bank+2 in EUDAQ
+ mask = 0x10
+ expander_id = 2
+
+ old_status = self._get_ioexpander_output(2, expander_id, cmd_byte) & 0xFF
+ new_status = old_status & (~mask) & 0xFF
+ if enable:
+ new_status = new_status | mask & 0xFF
+
+ self._set_ioexpander_output(2, expander_id, cmd_byte, new_status)
+ if enable:
+ self.switch_led(5, "g")
+ else:
+ self.switch_led(5, "off")
+ self.log.info("Clock LEMO output %s" % ("enabled" if enable else "disabled"))
+
+ """ General Expander Control """
+
+ def _set_ioexpander_polarity(
+ self, io_exp: int, exp_id: int, cmd_byte: int, polarity: bool = False
+ ) -> None:
+ """Set content of register 4 or 5 which determine polarity of ports.
+ A command byte of 4 or 5 determines the polarity of ports on the two different banks of the chip.
+ io_exp and exp_id control the 2 expander for the LEDs and 2 for the output control.
+
+ Args:
+ io_exp (int): Expander (1 or 2). The LED expander on 1 the output expander on 2.
+ exp_id (int): ID of the Expander (1 or 2))
+ cmd_byte (int): The Command byte is used as a pointer to a specific register see datasheet PC9539.
+ polarity (bool, optional): False (0) = normal, True (1) = inverted. Defaults to False.
+ """
+ if io_exp not in [1, 2]:
+ raise ValueError("Expander should be 1 or 2")
+ if cmd_byte not in [4, 5]:
+ raise ValueError("Command byte should be 4 or 5")
+ if exp_id not in [1, 2]:
+ raise ValueError("Expander ID should be 1 or 2")
+
+ if io_exp == 1:
+ exp = "led_expander"
+ else:
+ exp = "expander"
+
+ self.i2c.write(self.i2c.modules["%s_%.1s" % (exp, exp_id)], cmd_byte, polarity)
+
+ def _set_ioexpander_direction(
+ self, io_exp: int, exp_id: int, cmd_byte: int, direction: str = "input"
+ ) -> None:
+ """Set content of register 6 or 7 which determine direction of signal.
+ A command byte of 6 or 7 determines the direction of signal on the two different banks of the chip.
+ io_exp and exp_id control the 2 expander for the LEDs and 2 for the output control.
+
+ Args:
+ io_exp (int): Expander (1 or 2). The LED expander on 1 the output expander on 2.
+ exp (int): ID of Expander (1 or 2))
+ cmd_byte (int): The Command byte is used as a pointer to a specific register see datasheet PC9539.
+ direction (str, optional): "input or "output" direction of port. Defaults to "input".
+ """
+ if io_exp not in [1, 2]:
+ raise ValueError("Expander should be 1 or 2")
+ if cmd_byte not in [6, 7]:
+ raise ValueError("Command byte should be 6 or 7")
+ if direction not in ["input", "output"]:
+ raise ValueError('Direction parameter must be "input" or "output"')
+ if exp_id not in [1, 2]:
+ raise ValueError("Expander ID should be 1 or 2")
+
+ if io_exp == 1:
+ exp = "led_expander"
+ else:
+ exp = "expander"
+
+ self.i2c.write(
+ self.i2c.modules["%s_%.1s" % (exp, exp_id)],
+ cmd_byte,
+ 1 if direction == "input" else 0,
+ )
+
+ def _set_ioexpander_output(
+ self, io_exp: int, exp_id: int, cmd_byte: int, value: int
+ ) -> None:
+ """Set content of register 2 or 3 which determine signal if direction is output
+ A command byte of 2 or 3 reflects the outgoing logic levels of the output pins on the two different banks of the chip.
+ io_exp and exp_id control the 2 expander for the LEDs and 2 for the output control.
+
+ Args:
+ io_exp (int): Expander (1 or 2). The LED expander on 1 the output expander on 2.
+ exp (int): ID of Expander (1 or 2))
+ cmd_byte (int): The Command byte is used as a pointer to a specific register see datasheet PC9539.
+ value (int): 8 bit value for the output
+ """
+ if io_exp not in [1, 2]:
+ raise ValueError("Expander should be 1 or 2")
+ if cmd_byte not in [2, 3]:
+ raise ValueError("Command byte should be 2 or 3")
+ if exp_id not in [1, 2]:
+ raise ValueError("Expander ID should be 1 or 2")
+
+ if io_exp == 1:
+ exp = "led_expander"
+ else:
+ exp = "expander"
+
+ self.i2c.write(
+ self.i2c.modules["%s_%.1s" % (exp, exp_id)], cmd_byte, value & 0xFF
+ )
+
+ def _get_ioexpander_output(self, io_exp: int, exp_id: int, cmd_byte: int) -> int:
+ """Get content of register 2 or 3
+ A command byte of 2 or 3 reflects the outgoing logic levels of the output pins on the two different banks of the chip.
+ io_exp and exp_id control the 2 expander for the LEDs and 2 for the output control.
+
+ Args:
+ io_exp (int): Expander (1 or 2). The LED expander on 1 the output expander on 2.
+ exp_id (int): ID of Expander (1 or 2).
+ cmd_byte (int): The Command byte is used as a pointer to a specific register see datasheet PC9539.
+ Returns:
+ int: content of the ioexpander
+ """
+ if io_exp not in [1, 2]:
+ raise ValueError("Expander should be 1 or 2")
+ if cmd_byte not in [2, 3]:
+ raise ValueError("Command byte should be 2 or 3")
+ if exp_id not in [1, 2]:
+ raise ValueError("Expander ID should be 1 or 2")
+
+ if io_exp == 1:
+ exp = "led_expander"
+ else:
+ exp = "expander"
+
+ output = self.i2c.read(self.i2c.modules["%s_%.1s" % (exp, exp_id)], cmd_byte)
+ return output
diff --git a/aidatlu/hardware/trigger_controller.py b/aidatlu/hardware/trigger_controller.py
new file mode 100644
index 0000000..f5d4dfd
--- /dev/null
+++ b/aidatlu/hardware/trigger_controller.py
@@ -0,0 +1,180 @@
+from aidatlu.hardware.i2c import I2CCore
+from aidatlu.hardware.utils import _pack_bits
+from aidatlu import logger
+
+
+class TriggerLogic(object):
+ def __init__(self, i2c: I2CCore) -> None:
+ self.log = logger.setup_derived_logger(__class__.__name__)
+ self.i2c = i2c
+
+ """ Internal Trigger Generation """
+
+ def set_internal_trigger_frequency(self, frequency: int) -> None:
+ """Sets the internal trigger frequency.
+ The maximum allowed Frequency is 160 MHz.
+
+ Args:
+ frequency (int): Frequency in Hz
+ """
+ self.log.info("Set internal trigger frequency to: %i Hz" % frequency)
+ max_freq = 160000000
+
+ if frequency < 0:
+ raise ValueError("Frequency smaller 0 does not work")
+ if frequency > max_freq:
+ raise ValueError("Frequency larger %s Hz not supported" % max_freq)
+ if frequency == 0:
+ interval = frequency
+ else:
+ interval = int(
+ max_freq / frequency
+ ) # TODO here is a rounding error that comes from the interval calculations at ~10kHz.
+ self._set_internal_trigger_interval(interval)
+ new_freq = self.get_internal_trigger_frequency()
+ if new_freq != frequency:
+ self.log.warning(
+ "Frequency set to different value. Internal Trigger frequency: %i Hz"
+ % self.get_internal_trigger_frequency()
+ )
+
+ def get_internal_trigger_frequency(self) -> int:
+ """Reads the internal trigger frequency from the register.
+
+ Returns:
+ int: Frequency in Hz
+ """
+ max_freq = 160000000
+ interval = self.i2c.read_register("triggerLogic.InternalTriggerIntervalR")
+ if interval == 0:
+ freq = 0
+ else:
+ freq = int(
+ max_freq / interval
+ ) # TODO here is prob. a rounding error I should use a round function this would prob. prevent the warning at ~10kHz.
+ return freq
+
+ def _set_internal_trigger_interval(self, interval: int) -> None:
+ """Number of internal clock cycles to be used as period for the internal trigger generator.
+ The period for the internal trigger generator is reduced by 2 prob. in some hardware configuration.
+
+ Args:
+ interval (int): Number of internal clock cycles.
+ """
+ self.i2c.write_register("triggerLogic.InternalTriggerIntervalW", interval)
+
+ """ Trigger Logic """
+
+ def set_trigger_veto(self, veto: bool) -> None:
+ """Enables or disables new trigger. This can be used to reset the procession of new triggers.
+ Args:
+ veto (bool): Sets a veto to the trigger logic of the tlu.
+ """
+ if type(veto) != bool:
+ raise TypeError("Veto must be type bool")
+
+ self.i2c.write_register("triggerLogic.TriggerVetoW", int(veto))
+ self.log.info("Trigger Veto set to: %s" % self.get_trigger_veto())
+
+ def set_trigger_polarity(self, value: int) -> int:
+ """Sets if the TLU triggers on rising or falling edge.
+
+ Args:
+ value (int): 1 triggers on falling, 0 on rising. #TODO not tested
+
+ """
+ trigger_polarity = 0x3F & value
+ self.i2c.write_register("triggerInputs.InvertEdgeW", trigger_polarity)
+ self.log.info("Trigger on %s edge" % ("falling" if value == 1 else "rising"))
+
+ def set_trigger_mask(self, mask_high: int, mask_low: int) -> None:
+ """Sets the trigger logic. Each of the 64 possible combination is divided into two 32-bit words mask high and mask low.
+
+ Args:
+ mask_high (int): The most significant 32-bit word generated from the trigger configuration.
+ mask_low (int): The least significant 32-bit word generated from the trigger configuration.
+ """
+ self.i2c.write_register("triggerLogic.TriggerPattern_lowW", mask_low)
+ self.i2c.write_register("triggerLogic.TriggerPattern_highW", mask_high)
+ self.log.debug("Trigger mask: %s" % self.get_trigger_mask())
+
+ def get_trigger_mask(self) -> int:
+ """Retrieves the trigger logic words from the registers. The trigger pattern represents one of the 64 possible logic combinations."""
+ mask_low = self.i2c.read_register("triggerLogic.TriggerPattern_lowR")
+ mask_high = self.i2c.read_register("triggerLogic.TriggerPattern_highR")
+ trigger_pattern = (mask_high << 32) | mask_low
+ return trigger_pattern
+
+ def get_trigger_veto(self) -> bool:
+ """Reads the trigger veto from the register."""
+ veto_state = self.i2c.read_register("triggerLogic.TriggerVetoR")
+ return bool(veto_state)
+
+ def get_post_veto_trigger(self) -> int:
+ """Gets the number of triggers recorded in the TLU after the veto is applied"""
+ return self.i2c.read_register("triggerLogic.PostVetoTriggersR")
+
+ def get_pre_veto_trigger(self) -> int:
+ """Number of triggers recorded in the TLU before the veto is applied."""
+ return self.i2c.read_register("triggerLogic.PreVetoTriggersR")
+
+ def set_trigger_mask_from_full_word(self, value: int) -> None:
+ """Sets the trigger logic. Each of the 64 possible combination is divided into two 32-bit words mask high and mask low.
+
+ Args:
+ value (int): Sets trigger logic from trigger logic combination word.
+ """
+ mask_high = (value >> 32) & 0xFF
+ mask_low = value & 0xFF
+ self.i2c.write_register("triggerLogic.TriggerPattern_lowW", mask_low)
+ self.i2c.write_register("triggerLogic.TriggerPattern_highW", mask_high)
+ self.log.debug("Trigger mask: %s" % self.get_trigger_mask())
+
+ """ Trigger Pulse Length and Delay """
+
+ def set_pulse_stretch_pack(self, vector: list) -> None:
+ """Stretch word for trigger pulses. Each element of the input vector is stretched by N clock cycles.
+ The input vector should have 6 elements for the different inputs.
+ The vector is packed into a single word.
+
+ Args:
+ vector (list): A vector containing six integers. Each trigger input is stretched by the integer number of clock cycles.
+ """
+ packed = _pack_bits(vector)
+ self._set_pulse_stretch(packed)
+ self.log.debug("Pulse stretch is set to %s" % self.get_pulse_stretch_pack())
+
+ def set_pulse_delay_pack(self, vector: list) -> None:
+ """Delay word for trigger pulses. Each element of the input vector is delayed by N clock cycles.
+ The vector is packed into a single word.
+
+ Args:
+ vector (list): A vector containing six integers. Each trigger input is delayed by the integer number of clock cycles.
+ """
+ packed = _pack_bits(vector)
+ self._set_pulse_delay(packed)
+ self.log.debug("Pulse Delay is set to %s" % self.get_pulse_delay_pack())
+
+ def get_pulse_stretch_pack(self) -> int:
+ """Get packed word describing the input pulse stretch."""
+ return self.i2c.read_register("triggerLogic.PulseStretchR")
+
+ def get_pulse_delay_pack(self) -> int:
+ """Get packed word describing the input pulse stretch."""
+ return self.i2c.read_register("triggerLogic.PulseDelayR")
+
+ def _set_pulse_stretch(self, value: int) -> None:
+ """Writes the packed word into the pulse stretch register.
+
+ Args:
+ value (int): The input vector packed to a single integer.
+ """
+ self.i2c.write_register("triggerLogic.PulseStretchW", value)
+
+ def _set_pulse_delay(self, value: int) -> None:
+ """Writes the packed word into the pulse delay register.
+
+ Args:
+ value (int): The input vector packed to a single integer.
+ """
+ self.i2c.write_register("triggerLogic.PulseDelayW", value)
diff --git a/aidatlu/hardware/utils.py b/aidatlu/hardware/utils.py
new file mode 100644
index 0000000..88df13c
--- /dev/null
+++ b/aidatlu/hardware/utils.py
@@ -0,0 +1,51 @@
+def _set_bit(value: int, index: int, set: bool = True) -> int:
+ """sets bit at given index of given value to bool set
+
+ Args:
+ value (int): input value
+ index (int): index where to change bit
+ set (bool, optional): change bit to bool
+
+ Returns:
+ int: value with a set bit at index
+ """
+
+ if set:
+ return value | (1 << index)
+ else:
+ return value & ~(1 << index)
+
+
+def _pack_bits(vector: list) -> int:
+ """Pack Vector of bits using 5-bits for each element.
+
+ Args:
+ vector (list): Vector of bits with variable length.
+
+ Returns:
+ int: 32-bit word representation of the input vector.
+ """
+ packed_bits = 0
+ temp_int = 0
+ for channel in range(len(vector)):
+ temp_int = int(vector[channel]) << channel * 5
+ packed_bits = packed_bits | temp_int
+ return packed_bits
+
+
+from pathlib import Path
+
+
+def find_latest_file(path: str, index: str):
+ """Find latest file that includes a given subset of strings called index in directory.
+ Args:
+ path (str): Path to directory. For same directory as python script use for e.q. './target_dir'.
+ index (str): (Optional) Find if specific characters are in Pathfile
+ Returns:
+ path: Path to file in target Director. Use str(find_path(.)) to obtain path as string.
+ """
+ p = Path(path)
+ return max(
+ [x for x in p.iterdir() if x.is_file() and index in str(x)],
+ key=lambda item: item.stat().st_ctime,
+ )
diff --git a/aidatlu/led_controller.py b/aidatlu/led_controller.py
deleted file mode 100644
index 029f89a..0000000
--- a/aidatlu/led_controller.py
+++ /dev/null
@@ -1,104 +0,0 @@
-import logger
-from i2c import I2CCore, i2c_addr
-
-
-class LEDControl(object):
- def __init__(self, i2c: I2CCore, int_ref: bool = False) -> None:
- self.log = logger.setup_derived_logger("LED Controller")
- self.i2c = i2c
- self._set_dac_reference(int_ref)
- # TODO: WHY?!
- self._set_ioexpander_polarity(exp=1, addr=4, polarity=False)
- self._set_ioexpander_direction(exp=1, addr=6, direction="output")
- self._set_ioexpander_output(exp=1, addr=2, value=0xFF)
- self._set_ioexpander_polarity(exp=1, addr=5, polarity=False)
- self._set_ioexpander_direction(exp=1, addr=7, direction="output")
- self._set_ioexpander_output(exp=1, addr=3, value=0xFF)
- self._set_ioexpander_polarity(exp=2, addr=4, polarity=False)
- self._set_ioexpander_direction(exp=2, addr=6, direction="output")
- self._set_ioexpander_output(exp=2, addr=2, value=0xFF)
- self._set_ioexpander_polarity(exp=2, addr=5, polarity=False)
- self._set_ioexpander_direction(exp=2, addr=7, direction="output")
- self._set_ioexpander_output(exp=2, addr=3, value=0xFF)
-
- def test_leds(self) -> None:
- pass
-
- def all_on(self, color: str = "w") -> None:
- """Set all LEDs to same color
-
- Args:
- color (str, optional): Color code, currently only white (w) supported. Defaults to "w".
- """
- self._set_ioexpander_output(exp=1, addr=2, value=0x0)
- self._set_ioexpander_output(exp=1, addr=3, value=0x0)
- self._set_ioexpander_output(exp=2, addr=2, value=0x0)
- self._set_ioexpander_output(exp=2, addr=3, value=0x0)
-
- def all_off(self) -> None:
- """Turn off all LEDs
- """
- self._set_ioexpander_output(exp=1, addr=2, value=0xFF)
- self._set_ioexpander_output(exp=1, addr=3, value=0xFF)
- self._set_ioexpander_output(exp=2, addr=2, value=0xFF)
- self._set_ioexpander_output(exp=2, addr=3, value=0xFF)
-
- def _set_dac_reference(self, internal: bool = False) -> None:
- """Choose internal or external DAC reference
-
- Args:
- internal (bool, optional): Defaults to False.
- """
- if internal:
- self.i2c.write(self.i2c.modules["pwr_dac"], 0x38, 0x0001)
- else:
- self.i2c.write(self.i2c.modules["pwr_dac"], 0x38, 0x0001)
- self.log.info(
- "Set %s DAC reference for LEDs" % ("internal" if internal else "external")
- )
-
- def _set_ioexpander_polarity(
- self, exp: int, addr: int, polarity: bool = False
- ) -> None:
- """Set content of register 4 or 5 which determine polarity of ports
-
- Args:
- exp (int): ID of LED Expander (1 or 2))
- addr (int): # TODO, what is this?!
- polarity (bool, optional): False (0) = normal, True (1) = inverted. Defaults to False.
- """
- if addr not in [4, 5]:
- raise ValueError("Address should be 4 or 5")
- self.i2c.write(self.i2c.modules["led_expander_%.1s" % exp], addr, polarity)
-
- def _set_ioexpander_direction(
- self, exp: int, addr: int, direction: str = "input"
- ) -> None:
- """Set content of register 6 or 7 which determine direction of signal
-
- Args:
- exp (int): ID of LED Expander (1 or 2))
- addr (int): # TODO, what is this?!
- direction (str, optional): "input or "output" direction of port. Defaults to "input".
- """
- if addr not in [6, 7]:
- raise ValueError("Address should be 6 or 7")
- if direction not in ["input", "output"]:
- raise ValueError('Direction parameter must be "input" or "output"')
- self.i2c.write(
- self.i2c.modules["led_expander_%.1s" % exp],
- addr,
- 1 if direction == "input" else 0,
- )
-
- def _set_ioexpander_output(self, exp: int, addr: int, value: int) -> None:
- """Set content of register 2 or 3 which determine signal if direction is output
-
- Args:
- exp (int): ID of LED Expander (1 or 2))
- addr (int): # TODO, what is this?!
- value (int): 8 bit value for the output
- """
- if addr not in [2, 3]:
- raise ValueError("Address should be 6 or 7")
- self.i2c.write(self.i2c.modules["led_expander_%.1s" % exp], addr, value & 0xFF)
diff --git a/aidatlu/logger.py b/aidatlu/logger.py
index 1221b3e..9fe919f 100644
--- a/aidatlu/logger.py
+++ b/aidatlu/logger.py
@@ -1,8 +1,8 @@
import logging
-
import coloredlogs
+import argparse
-FORMAT = "%(asctime)s [%(name)-14s] - %(levelname)-7s %(message)s"
+FORMAT = "%(asctime)s [%(name)-18s] - %(levelname)-7s %(message)s"
def setup_main_logger(name="AidaTLU", level=logging.INFO):
diff --git a/packages/TLU_v1e/__init__.py b/aidatlu/main/__init__.py
similarity index 100%
rename from packages/TLU_v1e/__init__.py
rename to aidatlu/main/__init__.py
diff --git a/aidatlu/main/config_parser.py b/aidatlu/main/config_parser.py
new file mode 100644
index 0000000..8f3b869
--- /dev/null
+++ b/aidatlu/main/config_parser.py
@@ -0,0 +1,266 @@
+import yaml
+import logging
+from aidatlu import logger
+
+
+class TLUConfigure(object):
+ def __init__(self, TLU, io_control, config_path) -> None:
+ self.log = logger.setup_main_logger(__class__.__name__)
+
+ self.tlu = TLU
+ self.io_control = io_control
+
+ config_path = config_path
+ with open(config_path, "r") as file:
+ self.conf = yaml.full_load(file)
+
+ def configure(self) -> None:
+ """Loads configuration file and configures the TLU accordingly."""
+ self.conf_dut()
+ self.conf_trigger_inputs()
+ self.conf_trigger_logic()
+ self.tlu.io_controller.clock_lemo_output(
+ self.conf["clock_lemo"]["enable_clock_lemo_output"]
+ )
+ [
+ self.tlu.dac_controller.set_voltage(
+ i + 1, self.conf["pmt_control"]["pmt_%s" % (i + 1)]
+ )
+ for i in range(len(self.conf["pmt_control"]))
+ ]
+ self.tlu.set_enable_record_data(1)
+ self.log.success("TLU configured")
+
+ def get_configuration_table(self) -> list:
+ """Creates the configuration list to save in the data files
+
+ Returns:
+ list: configuration list
+ """
+ conf = [
+ (
+ "internal_trigger_rate",
+ self.conf["internal_trigger"]["internal_trigger_rate"],
+ ),
+ ("DUT_1", self.conf["dut_module"]["dut_1"]["mode"]),
+ ("DUT_2", self.conf["dut_module"]["dut_2"]["mode"]),
+ ("DUT_3", self.conf["dut_module"]["dut_3"]["mode"]),
+ ("DUT_4", self.conf["dut_module"]["dut_4"]["mode"]),
+ ("threshold_1", self.conf["trigger_inputs"]["threshold"]["threshold_1"]),
+ ("threshold_2", self.conf["trigger_inputs"]["threshold"]["threshold_2"]),
+ ("threshold_3", self.conf["trigger_inputs"]["threshold"]["threshold_3"]),
+ ("threshold_4", self.conf["trigger_inputs"]["threshold"]["threshold_4"]),
+ ("threshold_5", self.conf["trigger_inputs"]["threshold"]["threshold_3"]),
+ ("threshold_6", self.conf["trigger_inputs"]["threshold"]["threshold_4"]),
+ (
+ "trigger_inputs_logic",
+ "%s" % (self.conf["trigger_inputs"]["trigger_inputs_logic"]),
+ ),
+ (
+ "trigger_signal_shape_stretch",
+ "%s"
+ % str(self.conf["trigger_inputs"]["trigger_signal_shape"]["stretch"]),
+ ),
+ (
+ "trigger_signal_shape_delay",
+ "%s"
+ % str(self.conf["trigger_inputs"]["trigger_signal_shape"]["delay"]),
+ ),
+ (
+ "enable_clock_lemo_output",
+ self.conf["clock_lemo"]["enable_clock_lemo_output"],
+ ),
+ ("pmt_control_1", self.conf["pmt_control"]["pmt_1"]),
+ ("pmt_control_2", self.conf["pmt_control"]["pmt_2"]),
+ ("pmt_control_3", self.conf["pmt_control"]["pmt_3"]),
+ ("pmt_control_4", self.conf["pmt_control"]["pmt_4"]),
+ ("save_data", self.conf["save_data"]),
+ ("output_data_path", self.conf["output_data_path"]),
+ ("zmq_connection", self.conf["zmq_connection"]),
+ ]
+ return conf
+
+ def get_data_handling(self) -> tuple:
+ """Information about data handling.
+
+ Returns:
+ tuple: two bools, save and interpret data.
+ """
+
+ return self.conf["save_data"], self.conf["save_data"]
+
+ def get_stop_condition(self) -> tuple:
+ """Information about tlu stop condition.
+
+ Returns:
+ tuple: maximum trigger number and timeout in seconds.
+ """
+ try:
+ max_number = int(self.conf["max_trigger_number"])
+ self.log.info("Stop condition maximum triggers: %s" % max_number)
+ except:
+ max_number = None
+ try:
+ timeout = float(self.conf["timeout"])
+ self.log.info("Stop condition timeout: %s s" % timeout)
+ except:
+ timeout = None
+ return max_number, timeout
+
+ def get_output_data_path(self) -> str:
+ """Parses the output data path
+
+ Returns:
+ str: output path
+ """
+ return self.conf["output_data_path"]
+
+ def get_zmq_connection(self) -> str:
+ """Information about the zmq Address
+
+ Returns:
+ str: ZMQ Address
+ """
+ return self.conf["zmq_connection"]
+
+ def conf_dut(self) -> None:
+ """Parse the configuration for the DUT interface to the AIDATLU."""
+ dut = [0, 0, 0, 0]
+ dut_mode = [0, 0, 0, 0]
+ for i in range(4):
+ if (
+ self.tlu.config_parser.conf["dut_module"]["dut_%s" % (i + 1)]["mode"]
+ == "eudet"
+ ):
+ self.tlu.io_controller.switch_led(i + 1, "g")
+ dut[i] = 2**i
+ # Clock output needs to be disabled for EUDET mode.
+ self.tlu.io_controller.clock_hdmi_output(i + 1, "off")
+ if (
+ self.tlu.config_parser.conf["dut_module"]["dut_%s" % (i + 1)]["mode"]
+ == "aidatrig"
+ ):
+ self.tlu.io_controller.switch_led(i + 1, "w")
+ dut[i] = 2**i
+ dut_mode[i] = 2 ** (2 * i)
+ # In AIDA mode the clock output is needed.
+ self.tlu.io_controller.clock_hdmi_output(i + 1, "chip")
+ if (
+ self.tlu.config_parser.conf["dut_module"]["dut_%s" % (i + 1)]["mode"]
+ == "aida"
+ ):
+ self.tlu.io_controller.switch_led(i + 1, "b")
+ dut[i] = 2**i
+ dut_mode[i] = 3 * (2) ** (2 * i)
+ self.tlu.io_controller.clock_hdmi_output(i + 1, "chip")
+ self.tlu.io_controller.configure_hdmi(i + 1, "0111")
+
+ [
+ self.log.info(
+ "DUT %i configured in %s"
+ % (
+ (i + 1),
+ self.tlu.config_parser.conf["dut_module"]["dut_%s" % (i + 1)][
+ "mode"
+ ],
+ )
+ )
+ for i in range(4)
+ ]
+
+ # This sets the right bits to the set dut mask registers according to the configuration parameter.
+ self.tlu.dut_logic.set_dut_mask(dut[0] | dut[1] | dut[2] | dut[3])
+ self.tlu.dut_logic.set_dut_mask_mode(
+ dut_mode[0] | dut_mode[1] | dut_mode[2] | dut_mode[3]
+ )
+
+ # Special configs
+ self.tlu.dut_logic.set_dut_mask_mode_modifier(0)
+ self.tlu.dut_logic.set_dut_ignore_busy(0)
+ self.tlu.dut_logic.set_dut_ignore_shutter(0x1)
+
+ def conf_trigger_logic(self) -> None:
+ """Configures the trigger logic. So the trigger polarity and the trigger pulse length and stretch."""
+
+ self.tlu.trigger_logic.set_trigger_polarity(
+ self.conf["trigger_inputs"]["trigger_polarity"]["polarity"]
+ )
+
+ self.tlu.trigger_logic.set_pulse_stretch_pack(
+ self.conf["trigger_inputs"]["trigger_signal_shape"]["stretch"]
+ )
+ self.tlu.trigger_logic.set_pulse_delay_pack(
+ self.conf["trigger_inputs"]["trigger_signal_shape"]["delay"]
+ )
+ self.log.info(
+ "Trigger input stretch: %s"
+ % self.conf["trigger_inputs"]["trigger_signal_shape"]["stretch"]
+ )
+ self.log.info(
+ "Trigger input delay : %s"
+ % self.conf["trigger_inputs"]["trigger_signal_shape"]["delay"]
+ )
+
+ self.tlu.trigger_logic.set_internal_trigger_frequency(
+ self.conf["internal_trigger"]["internal_trigger_rate"]
+ )
+
+ def conf_trigger_inputs(self) -> None:
+ """Configures the trigger inputs. Each input can have a different threshold.
+ The two trigger words mask_low and mask_high are generated with the use of two support functions.
+ """
+ [
+ self.tlu.dac_controller.set_threshold(
+ i + 1,
+ self.conf["trigger_inputs"]["threshold"]["threshold_%s" % (i + 1)],
+ )
+ for i in range(6)
+ ]
+
+ trigger_configuration = self.conf["trigger_inputs"]["trigger_inputs_logic"]
+
+ self.log.info("Trigger Configuration: %s" % (trigger_configuration))
+
+ # Sets the Trigger Leds to green if the Input is enabled and to red if the input is set to VETO.
+ # TODO this breaks when there are multiple enabled and veto statements.
+ if trigger_configuration != None:
+ for trigger_led in range(6):
+ if "~CH%i" % (trigger_led + 1) in trigger_configuration:
+ self.io_control.switch_led(trigger_led + 6, "r")
+ elif "CH%i" % (trigger_led + 1) in trigger_configuration:
+ self.io_control.switch_led(trigger_led + 6, "g")
+
+ long_word = 0x0
+ # Goes through all possible trigger combinations and checks if the combination is valid with the trigger logic.
+ # When the word is valid this is added to the longword.
+ for combination in range(64):
+ pattern_list = [(combination >> element) & 0x1 for element in range(6)]
+ CCH5 = pattern_list[5]
+ CCH4 = pattern_list[4]
+ CCH3 = pattern_list[3]
+ CCH2 = pattern_list[2]
+ CCH1 = pattern_list[1]
+ CCH0 = pattern_list[0]
+ valid = (
+ lambda CH1, CH2, CH3, CH4, CH5, CH6: eval(trigger_configuration)
+ )(CCH0, CCH1, CCH2, CCH3, CCH4, CCH5)
+ long_word = (valid << combination) | long_word
+
+ mask_low, mask_high = self._mask_words(long_word)
+ self.log.debug(
+ "mask high: %s, mask low: %s" % (hex(mask_high), hex(mask_low))
+ )
+ self.tlu.trigger_logic.set_trigger_mask(mask_high, mask_low)
+
+ def _mask_words(self, word: int) -> tuple:
+ """Transforms the long word variant of the trigger word to the mask_low mask_high variant.
+
+ Args:
+ word (int): Long word variant of the trigger word.
+
+ Returns:
+ tuple: mask_low and mask_high trigger words
+ """
+ mask_low = 0xFFFFFFFF & word
+ mask_high = word >> 32
+ return (mask_low, mask_high)
diff --git a/aidatlu/main/data_parser.py b/aidatlu/main/data_parser.py
new file mode 100644
index 0000000..96351c1
--- /dev/null
+++ b/aidatlu/main/data_parser.py
@@ -0,0 +1,220 @@
+import numpy as np
+import tables as tb
+from aidatlu import logger
+import logging
+from tqdm import tqdm
+
+
+class DataParser(object):
+ def __init__(self) -> None:
+ self.log = logger.setup_main_logger(__class__.__name__)
+ self.features = np.dtype(
+ [
+ ("eventnumber", "u4"),
+ ("timestamp", "u8"),
+ ("overflow", "u8"),
+ ("eventtype", "u4"),
+ ("input1", "bool"),
+ ("input2", "bool"),
+ ("input3", "bool"),
+ ("input4", "bool"),
+ ("input5", "bool"),
+ ("input6", "bool"),
+ ("sc1", "u4"),
+ ("sc2", "u4"),
+ ("sc3", "u4"),
+ ("sc4", "u4"),
+ ("sc5", "u4"),
+ ("sc6", "u4"),
+ ]
+ )
+ self.raw_features = np.dtype([("raw", "u4")])
+
+ def interpret_data(
+ self, filepath_in: str, filepath_out: str, chunk_size: int = 2000000
+ ) -> None:
+ """Interprets raw tlu data. The data is interpreted in chunksizes.
+ The data is parsed form filepath_in to filepath_out.
+ An event consists of six consecutive raw data entries tha last entry should be a 0.
+ The raw data is sliced and the last data entry checked for corrupted data.
+
+ Args:
+ filepath_in (str): raw data file path
+ filepath_out (str): output path of the interpreted data
+ """
+ self.log.info("Interpreting Data")
+ chunk_size = chunk_size * 6
+ with tb.open_file(filepath_in, "r") as file:
+ n_words = file.root.raw_data.shape[0]
+ self.conf = np.array(file.root.conf[:])
+
+ if n_words == 0:
+ self.log.warning("Data is empty. Skip analysis!")
+ return
+
+ with tb.open_file(
+ filepath_out, mode="w", title="TLU_interpreted"
+ ) as h5_file:
+ data_table = self._create_table(
+ h5_file, name="interpreted_data", title="data", dtype=self.features
+ )
+ for chunk in tqdm(range(0, n_words, chunk_size)):
+ chunk_offset = chunk
+ stop = chunk_offset + chunk_size
+ if chunk + chunk_size > n_words:
+ stop = n_words
+ table = file.root.raw_data[chunk_offset:stop]
+ raw_data = np.array(table[:], dtype=self.raw_features)
+ data = self._transform_data(
+ raw_data["raw"][::6],
+ raw_data["raw"][1::6],
+ raw_data["raw"][2::6],
+ raw_data["raw"][3::6],
+ raw_data["raw"][4::6],
+ raw_data["raw"][5::6],
+ )
+ data_table.append(data)
+
+ config = np.dtype(
+ [
+ ("attribute", "S32"),
+ ("value", "S32"),
+ ]
+ )
+ config_table = h5_file.create_table(
+ h5_file.root,
+ name="conf",
+ description=config,
+ )
+ config_table.append(self.conf)
+ self.log.success('Data parsed from "%s" to "%s"' % (filepath_in, filepath_out))
+
+ def _create_table(self, out_file, name, title, dtype):
+ """Create hit table node for storage in out_file.
+ Copy configuration nodes from raw data file.
+ """
+ table = out_file.create_table(
+ out_file.root,
+ name=name,
+ description=dtype,
+ title=title,
+ filters=tb.Filters(complib="blosc", complevel=5, fletcher32=False),
+ )
+
+ return table
+
+ def _transform_data(
+ self,
+ w0: np.array,
+ w1: np.array,
+ w2: np.array,
+ w3: np.array,
+ w4: np.array,
+ w5: np.array,
+ ) -> np.array:
+ """Transforms raw data from the FIFO to a readable dataformat
+
+ Args:
+ w0 (np.array): contains information which trigger input fired
+ w1 (np.array): contains timestamp information
+ w2 (np.array): trigger input information
+ w3 (np.array): eventnumber
+ w4 (np.array): trigger input information
+ w5 (np.array): this should always be 0.
+
+ Returns:
+ np.array: array with coloumns
+ """
+ if np.any(w5) != 0:
+ self.log.warning("Corrupted Data found")
+ out_array = np.zeros(len(w3), dtype=self.features)
+ out_array["eventnumber"] = w3
+ out_array["timestamp"] = (w0 & 0x0000FFFF << 32) + w1
+ out_array["overflow"] = w0 & 0xFFFF
+ # TODO not sure what this is per. mode?
+ out_array["eventtype"] = (w0 >> 28) & 0xF
+ # Which trigger input produced the event.
+ out_array["input1"] = (w0 >> 16) & 0x1
+ out_array["input2"] = (w0 >> 17) & 0x1
+ out_array["input3"] = (w0 >> 18) & 0x1
+ out_array["input4"] = (w0 >> 19) & 0x1
+ out_array["input5"] = (w0 >> 20) & 0x1
+ out_array["input6"] = (w0 >> 21) & 0x1
+ # TODO not sure what these are prob. something from the DACs
+ out_array["sc1"] = (w2 >> 24) & 0xFF
+ out_array["sc2"] = (w2 >> 16) & 0xFF
+ out_array["sc3"] = (w2 >> 8) & 0xFF
+ out_array["sc4"] = w2 & 0xFF
+ out_array["sc5"] = (w4 >> 24) & 0xFF
+ out_array["sc6"] = (w4 >> 16) & 0xFF
+ return out_array
+
+ def _parse(self, filepath_in: str, filepath_out: str) -> None:
+ """Parse the data from filepath in readable form to filepath out
+
+ Args:
+ filepath_in (str): Raw data file from TLU.
+ filepath_out (str): New interpreted data file.
+ """
+ table = self.read_file(filepath_in)
+ data = self.transform_data(
+ table["raw"][::6],
+ table["raw"][1::6],
+ table["raw"][2::6],
+ table["raw"][3::6],
+ table["raw"][4::6],
+ table["raw"][5::6],
+ )
+ self.write_data(filepath_out, data)
+
+ self.log.info('Data parsed from "%s" to "%s"' % (filepath_in, filepath_out))
+
+ def _read_file(self, filepath: str) -> list:
+ """Reads raw data file of the TLU
+
+ Args:
+ filepath (str): filepath to the data file
+
+ Returns:
+ table: pytable of the raw data
+ """
+ data = np.dtype([("raw", "u4")])
+ with tb.open_file(filepath, "r") as file:
+ table = file.root.raw_data
+ raw_data = np.array(table[:], dtype=data)
+ self.conf = np.array(file.root.conf[:])
+ return raw_data
+
+ def _write_data(self, filepath: str, data: np.array) -> None:
+ """Analyzes the raw data table and writes it into a new .h5 file
+
+ Args:
+ filepath (str): Path to the new .h5 file.
+ data (table): raw data
+ """
+ config = np.dtype(
+ [
+ ("attribute", "S32"),
+ ("value", "S32"),
+ ]
+ )
+ with tb.open_file(filepath, mode="w", title="TLU_interpreted") as h5_file:
+ data_table = self._create_table(
+ h5_file, name="interpreted_data", title="data", dtype=self.features
+ )
+ data_table.append(data)
+ config_table = h5_file.create_table(
+ h5_file.root,
+ name="conf",
+ description=config,
+ )
+ config_table.append(self.conf)
+
+
+if __name__ == "__main__":
+ path_in = "../tlu_data/tlu_raw" + ".h5"
+ path_out = "../tlu_data/tlu_interpreted" + ".h5"
+
+ data_parser = DataParser()
+
+ data_parser.interpret_data(path_in, path_out)
diff --git a/aidatlu/main/tlu.py b/aidatlu/main/tlu.py
new file mode 100644
index 0000000..e193e8a
--- /dev/null
+++ b/aidatlu/main/tlu.py
@@ -0,0 +1,526 @@
+import logging
+import uhal
+import aidatlu.logger as logger
+import numpy as np
+import tables as tb
+from datetime import datetime
+import zmq
+from pathlib import Path
+import time
+import threading
+
+from aidatlu.hardware.i2c import I2CCore
+from aidatlu.hardware.clock_controller import ClockControl
+from aidatlu.hardware.ioexpander_controller import IOControl
+from aidatlu.hardware.dac_controller import DacControl
+from aidatlu.hardware.trigger_controller import TriggerLogic
+from aidatlu.hardware.dut_controller import DUTLogic
+from aidatlu.main.config_parser import TLUConfigure
+from aidatlu.main.data_parser import DataParser
+
+
+class AidaTLU(object):
+ def __init__(self, hw, config_path, clock_config_path) -> None:
+ self.log = logger.setup_main_logger(__class__.__name__)
+
+ self.i2c = I2CCore(hw)
+ self.i2c_hw = hw
+ self.log.info("Initializing IPbus interface")
+ self.i2c.init()
+ if self.i2c.modules["eeprom"]:
+ self.log.info("Found device with ID %s" % hex(self.get_device_id()))
+
+ # TODO some configuration also sends out ~70 triggers.
+ self.io_controller = IOControl(self.i2c)
+ self.dac_controller = DacControl(self.i2c)
+ self.clock_controller = ClockControl(self.i2c, self.io_controller)
+ self.clock_controller.write_clock_conf(clock_config_path)
+ self.trigger_logic = TriggerLogic(self.i2c)
+ self.dut_logic = DUTLogic(self.i2c)
+
+ self.reset_configuration()
+ self.config_parser = TLUConfigure(self, self.io_controller, config_path)
+ self.data_parser = DataParser()
+
+ self.log.success("TLU initialized")
+
+ def configure(self) -> None:
+ """loads the conf.yaml and configures the TLU accordingly."""
+ self.config_parser.configure()
+ self.conf_list = self.config_parser.get_configuration_table()
+ self.get_event_fifo_fill_level()
+ self.get_event_fifo_csr()
+ self.get_scalar()
+
+ def reset_configuration(self) -> None:
+ """Switch off all outputs, reset all counters and set threshold to 1.2V"""
+ # Disable all outputs
+ self.io_controller.clock_lemo_output(False)
+ for i in range(4):
+ self.io_controller.configure_hdmi(i + 1, 1)
+ self.dac_controller.set_voltage(5, 0)
+ self.io_controller.all_off()
+ # sets all thresholds to 1.2 V
+ for i in range(6):
+ self.dac_controller.set_threshold(i + 1, 0)
+ # Resets all internal counters and raise the trigger veto.
+ self.set_run_active(False)
+ self.reset_status()
+ self.reset_counters()
+ self.trigger_logic.set_trigger_veto(True)
+ self.reset_fifo()
+ self.reset_timestamp()
+ self.run_number = 0
+ try:
+ self.h5_file.close()
+ except:
+ pass
+
+ def get_device_id(self) -> int:
+ """Read back board id. Consists of six blocks of hex data
+
+ Returns:
+ int: Board id as 48 bits integer
+ """
+ id = []
+ for addr in range(6):
+ id.append(self.i2c.read(self.i2c.modules["eeprom"], 0xFA + addr) & 0xFF)
+ return int("0x" + "".join(["{:x}".format(i) for i in id]), 16) & 0xFFFFFFFFFFFF
+
+ def get_fw_version(self) -> int:
+ return self.i2c.read_register("version")
+
+ def reset_timestamp(self) -> None:
+ """Sets bit to 'ResetTimestampW' register to reset the time stamp."""
+ self.i2c.write_register("Event_Formatter.ResetTimestampW", 1)
+
+ def reset_counters(self) -> None:
+ """Resets the trigger counters."""
+ self.write_status(0x2)
+ self.write_status(0x0)
+
+ def reset_status(self) -> None:
+ """Resets the complete status and all counters."""
+ self.write_status(0x3)
+ self.write_status(0x0)
+ self.write_status(0x4)
+ self.write_status(0x0)
+
+ def reset_fifo(self) -> None:
+ """Sets 0 to 'EventFifoCSR' this resets the FIFO."""
+ self.set_event_fifo_csr(0x0)
+
+ def set_event_fifo_csr(self, value: int) -> None:
+ """Sets value to the EventFifoCSR register.
+
+ Args:
+ value (int): 0 resets the FIFO. #TODO can do other stuff that is not implemented
+
+ """
+ self.i2c.write_register("eventBuffer.EventFifoCSR", value)
+
+ def write_status(self, value: int) -> None:
+ """Sets value to the 'SerdesRstW' register.
+
+ Args:
+ value (int): Bit 0 resets the status, bit 1 resets trigger counters and bit 2 calibrates IDELAY.
+ """
+ self.i2c.write_register("triggerInputs.SerdesRstW", value)
+
+ def set_run_active(self, state: bool) -> None:
+ """Raises internal run active signal.
+
+ Args:
+ state (bool): True sets run active, False disables it.
+ """
+ if type(state) != bool:
+ raise TypeError("State has to be bool")
+ self.i2c.write_register("Shutter.RunActiveRW", int(state))
+ self.log.info("Run active: %s" % self.get_run_active())
+
+ def get_run_active(self) -> bool:
+ """Reads register 'RunActiveRW'
+
+ Returns:
+ bool: Returns bool of the run active register.
+ """
+ return bool(self.i2c.read_register("Shutter.RunActiveRW"))
+
+ def test_configuration(self) -> None:
+ """Configure DUT 1 to run in a default test configuration.
+ Runs in EUDET mode with internal generated triggers.
+ This is just for testing and bugfixing.
+ """
+ self.log.info("Configure DUT 1 in EUDET test mode")
+
+ test_stretch = [1, 1, 1, 1, 1, 1]
+ test_delay = [0, 0, 0, 0, 0, 0]
+
+ self.io_controller.configure_hdmi(1, "0111")
+ self.io_controller.clock_hdmi_output(1, "off")
+ self.trigger_logic.set_pulse_stretch_pack(test_stretch)
+ self.trigger_logic.set_pulse_delay_pack(test_delay)
+ self.trigger_logic.set_trigger_mask(mask_high=0x00000000, mask_low=0x00000002)
+ self.trigger_logic.set_trigger_polarity(1)
+ self.dut_logic.set_dut_mask("0001")
+ self.dut_logic.set_dut_mask_mode("00000000")
+ self.trigger_logic.set_internal_trigger_frequency(500)
+
+ def default_configuration(self) -> None:
+ """Default configuration. Configures DUT 1 to run in EUDET mode.
+ This is just for testing and bugfixing.
+ """
+ test_stretch = [1, 1, 1, 1, 1, 1]
+ test_delay = [0, 0, 0, 0, 0, 0]
+
+ self.io_controller.configure_hdmi(1, "0111")
+ self.io_controller.configure_hdmi(2, "0111")
+ self.io_controller.configure_hdmi(3, "0111")
+ self.io_controller.configure_hdmi(4, "0111")
+ self.io_controller.clock_hdmi_output(1, "off")
+ self.io_controller.clock_hdmi_output(2, "off")
+ self.io_controller.clock_hdmi_output(3, "off")
+ self.io_controller.clock_hdmi_output(4, "off")
+ self.io_controller.clock_lemo_output(False)
+ self.dac_controller.set_threshold(1, -0.04)
+ self.dac_controller.set_threshold(2, -0.04)
+ self.dac_controller.set_threshold(3, -0.04)
+ self.dac_controller.set_threshold(4, -0.04)
+ self.dac_controller.set_threshold(5, -0.2)
+ self.dac_controller.set_threshold(6, -0.2)
+ self.trigger_logic.set_pulse_stretch_pack(test_stretch)
+ self.trigger_logic.set_pulse_delay_pack(test_delay)
+ self.trigger_logic.set_trigger_mask(mask_high=0, mask_low=2)
+ self.trigger_logic.set_trigger_polarity(1)
+ self.dut_logic.set_dut_mask("0001")
+ self.dut_logic.set_dut_mask_mode("00000000")
+ self.dut_logic.set_dut_mask_mode_modifier(0)
+ self.dut_logic.set_dut_ignore_busy(0)
+ self.dut_logic.set_dut_ignore_shutter(0x1)
+ self.trigger_logic.set_internal_trigger_frequency(0)
+
+ def start_run(self) -> None:
+ """Start run configurations"""
+ self.reset_counters()
+ self.reset_fifo()
+ self.set_run_active(True)
+ self.trigger_logic.set_trigger_veto(False)
+
+ def stop_run(self) -> None:
+ """Stop run configurations"""
+ self.trigger_logic.set_trigger_veto(True)
+ self.set_run_active(False)
+ self.run_number += 1
+
+ def set_enable_record_data(self, value: int) -> None:
+ """#TODO not sure what this does. Looks like a seperate internal event buffer to the FIFO.
+
+ Args:
+ value (int): #TODO I think this does not work
+ """
+ self.i2c.write_register("Event_Formatter.Enable_Record_Data", value)
+
+ def get_event_fifo_csr(self) -> int:
+ """Reads value from 'EventFifoCSR'
+
+ Returns:
+ int: number of events
+ """
+ return self.i2c.read_register("eventBuffer.EventFifoCSR")
+
+ def get_event_fifo_fill_level(self) -> int:
+ """Reads value from 'EventFifoFillLevel'
+
+ Returns:
+ int: buffer level of the fifi
+ """
+ return self.i2c.read_register("eventBuffer.EventFifoFillLevel")
+
+ def reset_timestamp(self) -> None:
+ """Resets the internal timestamp by asserting a bit in 'ResetTimestampW'."""
+ self.i2c.write_register("Event_Formatter.ResetTimestampW", 1)
+
+ def get_timestamp(self) -> int:
+ """Get current time stamp.
+
+ Returns:
+ int: Time stamp is not formatted.
+ """
+ time = self.i2c.read_register("Event_Formatter.CurrentTimestampHR")
+ time = time << 32
+ time = time + self.i2c.read_register("Event_Formatter.CurrentTimestampLR")
+ return time
+
+ def pull_fifo_event(self) -> list:
+ """Pulls event from the FIFO. This is needed in the run loop to prevent the buffer to get stuck.
+ if this register is full the fifo needs to be reset or new triggers are generated but not sent out.
+ #TODO check here if the FIFO is full and reset it if needed would prob. make sense.
+
+ Returns:
+ list: 6 element long vector containing bitwords of the data.
+ """
+ event_numb = self.get_event_fifo_fill_level()
+ if event_numb:
+ if event_numb * 6 == 0xFEA:
+ self.log.warning("FIFO is full")
+ fifo_content = self.i2c_hw.getNode("eventBuffer.EventFifoData").readBlock(
+ event_numb
+ )
+ self.i2c_hw.dispatch()
+ return np.array(fifo_content)
+ pass
+
+ def get_scalar(self):
+ s0 = self.i2c.read_register("triggerInputs.ThrCount0R")
+ s1 = self.i2c.read_register("triggerInputs.ThrCount1R")
+ s2 = self.i2c.read_register("triggerInputs.ThrCount2R")
+ s3 = self.i2c.read_register("triggerInputs.ThrCount3R")
+ s4 = self.i2c.read_register("triggerInputs.ThrCount4R")
+ s5 = self.i2c.read_register("triggerInputs.ThrCount5R")
+ return s0, s1, s2, s3, s4, s5
+
+ def init_raw_data_table(self) -> None:
+ """Initializes the raw data table, where the raw FIFO data is found."""
+ self.data = np.dtype(
+ [
+ ("raw", "u4"),
+ ]
+ )
+
+ config = np.dtype(
+ [
+ ("attribute", "S32"),
+ ("value", "S32"),
+ ]
+ )
+
+ Path(self.path).mkdir(parents=True, exist_ok=True)
+ self.filter_data = tb.Filters(complib="blosc", complevel=5)
+ self.h5_file = tb.open_file(self.raw_data_path, mode="w", title="TLU")
+ self.data_table = self.h5_file.create_table(
+ self.h5_file.root,
+ name="raw_data",
+ description=self.data,
+ title="data",
+ filters=self.filter_data,
+ )
+ config_table = self.h5_file.create_table(
+ self.h5_file.root,
+ name="conf",
+ description=config,
+ filters=self.filter_data,
+ )
+ self.buffer = []
+ config_table.append(self.conf_list)
+
+ def handle_status(self) -> None:
+ t = threading.current_thread()
+ while getattr(t, "do_run", True):
+ time.sleep(0.5)
+ last_time = self.get_timestamp()
+ current_time = (last_time - self.start_time) * 25 / 1000000000
+ # Logs and poss. sends status every 1s.
+ if current_time - self.last_time > 1:
+ self.log_sent_status(current_time)
+ # Stops the TLU after some time in seconds.
+ if self.timeout != None:
+ if current_time > self.timeout:
+ self.stop_condition = True
+ if self.max_trigger != None:
+ if self.trigger_logic.get_post_veto_trigger() > self.max_trigger:
+ self.stop_condition = True
+
+ def log_sent_status(self, time: int) -> None:
+ """Logs the status of the TLU run with trigger number, runtime usw.
+ Also calculates the mean trigger frequency between function calls.
+
+ Args:
+ time (int): current runtime of the TLU
+ """
+ self.hit_rate = (
+ self.trigger_logic.get_post_veto_trigger() - self.last_triggers_freq
+ ) / (time - self.last_time)
+ self.particle_rate = (
+ self.trigger_logic.get_pre_veto_trigger() - self.last_particle_freq
+ ) / (time - self.last_time)
+ self.run_time = time
+ self.event_number = self.trigger_logic.get_post_veto_trigger()
+ self.total_trigger_number = self.trigger_logic.get_pre_veto_trigger()
+ s0, s1, s2, s3, s4, s5 = self.get_scalar()
+
+ if self.zmq_address not in [None, "off"]:
+ self.socket.send_string(
+ str(
+ [
+ self.run_time,
+ self.event_number,
+ self.total_trigger_number,
+ self.particle_rate,
+ self.hit_rate,
+ ]
+ ),
+ flags=zmq.NOBLOCK,
+ )
+
+ self.last_time = time
+ self.last_triggers_freq = self.trigger_logic.get_post_veto_trigger()
+ self.last_particle_freq = self.trigger_logic.get_pre_veto_trigger()
+
+ self.log.info(
+ "Run time: %.3f s, Event: %s, Total trigger: %s, Trigger in freq: %.f Hz, Trigger out freq.: %.f Hz"
+ % (
+ self.run_time,
+ self.event_number,
+ self.total_trigger_number,
+ self.particle_rate,
+ self.hit_rate,
+ )
+ )
+
+ self.log.debug("Scalar %i:%i:%i:%i:%i:%i" % (s0, s1, s2, s3, s4, s5))
+ self.log.debug("FIFO level: %s" % self.get_event_fifo_fill_level())
+ self.log.debug("FIFO level 2: %s" % self.get_event_fifo_csr())
+ self.log.debug(
+ "fifo csr: %s fifo fill level: %s"
+ % (self.get_event_fifo_csr(), self.get_event_fifo_csr())
+ )
+ self.log.debug(
+ "post: %s pre: %s"
+ % (
+ self.trigger_logic.get_post_veto_trigger(),
+ self.trigger_logic.get_pre_veto_trigger(),
+ )
+ )
+ self.log.debug("time stamp: %s" % (self.get_timestamp()))
+
+ def log_trigger_inputs(self, event_vector: list) -> None:
+ """Logs which inputs triggered the event corresponding to the event vector.
+
+ Args:
+ event_vector (list): 6 data long event vector from the FIFO.
+ """
+ w0 = event_vector[0]
+ input_1 = (w0 >> 16) & 0x1
+ input_2 = (w0 >> 17) & 0x1
+ input_3 = (w0 >> 18) & 0x1
+ input_4 = (w0 >> 19) & 0x1
+ input_5 = (w0 >> 20) & 0x1
+ input_6 = (w0 >> 21) & 0x1
+ self.log.info("Event triggered:")
+ self.log.info(
+ "Input 1: %s, Input 2: %s, Input 3: %s, Input 4: %s, Input 5: %s, Input 6: %s"
+ % (input_1, input_2, input_3, input_4, input_5, input_6)
+ )
+
+ def setup_zmq(self) -> None:
+ self.context = zmq.Context()
+ self.socket = self.context.socket(zmq.PUB)
+ self.socket.bind(self.zmq_address)
+ self.log.info("Connected ZMQ socket with address: %s" % self.zmq_address)
+
+ def run(self) -> None:
+ """Start run of the TLU."""
+ self.start_run()
+ self.get_fw_version()
+ self.get_device_id()
+ run_active = True
+ # reset starting parameter
+ self.start_time = self.get_timestamp()
+ self.last_time = 0
+ self.last_triggers_freq = self.trigger_logic.get_post_veto_trigger()
+ self.last_particle_freq = self.trigger_logic.get_pre_veto_trigger()
+ first_event = True
+ self.stop_condition = False
+ # prepare data handling and zmq connection
+ save_data, interpret_data = self.config_parser.get_data_handling()
+ self.zmq_address = self.config_parser.get_zmq_connection()
+ self.max_trigger, self.timeout = self.config_parser.get_stop_condition()
+
+ if save_data:
+ self.path = self.config_parser.get_output_data_path()
+ if self.path == None:
+ self.path = "tlu_data/"
+ if __name__ == "__main__":
+ self.path = "../tlu_data/"
+ self.raw_data_path = self.path + "tlu_raw_run%s_%s.h5" % (
+ self.run_number,
+ datetime.now().strftime("%Y_%m_%d_%H_%M_%S"),
+ )
+ self.interpreted_data_path = self.path + "tlu_interpreted_run%s_%s.h5" % (
+ self.run_number,
+ datetime.now().strftime("%Y_%m_%d_%H_%M_%S"),
+ )
+ self.init_raw_data_table()
+
+ if self.zmq_address not in [None, "off"]:
+ self.setup_zmq()
+
+ t = threading.Thread(target=self.handle_status)
+ t.start()
+ while run_active:
+ try:
+ time.sleep(0.000001)
+ current_event = self.pull_fifo_event()
+ try:
+ if save_data and np.size(current_event) > 1:
+ self.data_table.append(current_event)
+ if self.stop_condition == True:
+ raise KeyboardInterrupt
+ except:
+ if KeyboardInterrupt:
+ run_active = False
+ t.do_run = False
+ self.stop_run()
+ else:
+ # If this happens: poss. Hitrate to high for FIFO and or Data handling.
+ self.log.warning("Incomplete Event handling...")
+
+ # This loop sents which inputs produced the trigger signal for the first event.
+ if (
+ np.size(current_event) > 1
+ ) and first_event: # TODO only first event?
+ self.log_trigger_inputs(current_event[0:6])
+ first_event = False
+
+ except:
+ KeyboardInterrupt
+ run_active = False
+ t.do_run = False
+ self.stop_run()
+
+ # Cleanup of FIFO
+ try:
+ while np.size(current_event) > 1:
+ current_event = self.pull_fifo_event()
+ except:
+ KeyboardInterrupt
+ self.log.warning("Interupted FIFO cleanup")
+
+ if self.zmq_address not in [None, "off"]:
+ self.socket.close()
+
+ if save_data:
+ self.h5_file.close()
+ if interpret_data:
+ try:
+ self.data_parser.interpret_data(
+ self.raw_data_path, self.interpreted_data_path
+ )
+ except:
+ self.log.warning("Cannot interpret data.")
+ self.log.success("Run finished")
+
+
+if __name__ == "__main__":
+ uhal.setLogLevelTo(uhal.LogLevel.NOTICE)
+ manager = uhal.ConnectionManager("file://../misc/aida_tlu_connection.xml")
+ hw = uhal.HwInterface(manager.getDevice("aida_tlu.controlhub"))
+
+ clock_path = "../misc/aida_tlu_clk_config.txt"
+ config_path = "../tlu_configuration.yaml"
+
+ tlu = AidaTLU(hw, config_path, clock_path)
+
+ tlu.configure()
+
+ tlu.run()
diff --git a/packages/__init__.py b/aidatlu/misc/__init__.py
similarity index 100%
rename from packages/__init__.py
rename to aidatlu/misc/__init__.py
diff --git a/EUDETdummy/scripts/EUDETdummyaddrmap.xml b/aidatlu/misc/aida_tlu_address-fw_version_0a.xml
similarity index 90%
rename from EUDETdummy/scripts/EUDETdummyaddrmap.xml
rename to aidatlu/misc/aida_tlu_address-fw_version_0a.xml
index 1d04eef..7408069 100644
--- a/EUDETdummy/scripts/EUDETdummyaddrmap.xml
+++ b/aidatlu/misc/aida_tlu_address-fw_version_0a.xml
@@ -1,28 +1,25 @@
-
+
-
-
@@ -32,25 +29,20 @@
-
-
-
-
-
+
-
+
+
+
+
+
@@ -93,4 +88,9 @@
+
diff --git a/TLU_v1c/scripts/TLUaddrmap.xml b/aidatlu/misc/aida_tlu_address-fw_version_14.xml
similarity index 76%
rename from TLU_v1c/scripts/TLUaddrmap.xml
rename to aidatlu/misc/aida_tlu_address-fw_version_14.xml
index 65fb534..880d97c 100644
--- a/TLU_v1c/scripts/TLUaddrmap.xml
+++ b/aidatlu/misc/aida_tlu_address-fw_version_14.xml
@@ -3,25 +3,30 @@
-
-
+
+
-
-
-
+
+
+
-
-
-
+
+
+
+
+
+
+
+
-
+
@@ -29,21 +34,21 @@
-
+
-
+
-
+
@@ -54,7 +59,7 @@
-
+
@@ -68,7 +73,7 @@
-
+
@@ -84,17 +89,17 @@
-
+
-->
-
+
-
+
+
+
+
diff --git a/aidatlu/misc/aida_tlu_test.conf b/aidatlu/misc/aida_tlu_test.conf
new file mode 100644
index 0000000..051edcf
--- /dev/null
+++ b/aidatlu/misc/aida_tlu_test.conf
@@ -0,0 +1,105 @@
+[Producer.aida_tlu]
+## GENERAL PARAMETERS
+verbose= 1
+skipconf= 0
+confid= 20180910
+delayStart= 200
+
+## HDMI CONFIGURATION
+# 4-bits to determine direction of HDMI pins
+HDMI1_set= 0x7
+HDMI2_set= 0x7
+HDMI3_set= 0x7
+HDMI4_set= 0x7
+# Clock source (0= no clock, 1= Si5345, 2= FPGA)
+HDMI1_clk = 1
+HDMI2_clk = 1
+HDMI3_clk = 1
+HDMI4_clk = 1
+# Enable/Disable clock on differential LEMO
+LEMOclk = 0
+
+## PMT POWER CONFIGURATION
+PMT1_V= 0.1
+PMT2_V= 0.2
+PMT3_V= 0.4
+PMT4_V= 0.8
+
+## TRIGGER CONFIGURATION
+trigMaskHi = 0x00000000
+trigMaskLo = 0x00000002
+in0_STR = 1
+in0_DEL = 0
+in1_STR = 1
+in1_DEL = 0
+in2_STR = 1
+in2_DEL = 0
+in3_STR = 1
+in3_DEL = 0
+in4_STR = 1
+in4_DEL = 0
+in5_STR = 1
+in5_DEL = 0
+# Generate internal triggers (in Hz, 0= no triggers)
+InternalTriggerFreq= 0
+
+## DISCRIMINATOR THRESHOLDS
+DACThreshold0 = -0.12
+DACThreshold1 = -0.12
+DACThreshold2 = -0.12
+DACThreshold3 = -0.12
+DACThreshold4 = -0.12
+DACThreshold5 = -0.12
+
+## DUT CONFIGURATION
+ # DUTMask Which DUTs are on
+DUTMask= 0x8
+ # DUTMaskMode Define AIDA (11) or EUDET (00) mode (2 bits per DUT)
+DUTMaskMode= 0xFC
+ # In EUDET mode: 0 = standard trigger/busy mode, 1 = raising BUSY outside handshake vetoes triggers (2 bits per DUT)
+DUTMaskModeModifier= 0xC0
+ # Ignore the BUSY signal for a DUT (0xF)
+DUTIgnoreBusy= 0xF
+ # Rising shutter ignores triggers
+DUTIgnoreShutterVeto= 0x1
+EnableRecordData= 1
+
+
+# EnableShutterMode: 0x1. If 1, shutter mode is enabled. If 0, shutter mode is disabled.
+EnableShutterMode= 0x1
+# Define which input is used for shutter source [0 - 5]
+ShutterSource = 5
+# 32-bit counter of clocks. Set to 0 to not use internal shutter generator.
+InternalShutterInterval = 0
+# 32-bit counter of clocks
+ShutterOnTime = 200
+# 32-bit counter of clocks
+ShutterVetoOffTime = 300
+# 32-bit counter of clocks
+ShutterOffTime = 400
+
+## DATA COLLECTOR
+EUDAQ_DC= my_dc
+
+
+[LogCollector.log]
+# Currently, all LogCollectors have a hardcoded runtime name: log
+# nothing
+
+
+[DataCollector.my_dc]
+EUDAQ_MN=my_mon
+# send assambled event to the monitor with runtime name my_mon;
+EUDAQ_FW=native
+# the format of data file
+EUDAQ_FW_PATTERN=test_$12D_run$6R$X
+# the name pattern of data file
+# the $12D will be converted a data/time string with 12 digits.
+# the $6R will be converted a run number string with 6 digits.
+# the $X will be converted the suffix name of data file.
+
+
+[Monitor.my_mon]
+EX0_ENABLE_PRINT=0
+EX0_ENABLE_STD_PRINT=0
+EX0_ENABLE_STD_CONVERTER=1
diff --git a/TLU_v1e/scripts/localIni.ini b/aidatlu/misc/aida_tlu_test.ini
similarity index 81%
rename from TLU_v1e/scripts/localIni.ini
rename to aidatlu/misc/aida_tlu_test.ini
index 2c79f2a..4db65fc 100644
--- a/TLU_v1e/scripts/localIni.ini
+++ b/aidatlu/misc/aida_tlu_test.ini
@@ -1,9 +1,10 @@
-[Producer.fmctlu]
-initid= 20170703
+[Producer.aida_tlu]
+initid= 20180910
verbose = 1
-ConnectionFile= "file://./fmctlu_connection.xml"
-DeviceName="fmctlu.udp"
-TLUmod= "1e"
+ConnectionFile= "file://./../user/eudet/misc/hw_conf/aida_tlu/aida_tlu_connection.xml"
+DeviceName = "aida_tlu.controlhub"
+#DeviceName = "aida_tlu.udp"
+TLUmod = "1e"
# number of HDMI inputs, leave 4 even if you only use fewer inputs
nDUTs = 4
nTrgIn = 6
@@ -25,8 +26,6 @@ I2C_ID_Addr = 0x50
I2C_EXP1_Addr = 0x74
#I2C address of 2st expander PCA9539PW
I2C_EXP2_Addr = 0x75
-#I2C address of EEPROM on powermodule
-I2C_pwrId_Addr = 0x51
#I2C address of AD5665R on powermodule
I2C_DACModule_Addr = 0x1C
# Max value for control voltage on PMTs (usually 1 V)
@@ -39,7 +38,7 @@ I2C_EXP2Module_Addr = 0x77
##CONFCLOCK 0= skip clock configuration, 1= configure si5345
CONFCLOCK= 1
-CLOCK_CFG_FILE = /home/silab/git/aida-tlu/TLU_v1e/scripts/localClock.txt
+CLOCK_CFG_FILE = "./../user/eudet/misc/hw_conf/aida_tlu/aida_tlu_clk_config.txt"
[LogCollector.log]
diff --git a/packages/TLU_v1e/output.csv b/aidatlu/online_monitor/__init__.py
similarity index 100%
rename from packages/TLU_v1e/output.csv
rename to aidatlu/online_monitor/__init__.py
diff --git a/aidatlu/online_monitor/configuration.yaml b/aidatlu/online_monitor/configuration.yaml
new file mode 100644
index 0000000..ce50979
--- /dev/null
+++ b/aidatlu/online_monitor/configuration.yaml
@@ -0,0 +1,12 @@
+
+converter :
+ AIDA_TLU_Converter :
+ kind : tlu_converter
+ frontend : tcp://127.0.0.1:6500
+ backend : tcp://127.0.0.1:7501
+ theshold: 10
+receiver :
+ AIDA_TLU :
+ kind : tlu_receiver
+ frontend : tcp://127.0.0.1:7501
+
\ No newline at end of file
diff --git a/aidatlu/online_monitor/tlu_converter.py b/aidatlu/online_monitor/tlu_converter.py
new file mode 100644
index 0000000..05ed4a1
--- /dev/null
+++ b/aidatlu/online_monitor/tlu_converter.py
@@ -0,0 +1,29 @@
+from online_monitor.converter.transceiver import Transceiver
+import zmq
+from online_monitor.utils import utils
+
+
+class AIDATLUConverter(Transceiver):
+ def deserialize_data(self, data):
+ m = data.decode()
+ m = "".join([i for i in m if i not in ["[", "]", " "]])
+ m = m.split(" ")
+ m = list(filter(None, m))
+ for i in range(len(m)):
+ m[i] = m[i].replace(",", "")
+ m = [float(i) for i in m]
+ return m
+
+ def interpret_data(self, data):
+ interpreted_data = {
+ "Address": data[0][0],
+ "Run Time": data[0][1][0],
+ "Event Number": data[0][1][1],
+ "Total trigger numb": data[0][1][2],
+ "Particle Rate": data[0][1][3],
+ "Trigger freq": data[0][1][4],
+ }
+ return [interpreted_data]
+
+ def serialize_data(self, data):
+ return utils.simple_enc(None, data)
diff --git a/aidatlu/online_monitor/tlu_receiver.py b/aidatlu/online_monitor/tlu_receiver.py
new file mode 100644
index 0000000..555a61c
--- /dev/null
+++ b/aidatlu/online_monitor/tlu_receiver.py
@@ -0,0 +1,118 @@
+from online_monitor.receiver.receiver import Receiver
+
+import pyqtgraph as pg
+from pyqtgraph.dockarea import DockArea, Dock
+from PyQt5 import QtWidgets
+import pyqtgraph as pg
+from pyqtgraph.dockarea import DockArea, Dock
+from online_monitor.utils import utils
+
+
+class AIDATLUReciever(Receiver):
+ def setup_receiver(self):
+ # self.set_bidirectional_communication() # We want to change converter settings
+ self.hitrate_data = []
+ self.runtime = []
+ self.particlerate_data = []
+
+ def setup_widgets(self, parent, name):
+ dock_area = DockArea()
+ parent.addTab(dock_area, name)
+ # Docks
+ dock_rate = Dock("Particle rate (Trigger rate)", size=(400, 400))
+ dock_status = Dock("Status", size=(800, 40))
+ dock_area.addDock(dock_rate, "above")
+ dock_area.addDock(dock_status, "top")
+
+ # Status dock on top
+ cw = QtWidgets.QWidget()
+ cw.setStyleSheet("QWidget {background-color:white}")
+ layout = QtWidgets.QGridLayout()
+ cw.setLayout(layout)
+
+ self.hit_rate_label = QtWidgets.QLabel("Trigger Frequency\n0 Hz")
+ self.timestamp_label = QtWidgets.QLabel("Run Time\n0 s")
+ self.event_numb_label = QtWidgets.QLabel("Event Number\n0")
+ self.total_trig_numb = QtWidgets.QLabel("Total Trigger Number\n0")
+ self.particle_rate_label = QtWidgets.QLabel("Particle Rate\n0")
+ self.reset_button = QtWidgets.QPushButton("Reset")
+ layout.addWidget(self.timestamp_label, 0, 0, 0, 1)
+ layout.addWidget(self.event_numb_label, 0, 1, 0, 1)
+ layout.addWidget(self.hit_rate_label, 0, 6, 0, 1)
+ layout.addWidget(self.particle_rate_label, 0, 3, 0, 1)
+ layout.addWidget(self.total_trig_numb, 0, 2, 0, 1)
+ layout.addWidget(self.reset_button, 0, 7, 0, 1)
+ dock_status.addWidget(cw)
+
+ self.reset_button.clicked.connect(lambda: self._reset())
+
+ # particle rate dock
+ trigger_rate_graphics = pg.GraphicsLayoutWidget()
+ trigger_rate_graphics.show()
+ plot_trigger_rate = pg.PlotItem(
+ labels={"left": "Rate / Hz", "bottom": "Run Time / s"}
+ )
+ self.trigger_rate_acc_curve = pg.PlotCurveItem(pen="#B00B13")
+ self.particle_rate_acc_curve = pg.PlotCurveItem(pen="#0000FF")
+
+ # add legend
+ legend_acc = pg.LegendItem(offset=(80, 10))
+ legend_acc.setParentItem(plot_trigger_rate)
+ legend_acc.addItem(self.trigger_rate_acc_curve, "Accepted Trigger Rate")
+ legend_real = pg.LegendItem(offset=(80, 50))
+ legend_real.setParentItem(plot_trigger_rate)
+ legend_real.addItem(self.particle_rate_acc_curve, "Particle Rate")
+
+ # add items to plots and customize plots viewboxes
+ plot_trigger_rate.addItem(self.trigger_rate_acc_curve)
+ plot_trigger_rate.addItem(self.particle_rate_acc_curve)
+
+ plot_trigger_rate.vb.setBackgroundColor("#E6E5F4")
+ # plot_trigger_rate.setXRange(0, 200)
+ plot_trigger_rate.getAxis("left").setZValue(0)
+ plot_trigger_rate.getAxis("left").setGrid(155)
+
+ # add plots to graphicslayout and layout to dock
+ trigger_rate_graphics.addItem(
+ plot_trigger_rate, row=0, col=1, rowspan=1, colspan=2
+ )
+ dock_rate.addWidget(trigger_rate_graphics)
+
+ # add dict of all used plotcurveitems for individual handling of each plot
+ self.plots = {
+ "trigger_rate_acc": self.trigger_rate_acc_curve,
+ "particle_rate_acc": self.particle_rate_acc_curve,
+ }
+ self.plot_delay = 0
+
+ def deserialize_data(self, data):
+ return utils.simple_dec(data)[1]
+
+ def refresh_data(self):
+ if len(self.hitrate_data) > 0:
+ self.trigger_rate_acc_curve.setData(x=self.runtime, y=self.hitrate_data)
+ if len(self.particlerate_data) > 0:
+ self.particle_rate_acc_curve.setData(
+ x=self.runtime, y=self.particlerate_data
+ )
+
+ def handle_data(self, data):
+ self.hitrate_data.append(data["Trigger freq"])
+ self.particlerate_data.append(data["Particle Rate"])
+ self.runtime.append(data["Run Time"])
+ self.timestamp_label.setText("Run Time\n%0.2f s" % data["Run Time"])
+ self.event_numb_label.setText("Event Number\n%i" % data["Event Number"])
+ self.total_trig_numb.setText(
+ "Total Trigger Number\n%i" % data["Total trigger numb"]
+ )
+ self.particle_rate_label.setText(
+ "Particle Rate\n%0.2f Hz" % data["Particle Rate"]
+ )
+ self.hit_rate_label.setText(
+ "Trigger Frequency\n%0.2f Hz" % data["Trigger freq"]
+ )
+
+ def _reset(self):
+ self.hitrate_data = []
+ self.runtime = []
+ self.particlerate_data = []
diff --git a/aidatlu/test/__init__.py b/aidatlu/test/__init__.py
new file mode 100644
index 0000000..e69de29
diff --git a/aidatlu/test/hardware_test.py b/aidatlu/test/hardware_test.py
new file mode 100644
index 0000000..f0015be
--- /dev/null
+++ b/aidatlu/test/hardware_test.py
@@ -0,0 +1,212 @@
+from aidatlu.main.tlu import AidaTLU
+from aidatlu.hardware.i2c import I2CCore
+from aidatlu.hardware.ioexpander_controller import IOControl
+from aidatlu.hardware.dac_controller import DacControl
+from aidatlu.hardware.clock_controller import ClockControl
+from aidatlu.hardware.dut_controller import DUTLogic
+from aidatlu.hardware.trigger_controller import TriggerLogic
+from aidatlu.main.config_parser import TLUConfigure
+
+import uhal
+import time
+import numpy as np
+
+
+class Test_IOCControl:
+ uhal.setLogLevelTo(uhal.LogLevel.NOTICE)
+ manager = uhal.ConnectionManager("file://../misc/aida_tlu_connection.xml")
+ hw = uhal.HwInterface(manager.getDevice("aida_tlu.controlhub"))
+
+ i2c = I2CCore(hw)
+ i2c.init()
+ ioexpander = IOControl(i2c)
+
+ def test_ioexpander_led(self) -> None:
+ self.ioexpander.all_off()
+ self.ioexpander.test_leds(single=True)
+ self.ioexpander.all_off()
+ time.sleep(1)
+ self.ioexpander.all_on()
+ time.sleep(2)
+ self.ioexpander.all_off()
+
+ def test_configure_hdmi(self) -> None:
+ for i in range(4):
+ self.ioexpander.configure_hdmi(i + 1, "1111")
+ self.ioexpander.clock_hdmi_output(i + 1, "chip")
+ time.sleep(1)
+ self.ioexpander.configure_hdmi(i + 1, "0000")
+ self.ioexpander.clock_hdmi_output(i + 1, "off")
+
+ def test_clock_lemo_output(self):
+ self.ioexpander.clock_lemo_output(True)
+ time.sleep(1)
+ self.ioexpander.clock_lemo_output(False)
+
+
+class Test_DacControl:
+ uhal.setLogLevelTo(uhal.LogLevel.NOTICE)
+ manager = uhal.ConnectionManager("file://../misc/aida_tlu_connection.xml")
+ hw = uhal.HwInterface(manager.getDevice("aida_tlu.controlhub"))
+
+ i2c = I2CCore(hw)
+ i2c.init()
+ dac_true = DacControl(i2c, True)
+ dac_false = DacControl(i2c, False)
+
+ def test_set_threshold(self) -> None:
+ for i in range(7):
+ for volts in np.arange(-1.3, 1.3, 1.3):
+ self.dac_true.set_threshold(i + 1, volts)
+ time.sleep(0.2)
+ self.dac_true.set_threshold(i + 1, 0)
+ time.sleep(0.5)
+ for i in range(7):
+ for volts in np.arange(-1.3, 1.3, 1.3):
+ self.dac_false.set_threshold(i + 1, volts)
+ time.sleep(0.2)
+ self.dac_false.set_threshold(i + 1, 0)
+
+ def test_set_voltage(self) -> None:
+ for i in range(4):
+ for volts in np.arange(0, 1, 0.5):
+ self.dac_true.set_voltage(i + 1, volts)
+ time.sleep(0.2)
+ self.dac_true.set_voltage(5, 0)
+
+
+class Test_ClockControl:
+ uhal.setLogLevelTo(uhal.LogLevel.NOTICE)
+ manager = uhal.ConnectionManager("file://../misc/aida_tlu_connection.xml")
+ hw = uhal.HwInterface(manager.getDevice("aida_tlu.controlhub"))
+ i2c = I2CCore(hw)
+ i2c.init()
+ ioexpander = IOControl(i2c)
+ clock = ClockControl(i2c, ioexpander)
+
+ def test_device_info(self) -> None:
+ self.clock.log.info("Device Version: %i" % self.clock.get_device_version())
+ self.clock.log.info("Design ID: %s" % self.clock.check_design_id())
+
+ def test_write_clock_register(self):
+ self.clock.write_clock_conf("../misc/aida_tlu_clk_config.txt")
+
+
+class Test_DUTLogic:
+ uhal.setLogLevelTo(uhal.LogLevel.NOTICE)
+ manager = uhal.ConnectionManager("file://../misc/aida_tlu_connection.xml")
+ hw = uhal.HwInterface(manager.getDevice("aida_tlu.controlhub"))
+
+ i2c = I2CCore(hw)
+ i2c.init()
+ dut = DUTLogic(i2c)
+
+ def test_set_dut_mask(self) -> None:
+ time.sleep(1)
+ self.dut.set_dut_mask("1010")
+ time.sleep(1)
+ self.dut.set_dut_mask("0000")
+
+ def test_set_dut_mask_mode(self):
+ self.dut.set_dut_mask_mode("00000000")
+ time.sleep(1)
+ self.dut.set_dut_mask_mode("11111111")
+ time.sleep(1)
+ self.dut.set_dut_mask_mode("01010101")
+
+ def test_set_dut_mask_modifier(self) -> None:
+ # TODO What input here?
+ self.dut.set_dut_mask_mode_modifier(1)
+ time.sleep(1)
+ self.dut.set_dut_mask_mode_modifier(0)
+
+ def test_set_dut_ignore_busy(self):
+ self.dut.set_dut_ignore_busy("1111")
+ time.sleep(1)
+ self.dut.set_dut_ignore_busy("0000")
+
+ def test_set_dut_ignore_busy(self) -> None:
+ self.dut.set_dut_ignore_shutter(0)
+
+
+class Test_TriggerLogic:
+ uhal.setLogLevelTo(uhal.LogLevel.NOTICE)
+ manager = uhal.ConnectionManager("file://../misc/aida_tlu_connection.xml")
+ hw = uhal.HwInterface(manager.getDevice("aida_tlu.controlhub"))
+
+ i2c = I2CCore(hw)
+ trigger = TriggerLogic(i2c)
+
+ def test_set_internal_trigger_frequency(self) -> None:
+ self.trigger.set_internal_trigger_frequency(0)
+ self.trigger.set_internal_trigger_frequency(10000)
+ self.trigger.set_internal_trigger_frequency(0)
+
+ def test_set_trigger_veto(self) -> None:
+ self.trigger.set_trigger_veto(True)
+ time.sleep(1)
+ self.trigger.set_trigger_veto(False)
+
+ def test_set_trigger_polarity(self):
+ self.trigger.set_trigger_polarity(1)
+ time.sleep(1)
+ self.trigger.set_trigger_polarity(0)
+
+ def test_set_trigger_mask(self):
+ self.trigger.set_trigger_mask(0b0, 0b1)
+ time.sleep(1)
+ self.trigger.set_trigger_mask(0b0, 0b0)
+
+ def test_set_pulse_stretch_pack(self) -> None:
+ self.trigger.set_pulse_stretch_pack([1, 1, 1, 1, 1, 1])
+ time.sleep(1)
+ self.trigger.set_pulse_stretch_pack([2, 2, 2, 2, 2, 2])
+
+ def test_set_pulse_delay_pack(self) -> None:
+ self.trigger.set_pulse_delay_pack([0, 0, 0, 0, 0, 0])
+ time.sleep(1)
+ self.trigger.set_pulse_delay_pack([1, 1, 1, 1, 1, 1])
+
+
+def test_run():
+ uhal.setLogLevelTo(uhal.LogLevel.NOTICE)
+ manager = uhal.ConnectionManager("file://.././misc/aida_tlu_connection.xml")
+ hw = uhal.HwInterface(manager.getDevice("aida_tlu.controlhub"))
+
+ config_path = "tlu_test_configuration.yaml"
+ clock_path = "../misc/aida_tlu_clk_config.txt"
+ tlu = AidaTLU(hw, config_path, clock_path)
+
+ tlu.configure()
+ tlu.run()
+
+
+if __name__ == "__main__":
+ test_io = Test_IOCControl()
+ test_io.test_clock_lemo_output()
+ test_io.test_configure_hdmi()
+ test_io.test_ioexpander_led()
+
+ test_dac = Test_DacControl()
+ test_dac.test_set_threshold()
+ test_dac.test_set_threshold()
+
+ test_dut = Test_DUTLogic()
+ test_dut.test_set_dut_ignore_busy()
+ test_dut.test_set_dut_mask()
+ test_dut.test_set_dut_mask_mode()
+ test_dut.test_set_dut_mask_modifier()
+
+ test_clock = Test_ClockControl()
+ test_clock.test_device_info()
+ test_clock.test_write_clock_register()
+
+ test_trigger = Test_TriggerLogic()
+ test_trigger.test_set_internal_trigger_frequency()
+ test_trigger.test_set_pulse_delay_pack()
+ test_trigger.test_set_pulse_stretch_pack()
+ test_trigger.test_set_trigger_mask()
+ test_trigger.test_set_trigger_polarity()
+ test_trigger.test_set_trigger_veto()
+
+ test_run = test_run()
diff --git a/aidatlu/test/interpreted_data.h5 b/aidatlu/test/interpreted_data.h5
new file mode 100644
index 0000000..f932b2a
Binary files /dev/null and b/aidatlu/test/interpreted_data.h5 differ
diff --git a/aidatlu/test/raw_data_test.h5 b/aidatlu/test/raw_data_test.h5
new file mode 100644
index 0000000..161a025
Binary files /dev/null and b/aidatlu/test/raw_data_test.h5 differ
diff --git a/aidatlu/test/software_test.py b/aidatlu/test/software_test.py
new file mode 100644
index 0000000..14b42b6
--- /dev/null
+++ b/aidatlu/test/software_test.py
@@ -0,0 +1,61 @@
+import numpy as np
+import tables as tb
+from aidatlu.main.data_parser import DataParser
+from aidatlu.main.config_parser import TLUConfigure
+
+
+def test_data_parser():
+ data_parser = DataParser()
+ data_parser.interpret_data("raw_data_test.h5", "interpreted_data_test.h5")
+
+
+def test_interpreted_data():
+ features = np.dtype(
+ [
+ ("eventnumber", "u4"),
+ ("timestamp", "u4"),
+ ("overflow", "u4"),
+ ("eventtype", "u4"),
+ ("input1", "u4"),
+ ("input2", "u4"),
+ ("input3", "u4"),
+ ("input4", "u4"),
+ ("inpu5", "u4"),
+ ("input6", "u4"),
+ ("sc1", "u4"),
+ ("sc2", "u4"),
+ ("sc3", "u4"),
+ ("sc4", "u4"),
+ ("sc5", "u4"),
+ ("sc6", "u4"),
+ ]
+ )
+
+ interpreted_data_path = "interpreted_data.h5"
+ interpreted_test_data_path = "interpreted_data_test.h5"
+
+ with tb.open_file(interpreted_data_path, "r") as file:
+ table = file.root.interpreted_data
+ interpreted_data = np.array(table[:], dtype=features)
+
+ with tb.open_file(interpreted_test_data_path, "r") as file:
+ table = file.root.interpreted_data
+ interpreted_test_data = np.array(table[:], dtype=features)
+
+ assert np.array_equal(interpreted_data, interpreted_test_data)
+
+
+def test_load_config():
+ config_path = "../tlu_configuration.yaml"
+ config_parser = TLUConfigure(TLU=None, io_control=None, config_path=config_path)
+ _ = config_parser.get_configuration_table()
+ _ = config_parser.get_data_handling()
+ _ = config_parser.get_output_data_path()
+ _ = config_parser.get_stop_condition()
+ _ = config_parser.get_zmq_connection()
+
+
+if __name__ == "__main__":
+ test_data_parser()
+ test_interpreted_data()
+ test_load_config()
diff --git a/aidatlu/test/tlu_test_configuration.yaml b/aidatlu/test/tlu_test_configuration.yaml
new file mode 100644
index 0000000..a5ebece
--- /dev/null
+++ b/aidatlu/test/tlu_test_configuration.yaml
@@ -0,0 +1,59 @@
+################################################
+#
+# This configuration is only used during tests
+#
+###############################################
+
+
+internal_trigger: #Generate TLU internal trigger with given rate in Hz
+ internal_trigger_rate: 100000
+
+dut_module:
+ dut_1:
+ mode: 'aida' # 'aida', 'aidatrig', 'eudet', 'any'
+ dut_2:
+ mode: 'off' # 'aida', 'aidatrig', 'eudet', 'any'
+ dut_3:
+ mode: 'off' # 'aida', 'aidatrig', 'eudet', 'any'
+ dut_4:
+ mode: 'off' # 'aida', 'aidatrig', 'eudet', 'any'
+
+trigger_inputs: #threshold voltages for the trigger inputs in V.
+ threshold:
+ threshold_1: -0.1
+ threshold_2: -0.1
+ threshold_3: -0.1
+ threshold_4: -0.1
+ threshold_5: -0.1
+ threshold_6: -0.1
+
+ # Trigger Logic configuration accept a python expression for the trigger inputs.
+ # The logic is set by using the variables for the input channels 'CH1', 'CH2', 'CH3', 'CH4', 'CH5' and 'CH6'
+ # and the Python bitwise operators AND: '&', OR: '|', NOT: '~' and so on. Dont forget to use brackets...
+ trigger_inputs_logic: CH1
+
+ trigger_polarity: #TLU triggers on rising (0) or falling (1) edge
+ polarity: 1
+
+ trigger_signal_shape: #Stretches and delays each trigger input signal for an number of clock cycles,
+ stretch: [2, 2, 2, 2, 2, 2]
+ delay: [0, 0, 0, 0, 0, 0]
+
+clock_lemo:
+ enable_clock_lemo_output: True
+
+pmt_control:
+ #PMT control voltages in V
+ pmt_1: 0.8
+ pmt_2: 0.8
+ pmt_3: 0
+ pmt_4: 0
+
+#Save data and generate interpreted data from the raw data set. Set to 'True' or 'False'.
+save_data: True
+output_data_path: 'test_output_data/'
+
+#zmq connection leave it blank or set to 'off' if not needed
+zmq_connection: 'off' #"tcp://:7500"
+
+timeout: 5
\ No newline at end of file
diff --git a/aidatlu/tlu.py b/aidatlu/tlu.py
deleted file mode 100644
index b9c711c..0000000
--- a/aidatlu/tlu.py
+++ /dev/null
@@ -1,38 +0,0 @@
-import logging
-
-import logger
-from i2c import I2CCore, i2c_addr
-from led_controller import LEDControl
-
-
-class AidaTLU(object):
- def __init__(self, hw) -> None:
- self.log = logger.setup_main_logger(__class__.__name__, logging.DEBUG)
-
- self.i2c = I2CCore(hw)
- self.i2c.init()
- if self.i2c.modules["eeprom"]:
- self.log.info("Found device with ID %s" % hex(self.get_device_id()))
- self.led_controller = LEDControl(self.i2c)
-
- # init pwrled
-
- # if present, init display
-
- def get_device_id(self) -> int:
- """Read back board id. Consists of six blocks of hex data
-
- Returns:
- int: Board id as 48 bits integer
- """
- id = []
- for addr in range(6):
- id.append(self.i2c.read(self.i2c.modules["eeprom"], 0xFA + addr) & 0xFF)
-
- return int("0x" + "".join(["{:x}".format(i) for i in id]), 16) & 0xFFFFFFFFFFFF
-
- def get_fw_version(self) -> int:
- return self.i2c.read_register("version")
-
- def init_power_leds(self) -> None:
- raise NotImplementedError("TODO")
diff --git a/aidatlu/tlu_configuration.yaml b/aidatlu/tlu_configuration.yaml
new file mode 100644
index 0000000..ce9e432
--- /dev/null
+++ b/aidatlu/tlu_configuration.yaml
@@ -0,0 +1,49 @@
+internal_trigger: #Generate TLU internal trigger with given rate in Hz
+ internal_trigger_rate: 10000
+
+dut_module:
+ dut_1:
+ mode: 'aida' # 'aida', 'aidatrig', 'eudet', 'any'
+ dut_2:
+ mode: 'aida' # 'aida', 'aidatrig', 'eudet', 'any'
+ dut_3:
+ mode: 'eudet' # 'aida', 'aidatrig', 'eudet', 'any'
+ dut_4:
+ mode: 'off' # 'aida', 'aidatrig', 'eudet', 'any'
+
+trigger_inputs: #threshold voltages for the trigger inputs in V.
+ threshold:
+ threshold_1: -0.1
+ threshold_2: -0.1
+ threshold_3: -0.1
+ threshold_4: -0.1
+ threshold_5: -0.1
+ threshold_6: -0.1
+
+ # Trigger Logic configuration accept a python expression for the trigger inputs.
+ # The logic is set by using the variables for the input channels 'CH1', 'CH2', 'CH3', 'CH4', 'CH5' and 'CH6'
+ # and the Python bitwise operators AND: '&', OR: '|', NOT: '~' and so on. Dont forget to use brackets...
+ trigger_inputs_logic: CH2 & CH4
+
+ trigger_polarity: #TLU triggers on rising (0) or falling (1) edge
+ polarity: 1
+
+ trigger_signal_shape: #Stretches and delays each trigger input signal for an number of clock cycles,
+ stretch: [2, 2, 2, 2, 2, 2]
+ delay: [0, 0, 0, 0, 0, 0]
+
+clock_lemo:
+ enable_clock_lemo_output: True
+pmt_control:
+ #PMT control voltages in V
+ pmt_1: 0.8
+ pmt_2: 0.8
+ pmt_3: 0
+ pmt_4: 0
+
+#Save data and generate interpreted data from the raw data set. Set to 'True' or 'False'.
+save_data: True
+output_data_path: '/media/data/ITK_DEBUG/tests_3/itk/chip_0/'
+
+#zmq connection leave it blank or set to 'off' if not needed
+zmq_connection: 'off' #"tcp://127.0.0.1:6500"
diff --git a/aidatlu/tlu_data/README.md b/aidatlu/tlu_data/README.md
new file mode 100644
index 0000000..6e6cd5f
--- /dev/null
+++ b/aidatlu/tlu_data/README.md
@@ -0,0 +1,2 @@
+Data folder to collect raw output data and interpreted data.
+The data format is: tlu_raw_runnumber_date or tlu_interpreted_runnumber_date.
\ No newline at end of file
diff --git a/docs/Makefile b/docs/Makefile
new file mode 100644
index 0000000..d0c3cbf
--- /dev/null
+++ b/docs/Makefile
@@ -0,0 +1,20 @@
+# Minimal makefile for Sphinx documentation
+#
+
+# You can set these variables from the command line, and also
+# from the environment for the first two.
+SPHINXOPTS ?=
+SPHINXBUILD ?= sphinx-build
+SOURCEDIR = source
+BUILDDIR = build
+
+# Put it first so that "make" without argument is like "make help".
+help:
+ @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+
+.PHONY: help Makefile
+
+# Catch-all target: route all unknown targets to Sphinx using the new
+# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS).
+%: Makefile
+ @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
diff --git a/docs/make.bat b/docs/make.bat
new file mode 100644
index 0000000..747ffb7
--- /dev/null
+++ b/docs/make.bat
@@ -0,0 +1,35 @@
+@ECHO OFF
+
+pushd %~dp0
+
+REM Command file for Sphinx documentation
+
+if "%SPHINXBUILD%" == "" (
+ set SPHINXBUILD=sphinx-build
+)
+set SOURCEDIR=source
+set BUILDDIR=build
+
+%SPHINXBUILD% >NUL 2>NUL
+if errorlevel 9009 (
+ echo.
+ echo.The 'sphinx-build' command was not found. Make sure you have Sphinx
+ echo.installed, then set the SPHINXBUILD environment variable to point
+ echo.to the full path of the 'sphinx-build' executable. Alternatively you
+ echo.may add the Sphinx directory to PATH.
+ echo.
+ echo.If you don't have Sphinx installed, grab it from
+ echo.https://www.sphinx-doc.org/
+ exit /b 1
+)
+
+if "%1" == "" goto help
+
+%SPHINXBUILD% -M %1 %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O%
+goto end
+
+:help
+%SPHINXBUILD% -M help %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O%
+
+:end
+popd
diff --git a/docs/source/Configuration.rst b/docs/source/Configuration.rst
new file mode 100644
index 0000000..57859d8
--- /dev/null
+++ b/docs/source/Configuration.rst
@@ -0,0 +1,7 @@
+.. mdinclude:: ../../aidatlu/README.md
+
+Configuration File
+**********************
+
+.. literalinclude:: ../../aidatlu/tlu_configuration.yaml
+ :language: yaml
\ No newline at end of file
diff --git a/docs/source/Documentation.rst b/docs/source/Documentation.rst
new file mode 100644
index 0000000..8b867f9
--- /dev/null
+++ b/docs/source/Documentation.rst
@@ -0,0 +1,353 @@
+Documentation
+==================
+
+.. image:: img/structure.png
+ :width: 600
+
+Introduction
+*************
+
+The documentation presented here describes a newly adapted Python based control system for the AIDA-2020 Trigger Logic Unit (TLU).
+This system is mostly based upon the EUDAQ2 TLU software (https://github.com/eudaq/eudaq/tree/master/user/tlu)
+with some additional features for better usability and integration into the SiLab-Bonn infrastructure.
+In the following the control of the different hardware components as well as additional features of the control software are described.
+And a rough summary of the original documentation (https://ohwr.org/project/fmc-mtlu) is presented.
+During developing the present software I stumbled over some technical details which are also shown below.
+
+Hardware
+********************
+
+Inter-Integrated Circuit I^2C
+---------------------------------
+
+The configuration of the different board features and hardware components goes via I^2C interface.
+This interface is widely used as a serial communication bus and provides the protocol for the Ethernet communication driver.
+IPbus (https://ipbus.web.cern.ch/doc/user/html/) allows the access to the FPGA hardware of the TLU.
+The user interface uHAL (https://ipbus.web.cern.ch/doc/user/html/software/uhalQuickTutorial.html) is a C++/Python library
+for all needed read/write hardware level functionality.
+Each register has an identifying address. The addresses can be found in a yaml file (take a look at /misc).
+The script i2c.py writes and reads bits to and from each of these registers.
+
+I/O Expander
+---------------------------------
+The TLU uses four I/O expander PCA9539PW.
+Each of these chips provide two 8-bit input output expansions and can be used in parallel.
+The 11 front panel LEDs are controlled by two expanders where the other two configure the 4 HDMI inputs and/or outputs of the DUT interfaces.
+To configure the chip and to set for e.q. the polarity of one of the 8-bit expansions a command byte is set to the register.
+Afterwards the actual data follows.
+The script ioexpander\_controller.py writes the command byte to the right expander.
+To control the four expanders the script uses an identifier for the two
+LED expanders (io\_exp = 1) and two output expanders (io\_exp = 2).
+To further differentiate each of the two expanders another identifier is used (exp\_id).
+
+Clock Chip
+---------------------------------
+A Si5345 is used for clock generation.
+This clock is used internally in for e.q. the trigger generation, but can also be distributed to each of the DUT's for synchronous operating mode.
+The chip allows the generation of internal triggers in principle up to 160 MHz.
+The trigger rate is calculated from clock intervals this leads to a rounding error for higher trigger frequencies.
+So higher trigger frequencies are shifted slightly.
+
+The clock chip needs to be configured. To do so a configuration file containing ~380 address-data pairs is written to the chip via I^2C.
+This configuration file can be generated by software (https://www.skyworksinc.com/en/application-pages/clockbuilder-pro-software).
+The default clock frequency using the default configuration file is 40 MHz. For now this frequency can not be changed.
+The script clock\_controller.py configures the chip.
+Most of the other functions are just used for bug fixing.
+
+Digital-Analog-Converter DAC
+---------------------------------
+To transform the different output and input voltages from digital signals to analog signals (or the other way around),
+three AD5665R DAC's are used.
+Here one DAC's is used for the photomultiplier (PMT) power outputs the other two for the threshold of the trigger inputs.
+According to the data sheet the DAC's have an internal reference voltage of 2.5 V.
+Nevertheless an external voltage of 1.3 V is set as default for all implemented user cases.
+Each DAC has four output pins that can be used in parallel.
+Functions to control the DAC's can be found in voltage\_controller.
+
+Power DAC's
++++++++++++++++
+The four output channels of one DAC are dedicated to the control voltage of the four different PMT power outputs.
+Each output has a range of 0 V to 1 V, using the external reference voltage.
+Where an internal reference voltage leads to a possible output voltage of up to 2 V.
+
+Power Module
++++++++++++++++++
+Four 4-pin LEMO connectors not only deliver a control voltage but also distribute power in general to the PMT's.
+The LEMO has the following pin connections.
+Pin 1 is used for 12 V general power, pin 2 is not connected.
+The control voltage is on pin 3 and has the range [0; 1] V.
+At last pin 4 is connected to ground.
+
+.. image:: img/4_pin_lemo.png
+ :width: 300
+
+Three green LEDs on the front panel indicate the correct functioning of the power module.
+The POWER LED for 12 V supply voltage, the other two are for 5 V voltage regulators.
+
+Threshold DAC's
++++++++++++++++++++
+To transform the analog signals of the 6 trigger inputs to digital signals two DAC's are in use.
+The first two inputs are connected to one DAC the last 4 to the other one.
+Each input channel is connected in reverse to the DAC input.
+A mapping in software corrects these connections.
+To set the threshold of one input channel one uses the function set\_threshold with the trigger input from 1 to 6
+and set the threshold to Volt. The threshold range is [-1.3; 1.3] V.
+The calculated voltage resolution is about 40 uV.
+These values correspond to the external reference voltage, as the default.
+Also some people say trigger input 2 has some glitches.
+
+DUT interfaces (HDMI connectors)
+---------------------------------
+Four HDMI connectors are used as the interface between the TLU and the different DUT devices.
+Each pin works bidirectional any two differential signal pairs can be set as output or input.
+The direction of the HDMI pins is set by two I/O expanders with the following signal pins.
+Where the first differential signal is a clock signal (CLK).
+This clock signal can be enabled/disabled and is provided either by the Clock Chip or directly from the FPGA clock.
+For now the clock from the FPGA does not work.
+Depending on the operating mode also different trigger words are sent through the clock line (e.q. trigger number in EUDET mode).
+The next signal is the content (CONT). This signal is used by the TLU to issue control commands.
+The BUSY signal is usually set by the DUT and raises a VETO for the generation of new trigger depending on operating mode.
+SPARE is only used by the AIDA mode and raises a reset signal at the start of runs and should also be driven by the TLU.
+Trigger (TRIG) is set by the TLU at default.
+Through the trigger line not only trigger signals are issued but also trigger words depending on the operating mode.
+Setting the correct polarity to these pins is essential for correct operation working of the TLU.
+One should also note that DUT interface should not be used in AIDA mode according to higher sources.
+
+.. image:: img/hdmi.png
+ :width: 400
+
+.. table::
+ :align: left
+
+ +---------+------------------+
+ |HDMI PIN | HDMI Signal Name |
+ +=========+==================+
+ |1 | CLK |
+ +---------+------------------+
+ |2 | GND |
+ +---------+------------------+
+ |3 | CLK* |
+ +---------+------------------+
+ |4 | CONT |
+ +---------+------------------+
+ |5 | GND |
+ +---------+------------------+
+ |6 | CONT* |
+ +---------+------------------+
+ |7 | BUSY |
+ +---------+------------------+
+ |8 | GND |
+ +---------+------------------+
+ |9 | BUSY* |
+ +---------+------------------+
+ |10 | SPARE |
+ +---------+------------------+
+ |11 | GND |
+ +---------+------------------+
+ |12 | SPARE* |
+ +---------+------------------+
+ |13 | n.c. |
+ +---------+------------------+
+ |14 | POWER |
+ +---------+------------------+
+ |15 | TRIG |
+ +---------+------------------+
+ |16 | TRIG* |
+ +---------+------------------+
+ |17 | GND |
+ +---------+------------------+
+ |18 | n.c. |
+ +---------+------------------+
+ |19 | n.c. |
+ +---------+------------------+
+
+DUT Logic
+---------------------------------
+The DUT logic in dut\_controller.py sets the DUT operating modes.
+Different DUT devices are enabled or disabled by the function set\_dut\_mask.
+One important thing is to only enable DUT interfaces that are in use.
+A not connected device configured in handshake mode blocks the working of the TLU.
+The operating mode is set by the function set\_dut\_mask\_mode each DUT is controlled by two bits in an 8-bit WORD.
+Bit 0 and 1 control DUT 1, bit 2 and 3 DUT 2 and so on. AIDA mode is set by setting the bits to 11 and EUDET mode by setting 00.
+So to set DUT 1 to AIDA mode and the rest to EUDET mode one hast to set the bit-WORD '00000011' to the function.
+
+Trigger Logic
+---------------------------------
+The TLU can produce valid triggers from six different trigger inputs.
+Each input can accept or veto new triggers.
+Between each trigger input there is also the possibility to set 'AND' or 'OR'.
+This leads to 64 possible combinations of so-called trigger words.
+Where each trigger word describes one specific trigger configuration.
+One obtains the resulting trigger configuration to write into the trigger logic register by adding up all desired valid trigger configurations.
+For example if one need triggers from input 1 or input 2.
+Than all valid trigger combinations, ignoring the inputs channels 3-6 are:
+
+.. table::
+ :align: left
+
+ +--------+---------+
+ |Input 1 | Input 2 |
+ +========+=========+
+ |1 | 0 |
+ +--------+---------+
+ |0 | 1 |
+ +--------+---------+
+ |1 | 1 |
+ +--------+---------+
+
+The software uses two different variants of these words.
+A long word variant which is just the 64-bit trigger word.
+For the second variant the long word is split into two 32-bit words (mask\_low and mask\_high).
+To help with the generation of these trigger words, the software uses a specific function to translate
+the trigger settings in the configuration file to these words.
+
+The trigger signals from the different trigger inputs can be stretched and delayed accounting for
+different trigger hardware setups.
+Also, the TLU can trigger on the rising or falling edge of incoming trigger signals.
+
+An additional feature of the trigger logic is the generation of internal triggers.
+In the configuration file a specific trigger frequency can be set and the TLU will then generate triggers with said frequency.
+The theoretical range of these triggers is between 0 Hz and 160 MHz.
+Because the trigger frequency is calculated in reference to a clock interval, there is for now a
+rounding error for higher frequency. This shifts the actual output trigger frequency.
+
+The number of triggers since the last trigger VETO is stored together with the
+total number of triggers per run.
+From these numbers general status messages for e.q. the trigger rate are generated.
+These status messages can also be distributed over a ZMQ socket using the online monitor.
+
+Operating Modes
+*****************
+The TLU runs in different operating modes. This allows more flexibility for different DUT readout setups.
+Different modes can provide clock synchronizations or distributes the trigger number together with the trigger signal.
+Each DUT can be run in different operating modes where a single one vetos new triggers for all devices.
+This vetoing for all devices can be disabled (but is not implemented).
+
+EUDET Handshake Mode
+---------------------------
+The TLU sets TRIGGER to high for 1 clock cycles. Afterwards the DUT asserts BUSY and sends a clock to the TLU through CLOCK.
+This clocks out the trigger number from the TLU to TRIGGER.
+To set the software to the EUDET operating mode a 0b00 is set to the according DUT logic.
+The clock output needs to be disabled for this mode to work.
+If the clock output is enabled then the trigger number is not clocked out correctly.
+Only the least significant 15 bit of the trigger word are sent out.
+
+AIDA Mode
+-----------
+In AIDA mode the clock of the TLU and the DUT is synchronized.
+For this the TLU clock needs to be distributed.
+The distribution of the clock via the LEMO has the problem that the clock signal form no longer arrives cleanly at the device.
+So distributing the clock usign the HDMI connectors is advised.
+An important step is to synchronize all delays (e.q. different cable length) of the clock signal with the trigger signal if encountered.
+
+At the start of a run the TLU sends out a RESET signal to the DUT.
+This signal can then be used by the DUT to synchronize the timestamp of the device and the TLU.
+Then the TLU sends triggers continuously to the DUT.
+Where each trigger signal has a length of one clock cycle.
+To generate a new trigger no answer of the DUT is needed.
+But the DUT can veto new trigger signals at any time by asserting BUSY.
+The following is a checklist for the working of the AIDA mode together with the (SiLab-Bonn) BDAQ board.
+
+ * AIDA Mode BDAQ Firmware. Here the external trigger clock is used also internally.
+ * Changes in testbench yaml.
+ * Change Trigger Mode from 3 to 2.
+ * Change Trigger Handshake Wait Cycle from 5 to 1.
+ * Use special clock cable configuration.
+ So enable the clock LEMO output of the TLU
+ and connect the clock output to the BDAQ board.
+ Or use special HDMI RJ45 AIDA mode adapter.
+ * Check Cable lengths to synchronize clock and trigger signals.
+ * Note when starting triggering,
+ the DUT scan needs to be started before the TLU scan for the timestamp
+ RESET to arrive.
+ * For now also the AIDA mode needs to be enabled in the scan configurations.
+ This can for now only be found on a special TJ DAQ branch.
+ Or in the testbench yaml, depending on the setup there is to enable RESET option.
+
+If only one BDAQ board is used in AIDA mode there is a chance for two very fast trigger to occur right one after the other.
+If the distance between the triggers is smaller than the distance between the first trigger signal and the BUSY signal.
+Then the tlu sends out two triggers because no handshake is awaited.
+This leads to an event number drift.
+This can be prevented by stretching the trigger input signal by some clock cycles.
+Another important thing is to follow the procedure for starting an AIDA run:
+
+ * configure TLU
+ * start all DUT's, telescopes and time reference plane scans
+ * start TLU run
+
+AIDA Mode with Trigger Number
+---------------------------------
+This operating mode is an extension of the AIDA mode.
+The difference to the standard AIDA mode is, that additionally at each trigger
+the trigger number is sent through RESET.
+
+Additional features
+********************
+
+Online Monitor
+----------------
+The Online Monitor (https://github.com/SiLab-Bonn/online_monitor) creates real-time plots of a dataset.
+This allows live observation of the trigger rate during operation.
+The TLU scripts sends status information containing the trigger rate, event number, trigger number and run time to a converter script.
+The converter script translates the data format and sends the data to a receiver script.
+The online monitor uses a receiver script to create the real time data plots.
+The Data is sent and received using ZMQ sockets (https://zeromq.org/).
+The ZMQ connection can be enabled and disabled in the configuration file.
+To start the online monitor one navigates to the directory and uses for e.q. the terminal command:
+
+.. code-block:: console
+
+ start_online_monitor configuration.yaml
+
+Another command reliable stops all instances of the running online monitor:
+
+.. code-block:: console
+
+ stop_online_monitor
+
+Tests
+------
+With pytest (https://docs.pytest.org/en/7.4.x/) the AIDA TLU control program can be tested.
+In the test directory different testing scripts can be found.
+The easiest way to test the whole setup it to navigate to the directory and type pytest into the terminal.
+This starts a series of testing functions that start and stop different aspects of the control software.
+The test setup helps to find bugs when further developing the TLU program and also to check for depreciated functions.
+For now this testing needs a functioning connection to a AIDA TLU.
+The command:
+
+.. code-block:: console
+
+ pytest
+
+executes the complete testing infrastructure.
+But also the individual log outputs can be displayed.
+
+.. code-block:: console
+
+ pytest -o log_cli=True
+
+Tests can be run individually.
+
+.. code-block:: console
+
+ pytest software_test.py
+
+Log Level
+------
+To set different log levels change the default log level in logger.py 'setup_main_logger' and 'setup_derived_logger'.
+
+Integration into EUDAQ2
+------------------------
+Due to the similarities of the python control software and the established EUDAQ TLU software
+an integration into EUDAQ2 is possible.
+The TLUPyProducer.py is an example skeleton of such integration.
+
+Testing setup
+--------------------------
+A small test setup inside the lab is realized using a Pulse Generator.
+With this pseudo scintillator pulses are generated.
+The TLU then processes these pulses and sends them to one or multiple BDAQ boards.
+One can then compare the Data recorded inside the TLU with the one recorded on the BDAQ boards.
+
+.. image:: img/test_setup_2.png
+ :width: 650
\ No newline at end of file
diff --git a/docs/source/Introduction.rst b/docs/source/Introduction.rst
new file mode 100644
index 0000000..fa518fc
--- /dev/null
+++ b/docs/source/Introduction.rst
@@ -0,0 +1,9 @@
+
+
+.. mdinclude:: ../../README.md
+
+Structure and communications of the AIDA 202 TLU python control software.
+
+.. image:: img/structure_software.png
+ :width: 600
+
diff --git a/docs/source/conf.py b/docs/source/conf.py
new file mode 100644
index 0000000..8f0001a
--- /dev/null
+++ b/docs/source/conf.py
@@ -0,0 +1,70 @@
+# Configuration file for the Sphinx documentation builder.
+#
+# For the full list of built-in configuration values, see the documentation:
+# https://www.sphinx-doc.org/en/master/usage/configuration.html
+
+# -- Project information -----------------------------------------------------
+# https://www.sphinx-doc.org/en/master/usage/configuration.html#project-information
+
+
+with open("../../VERSION") as version_file:
+ version = version_file.read().strip()
+
+project = "AIDA-TLU"
+copyright = "2023, SiLab, Institute of Physics, University of Bonn"
+author = "Rasmus Partzsch"
+release = version
+
+import sys
+import os
+
+# If extensions (or modules to document with autodoc) are in another directory,
+# add these directories to sys.path here. If the directory is relative to the
+# documentation root, use os.path.abspath to make it absolute, like shown here.
+sys.path.insert(0, os.path.abspath("../aidatlu"))
+sys.path.insert(0, os.path.abspath("../aidatlu/hardware"))
+sys.path.insert(0, os.path.abspath("../aidatlu/main"))
+
+# -- General configuration ---------------------------------------------------
+# https://www.sphinx-doc.org/en/master/usage/configuration.html#general-configuration
+
+extensions = [
+ "sphinx.ext.napoleon",
+ "sphinx.ext.doctest",
+ "sphinx.ext.autodoc",
+ "sphinx.ext.autosummary",
+ "sphinx.ext.todo",
+ "sphinx_mdinclude",
+ "sphinx.ext.viewcode",
+]
+
+autosectionlabel_prefix_document = True
+
+templates_path = ["_templates"]
+exclude_patterns = []
+
+
+source_suffix = {
+ ".rst": "restructuredtext",
+ ".txt": "markdown",
+ ".md": "markdown",
+}
+
+autodoc_mock_imports = ["hardware", "DutLogic", "main", "uhal"]
+
+# -- Options for HTML output -------------------------------------------------
+# https://www.sphinx-doc.org/en/master/usage/configuration.html#options-for-html-output
+
+html_theme = "pydata_sphinx_theme"
+html_static_path = ["_static"]
+
+html_theme_options = {
+ # [...]
+ # "show_toc_level": 2,
+ # "show_nav_level": 3,
+ "primary_sidebar_end": ["indices.html", "sidebar-ethical-ads.html"],
+ "secondary_sidebar_items": [],
+ # [...]
+}
+
+html_sidebars = {"*": ["page-toc", "edit-this-page", "sourcelink"]}
diff --git a/docs/source/hardware_code.rst b/docs/source/hardware_code.rst
new file mode 100644
index 0000000..bccfdb3
--- /dev/null
+++ b/docs/source/hardware_code.rst
@@ -0,0 +1,40 @@
+
+Hardware Level
+========================
+
+Clock Control
+--------------------
+
+.. autoclass:: aidatlu.hardware.clock_controller.ClockControl
+ :members:
+
+DAC Control
+--------------------
+
+.. autoclass:: aidatlu.hardware.dac_controller.DacControl
+ :members:
+
+DUT Control
+--------------------
+
+.. autoclass:: aidatlu.hardware.dut_controller.DUTLogic
+ :members:
+
+I2C
+--------------------
+
+.. autoclass:: aidatlu.hardware.i2c.I2CCore
+ :members:
+
+IO Expander Control
+--------------------
+
+.. autoclass:: aidatlu.hardware.ioexpander_controller.IOControl
+ :members:
+
+Trigger Control
+--------------------
+
+.. autoclass:: aidatlu.hardware.trigger_controller.TriggerLogic
+ :members:
+
diff --git a/docs/source/img/4_pin_lemo.png b/docs/source/img/4_pin_lemo.png
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diff --git a/docs/source/img/hdmi.png b/docs/source/img/hdmi.png
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diff --git a/docs/source/img/structure.png b/docs/source/img/structure.png
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diff --git a/docs/source/img/structure_software.png b/docs/source/img/structure_software.png
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diff --git a/docs/source/img/test_setup_2.png b/docs/source/img/test_setup_2.png
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diff --git a/docs/source/index.rst b/docs/source/index.rst
new file mode 100644
index 0000000..e1cee5c
--- /dev/null
+++ b/docs/source/index.rst
@@ -0,0 +1,26 @@
+.. AIDATLU documentation master file, created by
+ sphinx-quickstart on Mon Nov 20 13:34:00 2023.
+ You can adapt this file completely to your liking, but it should at least
+ contain the root `toctree` directive.
+
+Welcome to AIDA-TLU's documentation!
+=====================================
+
+.. toctree::
+ :maxdepth: 2
+
+ Introduction
+ Configuration
+ Documentation
+
+.. toctree::
+ :maxdepth: 1
+
+ hardware_code
+ main_code
+
+Indices and tables
+==================
+
+* :ref:`genindex`
+* :ref:`search`
diff --git a/docs/source/main_code.rst b/docs/source/main_code.rst
new file mode 100644
index 0000000..3d375c4
--- /dev/null
+++ b/docs/source/main_code.rst
@@ -0,0 +1,21 @@
+
+Main Level
+====================
+
+Trigger Logic Unit
+####################
+
+.. autoclass:: aidatlu.main.tlu.AidaTLU
+ :members:
+
+Configuration Parser
+####################
+
+.. autoclass:: aidatlu.main.config_parser.TLUConfigure
+ :members:
+
+Data Parser
+####################
+
+.. autoclass:: aidatlu.main.data_parser.DataParser
+ :members:
diff --git a/miniTLU/.ftpconfig b/miniTLU/.ftpconfig
deleted file mode 100644
index 100a040..0000000
--- a/miniTLU/.ftpconfig
+++ /dev/null
@@ -1,20 +0,0 @@
-{
- "protocol": "sftp",
- "host": "fortis.phy.bris.ac.uk",
- "port": 22,
- "user": "phpgb",
- "pass": "",
- "promptForPass": true,
- "remote": "/users/phpgb/worklib/fmc-mtlu/firmware/scripts/",
- "local": "",
- "agent": "",
- "privatekey": "",
- "passphrase": "",
- "hosthash": "",
- "ignorehost": true,
- "connTimeout": 10000,
- "keepalive": 10000,
- "keyboardInteractive": false,
- "watch": [],
- "watchTimeout": 500
-}
diff --git a/miniTLU/FmcTluI2c.py b/miniTLU/FmcTluI2c.py
deleted file mode 100644
index 04bf598..0000000
--- a/miniTLU/FmcTluI2c.py
+++ /dev/null
@@ -1,132 +0,0 @@
-import time
-#from PyChipsUser import *
-from I2cBusProperties import *
-from RawI2cAccess import *
-
-
-class FmcTluI2c:
-
-
- ############################
- ### configure i2c connection
- ############################
- def __init__(self,board):
- self.board = board
- i2cClockPrescale = 0x30
- self.i2cBusProps = I2cBusProperties(self.board, i2cClockPrescale)
- return
-
-
- ##########################
- ### scan all i2c addresses
- ##########################
- def i2c_scan(self):
- list=[]
- for islave in range(128):
- i2cscan = RawI2cAccess(self.i2cBusProps, islave)
- try:
- i2cscan.write([0x00])
- device="slave address "+hex(islave)+" "
- if islave==0x1f:
- device+="(DAC)"
- elif islave==0x50:
- device+="(serial number PROM)"
- elif islave>=0x54 and islave<=0x57:
- device+="(sp601 onboard EEPROM)"
- else:
- device+="(???)"
- pass
- list.append(device)
- pass
- except:
- pass
- pass
- return list
-
-
- ###################
- ### write to EEPROM
- ###################
- def eeprom_write(self,address,value):
- if address<0 or address>127:
- print "eeprom_write ERROR: address",address,"not in range 0-127"
- return
- if value<0 or value>255:
- print "eeprom_write ERROR: value",value,"not in range 0-255"
- return
- i2cSlaveAddr = 0x50 # seven bit address, binary 1010000
- prom = RawI2cAccess(self.i2cBusProps, i2cSlaveAddr)
- prom.write([address,value])
- time.sleep(0.01) # write cycle time is 5ms. let's wait 10 to make sure.
- return
-
-
- ####################
- ### read from EEPROM
- ####################
- def eeprom_read(self,address):
- if address<0 or address>255:
- print "eeprom_write ERROR: address",address,"not in range 0-127"
- return
- i2cSlaveAddr = 0x50 # seven bit address, binary 1010000
- prom = RawI2cAccess(self.i2cBusProps, i2cSlaveAddr)
- prom.write([address])
- return prom.read(1)[0]
-
-
- ######################
- ### read serial number
- ######################
- def get_serial_number(self):
- result=""
- for iaddr in [0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff]:
- result+="%02x "%(self.eeprom_read(iaddr))
- pass
- return result
-
-
- #################
- ### set DAC value
- #################
- def set_dac(self,channel,value , vrefOn = 0 , i2cSlaveAddrDac = 0x1F):
- if channel<0 or channel>7:
- print "set_dac ERROR: channel",channel,"not in range 0-7 (bit mask)"
- return -1
- if value<0 or value>0xFFFF:
- print "set_dac ERROR: value",value,"not in range 0-0xFFFF"
- return -1
- # AD5665R chip with A0,A1 tied to ground
- #i2cSlaveAddrDac = 0x1F # seven bit address, binary 00011111
- print "I2C address of DAC = " , hex(i2cSlaveAddrDac)
- dac = RawI2cAccess(self.i2cBusProps, i2cSlaveAddrDac)
- # if we want to enable internal voltage reference:
- if vrefOn:
- # enter vref-on mode:
- print "Turning internal reference ON"
- dac.write([0x38,0x00,0x01])
- else:
- print "Turning internal reference OFF"
- dac.write([0x38,0x00,0x00])
- # now set the actual value
- sequence=[( 0x18 + ( channel &0x7 ) ) , (value/256)&0xff , value&0xff]
- print sequence
- dac.write(sequence)
-
-
-
- ##################################################
- ### convert required threshold voltage to DAC code
- ##################################################
- def convert_voltage_to_dac(self, desiredVoltage, Vref=1.300):
- Vdaq = ( desiredVoltage + Vref ) / 2
- dacCode = 0xFFFF * Vdaq / Vref
- return int(dacCode)
-
-
- ##################################################
- ### calculate the DAC code required and set DAC
- ##################################################
- def set_threshold_voltage(self, channel , voltage ):
- dacCode = self.convert_voltage_to_dac(voltage)
- print " requested voltage, calculated DAC code = " , voltage , dacCode
- self.set_dac(channel , dacCode)
diff --git a/miniTLU/I2CuHal.py b/miniTLU/I2CuHal.py
deleted file mode 100644
index 694c9ef..0000000
--- a/miniTLU/I2CuHal.py
+++ /dev/null
@@ -1,1000 +0,0 @@
-"""
-solidfpa.py provides functionality to control the front end boards currently
-being prototyped.
-
-For the ADC:
- One or more LTM9007 ADCs can be controlled via the IPbus SPI block.
- Each chip is really two four channel ADCs, with each controlled with a
- separate chip select line. Bank A is channels 1, 4, 5, 8.
- Bank B is 2, 3, 6, 7.
-
- Control is via a simple SPI interface where 16 bits are transferred.
- b0 is read/!write
- b7:1 are the register address
- b15:b8 are the data sent to/from the ADC
-
- If the ADC.cehckwrite flag is True then all write commands will immediately
- be confirmed by a read command to the same address.
-"""
-
-import time
-
-import uhal
-
-verbose = True
-"""
-class SoLidFPGA:
-
- def __init__(self, board, nadc=4, verbose=False, minversion=None):
- cm = uhal.ConnectionManager("file://solidfpga.xml")
- self.target = cm.getDevice(board)
- #self.config()
- self.offsets = TimingOffsets(self.target)
- self.trigger = Trigger(self.target)
- self.databuffer = OutputBuffer(self.target)
- self.spi = SPICore(self.target, 31.25e6, 100e3)
- self.clock_i2c = I2CCore(self.target, 31.25e6, 40e3, "io.clock_i2c")
- self.analog_i2c = I2CCore(self.target, 31.25e6, 40e3, "io.analog_i2c")
- self.clockchip = Si5326(self.clock_i2c)
- self.adcs = []
- for i in range(1):
- self.adcs.append(ADCLTM9007(self.spi, 2 * i, 2 * i + 1))
- # For board Wim sent to Bristol for testing the MCP4725 address seems
- # to be 0b1100001, whereas for the first test board the address was
- # 0b1100111.
- self.gdac = DACMCP4725(self.analog_i2c, 0b1100001, 4.45)
- self.trimdacs = [
- DACMCP4728(self.analog_i2c, 0b1100011, 4.45),
- DACMCP4728(self.analog_i2c, 0b1100101, 4.45)
- ]
- self.temp = TempMCP9808(self.analog_i2c)
- self.firmwareversion = None
- self.minversion = minversion
- self.config(7, 16)
-
- def config(self, slip, tap):
- # check ID
- boardid = self.target.getNode("ctrl_reg.id").read()
- stat = self.target.getNode("ctrl_reg.stat").read()
- self.target.dispatch()
- if verbose:
- print "ID = 0x%x, stat = 0x%x" % (boardid, stat)
- self.id = (boardid & 0xffff0000) >> 16
- self.firmwareversion = boardid & 0x0000ffff
- if self.minversion is not None:
- msg = "Old version of firmware (v%d) running, require >= v%d." % (
- self.firmwareversion, self.minversion)
- assert self.firmwareversion >= self.minversion, msg
- self.spi.config()
- self.clock_i2c.config()
- self.analog_i2c.config()
- # Check for 40 MHz clock lock
- lock = self.target.getNode("ctrl_reg.stat.mmcm_locked").read()
- self.target.dispatch()
- #assert lock == 1, "No 40 MHz clock clock, code not yet moved to frontend.py"
- if lock != 1:
- # Config clock chip
- self.clockchip.config("siclock/si5326.txt")
- time.sleep(1.0)
- lock = self.target.getNode("ctrl_reg.stat.mmcm_locked").read()
- self.target.dispatch()
- assert lock == 1, "No 40 MHz clock clock, Si53266 configuration must have failed."
- # Reset clock
- timing_rst = self.target.getNode("timing.csr.ctrl.rst")
- timing_rst.write(0x1)
- self.target.dispatch()
- timing_rst.write(0x0)
- self.target.dispatch()
- lock = False
- while not lock:
- lock = self.target.getNode("ctrl_reg.stat.mmcm_locked").read()
- self.target.dispatch()
- clkcount = self.target.getNode("io.freq_ctr.freq.count").read()
- self.target.dispatch()
- freq = int(clkcount) / 8388.608 # not sure why, from Lukas
- if verbose:
- print "Frequency = %g MHz" % freq
- assert freq > 39 and freq < 41
- # Configure trigger block
- self.trigger.config()
- # Set timing offset on inputs from ADC
- self.offsets.setoffset(slip, tap)
- for adc in self.adcs:
- adc.config()
- print "Analog board temperature = %g C." % self.temp.temp()
-
- def reset(self, slip=7, tap=16):
- if verbose:
- print "Resetting board."
- # Soft reset
- soft_rst = self.target.getNode("ctrl_reg.ctrl.soft_rst")
- soft_rst.write(1)
- soft_rst.write(0)
- self.target.dispatch()
- time.sleep(1.0)
- if verbose:
- print "Reset complete."
- self.config(slip, tap)
-
- def readvoltages(self):
- bias = self.gdac.readbias()
- print "Global bias = %g V" % bias
- trims = "Channel trims:\n"
- ichan = 0
- for dac in self.trimdacs:
- voltages = dac.readvoltages()
- for v in voltages:
- trims += " Chan %d, v = %g V\n" % (ichan, v)
- ichan += 1
- print trims
-
- def bias(self, bias):
- self.gdac.setbias(bias)
-
- def trim(self, trim):
- for i in range(4):
- for trimdac in self.trimdacs:
- trimdac.setvoltage(i, trim)
-
- def trims(self, trims):
- for chan in trims:
- trim = trims[chan]
- ndac = chan / 4
- nchan = chan % 4
- self.trimdacs[ndac].setvoltage(nchan, trim)
-
-# IPbus blocks
-class TimingOffsets:
- #Timing offsets for the ADC data deserialisation.
-
- def __init__(self, target):
- self.target = target
-
- def setoffset(self, slip=7, tap=16):
- if verbose:
- print "Setting timing offset with channel slip = %d and %d taps." % (slip, tap)
- chan_slip = self.target.getNode("timing.csr.ctrl.chan_slip")
- for i in range(slip):
- chan_slip.write(1)
- self.target.dispatch()
- chan_slip.write(0)
- self.target.dispatch()
- chan_inc = self.target.getNode("timing.csr.ctrl.chan_inc")
- for i in range(tap):
- chan_inc.write(1)
- self.target.dispatch()
- chan_inc.write(0)
- self.target.dispatch()
-
-class Trigger:
-
- def __init__(self, target, nsamples=0x800):
- self.target = target
- self.nsamples = nsamples
- self.capture = target.getNode("timing.csr.ctrl.chan_cap")
- self.chanselect = target.getNode("ctrl_reg.ctrl.chan")
- self.fifo = target.getNode("chan.fifo")
-
- def config(self):
- # Set up channels
- for i in range(8):
- self.target.getNode("ctrl_reg.ctrl.chan").write(i)
- self.target.getNode("chan.csr.ctrl.en_sync").write(1)
- self.target.dispatch()
-
- def trigger(self):
- data = []
- self.capture.write(1)
- self.capture.write(0)
- self.target.dispatch()
- for i in range(8):
- self.chanselect.write(i)
- wf = self.fifo.readBlock(self.nsamples)
- self.target.dispatch()
- data.append(wf)
- return data
-
-class OutputBuffer:
- #Output data block.
-
- def __init__(self, target):
- self.target = target
-"""
-
-
-################################################################################
-# /*
-# I2C CORE
-# */
-################################################################################
-
-
-
-"""
-I2C core XML:
-
-
-
-
-
-
-
-
-
-"""
-class I2CCore:
- """I2C communication block."""
-
- # Define bits in cmd_stat register
- startcmd = 0x1 << 7
- stopcmd = 0x1 << 6
- readcmd = 0x1 << 5
- writecmd = 0x1 << 4
- ack = 0x1 << 3
- intack = 0x1
-
- recvdack = 0x1 << 7
- busy = 0x1 << 6
- arblost = 0x1 << 5
- inprogress = 0x1 << 1
- interrupt = 0x1
-
- def __init__(self, target, wclk, i2cclk, name="i2c", delay=None):
- self.target = target
- self.name = name
- self.delay = delay
- self.prescale_low = self.target.getNode("%s.i2c_pre_lo" % name)
- self.prescale_high = self.target.getNode("%s.i2c_pre_hi" % name)
- self.ctrl = self.target.getNode("%s.i2c_ctrl" % name)
- self.data = self.target.getNode("%s.i2c_rxtx" % name)
- self.cmd_stat = self.target.getNode("%s.i2c_cmdstatus" % name)
- self.wishboneclock = wclk
- self.i2cclock = i2cclk
- self.config()
-
- def state(self):
- status = {}
- status["ps_low"] = self.prescale_low.read()
- status["ps_hi"] = self.prescale_high.read()
- status["ctrl"] = self.ctrl.read()
- status["data"] = self.data.read()
- status["cmd_stat"] = self.cmd_stat.read()
- self.target.dispatch()
- status["prescale"] = status["ps_hi"] << 8
- status["prescale"] |= status["ps_low"]
- for reg in status:
- val = status[reg]
- bval = bin(int(val))
- if verbose:
- print "reg %s = %d, 0x%x, %s" % (reg, val, val, bval)
-
- def clearint(self):
- self.ctrl.write(0x1)
- self.target.dispatch()
-
- def config(self):
- #INITIALIZATION OF THE I2S MASTER CORE
- #Disable core
- self.ctrl.write(0x0 << 7)
- self.target.dispatch()
- #Write pre-scale register
- #prescale = int(self.wishboneclock / (5.0 * self.i2cclock)) - 1
- prescale = 0x30 #FOR NOW HARDWIRED, TO BE MODIFIED
- self.prescale_low.write(prescale & 0xff)
- self.prescale_high.write((prescale & 0xff00) >> 8)
- #Enable core
- self.ctrl.write(0x1 << 7)
- self.target.dispatch()
-
- def checkack(self):
- inprogress = True
- ack = False
- while inprogress:
- cmd_stat = self.cmd_stat.read()
- self.target.dispatch()
- inprogress = (cmd_stat & I2CCore.inprogress) > 0
- ack = (cmd_stat & I2CCore.recvdack) == 0
- return ack
-
- def delayorcheckack(self):
- ack = True
- if self.delay is None:
- ack = self.checkack()
- else:
- time.sleep(self.delay)
- ack = self.checkack()#Remove this?
- return ack
-
-################################################################################
-# /*
-# I2C WRITE
-# */
-################################################################################
-
-
-
- def write(self, addr, data, stop=True):
- """Write data to the device with the given address."""
- # Start transfer with 7 bit address and write bit (0)
- nwritten = -1
- addr &= 0x7f
- addr = addr << 1
- startcmd = 0x1 << 7
- stopcmd = 0x1 << 6
- writecmd = 0x1 << 4
- #Set transmit register (write operation, LSB=0)
- self.data.write(addr)
- #Set Command Register to 0x90 (write, start)
- self.cmd_stat.write(I2CCore.startcmd | I2CCore.writecmd)
- self.target.dispatch()
- ack = self.delayorcheckack()
- if not ack:
- self.cmd_stat.write(I2CCore.stopcmd)
- self.target.dispatch()
- return nwritten
- nwritten += 1
- for val in data:
- val &= 0xff
- #Write slave memory address
- self.data.write(val)
- #Set Command Register to 0x10 (write)
- self.cmd_stat.write(I2CCore.writecmd)
- self.target.dispatch()
- ack = self.delayorcheckack()
- if not ack:
- self.cmd_stat.write(I2CCore.stopcmd)
- self.target.dispatch()
- return nwritten
- nwritten += 1
- if stop:
- self.cmd_stat.write(I2CCore.stopcmd)
- self.target.dispatch()
- return nwritten
-
-################################################################################
-# /*
-# I2C READ
-# */
-################################################################################
-
-
-
- def read(self, addr, n):
- """Read n bytes of data from the device with the given address."""
- # Start transfer with 7 bit address and read bit (1)
- data = []
- addr &= 0x7f
- addr = addr << 1
- addr |= 0x1 # read bit
- self.data.write(addr)
- self.cmd_stat.write(I2CCore.startcmd | I2CCore.writecmd)
- self.target.dispatch()
- ack = self.delayorcheckack()
- if not ack:
- self.cmd_stat.write(I2CCore.stopcmd)
- self.target.dispatch()
- return data
- for i in range(n):
- self.cmd_stat.write(I2CCore.readcmd)
- self.target.dispatch()
- ack = self.delayorcheckack()
- val = self.data.read()
- self.target.dispatch()
- data.append(val & 0xff)
- self.cmd_stat.write(I2CCore.stopcmd)
- self.target.dispatch()
- return data
-
-################################################################################
-# /*
-# I2C WRITE-READ
-# */
-################################################################################
-
-
-
- def writeread(self, addr, data, n):
- """Write data to device, then read n bytes back from it."""
- nwritten = self.write(addr, data, stop=False)
- readdata = []
- if nwritten == len(data):
- readdata = self.read(addr, n)
- return nwritten, readdata
-
-"""
-SPI core XML:
-
-
-
-
-
-
-
-
-
-
-"""
-class SPICore:
-
- go_busy = 0x1 << 8
- rising = 1
- falling = 0
-
-
- def __init__(self, target, wclk, spiclk, basename="io.spi"):
- self.target = target
- # Only a single data register is required since all transfers are
- # 16 bit long
- self.data = target.getNode("%s.d0" % basename)
- self.control = target.getNode("%s.ctrl" % basename)
- self.control_val = 0b0
- self.divider = target.getNode("%s.divider" % basename)
- self.slaveselect = target.getNode("%s.ss" % basename)
- self.divider_val = int(wclk / spiclk / 2.0 - 1.0)
- self.divider_val = 0x7f
- self.configured = False
-
- def config(self):
- "Configure SPI interace for communicating with ADCs."
- self.divider_val = int(self.divider_val) % 0xffff
- if verbose:
- print "Configuring SPI core, divider = 0x%x" % self.divider_val
- self.divider.write(self.divider_val)
- self.target.dispatch()
- self.control_val = 0x0
- self.control_val |= 0x0 << 13 # Automatic slave select
- self.control_val |= 0x0 << 12 # No interrupt
- self.control_val |= 0x0 << 11 # MSB first
- # ADC samples data on rising edge of SCK
- self.control_val |= 0x1 << 10 # change ouput on falling edge of SCK
- # ADC changes output shortly after falling edge of SCK
- self.control_val |= 0x0 << 9 # read input on rising edge
- self.control_val |= 0x10 # 16 bit transfers
- if verbose:
- print "SPI control val = 0x%x = %s" % (self.control_val, bin(self.control_val))
- self.configured = True
-
- def transmit(self, chip, value):
- if not self.configured:
- self.config()
- assert chip >= 0 and chip < 8
- value &= 0xffff
- self.data.write(value)
- checkdata = self.data.read()
- self.target.dispatch()
- assert checkdata == value
- self.control.write(self.control_val)
- self.slaveselect.write(0xff ^ (0x1 << chip))
- self.target.dispatch()
- self.control.write(self.control_val | SPICore.go_busy)
- self.target.dispatch()
- busy = True
- while busy:
- status = self.control.read()
- self.target.dispatch()
- busy = status & SPICore.go_busy > 0
- self.slaveselect.write(0xff)
- data = self.data.read()
- ss = self.slaveselect.read()
- status = self.control.read()
- self.target.dispatch()
- #print "Received data: 0x%x, status = 0x%x, ss = 0x%x" % (data, status, ss)
- return data
-"""
- print "Data to send: 0x%x = %s" % (checkdata, bin(int(checkdata)))
- ss = 0x1 << chip
- nss = ss ^ 0xffff
- print "chip = %d, nSS = 0x%x = %s" % (chip, nss, bin(nss))
- ctrl = self.control.read()
- self.target.dispatch()
- busy = (ctrl & SPICore.go_busy) > 0
- while busy:
- ctrl = self.control.read()
- self.target.dispatch()
- busy = (ctrl & SPICore.go_busy) > 0
- self.slaveselect.write(nss)
- self.target.dispatch()
- self.control.write(self.control_val)
- self.target.dispatch()
- self.control.write(self.control_val | SPICore.go_busy)
- self.target.dispatch()
- time.sleep(0.1)
- ncheck = 0
- finished = False
- while not finished:
- ctrl = self.control.read()
- self.target.dispatch()
- # Check if transfer is complete by reading the GO_BSY bit of CTRL
- finished = (ctrl & SPICore.go_busy) == 0
- ncheck += 1
- # assert ncheck < 10, "ctrl = 0x%x, %s finished = %s" % (ctrl, bin(int(ctrl)), str(finished))
- # time.sleep(0.1)
- print "%d checks before busy not asserted." % ncheck
- self.slaveselect.write(0xffff)
- self.target.dispatch()
- ss = self.slaveselect.read()
- data = self.data.read()
- self.target.dispatch()
- print "After transmit, ss = 0x%x" % ss
- print "Received 0x%x = %s" % (data, bin(int(data)))
- time.sleep(0.1)
- return data
-"""
-
-# External chips
-
-class Si5326:
-
- def __init__(self, i2c, slaveaddr=0b1101000):
- self.i2c = i2c
- self.slaveaddr = slaveaddr
-
- def config(self, fn):
- if verbose:
- print "Loading Si5326 configuration from %s" % fn
- inp = open(fn, "r")
- inmap = False
- regvals = {}
- for line in inp:
- if inmap:
- if "END_REGISTER_MAP" in line:
- inmap = False
- continue
- line = line.split(",")
- reg = int(line[0])
- val = line[1].strip().replace("h", "")
- val = int(val, 16)
- regvals[reg] = val
- if "#REGISTER_MAP" in line:
- inmap = True
- inp.close()
- if verbose:
- print "Register map: %s" % str(regvals)
- for reg in regvals:
- n = self.i2c.write(self.slaveaddr, [reg, regvals[reg]])
- assert n == 2, "Only wrote %d of 2 bytes over I2C." % n
- if verbose:
- print "Clock configured"
-
-lvdscurrents = {
- 3.5: 0b000,
- 4.0: 0b001,
- 4.5: 0b010,
- 3.0: 0b100,
- 2.5: 0b101,
- 2.1: 0b110,
- 1.75: 0b111
-}
-
-napchannels = {
- 1: 0b0001,
- 2: 0b0001,
- 3: 0b0010,
- 4: 0b0010,
- 5: 0b0100,
- 6: 0b0100,
- 7: 0b1000,
- 8: 0b1000
-}
-
-class ADCLTM9007:
-
- def __init__(self, spicore, csA, csB, checkwrite=False):
- self.checkwrite = checkwrite
- self.spicore = spicore
- self.csA = csA
- self.csB = csB
-
- def config(self):
- self.reset()
- self.testpattern(False)
- self.setoutputmode(3.5, False, True, 1, 14)
- self.setformat(False, False)
-
- def writereg(self, bank, addr, data):
- value = 0x0
- value |= 0x0 << 15 # write bit
- value |= (addr & 0x7f) << 8
- value |= data & 0xff
- #print "writereg sending 0x%x = %s" % (value, bin(value))
- assert bank in ["A", "B"]
- if bank == "A":
- reply = self.spicore.transmit(self.csA, value)
- else:
- reply = self.spicore.transmit(self.csB, value)
- if self.checkwrite:
- readdata = self.readreg(bank, addr)
- msg = "Incorrect data from bank %s register 0x%x: " (bank, addr)
- msg += " after writing 0x%x, read 0x%x.\n" % (data, readdata)
- assert readdata == data, msg
-
-
- def writerega(self, addr, data):
- self.writereg("A", addr, data)
-
- def writeregb(self, addr, data):
- self.writereg("B", addr, data)
-
- def readreg(self, bank, addr):
- value = 0x0
- value |= 0x1 << 15
- value |= (addr & 0x7f) << 8
- #print "readreg sending 0x%x = %s" % (value, bin(value))
- assert bank in ["A", "B"]
- if bank == "A":
- reply = self.spicore.transmit(self.csA, value)
- else:
- reply = self.spicore.transmit(self.csB, value)
- reply16 = 0xff & reply
- #print "Reply = 0x%x -> 0x%x" % (reply, reply16)
- return reply16
-
- def readrega(self, addr):
- return self.readreg("A", addr)
-
- def readregb(self, addr):
- return self.readreg("B", addr)
-
- def reset(self, bank=None):
- """Reset ADC bank(s)."""
- if verbose:
- print "Resetting ADC."
- rstcmd = 0x1 << 7
- if bank == "A" or bank is None:
- if verbose:
- print "Reset A"
- self.writerega(0x0, rstcmd)
- time.sleep(0.5)
- if bank == "B" or bank is None:
- if verbose:
- print "Reset B"
- self.writeregb(0x0, rstcmd)
- time.sleep(0.5)
-
- def testpattern(self, on, pattern=0x0, bank=None):
- """Set bank(s)'s test pattern and en/disable it."""
- pattern = int(pattern) & 0x3fff
- if verbose:
- if on:
- print "Setting ADC test pattern = 0x%x = %s." % (pattern, bin(pattern))
- else:
- print "Setting ADC test pattern off."
- msb = 0x0
- if on:
- msb = 0x1 << 7
- msb |= ((pattern & 0x3f00) >> 8)
- lsb = pattern & 0xff
- if verbose:
- print "msb = 0x%x = %s, lsb = 0x%x = %s" % (msb, bin(msb), lsb, bin(lsb))
- if bank is None or bank == "A":
- self.writerega(0x4, lsb)
- self.writerega(0x3, msb)
- if bank is None or bank == "B":
- self.writeregb(0x4, lsb)
- self.writeregb(0x3, msb)
-
- def gettestpattern(self):
- valA = self.readrega(0x3) << 8
- valA |= self.readrega(0x4)
- print "Test pattern on bank A: 0x%x, %s" % (valA, bin(valA))
- valB = self.readregb(0x3) << 8
- valB |= self.readregb(0x4)
- print "Test pattern on bank B: 0x%x, %s" % (valB, bin(valB))
-
- def getstatus(self):
- print "Bank A:"
- for reg in range(5):
- val = self.readrega(reg)
- print " reg%d = 0x%x = %s" % (reg, val, bin(val))
- print "Bank B:"
- for reg in range(5):
- val = self.readregb(reg)
- print " reg%d = 0x%x = %s" % (reg, val, bin(val))
-
- def setoutputmode(self, lvdscurrent, lvdstermination, outenable, lanes, bits, bank=None):
- """Configure bank(s)'s output mode."""
- if verbose:
- print "Setting ADC output mode."
- mode = 0x0
- assert lanes in [1, 2] and bits in [12, 14, 16]
- if lanes == 1:
- if bits == 12:
- mode |= 0b110
- elif bits == 14:
- mode |= 0b101
- else: # bits = 16
- mode |= 0b111
- else: # lanes = 2
- if bits == 12:
- mode |= 0b010
- elif bits == 14:
- mode |= 001
- else: # bits = 16
- mode |= 0b111
- if not outenable:
- mode |= 0b1000
- if lvdstermination:
- mode |= (0x1 << 4)
- mode |= (lvdscurrents[lvdscurrent] << 5)
- if bank is None or bank == "A":
- self.writerega(0x2, mode)
- if bank is None or bank == "B":
- self.writeregb(0x2, mode)
-
- def setformat(self, randomiser, twoscomp, stabiliser=True, bank=None):
- """Configure bank(s)'s output format."""
- if verbose:
- print "Setting ADC format."
- if bank is None or bank == "A":
- data = self.readrega(0x1)
- if twoscomp:
- data |= (0x1 << 5)
- else:
- data &= 0xff ^ (0x1 << 5)
- if randomiser:
- data |= (0x1 << 6)
- else:
- data &= 0xff ^ (0x1 << 6)
- if not stabiliser:
- data |= (0x1 << 7)
- else:
- data &= 0xff ^ (0x1 << 7)
- self.writerega(0x1, data)
- if bank is None or bank == "B":
- data = self.readregb(0x1)
- if twoscomp:
- data |= (0x1 << 5)
- else:
- data &= 0xff ^ (0x1 << 5)
- if randomiser:
- data |= (0x1 << 6)
- else:
- data &= 0xff ^ (0x1 << 6)
- if not stabiliser:
- data |= (0x1 << 7)
- else:
- data &= 0xff ^ (0x1 << 7)
- self.writeregb(0x1, data)
-
- def setsleep(self, sleep, bank=None):
- """Put ADC bank(s) to sleep."""
- if verbose:
- print "Setting ADC sleep mode"
- if bank is None or bank == "A":
- data = self.readrega(0x1)
- if sleep:
- data |= (0x1 << 4)
- else:
- data &= 0xff ^ (0x1 << 4)
- self.writerega(0x1, data)
- if bank is None or bank == "B":
- data = self.readregb(0x1)
- if sleep:
- data |= (0x1 << 4)
- else:
- data &= 0xff ^ (0x1 << 4)
- self.writeregb(0x1, data)
-
- def nap(self, channels):
- """Provide a list of channels to put down for a nap, all others will be not napping."""
- if verbose:
- print "Setting ADC channel nap."
- dataa = self.readrega(0x1)
- dataa &= 0xf0
- datab = self.readregb(0x1)
- datab &= 0xf0
- for chan in channels:
- assert chan < 9 and chan > 0
- if chan in [1, 4, 5, 8]:
- dataa |= napchannels[chan]
- else:
- datab |= napchannels[chan]
- self.writerega(0x1, dataa)
- self.writeregb(0x1, datab)
-
-class MCP472XPowerMode:
-
- on = 0b00
- off1k = 0b01
- off100k = 0b10
- off500k = 0b11
-
-class DACMCP4725:
- """Global trim DAC"""
-
- # Write modes
- fast = 0b00
- writeDAC = 0b10
- writeDACEEPROM = 0b11
-
- def __init__(self, i2ccore, addr=0b1100111, vdd=5.0):
- self.i2ccore = i2ccore
- self.slaveaddr = addr & 0x7f
- self.vdd = float(vdd)
-
- def setbias(self, bias):
- # DAC voltage goes through potential divider to HV chip, where it is scaled up
- r1 = 1.0
- r2 = 2.4
- divider = r2 / (r1 + r2)
- voltage = bias / 30.0 / divider
- self.setvoltage(voltage)
-
- def setvoltage(self, voltage, powerdown=MCP472XPowerMode.on):
- if voltage > self.vdd:
- print "Overriding MCP4725 voltage: %g -> %g V (max of range)" % (voltage, self.vdd)
- voltage = self.vdd
- value = int(voltage / float(self.vdd) * 4096)
- #print "%g -> %d" % (voltage, value)
- self.setvalue(value, powerdown, self.writeDACEEPROM)
-
- def setvalue(self, value, powerdown, mode):
- value = int(value)
- value &= 0xfff
- if mode == self.fast:
- data = []
- data.append((powerdown << 4) | ((value & 0xf00) >> 8))
- data.append(value & 0x0ff)
- self.i2ccore.write(self.slaveaddr, data)
- else:
- data = []
- data.append((mode << 5) | (powerdown << 1))
- data.append((value & 0xff0) >> 4)
- data.append((value & 0x00f) << 4)
- #print "Writing %s" % str(data)
- self.i2ccore.write(self.slaveaddr, data)
-
- def status(self):
- data = self.i2ccore.read(self.slaveaddr, 5)
- assert len(data) == 5, "Only recieved %d of 5 expected bytes from MCP4725." % len(data)
- dx = "0x"
- db = ""
- for val in data:
- dx += "%02x" % val
- db += "%s " % bin(val)
- #print dx, db
- ready = (data[0] & (0x1 << 7)) > 0
- por = (data[0] & (0x1 << 6)) > 0 # power on reset?
- powerdown = (data[0] & 0b110) >> 1
- dacvalue = data[1] << 4
- dacvalue |= (data[2] & 0xf0) >> 4
- voltage = self.vdd * dacvalue / 2**12
- #print dacvalue, voltage
- return dacvalue, voltage, ready, por, powerdown
-
- def readvoltage(self):
- vals = self.status()
- return vals[1]
-
- def readbias(self):
- v = self.readvoltage()
- r1 = 1.0
- r2 = 2.4
- divider = r2 / (r1 + r2)
- bias = v * 30.0 * divider
- return bias
-
-# class MCP4728ChanStatus:
-#
-# def __init__(self, data):
-# assert len(data) == 3
-# s = "0x"
-# for val in data:
-# s += "%02x" % val
-# #print data, s
-# self.ready = (data[0] & (0x1 << 7)) > 0
-# self.por = (data[0] & (0x1 << 6)) > 0
-# self.chan = (data[0] & (0b11 << 4)) >> 4
-# self.addr = data[0] & 0x0f
-# self.vref = (data[1] & (0b1 << 7)) > 0
-# self.powerdown = (data[1] & (0b11 << 5)) >> 5
-# self.gain = (data[1] & (0b1 << 4)) > 0
-# self.value = (data[1] & 0x0f) << 8
-# self.value |= data[2]
-#
-# def __repr__(self):
-# return "chan %d: vref = %s, powerdown = %d, value = %d" % (self.chan, str(self.vref), self.powerdown, self.value)
-
-# class MCP4728Channel:
-#
-# def __init__(self, data):
-# assert len(data) == 6
-# self.output = MCP4728ChanStatus(data[:3])
-# self.EEPROM = MCP4728ChanStatus(data[3:])
-# self.chan = self.EEPROM.chan
-# #print self.output
-
-# class DACMCP4728:
-# """Channel trim DAC"""
-#
-# # Commands
-# writeDACEEPROM = 0b010
-#
-# # write functions
-# multiwrite = 0b00
-# sequentialwrite = 0b10
-# singlewrite = 0b11
-#
-# # stuff
-# vref = 0b0 << 7 # Uses external reference, ie Vdd
-#
-# def __init__(self, i2ccore, addr, vdd=5.0):
-# self.i2ccore = i2ccore
-# self.slaveaddr = addr & 0x7f
-# self.vdd = float(vdd)
-#
-# def setvoltage(self, channel, voltage, powerdown=MCP472XPowerMode.on):
-# value = int(voltage / self.vdd * 2**12)
-# #print "%g V -> %d" % (voltage, value)
-# self.setvalue(channel, value, powerdown)
-#
-# def setvalue(self, channel, value, powerdown=MCP472XPowerMode.on):
-# value = int(value) & 0xfff
-# data = [] # data is an empty array that gets filled as below
-# cmd = DACMCP4728.writeDACEEPROM << 5
-# cmd |= DACMCP4728.singlewrite << 3
-# cmd |= (channel & 0b11) << 1
-# data.append(cmd) data gets appende the cmd string
-# val = DACMCP4728.vref | ((powerdown & 0b11) << 5)
-# val |= (value & 0xf00) >> 8
-# data.append(val)
-# data.append(value & 0xff)
-# sx = "0x"
-# sb = ""
-# for val in data:
-# sx += "%02x" % val
-# sb += "%s " % bin(val)
-# #print "Writing data to %s value: " % bin(self.slaveaddr), data, sx, sb
-# nwritten = self.i2ccore.write(self.slaveaddr, data)
-# assert nwritten == len(data), "Only wrote %d of %d bytes setting MCP4728." % (nwritten, len(data))
-# time.sleep(0.2)
-#
-# def status(self):
-# data = self.i2ccore.read(self.slaveaddr, 24)
-# assert len(data) == 24, "Only read %d of 24 bytes getting MCP4728 status." % len(data)
-# #print data
-# chans = []
-# for chan in range(4):
-# i = chan * 6
-# chans.append(MCP4728Channel(data[i:i+6]))
-# return chans
-#
-# def readvoltages(self):
-# chans = self.status()
-# voltages = []
-# for chan in chans:
-# value = float(chan.output.value)
-# voltage = self.vdd * value / 2**12
-# voltages.append(voltage)
-# return voltages
-
-class TempMCP9808:
- """Temperture chip on analog board."""
-
- regTemp = 0x5
-
- def __init__(self, i2ccore, addr=0b0011000):
- self.i2ccore = i2ccore
- self.slaveaddr = addr & 0x7f
-# Here the chip needs a specific register written as a command before it knows
-# where to write to, which is the regaddr byte that is passed upself.
-
- def readreg(self, regaddr):
- n, data = self.i2ccore.writeread(self.slaveaddr, [regaddr], 2)
- assert n == 1 # this is the one byte address for the registry
- assert len(data) == 2 # this is teh length of the data read from the chip
- val = data[0] << 8
- val |= data[1]
- return val
-
- def temp(self):
- val = self.readreg(TempMCP9808.regTemp)
- return self.u16todeg(val)
-
- def u16todeg(self, val):
- val &= 0x1fff
- neg = val & 0x1000 > 0
- val &= 0x0fff
- if neg:
- return -float(0xfff - val) / 16.0
- return float(val) / 16.0
diff --git a/miniTLU/I2cBusProperties.py b/miniTLU/I2cBusProperties.py
deleted file mode 100644
index a23f30c..0000000
--- a/miniTLU/I2cBusProperties.py
+++ /dev/null
@@ -1,122 +0,0 @@
-##########################################################
-# I2cBusProperties - simple encapsulation of all items
-# required to control an I2C bus.
-#
-# Carl Jeske, July 2010
-# Refactored by Robert Frazier, May 2011
-##########################################################
-
-
-class I2cBusProperties(object):
- """Encapsulates details of an I2C bus master in the form of a host device, a clock prescale value, and seven I2C master registers
-
- Provide the ChipsBus instance to the device hosting your I2C core, a 16-bit clock prescaling
- value for the Serial Clock Line (see I2C core docs for details), and the names of the seven
- registers that define/control the bus (assuming these names are not the defaults specified
- in the constructor below). The seven registers consist of the two clock pre-scaling
- registers (PRElo, PREhi), and five bus master registers (CONTROL, TRANSMIT, RECEIVE,
- COMMAND and STATUS).
-
- Usage: You'll need to create an instance of this class to give to a concrete I2C bus instance, such
- as OpenCoresI2cBus. This I2cBusProperties class is simply a container to hold the properties
- that define the bus; a class such as OpenCoresI2cBus will make use of these properties.
-
- Access the items stored by this class via these (deliberately compact) variable names:
-
- chipsBus -- the ChipsBus device hosting the I2C core
- preHiVal -- the top byte of the clock prescale value
- preLoVal -- the bottom byte of the clock prescale value
- preHiReg -- the register the top byte of the clk prescale value (preHiVal) gets written to
- preLoReg -- the register the bottom byte of the clk prescale value (preLoVal) gets written to
- ctrlReg -- the I2C Control register
- txReg -- the I2C Transmit register
- rxReg -- the I2C Receive register
- cmdReg -- the I2C Command register
- statusReg -- the I2C Status register
-
-
- Compatibility Notes: The seven register names are the registers typically required to operate an
- OpenCores or similar I2C Master (Lattice Semiconductor's I2C bus master works
- the same way as the OpenCores one). This software is not compatible with your
- I2C bus master if it doesn't use this register interface.
- """
-
- def __init__(self,
- chipsBusDevice,
- clkPrescaleU16,
- clkPrescaleLoByteReg = "i2c_pre_lo",
- clkPrescaleHiByteReg = "i2c_pre_hi",
- controlReg = "i2c_ctrl",
- transmitReg = "i2c_tx",
- receiveReg = "i2c_rx",
- commandReg = "i2c_cmd",
- statusReg = "i2c_status"):
-
- """Provide a host ChipsBus device that is controlling the I2C bus, and the names of five I2C control registers.
-
- chipsBusDevice: Provide a ChipsBus instance to the device where the I2C bus is being
- controlled. The address table for this device must contain the five registers
- that control the bus, as declared next...
-
- clkPrescaleU16: A 16-bit value used to prescale the Serial Clock Line based on the host
- master-clock. This value gets split into two 8-bit values and ultimately will
- get written to the two I2C clock-prescale registers as declared below. See
- the OpenCores or Lattice Semiconductor I2C documentation for more details.
-
- clkPrescaleLoByteReg: The register where the lower byte of the clock prescale value is set. The default
- name for this register is "i2c_pre_lo".
-
- clkPrescaleHiByteReg: The register where the higher byte of the clock prescale value is set. The default
- name for this register is "i2c_pre_hi"
-
- controlReg: The CONTROL register, used for enabling/disabling the I2C core, etc. This register is
- usually read and write accessible. The default name for this register is "i2c_ctrl".
-
- transmitReg: The TRANSMIT register, used for holding the data to be transmitted via I2C, etc. This
- typically shares the same address as the RECEIVE register, but has write-only access. The default
- name for this register is "i2c_tx".
-
- receiveReg: The RECEIVE register - allows access to the byte received over the I2C bus. This
- typically shares the same address as the TRANSMIT register, but has read-only access. The
- default name for this register is "i2c_rx".
-
- commandReg: The COMMAND register - stores the command for the next I2C operation. This typically
- shares the same address as the STATUS register, but has write-only access. The default name for
- this register is "i2c_cmd".
-
- statusReg: The STATUS register - allows monitoring of the I2C operations. This typically shares
- the same address as the COMMAND register, but has read-only access. The default name for this
- register is "i2c_status".
- """
-
- object.__init__(self)
- self.chipsBus = chipsBusDevice
- self.preHiVal = ((clkPrescaleU16 & 0xff00) >> 8)
- self.preLoVal = (clkPrescaleU16 & 0xff)
-
- # Check to see all the registers are in the address table
- registers = [clkPrescaleLoByteReg, clkPrescaleHiByteReg, controlReg, transmitReg, receiveReg, commandReg, statusReg]
- for reg in registers:
- if not self.chipsBus.addrTable.checkItem(reg):
- raise ChipsException("I2cBusProperties error: register '" + reg + "' is not present in the address table of the device hosting the I2C bus master!")
-
- # Check that the registers we'll need to write to are indeed writable
- writableRegisters = [clkPrescaleLoByteReg, clkPrescaleHiByteReg, controlReg, transmitReg, commandReg]
- for wReg in writableRegisters:
- if not self.chipsBus.addrTable.getItem(wReg).getWriteFlag():
- raise ChipsException("I2cBusProperties error: register '" + wReg + "' does not have the necessary write permission!")
-
- # Check that the registers we'll need to read from are indeed readable
- readableRegisters = [clkPrescaleLoByteReg, clkPrescaleHiByteReg, controlReg, receiveReg, statusReg]
- for rReg in readableRegisters:
- if not self.chipsBus.addrTable.getItem(rReg).getReadFlag():
- raise ChipsException("I2cBusProperties error: register '" + rReg + "' does not have the necessary read permission!")
-
- # Store the various register name strings
- self.preHiReg = clkPrescaleHiByteReg
- self.preLoReg = clkPrescaleLoByteReg
- self.ctrlReg = controlReg
- self.txReg = transmitReg
- self.rxReg = receiveReg
- self.cmdReg = commandReg
- self.statusReg = statusReg
diff --git a/miniTLU/RawI2cAccess.py b/miniTLU/RawI2cAccess.py
deleted file mode 100644
index 2846132..0000000
--- a/miniTLU/RawI2cAccess.py
+++ /dev/null
@@ -1,261 +0,0 @@
-# Created on Sep 10, 2012
-# @author: Kristian Harder, based on code by Carl Jeske
-
-from I2cBusProperties import I2cBusProperties
-from ChipsBus import ChipsBus
-from ChipsLog import chipsLog
-from ChipsException import ChipsException
-
-
-class RawI2cAccess:
-
- def __init__(self, i2cBusProps, slaveAddr):
-
- # For performing read/writes over an OpenCores-compatible I2C bus master
- #
- # An instance of this class is required to communicate with each
- # I2C slave on the I2C bus.
- #
- # i2cBusProps: an instance of the class I2cBusProperties that contains
- # the relevant ChipsBus host and the I2C bus-master registers (if
- # they differ from the defaults specified by the I2cBusProperties
- # class).
- #
- #slaveAddr: The address of the I2C slave you wish to communicate with.
- #
-
- self._i2cProps = i2cBusProps # The I2C Bus Properties
- self._slaveAddr = 0x7f & slaveAddr # 7-bit slave address
-
-
- def resetI2cBus(self):
-
- # Resets the I2C bus
- #
- # This function does the following:
- # 1) Disables the I2C core
- # 2) Sets the clock prescale registers
- # 3) Enables the I2C core
- # 4) Sets all writable bus-master registers to default values
-
- try:
- self._chipsBus().queueWrite(self._i2cProps.ctrlReg, 0x00)
- #self._chipsBus().getNode(self._i2cProps.ctrlReg).write(0)
- self._chipsBus().queueWrite(self._i2cProps.preHiReg,
- self._i2cProps.preHiVal)
- self._chipsBus().queueWrite(self._i2cProps.preLoReg,
- self._i2cProps.preLoVal)
- self._chipsBus().queueWrite(self._i2cProps.ctrlReg, 0x80)
- self._chipsBus().queueWrite(self._i2cProps.txReg, 0x00)
- self._chipsBus().queueWrite(self._i2cProps.cmdReg, 0x00)
- self._chipsBus().queueRun()
- except ChipsException, err:
- raise ChipsException("I2C reset error:\n\t" + str(err))
-
-
- def read(self, numBytes):
-
- # Performs an I2C read. Returns the 8-bit read result(s).
- #
- # numBytes: number of bytes expected as response
- #
-
- try:
- result = self._privateRead(numBytes)
- except ChipsException, err:
- raise ChipsException("I2C read error:\n\t" + str(err))
- return result
-
-
- def write(self, listDataU8):
-
- # Performs an 8-bit I2C write.
- #
- # listDataU8: The 8-bit data values to be written.
- #
-
- try:
- self._privateWrite(listDataU8)
- except ChipsException, err:
- raise ChipsException("I2C write error:\n\t" + str(err))
- return
-
-
- def _chipsBus(self):
-
- # Returns the instance of the ChipsBus device that's hosting
- # the I2C bus master
-
- return self._i2cProps.chipsBus
-
-
- def _privateRead(self, numBytes):
-
- # I2C read implementation.
- #
- # Fast I2C read implementation,
- # i.e. done with the fewest packets possible.
-
-
- # transmit reg definitions
- # bits 7-1: 7-bit slave address during address transfer
- # or first 7 bits of byte during data transfer
- # bit 0: RW flag during address transfer or LSB during data transfer.
- # '1' = reading from slave
- # '0' = writing to slave
-
- # command reg definitions
- # bit 7: Generate start condition
- # bit 6: Generate stop condition
- # bit 5: Read from slave
- # bit 4: Write to slave
- # bit 3: 0 when acknowledgement is received
- # bit 2:1: Reserved
- # bit 0: Interrupt acknowledge. When set, clears a pending interrupt
-
- # Reset bus before beginning
- self.resetI2cBus()
-
- # Set slave address in bits 7:1, and set bit 0 to zero
- # (i.e. we're writing an address to the bus)
- self._chipsBus().queueWrite(self._i2cProps.txReg,
- (self._slaveAddr << 1) | 0x01)
- # Set start and write bit in command reg
- self._chipsBus().queueWrite(self._i2cProps.cmdReg, 0x90)
- # Run the queue
- self._chipsBus().queueRun()
- # Wait for transaction to finish.
- self._i2cWaitUntilFinished()
-
- result=[]
- for ibyte in range(numBytes):
- if ibyte==numBytes-1:
- stop_bit=0x40
- ack_bit=0x08
- else:
- stop_bit=0
- ack_bit=0
- pass
- # Set read bit, acknowledge and stop bit in command reg
- self._chipsBus().write(self._i2cProps.cmdReg, 0x20+ack_bit+stop_bit)
- # Wait for transaction to finish.
- # Don't expect an ACK, do expect bus free at finish.
- if stop_bit:
- self._i2cWaitUntilFinished(requireAcknowledgement = False,
- requireBusIdleAtEnd = True)
- else:
- self._i2cWaitUntilFinished(requireAcknowledgement = False,
- requireBusIdleAtEnd = False)
- pass
- result.append(self._chipsBus().read(self._i2cProps.rxReg))
-
- return result
-
-
- def _privateWrite(self, listDataU8):
-
- # I2C write implementation.
- #
- # Fast I2C write implementation,
- # i.e. done with the fewest packets possible.
-
- # transmit reg definitions
- # bits 7-1: 7-bit slave address during address transfer
- # or first 7 bits of byte during data transfer
- # bit 0: RW flag during address transfer or LSB during data transfer.
- # '1' = reading from slave
- # '0' = writing to slave
-
- # command reg definitions
- # bit 7: Generate start condition
- # bit 6: Generate stop condition
- # bit 5: Read from slave
- # bit 4: Write to slave
- # bit 3: 0 when acknowledgement is received
- # bit 2:1: Reserved
- # bit 0: Interrupt acknowledge. When set, clears a pending interrupt
- # Reset bus before beginning
- self.resetI2cBus()
-
- # Set slave address in bits 7:1, and set bit 0 to zero (i.e. "write mode")
- self._chipsBus().queueWrite(self._i2cProps.txReg,
- (self._slaveAddr << 1) & 0xfe)
- # Set start and write bit in command reg
- self._chipsBus().queueWrite(self._i2cProps.cmdReg, 0x90)
- # Run the queue
- self._chipsBus().queueRun()
- # Wait for transaction to finish.
- self._i2cWaitUntilFinished()
-
- for ibyte in range(len(listDataU8)):
- dataU8 = listDataU8[ibyte]
- if ibyte==len(listDataU8)-1:
- stop_bit=0x40
- else:
- stop_bit=0x00
- pass
- # Set data to be written in transmit reg
- self._chipsBus().queueWrite(self._i2cProps.txReg, (dataU8 & 0xff))
- # Set write and stop bit in command reg
- self._chipsBus().queueWrite(self._i2cProps.cmdReg, 0x10+stop_bit)
- # Run the queue
- self._chipsBus().queueRun()
- # Wait for transaction to finish.
- # Do expect an ACK and do expect bus to be free at finish
- if stop_bit:
- self._i2cWaitUntilFinished(requireAcknowledgement = True,
- requireBusIdleAtEnd = True)
- else:
- self._i2cWaitUntilFinished(requireAcknowledgement = True,
- requireBusIdleAtEnd = False)
- pass
- pass
-
- return
-
-
- def _i2cWaitUntilFinished(self, requireAcknowledgement = True,
- requireBusIdleAtEnd = False):
-
- # Ensures the current bus transaction has finished successfully
- # before allowing further I2C bus transactions
-
- # This method monitors the status register
- # and will not allow execution to continue until the
- # I2C bus has completed properly. It will throw an exception
- # if it picks up bus problems or a bus timeout occurs.
-
- maxRetry = 20
- attempt = 1
- while attempt <= maxRetry:
-
- # Get the status
- i2c_status = self._chipsBus().read(self._i2cProps.statusReg)
-
- receivedAcknowledge = not bool(i2c_status & 0x80)
- busy = bool(i2c_status & 0x40)
- arbitrationLost = bool(i2c_status & 0x20)
- transferInProgress = bool(i2c_status & 0x02)
- interruptFlag = bool(i2c_status & 0x01)
-
- if arbitrationLost: # This is an instant error at any time
- raise ChipsException("I2C error: Arbitration lost!")
-
- if not transferInProgress:
- break # The transfer looks to have completed successfully, pending further checks
-
- attempt += 1
-
- # At this point, we've either had too many retries, or the
- # Transfer in Progress (TIP) bit went low. If the TIP bit
- # did go low, then we do a couple of other checks to see if
- # the bus operated as expected:
-
- if attempt > maxRetry:
- raise ChipsException("I2C error: Transaction timeout - the 'Transfer in Progress' bit remained high for too long!")
-
- if requireAcknowledgement and not receivedAcknowledge:
- raise ChipsException("I2C error: No acknowledge received!")
-
- if requireBusIdleAtEnd and busy:
- raise ChipsException("I2C error: Transfer finished but bus still busy!")
diff --git a/miniTLU/aida_mini_tlu_addr_map.txt b/miniTLU/aida_mini_tlu_addr_map.txt
deleted file mode 100644
index 1f4693a..0000000
--- a/miniTLU/aida_mini_tlu_addr_map.txt
+++ /dev/null
@@ -1,72 +0,0 @@
-*RegName RegAddr RegMask R W
-*-------------------------------------------------------------
-FirmwareId 0x00000000 0xffffffff 1 0
-*
-* DUT interfaces base = 0x020
-DUTMaskW 0x00000020 0xffffffff 0 1
-IgnoreDUTBusyW 0x00000021 0xffffffff 0 1
-IgnoreShutterVetoW 0x00000022 0xffffffff 0 1
-DUTInterfaceModeW 0x00000023 0xffffffff 0 1
-DUTInterfaceModeModifierW 0x00000024 0xffffffff 0 1
-DUTMaskR 0x00000028 0xffffffff 1 0
-IgnoreDUTBusyR 0x00000029 0xffffffff 1 0
-IgnoreShutterVetoR 0x0000002A 0xffffffff 1 0
-DUTInterfaceModeR 0x0000002B 0xffffffff 1 0
-DUTInterfaceModeModifierR 0x0000002C 0xffffffff 1 0
-*
-* trigger inputs = 0x040
-SerdesRstW 0x00000040 0xffffffff 0 1
-SerdesRstR 0x00000048 0xffffffff 1 0
-ThrCount0R 0x00000049 0xffffffff 1 0
-ThrCount1R 0x0000004a 0xffffffff 1 0
-ThrCount2R 0x0000004b 0xffffffff 1 0
-ThrCount3R 0x0000004c 0xffffffff 1 0
-*
-* trigger logic = 0x060 **Note the different read and write directions
-
-InternalTriggerIntervalW 0x00000062 0xffffffff 0 1
-TriggerPatternW 0x00000063 0xffffffff 0 1
-TriggerVetoW 0x00000064 0xffffffff 0 1
-PulseStretchW 0x00000066 0xffffffff 0 1
-PulseDelayW 0x00000067 0xffffffff 0 1
-TriggerHoldOffW 0x00000068 0xffffffff 0 1
-
-PostVetoTriggersR 0x00000070 0xffffffff 1 0
-PreVetoTriggersR 0x00000071 0xffffffff 1 0
-InternalTriggerIntervalR 0x00000072 0xffffffff 1 0
-TriggerPatternR 0x00000073 0xffffffff 1 0
-TriggerVetoR 0x00000074 0xffffffff 1 0
-ExternalTriggerVetoR 0x00000075 0xffffffff 1 0
-PulseStretchR 0x00000076 0xffffffff 1 0
-PulseDelayR 0x00000077 0xffffffff 1 0
-TriggerHoldOffR 0x00000078 0xffffffff 1 0
-AuxTriggerCountR 0x00000079 0xffffffff 1 0
-*
-* event buffer = 0x080
-EventFifoData 0x00000080 0xffffffff 1 0
-EventFifoFillLevel 0x00000081 0xffffffff 1 0
-EventFifoCSR 0x00000082 0xffffffff 1 1
-EventFifoFillLevelFlags 0x00000083 0xffffffff 1 0
-*
-* logic clocks = 0x0A0
-LogicClocksCSR 0x000000A0 0xffffffff 1 1
-LogicRst 0x000000A1 0xffffffff 0 1
-*
-* I2C = 0x0C0
-i2c_pre_lo 0x000000C0 0x000000ff 1 1
-i2c_pre_hi 0x000000C1 0x000000ff 1 1
-i2c_ctrl 0x000000C2 0x000000ff 1 1
-i2c_tx 0x000000C3 0x000000ff 0 1
-i2c_rx 0x000000C3 0x000000ff 1 0
-i2c_cmd 0x000000C4 0x000000ff 0 1
-i2c_status 0x000000C4 0x000000ff 1 0
-*
-* Event formatter = 0x140
-Enable_Record_Data 0x00000140 0xffffffff 1 1
-ResetTimestampW 0x00000141 0xffffffff 0 1
-CurrentTimestampLR 0x00000142 0xffffffff 1 0
-CurrentTimestampHR 0x00000143 0xffffffff 1 0
-*
-* Shutter/T0 control = 0x160
-ShutterStateW 0x00000160 0xffffffff 0 1
-PulseT0 0x00000161 0xffffffff 0 1
diff --git a/miniTLU/connection.xml b/miniTLU/connection.xml
deleted file mode 100644
index 647c1ad..0000000
--- a/miniTLU/connection.xml
+++ /dev/null
@@ -1,6 +0,0 @@
-
-
-
-
-
diff --git a/miniTLU/initTLU.py b/miniTLU/initTLU.py
deleted file mode 100644
index eb1ae65..0000000
--- a/miniTLU/initTLU.py
+++ /dev/null
@@ -1,184 +0,0 @@
-#
-# Function to initialize TLU
-#
-# David Cussans, October 2015
-#
-# Nasty hack - use both PyChips and uHAL ( for block read ... )
-
-from PyChipsUser import *
-from FmcTluI2c import *
-
-import uhal
-
-import sys
-import time
-
-def startTLU( uhalDevice , pychipsBoard , writeTimestamps):
-
- print "RESETTING FIFO"
- pychipsBoard.write("EventFifoCSR",0x2)
- eventFifoFillLevel = pychipsBoard.read("EventFifoFillLevel")
- print "FIFO FILL LEVEL AFTER RESET= " , eventFifoFillLevel
-
-
- if writeTimestamps:
- print "ENABLING DATA RECORDING"
- pychipsBoard.write("Enable_Record_Data",1)
- else:
- print "Disabling data recording"
- pychipsBoard.write("Enable_Record_Data",0)
-
- print "Pulsing T0"
- pychipsBoard.write("PulseT0",1)
-
- print "Turning off software trigger veto"
- pychipsBoard.write("TriggerVetoW",0)
-
- print "TLU is running"
-
-
-def stopTLU( uhalDevice , pychipsBoard ):
-
- print "Turning on software trigger veto"
- pychipsBoard.write("TriggerVetoW",1)
-
- print "TLU triggers are stopped"
-
-def initTLU( uhalDevice , pychipsBoard , listenForTelescopeShutter , pulseDelay , pulseStretch , triggerPattern , DUTMask , ignoreDUTBusy , triggerInterval , thresholdVoltage ):
-
- print "SETTING UP AIDA TLU"
-
- fwVersion = uhalDevice.getNode("version").read()
- uhalDevice.dispatch()
- print "\tVersion (uHAL)= " , hex(fwVersion)
-
- print "\tTurning on software trigger veto"
- pychipsBoard.write("TriggerVetoW",1)
-
- # Check the bus for I2C devices
- pychipsBoardi2c = FmcTluI2c(pychipsBoard)
-
- print "\tScanning I2C bus:"
- scanResults = pychipsBoardi2c.i2c_scan()
- #print scanResults
- print '\t', ', '.join(scanResults), '\n'
-
- boardId = pychipsBoardi2c.get_serial_number()
- print "\tFMC-TLU serial number= " , boardId
-
- resetClocks = 0
- resetSerdes = 0
-
-# set DACs to -200mV
- print "\tSETTING ALL DAC THRESHOLDS TO" , thresholdVoltage , "V"
- pychipsBoardi2c.set_threshold_voltage(7, thresholdVoltage)
-
- clockStatus = pychipsBoard.read("LogicClocksCSR")
- print "\tCLOCK STATUS (should be 3 if all clocks locked)= " , hex(clockStatus)
- assert ( clockStatus == 3 ) , "Clocks in TLU FPGA are not locked. No point in continuing. Re-prgramme or power cycle board"
-
- if resetClocks:
- print "Resetting clocks"
- pychipsBoard.write("LogicRst", 1 )
-
- clockStatus = pychipsBoard.read("LogicClocksCSR")
- print "Clock status after reset = " , hex(clockStatus)
-
- inputStatus = pychipsBoard.read("SerdesRstR")
- print "Input status = " , hex(inputStatus)
-
- if resetSerdes:
- pychipsBoard.write("SerdesRstW", 0x00000003 )
- inputStatus = pychipsBoard.read("SerdesRstR")
- print "Input status during reset = " , hex(inputStatus)
-
- pychipsBoard.write("SerdesRstW", 0x00000000 )
- inputStatus = pychipsBoard.read("SerdesRstR")
- print "Input status after reset = " , hex(inputStatus)
-
- pychipsBoard.write("SerdesRstW", 0x00000004 )
- inputStatus = pychipsBoard.read("SerdesRstR")
- print "Input status during calibration = " , hex(inputStatus)
-
- pychipsBoard.write("SerdesRstW", 0x00000000 )
- inputStatus = pychipsBoard.read("SerdesRstR")
- print "Input status after calibration = " , hex(inputStatus)
-
-
- inputStatus = pychipsBoard.read("SerdesRstR")
- print "\tINPUT STATUS= " , hex(inputStatus)
-
- count0 = pychipsBoard.read("ThrCount0R")
- print "\t Count 0= " , count0
-
- count1 = pychipsBoard.read("ThrCount1R")
- print "\t Count 1= " , count1
-
- count2 = pychipsBoard.read("ThrCount2R")
- print "\t Count 2= " , count2
-
- count3 = pychipsBoard.read("ThrCount3R")
- print "\t Count 3= " , count3
-
-# Stop internal triggers until setup complete
- pychipsBoard.write("InternalTriggerIntervalW",0)
-
- print "\tSETTING INPUT COINCIDENCE WINDOW TO",pulseStretch,"[Units= 160MHz clock cycles, Four 5-bit values (one per input) packed in to 32-bit word]"
- pychipsBoard.write("PulseStretchW",int(pulseStretch))
- pulseStretchR = pychipsBoard.read("PulseStretchR")
- print "\t Pulse stretch read back as:", hex(pulseStretchR)
- # assert (int(pulseStretch) == pulseStretchR) , "Pulse stretch read-back doesn't equal written value"
-
- print "\tSETTING INPUT TRIGGER DELAY TO",pulseDelay , "[Units= 160MHz clock cycles, Four 5-bit values (one per input) packed in to 32-bit word]"
- pychipsBoard.write("PulseDelayW",int(pulseDelay))
- pulseDelayR = pychipsBoard.read("PulseDelayR")
- print "\t Pulse delay read back as:", hex(pulseDelayR)
-
- print "\tSETTING TRIGGER PATTERN (for external triggers) TO 0x%08X. Two 16-bit patterns packed into 32 bit word " %(triggerPattern)
- pychipsBoard.write("TriggerPatternW",int(triggerPattern))
- triggerPatternR = pychipsBoard.read("TriggerPatternR")
- print "\t Trigger pattern read back as: 0x%08X " % (triggerPatternR)
-
- print "\tENABLING DUT(s): Mask= " , hex(DUTMask)
- pychipsBoard.write("DUTMaskW",int(DUTMask))
- DUTMaskR = pychipsBoard.read("DUTMaskR")
- print "\t DUTMask read back as:" , hex(DUTMaskR)
-
- print "\tSETTING ALL DUTs IN AIDA MODE"
- pychipsBoard.write("DUTInterfaceModeW", 0xFF)
- DUTInterfaceModeR = pychipsBoard.read("DUTInterfaceModeR")
- print "\t DUT mode read back as:" , DUTInterfaceModeR
-
- print "\tSET DUT MODE MODIFIER"
- pychipsBoard.write("DUTInterfaceModeModifierW", 0xFF)
- DUTInterfaceModeModifierR = pychipsBoard.read("DUTInterfaceModeModifierR")
- print "\t DUT mode modifier read back as:" , DUTInterfaceModeModifierR
-
- if listenForTelescopeShutter:
- print "\tSET IgnoreShutterVetoW TO LISTEN FOR VETO FROM SHUTTER"
- pychipsBoard.write("IgnoreShutterVetoW",0)
- else:
- print "\tSET IgnoreShutterVetoW TO IGNORE VETO FROM SHUTTER"
- pychipsBoard.write("IgnoreShutterVetoW",1)
- IgnoreShutterVeto = pychipsBoard.read("IgnoreShutterVetoR")
- print "\t IgnoreShutterVeto read back as:" , IgnoreShutterVeto
-
- print "\tSETTING IGNORE VETO BY DUT BUSY MASK TO" , hex(ignoreDUTBusy)
- pychipsBoard.write("IgnoreDUTBusyW",int(ignoreDUTBusy))
- IgnoreDUTBusy = pychipsBoard.read("IgnoreDUTBusyR")
- print "\t IgnoreDUTBusy read back as:" , hex(IgnoreDUTBusy)
-
-#print "Enabling handshake: No-handshake"
-#board.write("HandshakeTypeW",1)
-
-
- print "\tSETTING INTERNAL TRIGGER INTERVAL TO" , triggerInterval , "(zero= no internal triggers)"
- if triggerInterval == 0:
- internalTriggerFreq = 0
- else:
- internalTriggerFreq = 160000.0/triggerInterval
- print "\tINTERNAL TRIGGER FREQUENCY= " , internalTriggerFreq , " kHz"
- pychipsBoard.write("InternalTriggerIntervalW",triggerInterval) #0->Internal pulse generator disabled. Any other value will generate pulses with a frequency of n*6.25ns
- trigIntervalR = pychipsBoard.read("InternalTriggerIntervalR")
- print "\t Trigger interval read back as:", trigIntervalR
- print "AIDA TLU SETUP COMPLETED"
diff --git a/miniTLU/miniTLU.py b/miniTLU/miniTLU.py
deleted file mode 100644
index e874a6f..0000000
--- a/miniTLU/miniTLU.py
+++ /dev/null
@@ -1,462 +0,0 @@
-import uhal;
-from FmcTluI2c import *
-from I2CuHal import I2CCore
-
-class MiniTLU:
- """docstring for miniTLU"""
- def __init__(self, dev_name, man_file):
- self.dev_name = dev_name
- self.manager= uhal.ConnectionManager(man_file)
- self.hw = self.manager.getDevice(self.dev_name)
- self.nChannels= 4
- self.VrefInt= 2.5 #Internal DAC voltage reference
- self.VrefExt= 1.3 #External DAC voltage reference
- self.intRefOn= False #Internal reference is OFF by default
-
- self.fwVersion = self.hw.getNode("version").read()
- self.hw.dispatch()
- print "uHAL VERSION= " , hex(self.fwVersion)
-
- # Instantiate a I2C core to configure the DACs
- self.TLU_I2C= I2CCore(self.hw, 10, 5, "i2c_master", None)
- self.TLU_I2C.state()
-
-
- def initialize(self):
- print "miniTLU INITIALIZING..."
- # We need to pass it listenForTelescopeShutter , pulseDelay , pulseStretch , triggerPattern , DUTMask , ignoreDUTBusy , triggerInterval , thresholdVoltage
-
- print "\tTurning on software trigger veto"
- cmd = int("0x1",16)
- self.setTriggerVetoStatus(cmd)
-
- #READ CONTENT OF EPROM VIA I2C
- self.getSN()
-
- #SET DACs
- targetV= 1.1
- intRef= False
- self.setDACintRef(intRef)
- DACchannel= 7
- self.writeThreshold(targetV, DACchannel)
-
- #Check clock status
- self.checkClkStatus()
-
- resetClocks = 0
- resetSerdes = 0
- if resetClocks:
- self.resetClocks()
- if resetSerdes:
- self.resetSerdes()
-
- # Get inputs status and counters
- self.getChStatus()
- self.getAllChannelsCounts()
-
- # Stop internal triggers until setup complete
- cmd = int("0x0",16)
- self.setInternalTrg(cmd)
-
- # Set pulse stretch
- pulseStretch= 0x000FFFFF
- self.setPulseStretch(pulseStretch)
-
- # Set pulse delay
- pulseDelay= 0x0
- #self.setPulseDelay(pulseDelay) #NEED TO FIX ADDRESS TABLE
-
- # Set trigger pattern
- triggerPattern= 0x0
- self.setTrgPattern(triggerPattern)
-
- # Set DUTs
- DUTMask= 0x1
- self.setDUTmask(DUTMask)
-
- # # Set mode
- DUTMode= 0x0
- self.setMode(DUTMode)
-
- # # Set modifier
- modifier = int("0xFF",16)
- self.setModeModifier(modifier)
-
- # Set veto shutter
- setVetoShutters=0
- self.setVetoShutters(setVetoShutters)
-
- # Set veto by DUT
- ignoreDUTBusy=0x0
- self.setVetoDUT(ignoreDUTBusy)
-
- # Set trigger interval (use 0 to disable internal triggers)
- triggerInterval=0
- self.setInternalTrg(triggerInterval)
-
- print "miniTLU INITIALIZED"
-
- def setModeModifier(self, modifier):
- print "\tDUT MODE MODIFIER:",modifier
- self.hw.getNode("DUTInterfaces.DUTInterfaceModeModifierW").write(modifier)
- self.hw.dispatch()
- self.getModeModifier()
-
- def getModeModifier(self):
- DUTInterfaceModeModifierR = self.hw.getNode("DUTInterfaces.DUTInterfaceModeModifierR").read()
- self.hw.dispatch()
- print "\t DUT mode modifier read back as:" , hex(DUTInterfaceModeModifierR)
- return DUTInterfaceModeModifierR
-
- def resetClock(self):
- print "\tClocks reset"
- cmd = int("0x1",16)
- self.hw.getNode("logic_clocks.LogicRst").write(cmd)
- self.hw.dispatch()
-
- def getClockStatus(self):
- clockStatus = self.hw.getNode("logic_clocks.LogicClocksCSR").read()
- self.hw.dispatch()
- print "\t Clock status=" , hex(clockStatus)
- return clockStatus
-
- def readEEPROM(self, startadd, bytes):
- mystop= 1
- time.sleep(0.1)
- myaddr= [startadd]#0xfa
- self.TLU_I2C.write( 0x50, [startadd], mystop)
- res= self.TLU_I2C.read( 0x50, bytes)
- return res
-
- def getSN(self):
- epromcontent=self.readEEPROM(0xfa, 6)
- print "\tFMC-TLU serial number (EEPROM):"
- result="\t "
- for iaddr in epromcontent:
- result+="%02x "%(iaddr)
- print result
- return epromcontent
-
- def writeThreshold(self, Vtarget, channel):
- #Writes the threshold. The DAC voltage differs from the threshold voltage because
- #the range is shifted to be symmetrical around 0V.
-
- #Check if the DACs are using the internal reference
- if (self.intRefOn):
- Vref= self.VrefInt
- else:
- Vref= self.VrefExt
-
- #Calculate offset voltage (because of the following shifter)
- Vdac= ( Vtarget + Vref ) / 2
- print"\tTHRESHOLD setting:"
- if channel==7:
- print "\t CH: ALL"
- else:
- print "\t CH:", channel
- print "\t Target V:", Vtarget
- dacValue = 0xFFFF * Vtarget / Vref
- self.writeDAC(int(dacValue), channel)
-
- def writeDAC(self, dacCode, channel):
- #Vtarget is the required voltage, channel is the DAC channel to target
- #intRef indicates whether to use the external voltage reference (True)
- #or the internal one (False).
-
- i2cSlaveAddrDac = 0x1F
-
- print "\t DAC value:" , dacCode
- if channel<0 or channel>7:
- print "writeDAC ERROR: channel",channel,"not in range 0-7 (bit mask)"
- ##return -1
- if dacCode<0:
- print "writeDAC ERROR: value",dacCode,"<0. Default to 0"
- dacCode=0
- elif dacCode>0xFFFF :
- print "writeDAC ERROR: value",dacCode,">0xFFFF. Default to 0xFFFF"
- dacCode=0xFFFF
-
- sequence=[( 0x18 + ( channel &0x7 ) ) , int(dacCode/256)&0xff , int(dacCode)&0xff]
- print "\t Writing DAC string:", sequence
- self.TLU_I2C.write( i2cSlaveAddrDac, sequence, 0)
-
- # def readDAC(self, channel):
- # #TO BE DONE
- # i2cSlaveAddrDac = 0x1F
- # bytes= 3
- # if channel<0 or channel>7:
- # print "writeDAC ERROR: channel",channel,"not in range 0-7 (bit mask)"
- # ##return -1
- # cmdDAC=[( 0x18 + ( channel &0x7 ) ) ]
- # self.TLU_I2C.write( i2cSlaveAddrDac, cmdDAC, 0)
- # res= self.TLU_I2C.read( i2cSlaveAddrDac, bytes)
- # print res
-
- def setDACintRef(self, intRef=False):
- i2cSlaveAddrDac = 0x1F
- self.intRefOn= intRef
- if intRef:
- print "\tDAC internal reference ON"
- cmdDAC= [0x38,0x00,0x01]
- else:
- print "\tDAC internal reference OFF"
- cmdDAC= [0x38,0x00,0x00]
- self.TLU_I2C.write( i2cSlaveAddrDac, cmdDAC, 0)
-
- # def getDACintRef(self):
- # #TO BE FIXED!
- # bytes= 3
- # i2cSlaveAddrDac = 0x1F
- # cmdDAC= [0x78]
- # self.TLU_I2C.write( i2cSlaveAddrDac, cmdDAC, 0)
- # res= self.TLU_I2C.read( i2cSlaveAddrDac, bytes)
- # print res
-
- def setTrgPattern(self, triggerPattern):
- triggerPattern &= 0xffffffff
- print "\tTRIGGER PATTERN (for external triggers) SET TO 0x%08X. Two 16-bit patterns packed into 32 bit word " %(triggerPattern)
- self.hw.getNode("triggerLogic.TriggerPatternW").write(triggerPattern)
- self.hw.dispatch()
- self.getTrgPattern()
-
- def getTrgPattern(self):
- triggerPatternR = self.hw.getNode("triggerLogic.TriggerPatternR").read()
- self.hw.dispatch()
- print "\t Trigger pattern read back as: 0x%08X " % (triggerPatternR)
- return triggerPatternR
-
- def setDUTmask(self, DUTMask):
- print "\tDUT MASK ENABLING: Mask= " , hex(DUTMask)
- self.hw.getNode("DUTInterfaces.DutMaskW").write(DUTMask)
- self.hw.dispatch()
- self.getDUTmask()
-
- def getDUTmask(self):
- DUTMaskR = self.hw.getNode("DUTInterfaces.DutMaskR").read()
- self.hw.dispatch()
- print "\t DUTMask read back as:" , hex(DUTMaskR)
- return DUTMaskR
-
- def setVetoShutters(self, newState):
- if newState:
- print "\tIgnoreShutterVetoW SET TO LISTEN FOR VETO FROM SHUTTER"
- cmd= int("0x0",16)
- else:
- print "\tIgnoreShutterVetoW SET TO IGNORE VETO FROM SHUTTER"
- cmd= int("0x1",16)
- self.hw.getNode("DUTInterfaces.IgnoreShutterVetoW").write(cmd)
- self.hw.dispatch()
- self.getVetoShutters()
-
- def getVetoShutters(self):
- IgnoreShutterVeto = self.hw.getNode("DUTInterfaces.IgnoreShutterVetoR").read()
- self.hw.dispatch()
- print "\t IgnoreShutterVeto read back as:" , IgnoreShutterVeto
- return IgnoreShutterVeto
-
- def setVetoDUT(self, ignoreDUTBusy):
- print "\tVETO IGNORE BY DUT BUSY MASK SET TO" , hex(ignoreDUTBusy)
- self.hw.getNode("DUTInterfaces.IgnoreDUTBusyW").write(ignoreDUTBusy)
- self.hw.dispatch()
- self.getVetoDUT()
-
- def getVetoDUT(self):
- IgnoreDUTBusyR = self.hw.getNode("DUTInterfaces.IgnoreDUTBusyR").read()
- self.hw.dispatch()
- print "\t IgnoreDUTBusy read back as:" , hex(IgnoreDUTBusyR)
- return IgnoreDUTBusyR
-
- def setInternalTrg(self, triggerInterval):
- print "\tTRIGGERS INTERNAL:"
- if triggerInterval == 0:
- internalTriggerFreq = 0
- print "\t disabled"
- else:
- internalTriggerFreq = 160000.0/triggerInterval
- print "\t Setting:", internalTriggerFreq, "Hz"
- self.hw.getNode("triggerLogic.InternalTriggerIntervalW").write(int(internalTriggerFreq))
- self.hw.dispatch()
- self.getInternalTrg()
-
- def getInternalTrg(self):
- trigIntervalR = self.hw.getNode("triggerLogic.InternalTriggerIntervalR").read()
- self.hw.dispatch()
- print "\t Trigger frequency read back as:", trigIntervalR, "Hz"
- return trigIntervalR
-
- def checkClkStatus(self):
- clockStatus = self.hw.getNode("logic_clocks.LogicClocksCSR").read()
- self.hw.dispatch()
- print "\tCLOCK STATUS [expected 3]"
- print "\t ", hex(clockStatus)
- assert ( clockStatus == 3 ) , "Clocks in TLU FPGA are not locked. No point in continuing. Re-prgramme or power cycle board"
- return clockStatus
-
- def setPulseStretch(self, pulseStretch):
- print "\tINPUT COINCIDENCE WINDOW SET TO", hex(pulseStretch) ,"[Units= 160MHz clock cycles, Four 5-bit values (one per input) packed in to 32-bit word]"
- self.hw.getNode("triggerLogic.InternalTriggerIntervalW").write(pulseStretch)
- self.hw.dispatch()
- self.getPulseStretch()
-
- def getPulseStretch(self):
- pulseStretchR = self.hw.getNode("triggerLogic.InternalTriggerIntervalR").read()
- self.hw.dispatch()
- print "\t Pulse stretch read back as:", hex(pulseStretchR)
- return pulseStretchR
-
- def getChCount(self, channel):
- regString= "triggerInputs.ThrCount"+ str(channel)+"R"
- count = self.hw.getNode(regString).read()
- self.hw.dispatch()
- print "\t Ch", channel, "Count:" , count
- return count
-
- def getChStatus(self):
- inputStatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
- self.hw.dispatch()
- print "\t Input status= " , hex(inputStatus)
- return inputStatus
-
- def setChStatus(self, cmd):
- self.hw.getNode("triggerInputs.SerdesRstW").write(cmd)
- inputStatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
- self.hw.dispatch()
- print "\tINPUT STATUS SET TO= " , hex(inputStatus)
-
- def resetSerdes(self):
- cmd = int("0x3",16)
- self.setChStatus(cmd)
- inputStatus= self.getChStatus()
- print "\t Input status during reset = " , hex(inputStatus)
-
- cmd = int("0x0",16)
- self.setChStatus(cmd)
- inputStatus= self.getChStatus()
- print "\t Input status after reset = " , hex(inputStatus)
-
- cmd = int("0x4",16)
- self.setChStatus(cmd)
- inputStatus= self.getChStatus()
- print "\t Input status during calibration = " , hex(inputStatus)
-
- cmd = int("0x0",16)
- self.setChStatus(cmd)
- inputStatus= self.getChStatus()
- print "\t Input status after calibration = " , hex(inputStatus)
-
- def resetClocks(self):
- #Reset clocks
- self.resetClock()
- #Get clock status after reset
- self.getClockStatus()
- #Get serdes status
- self.getChStatus()
-
- def getAllChannelsCounts(self):
- chCounts=[]
- for ch in range (0,self.nChannels):
- chCounts.append(int(self.getChCount(ch)))
- return chCounts
-
- def setPulseDelay(self, pulseDelay):
- print "\tTRIGGER DELAY SET TO", pulseDelay, "[Units= 160MHz clock, Four 5-bit values (one per input) packed in to 32-bit word]"
- self.hw.getNode("triggerLogic.PulseDelayW").write(pulseDelay)
- self.hw.dispatch()
- self.getPulseDelay()
-
- def getPulseDelay(self):
- pulseDelayR = self.hw.getNode("triggerLogic.PulseDelayR").read()
- self.hw.dispatch()
- print "\t Pulse delay read back as:", hex(pulseDelayR)
- return pulseDelayR
-
- def setMode(self, mode):
- print "\tDUT MODE SET TO: ", mode
- self.hw.getNode("DUTInterfaces.DUTInterfaceModeW").write(mode)
- self.hw.dispatch()
- self.getMode()
-
- def getMode(self):
- DUTInterfaceModeR = self.hw.getNode("DUTInterfaces.DUTInterfaceModeR").read()
- self.hw.dispatch()
- print "\t DUT mode read back as:" , DUTInterfaceModeR
- return DUTInterfaceModeR
-
- def setFifoCSR(self, cmd):
- self.hw.getNode("eventBuffer.EventFifoCSR").write(cmd)
- self.hw.dispatch()
- self.getFifoCSR()
-
- def getFifoCSR(self):
- FifoCSR= self.hw.getNode("eventBuffer.EventFifoCSR").read()
- self.hw.dispatch()
- print "\t FIFO CSR read back as:", hex(FifoCSR)
- return FifoCSR
-
- def getFifoLevel(self):
- FifoFill= self.hw.getNode("eventBuffer.EventFifoFillLevel").read()
- self.hw.dispatch()
- print "\t FIFO level read back as:", hex(FifoFill)
- return FifoFill
-
- def setRecordDataStatus(self, status=False):
- self.hw.getNode("Event_Formatter.Enable_Record_Data").write(status)
- self.hw.dispatch()
- self.getRecordDataStatus()
-
- def getRecordDataStatus(self):
- RecordStatus= self.hw.getNode("Event_Formatter.Enable_Record_Data").read()
- self.hw.dispatch()
- print "\t Data recording:", RecordStatus
- return RecordStatus
-
- def pulseT0(self):
- cmd = int("0x1",16)
- self.hw.getNode("Shutter.PulseT0").write(cmd)
- self.hw.dispatch()
- print "\tPulsing T0"
-
- def setTriggerVetoStatus(self, status=False):
- self.hw.getNode("triggerLogic.TriggerVetoW").write(status)
- self.hw.dispatch()
- self.getTriggerVetoStatus()
-
- def getTriggerVetoStatus(self):
- trgVetoStatus= self.hw.getNode("triggerLogic.TriggerVetoR").read()
- self.hw.dispatch()
- print "\t Trigger veto status read back as:", trgVetoStatus
- return trgVetoStatus
-
- def start(self, logtimestamps=False):
- print "miniTLU STARTING..."
-
- print "\tFIFO RESET:"
- FIFOcmd= 0x2
- self.setFifoCSR(FIFOcmd)
-
- eventFifoFillLevel= self.getFifoLevel()
-
- if logtimestamps:
- print "\tData recording set: ON"
- self.setRecordDataStatus(True)
- else:
- print "\tData recording set: OFF"
- self.setRecordDataStatus(False)
-
- # Pulse T0
- self.pulseT0()
-
- print "\tTurning off software trigger veto"
- cmd = int("0x0",16)
- self.setTriggerVetoStatus(cmd)
-
- print "miniTLU RUNNING"
-
- def stop(self):
- print "miniTLU STOPPING..."
-
- print "\tTurning on software trigger veto"
- cmd = int("0x1",16)
- self.setTriggerVetoStatus(cmd)
-
- print "miniTLU STOPPED"
diff --git a/miniTLU/miniTLU.xml b/miniTLU/miniTLU.xml
deleted file mode 100644
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+++ /dev/null
@@ -1,87 +0,0 @@
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diff --git a/miniTLU/miniTLU_old.xml b/miniTLU/miniTLU_old.xml
deleted file mode 100644
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+++ /dev/null
@@ -1,74 +0,0 @@
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diff --git a/miniTLU/startTLU_v6.py b/miniTLU/startTLU_v6.py
deleted file mode 100644
index b7948f2..0000000
--- a/miniTLU/startTLU_v6.py
+++ /dev/null
@@ -1,232 +0,0 @@
-#
-# Script to setup AIDA TLU for TPix3 telescope <--> TORCH synchronization
-#
-# David Cussans, December 2012
-#
-# Nasty hack - use both PyChips and uHAL ( for block read ... )
-
-from PyChipsUser import *
-from FmcTluI2c import *
-
-import uhal
-
-import sys
-
-import time
-
-from datetime import datetime
-
-from optparse import OptionParser
-
-# For single character non-blocking input:
-import select
-import tty
-import termios
-
-from initTLU import *
-
-def isData():
- return select.select([sys.stdin], [], [], 0) == ([sys.stdin], [], [])
-
-now = datetime.now().strftime('%Y-%m-%dT%H_%M_%S')
-default_filename = 'tluData_' + now + '.root'
-parser = OptionParser()
-
-parser.add_option('-r','--rootFname',dest='rootFname',
- default=default_filename,help='Path of output file')
-parser.add_option('-o','--writeTimestamps',dest='writeTimestamps',
- default="True",help='Set True to write timestamps to ROOT file')
-parser.add_option('-p','--printTimestamps',dest='printTimestamps',
- default="True",help='Set True to print timestamps to screen (nothing printed unless also output to file) ')
-parser.add_option('-s','--listenForTelescopeShutter',dest='listenForTelescopeShutter',
- default=False,help='Set True to veto triggers when shutter goes high')
-parser.add_option('-d','--pulseDelay',dest='pulseDelay', type=int,
- default=0x00,help='Delay added to input triggers. Four 5-bit numbers packed into 32-bt word, Units of 6.125ns')
-parser.add_option('-w','--pulseStretch',dest='pulseStretch',type=int,
- default=0x00,help='Width added to input triggers. Four 5-bit numbers packed into 32-bt word. Units of 6.125ns')
-parser.add_option('-t','--triggerPattern',dest='triggerPattern',type=int,
- default=0xFFFEFFFE,help='Pattern match to generate trigger. Two 16-bit words packed into 32-bit word.')
-parser.add_option('-m','--DUTMask',dest='DUTMask',type=int,
- default=0x01,help='Three-bit mask selecting which DUTs are active.')
-parser.add_option('-y','--ignoreDUTBusy',dest='ignoreDUTBusy',type=int,
- default=0x0F,help='Three-bit mask selecting which DUTs can veto triggers by setting BUSY high. Low = can veto, high = ignore busy.')
-parser.add_option('-i','--triggerInterval',dest='triggerInterval',type=int,
- default=0,help='Interval between internal trigers ( in units of 6.125ns ). Set to zero to turn off internal triggers')
-parser.add_option('-v','--thresholdVoltage',dest='thresholdVoltage',type=float,
- default=-0.2,help='Threshold voltage for TLU inputs ( units of volts)')
-
-(options, args) = parser.parse_args(sys.argv[1:])
-
-from ROOT import TFile, TTree
-from ROOT import gROOT
-
-print "SETTING UP AIDA TLU TO SUPPLY CLOCK AND TRIGGER TO TORCH READOUT\n"
-
-# Point to board in uHAL
-manager = uhal.ConnectionManager("file://./connection.xml")
-hw = manager.getDevice("minitlu")
-device_id = hw.id()
-
-# Point to TLU in Pychips
-bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
-
-# Assume DIP-switch controlled address. Switches at 2
-board = ChipsBusUdp(bAddrTab,"192.168.200.32",50001)
-
-# Open Root file
-print "OPENING ROOT FILE:", options.rootFname
-f = TFile( options.rootFname, 'RECREATE' )
-
-# Create a root "tree"
-tree = TTree( 'T', 'TLU Data' )
-highWord =0
-lowWord =0
-evtNumber=0
-timeStamp=0
-evtType=0
-trigsFired=0
-bufPos = 0
-
-# Create a branch for each piece of data
-tree.Branch( 'tluHighWord' , highWord , "HighWord/l")
-tree.Branch( 'tluLowWord' , lowWord , "LowWord/l")
-tree.Branch( 'tluTimeStamp' , timeStamp , "TimeStamp/l")
-tree.Branch( 'tluBufPos' , bufPos , "Bufpos/s")
-tree.Branch( 'tluEvtNumber' , evtNumber , "EvtNumber/i")
-tree.Branch( 'tluEvtType' , evtType , "EvtType/b")
-tree.Branch( 'tluTrigFired' , trigsFired, "TrigsFired/b")
-
-# Initialize TLU registers
-initTLU( uhalDevice = hw, pychipsBoard = board, listenForTelescopeShutter = options.listenForTelescopeShutter, pulseDelay = options.pulseDelay, pulseStretch = options.pulseStretch, triggerPattern = options.triggerPattern , DUTMask = options.DUTMask, ignoreDUTBusy = options.ignoreDUTBusy , triggerInterval = options.triggerInterval, thresholdVoltage = options.thresholdVoltage )
-
-loopWait = 0.1
-oldEvtNumber = 0
-
-oldPreVetotriggerCount = board.read("PreVetoTriggersR")
-oldPostVetotriggerCount = board.read("PostVetoTriggersR")
-
-oldThresholdCounter0 =0
-oldThresholdCounter1 =0
-oldThresholdCounter2 =0
-oldThresholdCounter3 =0
-
-print "STARTING POLLING LOOP"
-
-eventFifoFillLevel = 0
-loopRunning = True
-runStarted = False
-
-oldTime = time.time()
-
-# Save old terminal settings
-oldTermSettings = termios.tcgetattr(sys.stdin)
-tty.setcbreak(sys.stdin.fileno())
-
-while loopRunning:
-
- if isData():
- c = sys.stdin.read(1)
- print "\tGOT INPUT:", c
- if c == 't':
- loopRunning = False
- print "\tTERMINATING LOOP"
- elif c == 'c':
- runStarted = True
- print "\tSTARTING RUN"
- startTLU( uhalDevice = hw, pychipsBoard = board, writeTimestamps = ( options.writeTimestamps == "True" ) )
- elif c == 'f':
- # runStarted = True
- print "\tSTOPPING TRIGGERS"
- stopTLU( uhalDevice = hw, pychipsBoard = board )
-
-
- if runStarted:
-
- eventFifoFillLevel = hw.getNode("eventBuffer.EventFifoFillLevel").read()
-
- preVetotriggerCount = hw.getNode("triggerLogic.PreVetoTriggersR").read()
- postVetotriggerCount = hw.getNode("triggerLogic.PostVetoTriggersR").read()
-
- timestampHigh = hw.getNode("Event_Formatter.CurrentTimestampHR").read()
- timestampLow = hw.getNode("Event_Formatter.CurrentTimestampLR").read()
-
- thresholdCounter0 = hw.getNode("triggerInputs.ThrCount0R").read()
- thresholdCounter1 = hw.getNode("triggerInputs.ThrCount1R").read()
- thresholdCounter2 = hw.getNode("triggerInputs.ThrCount2R").read()
- thresholdCounter3 = hw.getNode("triggerInputs.ThrCount3R").read()
-
- hw.dispatch()
-
- newTime = time.time()
- timeDelta = newTime - oldTime
- oldTime = newTime
- #print "time delta = " , timeDelta
- preVetoFreq = (preVetotriggerCount-oldPreVetotriggerCount)/timeDelta
- postVetoFreq = (postVetotriggerCount-oldPostVetotriggerCount)/timeDelta
- oldPreVetotriggerCount = preVetotriggerCount
- oldPostVetotriggerCount = postVetotriggerCount
-
- deltaCounts0 = thresholdCounter0 - oldThresholdCounter0
- oldThresholdCounter0 = thresholdCounter0
- deltaCounts1 = thresholdCounter1 - oldThresholdCounter1
- oldThresholdCounter1 = thresholdCounter1
- deltaCounts2 = thresholdCounter2 - oldThresholdCounter2
- oldThresholdCounter2 = thresholdCounter2
- deltaCounts3 = thresholdCounter3 - oldThresholdCounter3
- oldThresholdCounter3 = thresholdCounter3
-
- print "pre , post veto triggers , pre , post frequency = " , preVetotriggerCount , postVetotriggerCount , preVetoFreq , postVetoFreq
-
- print "CURRENT TIMESTAMP HIGH, LOW (hex) = " , hex(timestampHigh) , hex(timestampLow)
-
- print "Input counts 0,1,2,3 = " , thresholdCounter0 , thresholdCounter1 , thresholdCounter2 , thresholdCounter3
- print "Input freq (Hz) 0,1,2,3 = " , deltaCounts0/timeDelta , deltaCounts1/timeDelta , deltaCounts2/timeDelta , deltaCounts3/timeDelta
-
- nEvents = int(eventFifoFillLevel)//4 # only read out whole events ( 4 x 32-bit words )
- wordsToRead = nEvents*4
-
- print "FIFO FILL LEVEL= " , eventFifoFillLevel
-
- print "# EVENTS IN FIFO = ",nEvents
- print "WORDS TO READ FROM FIFO = ",wordsToRead
-
- # get timestamp data and fifo fill in same outgoing packet.
- timestampData = hw.getNode("eventBuffer.EventFifoData").readBlock(wordsToRead)
-
- hw.dispatch()
-
- # print timestampData
- for bufPos in range (0, nEvents ):
- lowWord = timestampData[bufPos*4 + 1] + 0x100000000* timestampData[ (bufPos*4) + 0] # timestamp
-
- highWord = timestampData[bufPos*4 + 3] + 0x100000000* timestampData[ (bufPos*4) + 2] # evt number
- evtNumber = timestampData[bufPos*4 + 3]
-
- if evtNumber != ( oldEvtNumber + 1 ):
- print "***WARNING *** Non sqeuential event numbers *** , evt,oldEvt = ", evtNumber , oldEvtNumber
-
- oldEvtNumber = evtNumber
-
- timeStamp = lowWord & 0xFFFFFFFFFFFF
-
- evtType = timestampData[ (bufPos*4) + 0] >> 28
-
- trigsFired = (timestampData[ (bufPos*4) + 0] >> 16) & 0xFFF
-
- if (options.printTimestamps == "True" ):
- print "bufferPos, highWord , lowWord , event-number , timestamp , evtType = %x %016x %016x %08x %012x %01x %03x" % ( bufPos , highWord , lowWord, evtNumber , timeStamp , evtType , trigsFired)
-
- # Fill root branch - see example in http://wlav.web.cern.ch/wlav/pyroot/tpytree.html : write raw data and decoded data for now.
- tree.Fill()
-
- time.sleep( loopWait)
-
-# Fixme - at the moment infinite loop.
-preVetotriggerCount = board.read("PreVetoTriggersR")
-postVetotriggerCount = board.read("PostVetoTriggersR")
-print "EXIT POLLING LOOP"
-print "\nTRIGGER COUNT AT THE END OF RUN [pre, post]:" , preVetotriggerCount , postVetotriggerCount
-
-termios.tcsetattr(sys.stdin, termios.TCSADRAIN, oldTermSettings)
-f.Write()
-f.Close()
diff --git a/miniTLU/startTLU_v6.sh b/miniTLU/startTLU_v6.sh
deleted file mode 100755
index beef09b..0000000
--- a/miniTLU/startTLU_v6.sh
+++ /dev/null
@@ -1,24 +0,0 @@
-#!/bin/bash
-
-echo "=========================="
-CURRENT_DIR=${0%/*}
-echo "CURRENT DIRECTORY: " $CURRENT_DIR
-
-echo "============"
-echo "SETTING PATHS"
-#export PYTHONPATH=$CURRENT_DIR/../../../../PyChips_1_5_0_pre2A/src
-export PYTHONPATH=$CURRENT_DIR/../../../../Python_Scripts/PyChips_1_5_0_pre2A/src:$PYTHONPATH
-echo "PYTHON PATH= " $PYTHONPATH
-export LD_LIBRARY_PATH=/opt/cactus/lib:$LD_LIBRARY_PATH
-echo "LD_LIBRARY_PATH= " $LD_LIBRARY_PATH
-export PATH=/usr/bin/:/opt/cactus/bin:$PATH
-echo "PATH= " $PATH
-
-cd $CURRENT_DIR
-
-echo "============"
-echo "STARTING PYTHON SCRIPT"
-#python $CURRENT_DIR/startTLU_v8.py $@
-
-python startTLU_v8.py $@
-#python testTLU_script.py
diff --git a/miniTLU/startTLU_v8.py b/miniTLU/startTLU_v8.py
deleted file mode 100644
index 2ad4aac..0000000
--- a/miniTLU/startTLU_v8.py
+++ /dev/null
@@ -1,70 +0,0 @@
-# miniTLU test script
-
-#from PyChipsUser import *
-from FmcTluI2c import *
-import uhal
-import sys
-import time
-# from ROOT import TFile, TTree
-# from ROOT import gROOT
-from datetime import datetime
-
-from miniTLU import MiniTLU
-# Use to have interactive shell
-import cmd
-
-class MyPrompt(cmd.Cmd):
-
-
- def do_startRun(self, args):
- """Starts the TLU run"""
- print "COMMAND RECEIVED: STARTING TLU RUN"
- startTLU( uhalDevice = self.hw, pychipsBoard = self.board, writeTimestamps = ( options.writeTimestamps == "True" ) )
- #print self.hw
-
- def do_stopRun(self, args):
- """Stops the TLU run"""
- print "COMMAND RECEIVED: STOP TLU RUN"
- #stopTLU( uhalDevice = hw, pychipsBoard = board )
-
- def do_quit(self, args):
- """Quits the program."""
- print "COMMAND RECEIVED: QUITTING SCRIPT."
- #raise SystemExit
- return True
-
-# # Override methods in Cmd object ##
-# def preloop(self):
-# """Initialization before prompting user for commands.
-# Despite the claims in the Cmd documentaion, Cmd.preloop() is not a stub.
-# """
-# cmd.Cmd.preloop(self) # # sets up command completion
-# self._hist = [] # # No history yet
-# self._locals = {} # # Initialize execution namespace for user
-# self._globals = {}
-# print "\nINITIALIZING"
-# now = datetime.now().strftime('%Y-%m-%dT%H_%M_%S')
-# default_filename = './rootfiles/tluData_' + now + '.root'
-# print "SETTING UP AIDA TLU TO SUPPLY CLOCK AND TRIGGER TO TORCH READOUT\n"
-# self.manager = uhal.ConnectionManager("file://./connection.xml")
-# self.hw = self.manager.getDevice("minitlu")
-# self.device_id = self.hw.id()
-#
-# # Point to TLU in Pychips
-# self.bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
-#
-# # Assume DIP-switch controlled address. Switches at 2
-# self.board = ChipsBusUdp(self.bAddrTab,"192.168.200.32",50001)
-
-
-#################################################
-if __name__ == "__main__":
- miniTLU= MiniTLU("minitlu", "file://./connection.xml")
- miniTLU.initialize()
-
- logdata= False
- miniTLU.start(logdata)
- miniTLU.stop()
- # prompt = MyPrompt()
- # prompt.prompt = '>> '
- # prompt.cmdloop("Welcome to miniTLU test console.\nType HELP for a list of commands.")
diff --git a/miniTLU/testTLU_script.py b/miniTLU/testTLU_script.py
deleted file mode 100644
index 9d8b334..0000000
--- a/miniTLU/testTLU_script.py
+++ /dev/null
@@ -1,79 +0,0 @@
-# miniTLU test script
-
-from FmcTluI2c import *
-import uhal
-import sys
-import time
-from I2CuHal import I2CCore
-from miniTLU import MiniTLU
-from datetime import datetime
-
-if __name__ == "__main__":
- print "\tTEST TLU SCRIPT"
- miniTLU= MiniTLU("minitlu", "file://./connection.xml")
- #(self, target, wclk, i2cclk, name="i2c", delay=None)
- TLU_I2C= I2CCore(miniTLU.hw, 10, 5, "i2c_master", None)
- TLU_I2C.state()
-
-
- #READ CONTENT OF EEPROM ON 24AA02E48 (0xFA - 0XFF)
- mystop= 1
- time.sleep(0.1)
- myaddr= [0xfa]
- TLU_I2C.write( 0x50, myaddr, mystop)
- res=TLU_I2C.read( 0x50, 6)
- print "Checkin EEPROM:"
- result="\t"
- for iaddr in res:
- result+="%02x "%(iaddr)
- print result
-
- #SCAN I2C ADDRESSES
- #WRITE PROM
- #WRITE DAC
-
-
- #Convert required threshold voltage to DAC code
- #def convert_voltage_to_dac(self, desiredVoltage, Vref=1.300):
- print("Writing DAC setting:")
- Vref= 1.300
- desiredVoltage= 3.3
- channel= 0
- i2cSlaveAddrDac = 0x1F
- vrefOn= 0
- Vdaq = ( desiredVoltage + Vref ) / 2
- dacCode = 0xFFFF * Vdaq / Vref
- dacCode= 0x391d
- print "\tVreq:", desiredVoltage
- print "\tDAC code:" , dacCode
- print "\tCH:", channel
- print "\tIntRef:", vrefOn
-
- #Set DAC value
- #def set_dac(self,channel,value , vrefOn = 0 , i2cSlaveAddrDac = 0x1F):
- if channel<0 or channel>7:
- print "set_dac ERROR: channel",channel,"not in range 0-7 (bit mask)"
- ##return -1
- if dacCode<0 or dacCode>0xFFFF:
- print "set_dac ERROR: value",dacCode ,"not in range 0-0xFFFF"
- ##return -1
- # AD5665R chip with A0,A1 tied to ground
- #i2cSlaveAddrDac = 0x1F # seven bit address, binary 00011111
-
- # print "I2C address of DAC = " , hex(i2cSlaveAddrDac)
- # dac = RawI2cAccess(self.i2cBusProps, i2cSlaveAddrDac)
- # # if we want to enable internal voltage reference:
-
- if vrefOn:
- # enter vref-on mode:
- print "\tTurning internal reference ON"
- #dac.write([0x38,0x00,0x01])
- TLU_I2C.write( i2cSlaveAddrDac, [0x38,0x00,0x01], 0)
- else:
- print "\tTurning internal reference OFF"
- #dac.write([0x38,0x00,0x00])
- TLU_I2C.write( i2cSlaveAddrDac, [0x38,0x00,0x00], 0)
- # Now set the actual value
- sequence=[( 0x18 + ( channel &0x7 ) ) , int(dacCode/256)&0xff , int(dacCode)&0xff]
- print "\tWriting byte sequence:", sequence
- TLU_I2C.write( i2cSlaveAddrDac, sequence, 0)
diff --git a/miniTLU/test_T0.py b/miniTLU/test_T0.py
deleted file mode 100644
index cf81b33..0000000
--- a/miniTLU/test_T0.py
+++ /dev/null
@@ -1,92 +0,0 @@
-#
-# Script to exercise AIDA mini-TLU
-#
-# David Cussans, December 2012
-#
-# Nasty hack - use both PyChips and uHAL ( for block read ... )
-
-from PyChipsUser import *
-from FmcTluI2c import *
-
-import sys
-import time
-
-
-# Point to TLU in Pychips
-bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
-# Assume DIP-switch controlled address. Switches at 2
-board = ChipsBusUdp(bAddrTab,"192.168.200.32",50001)
-
-# Check the bus for I2C devices
-boardi2c = FmcTluI2c(board)
-
-firmwareID=board.read("FirmwareId")
-
-print "Firmware (from PyChips) = " , hex(firmwareID)
-
-print "Scanning I2C bus:"
-scanResults = boardi2c.i2c_scan()
-print scanResults
-
-boardId = boardi2c.get_serial_number()
-print "FMC-TLU serial number = " , boardId
-
-resetClocks = 0
-
-
-
-clockStatus = board.read("LogicClocksCSR")
-print "Clock status = " , hex(clockStatus)
-
-if resetClocks:
- print "Resetting clocks"
- board.write("LogicRst", 1 )
-
- clockStatus = board.read("LogicClocksCSR")
- print "Clock status after reset = " , hex(clockStatus)
-
-
-board.write("InternalTriggerIntervalW",0)
-
-print "Enabling DUT 0 and 1"
-board.write("DUTMaskW",3)
-DUTMask = board.read("DUTMaskR")
-print "DUTMaskR = " , DUTMask
-
-print "Ignore veto on DUT 0 and 1"
-board.write("IgnoreDUTBusyW",3)
-IgnoreDUTBusy = board.read("IgnoreDUTBusyR")
-print "IgnoreDUTBusyR = " , IgnoreDUTBusy
-
-print "Turning off software trigger veto"
-board.write("TriggerVetoW",0)
-
-print "Reseting FIFO"
-board.write("EventFifoCSR",0x2)
-eventFifoFillLevel = board.read("EventFifoFillLevel")
-print "FIFO fill level after resetting FIFO = " , eventFifoFillLevel
-
-print "Enabling data recording"
-board.write("Enable_Record_Data",1)
-
-#print "Enabling handshake: No-handshake"
-#board.write("HandshakeTypeW",1)
-
-#TriggerInterval = 400000
-TriggerInterval = 0
-print "Setting internal trigger interval to " , TriggerInterval
-board.write("InternalTriggerIntervalW",TriggerInterval) #0->Internal pulse generator disabled. Any other value will generate pulses with a frequency of n*6.25ns
-trigInterval = board.read("InternalTriggerIntervalR")
-print "Trigger interval read back as ", trigInterval
-
-print "Setting TPix_maskexternal to ignore external shutter and T0"
-board.write("TPix_maskexternal",0x0003)
-
-numLoops = 500000
-oldEvtNumber = 0
-
-for iLoop in range(0,numLoops):
-
- board.write("TPix_T0", 0x0001)
-
-# time.sleep( 1.0)
diff --git a/packages/AD5665R.py b/packages/AD5665R.py
deleted file mode 100644
index b377183..0000000
--- a/packages/AD5665R.py
+++ /dev/null
@@ -1,45 +0,0 @@
-# -*- coding: utf-8 -*-
-import uhal
-from packages.I2CuHal import I2CCore
-
-
-class AD5665R:
- #Class to configure the DAC modules
-
- def __init__(self, i2c, slaveaddr=0x1F):
- self.i2c = i2c
- self.slaveaddr = slaveaddr
-
-
- def setIntRef(self, intRef=False, verbose=False):
- mystop=True
- if intRef:
- cmdDAC= [0x38,0x00,0x01]
- else:
- cmdDAC= [0x38,0x00,0x00]
- self.i2c.write( self.slaveaddr, cmdDAC, mystop)
- if verbose:
- print(" AD5665R")
- print("\tDAC int ref:", intRef)
-
-
- def writeDAC(self, dacCode, channel, verbose=False):
- #Vtarget is the required voltage, channel is the DAC channel to target
- #intRef indicates whether to use the external voltage reference (True)
- #or the internal one (False).
-
- print("\tDAC value:" , hex(dacCode))
- if channel<0 or channel>7:
- print("writeDAC ERROR: channel",channel,"not in range 0-7 (bit mask)")
- return -1
- if dacCode<0:
- print("writeDAC ERROR: value",dacCode,"<0. Default to 0")
- dacCode=0
- elif dacCode>0xFFFF :
- print("writeDAC ERROR: value",dacCode,">0xFFFF. Default to 0xFFFF")
- dacCode=0xFFFF
-
- sequence=[( 0x18 + ( channel &0x7 ) ) , int(dacCode/256)&0xff , int(dacCode)&0xff]
- print("\tWriting DAC string:", sequence)
- mystop= False
- self.i2c.write( self.slaveaddr, sequence, mystop)
diff --git a/packages/ADN2814ACPZ.py b/packages/ADN2814ACPZ.py
deleted file mode 100644
index 31b3dc6..0000000
--- a/packages/ADN2814ACPZ.py
+++ /dev/null
@@ -1,144 +0,0 @@
-# -*- coding: utf-8 -*-
-import uhal
-from I2CuHal import I2CCore
-import StringIO
-import math
-
-class ADN2814ACPZ:
- #Class to configure the ADN2814 clock and data recovery chip (CDR)
- # The I2C address can either be 0x40 or 0x60
-
- def __init__(self, i2c, slaveaddr=0x40):
- self.i2c = i2c
- self.slaveaddr = slaveaddr
- self.regDictionary= {'freq0': 0x0, 'freq1': 0x1, 'freq2': 0x2, 'rate': 0x3, 'misc': 0x4, 'ctrla': 0x8, 'ctrlb': 0x9, 'ctrlc': 0x11}
-
- def writeReg(self, regN, regContent, verbose=False):
- #Basic functionality to write to register.
- regContent= regContent & 0xFF
- mystop=True
- cmd= [regN, regContent]
- self.i2c.write( self.slaveaddr, cmd, mystop)
-
-
- def readReg(self, regN, nwords, verbose=False):
- #Basic functionality to read from register.
- mystop=False
- self.i2c.write( self.slaveaddr, [regN], mystop)
- res= self.i2c.read( self.slaveaddr, nwords)
- return res
-
- def readf0(self, verbose=False):
- res= self.readReg(self.regDictionary['freq0'], 1, False)
- if verbose:
- print "\tfreq0 is", res[0]
- return res[0]
-
- def readf1(self, verbose=False):
- res= self.readReg(self.regDictionary['freq1'], 1, False)
- if verbose:
- print "\tfreq1 is", res[0]
- return res[0]
-
- def readf2(self, verbose=False):
- res= self.readReg(self.regDictionary['freq2'], 1, False)
- if verbose:
- print "\tfreq2 is", res[0]
- return res[0]
-
- def readFrequency(self, verbose=False):
- # write 1 to CTRLA[1]
- # reset MISC[2] by writing a 1 followed by a 0 to CTRLB[3]
- # read back MISC[2], if 0 the measurement is not complete (typ 80 ms). If 1 the data rate can be read by reading FREQ[22:0]
- # read FREQ2, FREQ1, FREQ0
- # rate= (FREQ[22:0]xFrefclk)/2^(14+SEL_RATE)
-
- return
-
- def readLOLstatus(self, verbose=False):
- # return the status of the LOL bit MISC[3] and the STATIC LOL MISC[4]
- # the STATIC LOL is asserted if a LOL condition occurred and remains asserted
- # until cleared by writing 1 followed by 0 to the CTRLB[6] bit
- misc= self.readReg(self.regDictionary['misc'], 1, False)[0]
- staticLOL= (misc & 0x10000) >> 4
- LOL= (misc & 0x1000) >> 3
- if verbose:
- print "MISC=", misc, "LOL=", LOL, "StaticLOL=", staticLOL
- return [LOL, staticLOL]
-
- def readRate(self, verbose=False):
- rate_msb= self.readReg(self.regDictionary['rate'], 1, False)[0]
- rate_lsb= self.readReg(self.regDictionary['misc'], 1, False)[0]
- rate_lsb= 0x1 & rate_lsb
- rate= (rate_msb << 1) | rate_lsb
- if verbose:
- print "\tcoarse rate is", rate
- return rate
-
- def _writeCTRLA(self, fRef, dataRatio, measureDataRate, lockToRef, verbose=False):
- #write content to register CTRLA:
- # fRef: reference frequency in MHz; range is [10 : 160]
- # dataRatio: integer in range [0 : 8] equal to Data Rate/Div_FREF Ratio
- # measureDataRate: set to 1 to measure data rate
- # lockToRef= 0 > lock to input data; 1 > lock to reference clock
- regContent= 0x0
- if fRef < 10:
- print "fRef must be comprised between 10 and 160. Coherced to 10"
- fRef = 10
- if fRef > 160:
- print "fRef must be comprised between 10 and 160. Coherced to 160"
- fRef = 160
- fRefRange={
- 10<= fRef <20 : 0x00,
- 20<= fRef <40 : 0x01,
- 40<= fRef <80 : 0x02,
- 80<= fRef <=160 : 0x03,
- }[1]
- fRefRange= fRefRange << 6
- regContent= regContent | fRefRange
-
- if ((1 <= dataRatio <= 256) & (isinstance(dataRatio, (int, long) )) ):
- ratioValue= math.log(dataRatio, 2)
- ratioValue= int(ratioValue)
- else:
- print " dataRatio should be an integer in the form 2^n with 0<= n <= 8. Coherced to 0"
- ratioValue= 0
- if verbose:
- print "\tratioValue=", ratioValue
- ratioValue = ratioValue << 2
- regContent= regContent | ratioValue
-
- measureDataRate= (measureDataRate & 0x1) << 1
- lockToRef= lockToRef & 0x1
- regContent= regContent | measureDataRate | lockToRef
-
- self.writeReg( self.regDictionary['ctrla'], regContent, verbose=False)
- return
-
- def _writeCTRLB(self, confLOL, rstMisc4, systemReset, rstMisc2, verbose=False):
- #write content to register CTRLB:
- # confLOL=0 > LOL pin normal operation; 1 > LOL pin is static LOL
- # rstMisc4= Write a 1 followed by 0 to reset MISC[4] (staticLOL)
- # systemReset= Write 1 followed by 0 to reset ADN2814
- # rsttMisc2= Write a 1 followed by 0 to reset MISC[2] (data read measure complete)
- regContent= 0x0
- confLOL= (confLOL & 0x1) << 7
- rstMisc4= (rstMisc4 & 0x1) << 6
- systemReset= (systemReset & 0x1) << 5
- rstMisc2= (rstMisc2 & 0x1) << 3
- regContent= regContent | confLOL | rstMisc4 | systemReset | rstMisc2
- self.writeReg( self.regDictionary['ctrlb'], regContent, verbose=False)
- return
-
- def _writeCTRLC(self, confLOS, squelch, outBoost, verbose=False):
- #write content to register CTRLC:
- # confLOS= 0 > active high LOS; 1 > active low LOS
- # squelch= 0 > squelch CLK and DATA; 1 > squelch CLK or DATA
- # outBoost= 0 > default swing; boost output swing
- regContent= 0x0
- confLOS= (confLOS & 0x1) << 2
- squelch= (squelch & 0x1) << 1
- outBoost= (outBoost & 0x1)
- regContent= regContent | confLOS | squelch | outBoost
- self.writeReg( self.regDictionary['ctrlc'], regContent, verbose=False)
- return
diff --git a/packages/ATSHA204A.py b/packages/ATSHA204A.py
deleted file mode 100644
index 32ec5ae..0000000
--- a/packages/ATSHA204A.py
+++ /dev/null
@@ -1,114 +0,0 @@
-# -*- coding: utf-8 -*-
-import uhal
-from packages.I2CuHal import I2CCore
-import numpy as np
-
-
-class ATSHA204A:
- #Class for Atmel ATSHA204A eeprom
-
- def __init__(self, i2c, slaveaddr= 0x64):
- self.i2c = i2c
- self.slaveaddr = slaveaddr
-
- #Slot size, in bytes.
- self.SLOT_SIZE_BYTES = 32;
- #Word size, in bytes. This is the base unit for all reads and writes.
- self.WORD_SIZE_BYTES = 4;
- #Maximum word offset per slot
- self.MAX_WORD_OFFSET = 7;
- #Size of the configuration zone, in bytes
- self.CONFIGURATION_ZONE_SIZE_BYTES = 88;
- #Number of slots in the configuration zone
- self.CONFIGURATION_ZONE_SIZE_SLOTS = 3;
- #Slot 3 in the configuration zone is only 24 bytes rather than 32, so the max word offset is limited to 5.
- self.CONFIGURATION_ZONE_SLOT_2_MAX_WORD_OFFSET = 5;
- #Size of the OTP zone, in bytes
- self.OTP_ZONE_SIZE_BYTES = 64;
- #Number of slots in the OTP zone
- self.OTP_ZONE_SIZE_SLOTS = 2;
- #Size of the data zone, in bytes
- self.DATA_ZONE_SIZE_BYTES = 512;
- #Number of slots in the data zone
- self.DATA_ZONE_SIZE_SLOTS = 16;
- #The data slot used for module configuration data
- self.DATA_ZONE_SLOT_MODULE_CONFIGURATION = 0;
- #Byte index of the OTP mode byte within its configuration word.
- self.OTP_MODE_WORD_BYTE_INDEX = 2;
-
-#-------------------------------------------------------------------------------------------------
-# Command packets and I/O
-#-------------------------------------------------------------------------------------------------
- #Command execution status response block size
- self.STATUS_RESPONSE_BLOCK_SIZE_BYTES = 4;
- #Byte index of count in response block
- self.STATUS_RESPONSE_COUNT_BYTE_INDEX = 0;
- #Byte index of status code in response block
- self.STATUS_RESPONSE_STATUS_BYTE_INDEX = 1;
- #Checksum size
- self.CHECKSUM_LENGTH_BYTES = 2;
- #Index of the count byte in a command packet
- self.COMMAND_PACKET_COUNT_BYTE_INDEX = 0;
- #Size of count in a command packet
- self.COMMAND_PACKET_COUNT_SIZE_BYTES = 1;
- #Index of the opcode byte in a command packet
- self.COMMAND_PACKET_OPCODE_BYTE_INDEX = 1;
- #Size of the opcode byte in a command packet
- self.COMMAND_PACKET_OPCODE_LENGTH_BYTES = 1;
- #Index of param 1 in a command packet
- self.COMMAND_PACKET_PARAM1_BYTE_INDEX = 2;
- #Size of param 1 in a command packet
- self.COMMAND_PACKET_PARAM1_SIZE_BYTES = 1;
- #Index of param 2 in a command packet
- self.COMMAND_PACKET_PARAM2_BYTE_INDEX = 3;
- #Size of param 2 in a command packet
- self.COMMAND_PACKET_PARAM2_SIZE_BYTES = 2;
-
- def _CalculateCrc(self, pData, dataLengthBytes):
- # Calculate a CRC-16 used when communicating with the device. Code taken from Atmel's library.
- #The Atmel documentation only specifies that the CRC algorithm used on the ATSHA204A is CRC-16 with polynomial
- #0x8005; compared to a standard CRC-16, however, the used algorithm doesn't use remainder reflection.
- #@param pData The data to calculate the CRC for
- #@param dataLengthBytes The number of bytes to process
- #@return The CRC
- polynomial = 0x8005
- crcRegister = 0
- if not pData:
- print("_CalculateCrc: No data to process")
- return 0
- for counter in range(0, dataLengthBytes):
- shiftRegister= 0x01
- for iShift in range(0, 8):
- if (pData[counter] & shiftRegister) :
- dataBit= 1
- else:
- dataBit=0
- crcBit= ((crcRegister) >> 15)
- crcRegister <<= 1
- crcRegister= crcRegister & 0xffff
- #print shiftRegister, "\t", dataBit, "\t", crcBit, "\t", crcRegister
- shiftRegister= shiftRegister << 1
- if (dataBit != crcBit):
- #print "poly"
- crcRegister ^= polynomial;
- return crcRegister
-
- def _wake(self, verifyDeviceIsAtmelAtsha204a, debug):
- dummyWriteData = 0x00
- mystop=True
- self.i2c.write( self.slaveaddr, [dummyWriteData], mystop)
-
- if (verifyDeviceIsAtmelAtsha204a):
- expectedStatusBlock= [ 0x04, 0x11, 0x33, 0x43 ];
- nwords= 4
- res= self.i2c.read( self.slaveaddr, nwords)
- if (res != expectedStatusBlock):
- print("Attempt to awake Atmel ATSHA204A failed")
- print(res)
-
- def _GetCommandPacketSize(self, additionalDataLengthBytes):
- packetSizeBytes = self.COMMAND_PACKET_COUNT_SIZE_BYTES + self.COMMAND_PACKET_OPCODE_LENGTH_BYTES \
- + self.COMMAND_PACKET_PARAM1_SIZE_BYTES + self.COMMAND_PACKET_PARAM2_SIZE_BYTES \
- + additionalDataLengthBytes + self.CHECKSUM_LENGTH_BYTES;
-
- return packetSizeBytes
diff --git a/packages/E24AA025E48T.py b/packages/E24AA025E48T.py
deleted file mode 100644
index 32cc429..0000000
--- a/packages/E24AA025E48T.py
+++ /dev/null
@@ -1,20 +0,0 @@
-# -*- coding: utf-8 -*-
-import uhal
-from I2CuHal import I2CCore
-import StringIO
-
-class E24AA025E48T:
- #Class to configure the EEPROM
-
- def __init__(self, i2c, slaveaddr=0x50):
- self.i2c = i2c
- self.slaveaddr = slaveaddr
-
-
- def readEEPROM(self, startadd, nBytes):
- #Read EEPROM memory locations
- mystop= False
- myaddr= [startadd]#0xfa
- self.i2c.write( self.slaveaddr, [startadd], mystop)
- res= self.i2c.read( self.slaveaddr, nBytes)
- return res
diff --git a/packages/FmcTluI2c.py b/packages/FmcTluI2c.py
deleted file mode 100644
index 04bf598..0000000
--- a/packages/FmcTluI2c.py
+++ /dev/null
@@ -1,132 +0,0 @@
-import time
-#from PyChipsUser import *
-from I2cBusProperties import *
-from RawI2cAccess import *
-
-
-class FmcTluI2c:
-
-
- ############################
- ### configure i2c connection
- ############################
- def __init__(self,board):
- self.board = board
- i2cClockPrescale = 0x30
- self.i2cBusProps = I2cBusProperties(self.board, i2cClockPrescale)
- return
-
-
- ##########################
- ### scan all i2c addresses
- ##########################
- def i2c_scan(self):
- list=[]
- for islave in range(128):
- i2cscan = RawI2cAccess(self.i2cBusProps, islave)
- try:
- i2cscan.write([0x00])
- device="slave address "+hex(islave)+" "
- if islave==0x1f:
- device+="(DAC)"
- elif islave==0x50:
- device+="(serial number PROM)"
- elif islave>=0x54 and islave<=0x57:
- device+="(sp601 onboard EEPROM)"
- else:
- device+="(???)"
- pass
- list.append(device)
- pass
- except:
- pass
- pass
- return list
-
-
- ###################
- ### write to EEPROM
- ###################
- def eeprom_write(self,address,value):
- if address<0 or address>127:
- print "eeprom_write ERROR: address",address,"not in range 0-127"
- return
- if value<0 or value>255:
- print "eeprom_write ERROR: value",value,"not in range 0-255"
- return
- i2cSlaveAddr = 0x50 # seven bit address, binary 1010000
- prom = RawI2cAccess(self.i2cBusProps, i2cSlaveAddr)
- prom.write([address,value])
- time.sleep(0.01) # write cycle time is 5ms. let's wait 10 to make sure.
- return
-
-
- ####################
- ### read from EEPROM
- ####################
- def eeprom_read(self,address):
- if address<0 or address>255:
- print "eeprom_write ERROR: address",address,"not in range 0-127"
- return
- i2cSlaveAddr = 0x50 # seven bit address, binary 1010000
- prom = RawI2cAccess(self.i2cBusProps, i2cSlaveAddr)
- prom.write([address])
- return prom.read(1)[0]
-
-
- ######################
- ### read serial number
- ######################
- def get_serial_number(self):
- result=""
- for iaddr in [0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff]:
- result+="%02x "%(self.eeprom_read(iaddr))
- pass
- return result
-
-
- #################
- ### set DAC value
- #################
- def set_dac(self,channel,value , vrefOn = 0 , i2cSlaveAddrDac = 0x1F):
- if channel<0 or channel>7:
- print "set_dac ERROR: channel",channel,"not in range 0-7 (bit mask)"
- return -1
- if value<0 or value>0xFFFF:
- print "set_dac ERROR: value",value,"not in range 0-0xFFFF"
- return -1
- # AD5665R chip with A0,A1 tied to ground
- #i2cSlaveAddrDac = 0x1F # seven bit address, binary 00011111
- print "I2C address of DAC = " , hex(i2cSlaveAddrDac)
- dac = RawI2cAccess(self.i2cBusProps, i2cSlaveAddrDac)
- # if we want to enable internal voltage reference:
- if vrefOn:
- # enter vref-on mode:
- print "Turning internal reference ON"
- dac.write([0x38,0x00,0x01])
- else:
- print "Turning internal reference OFF"
- dac.write([0x38,0x00,0x00])
- # now set the actual value
- sequence=[( 0x18 + ( channel &0x7 ) ) , (value/256)&0xff , value&0xff]
- print sequence
- dac.write(sequence)
-
-
-
- ##################################################
- ### convert required threshold voltage to DAC code
- ##################################################
- def convert_voltage_to_dac(self, desiredVoltage, Vref=1.300):
- Vdaq = ( desiredVoltage + Vref ) / 2
- dacCode = 0xFFFF * Vdaq / Vref
- return int(dacCode)
-
-
- ##################################################
- ### calculate the DAC code required and set DAC
- ##################################################
- def set_threshold_voltage(self, channel , voltage ):
- dacCode = self.convert_voltage_to_dac(voltage)
- print " requested voltage, calculated DAC code = " , voltage , dacCode
- self.set_dac(channel , dacCode)
diff --git a/packages/I2CDISP.py b/packages/I2CDISP.py
deleted file mode 100644
index 06ac0d8..0000000
--- a/packages/I2CDISP.py
+++ /dev/null
@@ -1,248 +0,0 @@
-# -*- coding: utf-8 -*-
-import uhal
-from packages.I2CuHal2 import I2CCore
-import time
-
-import math
-import numpy as np
-
-#######################################################################################
-class CFA632:
- #Class to configure the CFA632 display
-
- def __init__(self, i2c, slaveaddr=0x2A):
- self.i2c = i2c
- self.slaveaddr = slaveaddr
-
- def test(self):
- print("Testing the display")
- return
-
- def writeSomething(self, i2ccmd):
- mystop= True
- print("Write to CFA632")
- print("\t", i2ccmd)
- #myaddr= [int(i2ccmd)]
- self.i2c.write( self.slaveaddr, i2ccmd, mystop)
- return
-
-#######################################################################################
-class LCD_ada:
- def __init__(self, i2c, slaveaddr=0x20):
- self.i2c = i2c
- self.slaveaddr = slaveaddr
- self.nRows= 2
- self.nCols= 16
-
- def test(self):
- mystop= True
- i2ccmd= []
- print("Write to LCD_ada")
- print("\t", i2ccmd)
- #myaddr= [int(i2ccmd)]
- self.getIOdir()
- self.setIOdir(0x7F)
- self.getIOdir()
- self.setGPIO(0x80)
- self.i2c.write( self.slaveaddr, i2ccmd, mystop)
-
- def getGPIO(self):
- # Read port (if configured as inputs)
- mystop=False
- regN= 0x09
- nwords= 1
- self.i2c.write( self.slaveaddr, [regN], mystop)
- res= self.i2c.read( self.slaveaddr, nwords)
- print("MCP23008 IOdir", res)
- return res
-
- def setGPIO(self, gpio):
- # Sets the output latch
- mystop= True
- i2ccmd= [9, gpio]
- print("Write GPIO to MCP23008")
- self.i2c.write( self.slaveaddr, i2ccmd, mystop)
-
- def getIOdir(self):
- mystop=False
- regN= 0x00
- nwords= 1
- self.i2c.write( self.slaveaddr, [regN], mystop)
- res= self.i2c.read( self.slaveaddr, nwords)
- print("MCP23008 IOdir", res)
- return res
-
- def setIOdir(self, iodir):
- # 1 indicates the port is an input
- # 0 indicates the port is an output
- mystop= True
- i2ccmd= [0, iodir]
- print("Write IODIR to MCP23008")
- self.i2c.write( self.slaveaddr, i2ccmd, mystop)
-
-#######################################################################################
-class LCD09052:
- #Class to configure the LCD09052 display
-
- def __init__(self, i2c, slaveaddr=0x3A):
- self.i2c = i2c
- self.slaveaddr = slaveaddr
- self.nRows= 2
- self.nCols= 16
- self.setLCDtype(self.nRows, self.nCols)
-
- def test(self):
- print("\tTesting display (LCD09052)")
- self.clear()
- self.setBrightness(0)
- time.sleep(0.2)
- self.setBrightness(250)
- time.sleep(0.2)
- self.setBrightness(0)
- time.sleep(0.2)
- self.setBrightness(250)
- for ipos in range(1, 17):
- self.writeChar(33)
- self.posCursor(1, ipos-1)
- time.sleep(0.1)
- self.writeChar(254)
- self.posCursor(2, 1)
- for ipos in range(1, 17):
- self.writeChar(33)
- self.posCursor(2, ipos-1)
- time.sleep(0.1)
- self.writeChar(254)
- self.clear
- self.clearLine(1)
- self.writeChar(33)
- time.sleep(0.1)
- self.writeChar(33)
- time.sleep(0.1)
- self.writeChar(33)
- time.sleep(0.1)
- self.writeChar(33)
- time.sleep(0.1)
- self.writeChar(33)
- time.sleep(0.1)
- self.clearLine(1)
- self.writeString([80, 81, 80, 81, 82])
- return
-
- def test2(self, myString1= "", myString2= ""):
- #myString= [80, 81, 80, 81, 82]
- self.clear()
- self.dispString(myString1)
- self.posCursor(2, 1)
- self.dispString(myString2)
- self.pulseLCD(1)
- time.sleep(0.3)
- myChar= [0, 17, 0, 0, 17, 14, 0, 0]
- #self.writeChar(1)
- #time.sleep(1)
- #self.createChar(1, [31, 31, 31, 0, 17, 14, 0, 0])
- #self.createChar(2, [0, 0, 17, 0, 0, 17, 14, 0])
- #time.sleep(1)
- #self.writeChar(1)
- return
-
- def dispString(self, myString):
- ### Writes the string on the display
- myInts=[]
- for iChar in list(myString):
- myInts.append(ord(iChar))
- self.writeString(myInts)
- return
-
- def writeString(self, myChars):
- ### Writes a list of chars from the current position of the cursor
- ## NOTE: myChars is a list of integers corresponding to the ASCII code of each
- ## character to be printed. Use "dispString" to input an actual string.
- #i2ccmd= [1, myChars]
- myChars.insert(0, 1)
- mystop= True
- self.i2c.write( self.slaveaddr, myChars, mystop)
-
- def posCursor(self, line, pos):
- ### Position the cursor on a specific location
- ## line can be 1 (top) or 2 (bottom)
- ## pos can be [1, 16}
- if ( ((line==1) or (line==2)) and (1 <= pos <= self.nCols)):
- i2ccmd= [2, line, pos]
- mystop= True
- self.i2c.write( self.slaveaddr, i2ccmd, mystop)
- else:
- print("Cursor line can only be 1 or 2, position must be in range [1,", self.nCols, "]")
-
- def clearLine(self, iLine):
- ### Clear line. Place cursor at beginning of line.
- if ((iLine==1) or (iLine==2)):
- i2ccmd= [3, iLine]
- mystop= True
- self.i2c.write( self.slaveaddr, i2ccmd, mystop)
-
- def clear(self):
- ### Clears the display and locates the curson on position (1,1), i.e. top left
- i2ccmd= [4]
- mystop= True
- self.i2c.write( self.slaveaddr, i2ccmd, mystop)
-
- def setLCDtype(self, nLines, nColumns):
- ### Specifies the number of lines and columns in the display.
- ## This does not seem to do much but we use it anyway.
- ## NOTE: no check is performed on the nLines and nColumns parameters so be
- ## carefuls in using this function.
- i2ccmd= [5, nLines, nColumns]
- mystop= True
- self.i2c.write( self.slaveaddr, i2ccmd, mystop)
-
- def setBrightness(self, value= 250):
- ### Sets the brightness level of the backlight.
- ## Value is an integer in range [0, 250]. 0= no light, 250= maximum light.
- if value < 0:
- print("setBrightness: minimum value= 0. Coherced to 0")
- value = 0
- if value > 250:
- print("setBrightness: maximum value= 250. Coherced to 250")
- value = 250
- i2ccmd= [7, value]
- mystop= True
- self.i2c.write( self.slaveaddr, i2ccmd, mystop)
-
- def writeChar(self, value):
- ### Writes a char in the current cursor position
- ## The cursor is then shifted right one position
- ## value must be an integer corresponding to the ascii code of the character
- i2ccmd= [10, value]
- mystop= True
- self.i2c.write( self.slaveaddr, i2ccmd, mystop)
- return
-
- def createChar(self, pos=1, myChar=[]):
- ### Define a personalized character and stores it in position "pos"
- ## NOTE: This is not working yet.
- mystop= True
- myChar= [0, 17, 0, 0, 17, 14, 0, 0]
- myChar.insert(0, 64)
- self.i2c.write( self.slaveaddr, myChar, mystop)
- return
-
- def writeSomething(self, i2ccmd):
- mystop= True
- print("Write to LCD09052")
- print("\t", i2ccmd)
- #myaddr= [int(i2ccmd)]
- self.i2c.write( self.slaveaddr, i2ccmd, mystop)
- return
-
- def pulseLCD(self, nCycles):
- ### Sets the backlight to pulse for N cycles.
- ## Each cycle lasts approximately 1.5 s and start/stop on full brightness
- ## The light varies according to a sinusoidal wave
- startP= 0
- endP= nCycles*(math.pi)
- nPoints= 15*nCycles
- myList= np.linspace(startP, endP, nPoints).tolist()
- for iPt in myList:
- iBright= int(250*abs(math.cos(iPt)))
- self.setBrightness(iBright)
- time.sleep(0.1)
diff --git a/packages/I2CuHal.py b/packages/I2CuHal.py
deleted file mode 100644
index 434cec1..0000000
--- a/packages/I2CuHal.py
+++ /dev/null
@@ -1,282 +0,0 @@
-# -*- coding: utf-8 -*-
-"""
-
-"""
-
-import time
-
-import uhal
-
-verbose = True
-
-
-
-################################################################################
-# /*
-# I2C CORE
-# */
-################################################################################
-
-
-
-
-class I2CCore:
- """I2C communication block."""
-
- # Define bits in cmd_stat register
- startcmd = 0x1 << 7
- stopcmd = 0x1 << 6
- readcmd = 0x1 << 5
- writecmd = 0x1 << 4
- ack = 0x1 << 3
- intack = 0x1
-
- recvdack = 0x1 << 7
- busy = 0x1 << 6
- arblost = 0x1 << 5
- inprogress = 0x1 << 1
- interrupt = 0x1
-
- def __init__(self, target, wclk, i2cclk, name="i2c", delay=None):
- self.target = target
- self.name = name
- self.delay = delay
- self.prescale_low = self.target.getNode("%s.i2c_pre_lo" % name)
- self.prescale_high = self.target.getNode("%s.i2c_pre_hi" % name)
- self.ctrl = self.target.getNode("%s.i2c_ctrl" % name)
- self.data = self.target.getNode("%s.i2c_rxtx" % name)
- self.cmd_stat = self.target.getNode("%s.i2c_cmdstatus" % name)
- self.wishboneclock = wclk
- self.i2cclock = i2cclk
- self.config()
-
- def state(self):
- status = {}
- status["ps_low"] = self.prescale_low.read()
- status["ps_hi"] = self.prescale_high.read()
- status["ctrl"] = self.ctrl.read()
- status["data"] = self.data.read()
- status["cmd_stat"] = self.cmd_stat.read()
- self.target.dispatch()
- status["prescale"] = status["ps_hi"] << 8
- status["prescale"] |= status["ps_low"]
- for reg in status:
- val = status[reg]
- bval = bin(int(val))
- if verbose:
- print("\treg %s = %d, 0x%x, %s" % (reg, val, val, bval))
-
- def clearint(self):
- self.ctrl.write(0x1)
- self.target.dispatch()
-
- def config(self):
- #INITIALIZATION OF THE I2S MASTER CORE
- #Disable core
- self.ctrl.write(0x0 << 7)
- self.target.dispatch()
- #Write pre-scale register
- #prescale = int(self.wishboneclock / (5.0 * self.i2cclock)) - 1
- #prescale = int(self.wishboneclock / (5.0 * self.i2cclock))
- prescale = 0x0100 #FOR NOW HARDWIRED, TO BE MODIFIED
- self.prescale_low.write(prescale & 0xff)
- self.prescale_high.write((prescale & 0xff00) >> 8)
- #Enable core
- self.ctrl.write(0x1 << 7)
- self.target.dispatch()
-
- def checkack(self):
- inprogress = True
- ack = False
- while inprogress:
- cmd_stat = self.cmd_stat.read()
- self.target.dispatch()
- inprogress = (cmd_stat & I2CCore.inprogress) > 0
- ack = (cmd_stat & I2CCore.recvdack) == 0
- return ack
-
- def delayorcheckack(self):
- ack = True
- if self.delay is None:
- ack = self.checkack()
- else:
- time.sleep(self.delay)
- ack = self.checkack()#Remove this?
- return ack
-
-################################################################################
-# /*
-# I2C WRITE
-# */
-################################################################################
-
-
-
- def write(self, addr, data, stop=True):
- """Write data to the device with the given address."""
- # Start transfer with 7 bit address and write bit (0)
- nwritten = -1
- addr &= 0x7f
- addr = addr << 1
- startcmd = 0x1 << 7
- stopcmd = 0x1 << 6
- writecmd = 0x1 << 4
- #Set transmit register (write operation, LSB=0)
- self.data.write(addr)
- #Set Command Register to 0x90 (write, start)
- self.cmd_stat.write(I2CCore.startcmd | I2CCore.writecmd)
- self.target.dispatch()
- ack = self.delayorcheckack()
- if not ack:
- self.cmd_stat.write(I2CCore.stopcmd)
- self.target.dispatch()
- print("no ack from I2C address", hex(addr>>1))
- return nwritten
- nwritten += 1
- for val in data:
- val &= 0xff
- #Write slave memory address
- self.data.write(val)
- #Set Command Register to 0x10 (write)
- self.cmd_stat.write(I2CCore.writecmd)
- self.target.dispatch()
- ack = self.delayorcheckack()
- if not ack:
- self.cmd_stat.write(I2CCore.stopcmd)
- self.target.dispatch()
- return nwritten
- nwritten += 1
- if stop:
- self.cmd_stat.write(I2CCore.stopcmd)
- self.target.dispatch()
- return nwritten
-
-################################################################################
-# /*
-# I2C READ
-# */
-################################################################################
- def read(self, addr, n):
- """Read n bytes of data from the device with the given address."""
- # Start transfer with 7 bit address and read bit (1)
- data = []
- addr &= 0x7f
- addr = addr << 1
- addr |= 0x1 # read bit
- self.data.write(addr)
- self.cmd_stat.write(I2CCore.startcmd | I2CCore.writecmd)
- self.target.dispatch()
- ack = self.delayorcheckack()
- if not ack:
- self.cmd_stat.write(I2CCore.stopcmd)
- self.target.dispatch()
- return data
- for i in range(n):
- if i < (n-1):
- self.cmd_stat.write(I2CCore.readcmd) # <---
- else:
- self.cmd_stat.write(I2CCore.readcmd | I2CCore.ack | I2CCore.stopcmd) # <--- This tells the slave that it is the last word
- self.target.dispatch()
- ack = self.delayorcheckack()
- val = self.data.read()
- self.target.dispatch()
- data.append(val & 0xff)
- #self.cmd_stat.write(I2CCore.stopcmd)
- #self.target.dispatch()
- return data
-
-################################################################################
-# /*
-# I2C WRITE-READ
-# */
-################################################################################
-
-
-
- # def writeread(self, addr, data, n):
- # """Write data to device, then read n bytes back from it."""
- # nwritten = self.write(addr, data, stop=False)
- # readdata = []
- # if nwritten == len(data):
- # readdata = self.read(addr, n)
- # return nwritten, readdata
-
-"""
-SPI core XML:
-
-
-
-
-
-
-
-
-
-
-"""
-class SPICore:
-
- go_busy = 0x1 << 8
- rising = 1
- falling = 0
-
-
- def __init__(self, target, wclk, spiclk, basename="io.spi"):
- self.target = target
- # Only a single data register is required since all transfers are
- # 16 bit long
- self.data = target.getNode("%s.d0" % basename)
- self.control = target.getNode("%s.ctrl" % basename)
- self.control_val = 0b0
- self.divider = target.getNode("%s.divider" % basename)
- self.slaveselect = target.getNode("%s.ss" % basename)
- self.divider_val = int(wclk / spiclk / 2.0 - 1.0)
- self.divider_val = 0x7f
- self.configured = False
-
- def config(self):
- "Configure SPI interace for communicating with ADCs."
- self.divider_val = int(self.divider_val) % 0xffff
- if verbose:
- print("Configuring SPI core, divider = 0x%x" % self.divider_val)
- self.divider.write(self.divider_val)
- self.target.dispatch()
- self.control_val = 0x0
- self.control_val |= 0x0 << 13 # Automatic slave select
- self.control_val |= 0x0 << 12 # No interrupt
- self.control_val |= 0x0 << 11 # MSB first
- # ADC samples data on rising edge of SCK
- self.control_val |= 0x1 << 10 # change ouput on falling edge of SCK
- # ADC changes output shortly after falling edge of SCK
- self.control_val |= 0x0 << 9 # read input on rising edge
- self.control_val |= 0x10 # 16 bit transfers
- if verbose:
- print("SPI control val = 0x%x = %s" % (self.control_val, bin(self.control_val)))
- self.configured = True
-
- def transmit(self, chip, value):
- if not self.configured:
- self.config()
- assert chip >= 0 and chip < 8
- value &= 0xffff
- self.data.write(value)
- checkdata = self.data.read()
- self.target.dispatch()
- assert checkdata == value
- self.control.write(self.control_val)
- self.slaveselect.write(0xff ^ (0x1 << chip))
- self.target.dispatch()
- self.control.write(self.control_val | SPICore.go_busy)
- self.target.dispatch()
- busy = True
- while busy:
- status = self.control.read()
- self.target.dispatch()
- busy = status & SPICore.go_busy > 0
- self.slaveselect.write(0xff)
- data = self.data.read()
- ss = self.slaveselect.read()
- status = self.control.read()
- self.target.dispatch()
- #print "Received data: 0x%x, status = 0x%x, ss = 0x%x" % (data, status, ss)
- return data
diff --git a/packages/I2CuHal2.py b/packages/I2CuHal2.py
deleted file mode 100644
index bf9f325..0000000
--- a/packages/I2CuHal2.py
+++ /dev/null
@@ -1,282 +0,0 @@
-# -*- coding: utf-8 -*-
-"""
-
-"""
-
-import time
-
-import uhal
-
-verbose = True
-
-
-
-################################################################################
-# /*
-# I2C CORE
-# */
-################################################################################
-
-### Same as the class defined in I2CuHal.py but the register names are changed to
-### comply with D. Newbold's notation. To be used in the Dune SFP Fanout (pc059a)
-
-class I2CCore:
- """I2C communication block."""
-
- # Define bits in cmd_stat register
- startcmd = 0x1 << 7
- stopcmd = 0x1 << 6
- readcmd = 0x1 << 5
- writecmd = 0x1 << 4
- ack = 0x1 << 3
- intack = 0x1
-
- recvdack = 0x1 << 7
- busy = 0x1 << 6
- arblost = 0x1 << 5
- inprogress = 0x1 << 1
- interrupt = 0x1
-
- def __init__(self, target, wclk, i2cclk, name="i2c", delay=None):
- self.target = target
- self.name = name
- self.delay = delay
- self.prescale_low = self.target.getNode("%s.ps_lo" % name)
- self.prescale_high = self.target.getNode("%s.ps_hi" % name)
- self.ctrl = self.target.getNode("%s.ctrl" % name)
- self.data = self.target.getNode("%s.data" % name)
- self.cmd_stat = self.target.getNode("%s.cmd_stat" % name)
- self.wishboneclock = wclk
- self.i2cclock = i2cclk
- self.config()
-
- def state(self):
- status = {}
- status["ps_low"] = self.prescale_low.read()
- status["ps_hi"] = self.prescale_high.read()
- status["ctrl"] = self.ctrl.read()
- status["data"] = self.data.read()
- status["cmd_stat"] = self.cmd_stat.read()
- self.target.dispatch()
- status["prescale"] = status["ps_hi"] << 8
- status["prescale"] |= status["ps_low"]
- for reg in status:
- val = status[reg]
- bval = bin(int(val))
- if verbose:
- print("\treg %s = %d, 0x%x, %s" % (reg, val, val, bval))
-
- def clearint(self):
- self.ctrl.write(0x1)
- self.target.dispatch()
-
- def config(self):
- #INITIALIZATION OF THE I2S MASTER CORE
- #Disable core
- self.ctrl.write(0x0 << 7)
- self.target.dispatch()
- #Write pre-scale register
- #prescale = int(self.wishboneclock / (5.0 * self.i2cclock)) - 1
- #prescale = int(self.wishboneclock / (5.0 * self.i2cclock))
- prescale = 0x0100 #FOR NOW HARDWIRED, TO BE MODIFIED
- self.prescale_low.write(prescale & 0xff)
- self.prescale_high.write((prescale & 0xff00) >> 8)
- #Enable core
- self.ctrl.write(0x1 << 7)
- self.target.dispatch()
-
- def checkack(self):
- inprogress = True
- ack = False
- while inprogress:
- cmd_stat = self.cmd_stat.read()
- self.target.dispatch()
- inprogress = (cmd_stat & I2CCore.inprogress) > 0
- ack = (cmd_stat & I2CCore.recvdack) == 0
- return ack
-
- def delayorcheckack(self):
- ack = True
- if self.delay is None:
- ack = self.checkack()
- else:
- time.sleep(self.delay)
- ack = self.checkack()#Remove this?
- return ack
-
-################################################################################
-# /*
-# I2C WRITE
-# */
-################################################################################
-
-
-
- def write(self, addr, data, stop=True):
- """Write data to the device with the given address."""
- # Start transfer with 7 bit address and write bit (0)
- nwritten = -1
- addr &= 0x7f
- addr = addr << 1
- startcmd = 0x1 << 7
- stopcmd = 0x1 << 6
- writecmd = 0x1 << 4
- #Set transmit register (write operation, LSB=0)
- self.data.write(addr)
- #Set Command Register to 0x90 (write, start)
- self.cmd_stat.write(I2CCore.startcmd | I2CCore.writecmd)
- self.target.dispatch()
- ack = self.delayorcheckack()
- if not ack:
- self.cmd_stat.write(I2CCore.stopcmd)
- self.target.dispatch()
- print("no ack from I2C address", hex(addr>>1))
- return nwritten
- nwritten += 1
- for val in data:
- val &= 0xff
- #Write slave memory address
- self.data.write(val)
- #Set Command Register to 0x10 (write)
- self.cmd_stat.write(I2CCore.writecmd)
- self.target.dispatch()
- ack = self.delayorcheckack()
- if not ack:
- self.cmd_stat.write(I2CCore.stopcmd)
- self.target.dispatch()
- return nwritten
- nwritten += 1
- if stop:
- self.cmd_stat.write(I2CCore.stopcmd)
- self.target.dispatch()
- return nwritten
-
-################################################################################
-# /*
-# I2C READ
-# */
-################################################################################
- def read(self, addr, n):
- """Read n bytes of data from the device with the given address."""
- # Start transfer with 7 bit address and read bit (1)
- data = []
- addr &= 0x7f
- addr = addr << 1
- addr |= 0x1 # read bit
- self.data.write(addr)
- self.cmd_stat.write(I2CCore.startcmd | I2CCore.writecmd)
- self.target.dispatch()
- ack = self.delayorcheckack()
- if not ack:
- self.cmd_stat.write(I2CCore.stopcmd)
- self.target.dispatch()
- return data
- for i in range(n):
- if i < (n-1):
- self.cmd_stat.write(I2CCore.readcmd) # <---
- else:
- self.cmd_stat.write(I2CCore.readcmd | I2CCore.ack | I2CCore.stopcmd) # <--- This tells the slave that it is the last word
- self.target.dispatch()
- ack = self.delayorcheckack()
- val = self.data.read()
- self.target.dispatch()
- data.append(val & 0xff)
- #self.cmd_stat.write(I2CCore.stopcmd)
- #self.target.dispatch()
- return data
-
-################################################################################
-# /*
-# I2C WRITE-READ
-# */
-################################################################################
-
-
-
- # def writeread(self, addr, data, n):
- # """Write data to device, then read n bytes back from it."""
- # nwritten = self.write(addr, data, stop=False)
- # readdata = []
- # if nwritten == len(data):
- # readdata = self.read(addr, n)
- # return nwritten, readdata
-
-"""
-SPI core XML:
-
-
-
-
-
-
-
-
-
-
-"""
-class SPICore:
-
- go_busy = 0x1 << 8
- rising = 1
- falling = 0
-
-
- def __init__(self, target, wclk, spiclk, basename="io.spi"):
- self.target = target
- # Only a single data register is required since all transfers are
- # 16 bit long
- self.data = target.getNode("%s.d0" % basename)
- self.control = target.getNode("%s.ctrl" % basename)
- self.control_val = 0b0
- self.divider = target.getNode("%s.divider" % basename)
- self.slaveselect = target.getNode("%s.ss" % basename)
- self.divider_val = int(wclk / spiclk / 2.0 - 1.0)
- self.divider_val = 0x7f
- self.configured = False
-
- def config(self):
- "Configure SPI interace for communicating with ADCs."
- self.divider_val = int(self.divider_val) % 0xffff
- if verbose:
- print("Configuring SPI core, divider = 0x%x" % self.divider_val)
- self.divider.write(self.divider_val)
- self.target.dispatch()
- self.control_val = 0x0
- self.control_val |= 0x0 << 13 # Automatic slave select
- self.control_val |= 0x0 << 12 # No interrupt
- self.control_val |= 0x0 << 11 # MSB first
- # ADC samples data on rising edge of SCK
- self.control_val |= 0x1 << 10 # change ouput on falling edge of SCK
- # ADC changes output shortly after falling edge of SCK
- self.control_val |= 0x0 << 9 # read input on rising edge
- self.control_val |= 0x10 # 16 bit transfers
- if verbose:
- print("SPI control val = 0x%x = %s" % (self.control_val, bin(self.control_val)))
- self.configured = True
-
- def transmit(self, chip, value):
- if not self.configured:
- self.config()
- assert chip >= 0 and chip < 8
- value &= 0xffff
- self.data.write(value)
- checkdata = self.data.read()
- self.target.dispatch()
- assert checkdata == value
- self.control.write(self.control_val)
- self.slaveselect.write(0xff ^ (0x1 << chip))
- self.target.dispatch()
- self.control.write(self.control_val | SPICore.go_busy)
- self.target.dispatch()
- busy = True
- while busy:
- status = self.control.read()
- self.target.dispatch()
- busy = status & SPICore.go_busy > 0
- self.slaveselect.write(0xff)
- data = self.data.read()
- ss = self.slaveselect.read()
- status = self.control.read()
- self.target.dispatch()
- #print "Received data: 0x%x, status = 0x%x, ss = 0x%x" % (data, status, ss)
- return data
diff --git a/packages/I2cBusProperties.py b/packages/I2cBusProperties.py
deleted file mode 100644
index a23f30c..0000000
--- a/packages/I2cBusProperties.py
+++ /dev/null
@@ -1,122 +0,0 @@
-##########################################################
-# I2cBusProperties - simple encapsulation of all items
-# required to control an I2C bus.
-#
-# Carl Jeske, July 2010
-# Refactored by Robert Frazier, May 2011
-##########################################################
-
-
-class I2cBusProperties(object):
- """Encapsulates details of an I2C bus master in the form of a host device, a clock prescale value, and seven I2C master registers
-
- Provide the ChipsBus instance to the device hosting your I2C core, a 16-bit clock prescaling
- value for the Serial Clock Line (see I2C core docs for details), and the names of the seven
- registers that define/control the bus (assuming these names are not the defaults specified
- in the constructor below). The seven registers consist of the two clock pre-scaling
- registers (PRElo, PREhi), and five bus master registers (CONTROL, TRANSMIT, RECEIVE,
- COMMAND and STATUS).
-
- Usage: You'll need to create an instance of this class to give to a concrete I2C bus instance, such
- as OpenCoresI2cBus. This I2cBusProperties class is simply a container to hold the properties
- that define the bus; a class such as OpenCoresI2cBus will make use of these properties.
-
- Access the items stored by this class via these (deliberately compact) variable names:
-
- chipsBus -- the ChipsBus device hosting the I2C core
- preHiVal -- the top byte of the clock prescale value
- preLoVal -- the bottom byte of the clock prescale value
- preHiReg -- the register the top byte of the clk prescale value (preHiVal) gets written to
- preLoReg -- the register the bottom byte of the clk prescale value (preLoVal) gets written to
- ctrlReg -- the I2C Control register
- txReg -- the I2C Transmit register
- rxReg -- the I2C Receive register
- cmdReg -- the I2C Command register
- statusReg -- the I2C Status register
-
-
- Compatibility Notes: The seven register names are the registers typically required to operate an
- OpenCores or similar I2C Master (Lattice Semiconductor's I2C bus master works
- the same way as the OpenCores one). This software is not compatible with your
- I2C bus master if it doesn't use this register interface.
- """
-
- def __init__(self,
- chipsBusDevice,
- clkPrescaleU16,
- clkPrescaleLoByteReg = "i2c_pre_lo",
- clkPrescaleHiByteReg = "i2c_pre_hi",
- controlReg = "i2c_ctrl",
- transmitReg = "i2c_tx",
- receiveReg = "i2c_rx",
- commandReg = "i2c_cmd",
- statusReg = "i2c_status"):
-
- """Provide a host ChipsBus device that is controlling the I2C bus, and the names of five I2C control registers.
-
- chipsBusDevice: Provide a ChipsBus instance to the device where the I2C bus is being
- controlled. The address table for this device must contain the five registers
- that control the bus, as declared next...
-
- clkPrescaleU16: A 16-bit value used to prescale the Serial Clock Line based on the host
- master-clock. This value gets split into two 8-bit values and ultimately will
- get written to the two I2C clock-prescale registers as declared below. See
- the OpenCores or Lattice Semiconductor I2C documentation for more details.
-
- clkPrescaleLoByteReg: The register where the lower byte of the clock prescale value is set. The default
- name for this register is "i2c_pre_lo".
-
- clkPrescaleHiByteReg: The register where the higher byte of the clock prescale value is set. The default
- name for this register is "i2c_pre_hi"
-
- controlReg: The CONTROL register, used for enabling/disabling the I2C core, etc. This register is
- usually read and write accessible. The default name for this register is "i2c_ctrl".
-
- transmitReg: The TRANSMIT register, used for holding the data to be transmitted via I2C, etc. This
- typically shares the same address as the RECEIVE register, but has write-only access. The default
- name for this register is "i2c_tx".
-
- receiveReg: The RECEIVE register - allows access to the byte received over the I2C bus. This
- typically shares the same address as the TRANSMIT register, but has read-only access. The
- default name for this register is "i2c_rx".
-
- commandReg: The COMMAND register - stores the command for the next I2C operation. This typically
- shares the same address as the STATUS register, but has write-only access. The default name for
- this register is "i2c_cmd".
-
- statusReg: The STATUS register - allows monitoring of the I2C operations. This typically shares
- the same address as the COMMAND register, but has read-only access. The default name for this
- register is "i2c_status".
- """
-
- object.__init__(self)
- self.chipsBus = chipsBusDevice
- self.preHiVal = ((clkPrescaleU16 & 0xff00) >> 8)
- self.preLoVal = (clkPrescaleU16 & 0xff)
-
- # Check to see all the registers are in the address table
- registers = [clkPrescaleLoByteReg, clkPrescaleHiByteReg, controlReg, transmitReg, receiveReg, commandReg, statusReg]
- for reg in registers:
- if not self.chipsBus.addrTable.checkItem(reg):
- raise ChipsException("I2cBusProperties error: register '" + reg + "' is not present in the address table of the device hosting the I2C bus master!")
-
- # Check that the registers we'll need to write to are indeed writable
- writableRegisters = [clkPrescaleLoByteReg, clkPrescaleHiByteReg, controlReg, transmitReg, commandReg]
- for wReg in writableRegisters:
- if not self.chipsBus.addrTable.getItem(wReg).getWriteFlag():
- raise ChipsException("I2cBusProperties error: register '" + wReg + "' does not have the necessary write permission!")
-
- # Check that the registers we'll need to read from are indeed readable
- readableRegisters = [clkPrescaleLoByteReg, clkPrescaleHiByteReg, controlReg, receiveReg, statusReg]
- for rReg in readableRegisters:
- if not self.chipsBus.addrTable.getItem(rReg).getReadFlag():
- raise ChipsException("I2cBusProperties error: register '" + rReg + "' does not have the necessary read permission!")
-
- # Store the various register name strings
- self.preHiReg = clkPrescaleHiByteReg
- self.preLoReg = clkPrescaleLoByteReg
- self.ctrlReg = controlReg
- self.txReg = transmitReg
- self.rxReg = receiveReg
- self.cmdReg = commandReg
- self.statusReg = statusReg
diff --git a/packages/NHDC0220Biz.py b/packages/NHDC0220Biz.py
deleted file mode 100644
index acb265b..0000000
--- a/packages/NHDC0220Biz.py
+++ /dev/null
@@ -1,23 +0,0 @@
-# -*- coding: utf-8 -*-
-import uhal
-from I2CuHal import I2CCore
-import StringIO
-
-class NHDC0220Biz:
- #Class to configure the EEPROM
-
- def __init__(self, i2c, slaveaddr=0x3c):
- self.i2c = i2c
- self.slaveaddr = 0x2a#slaveaddr
-
- def test(self):
- print "Testing the display"
- return
-
- def writeSomething(self):
- mystop= True
- print "Write random stuff"
- myaddr= [0x08, 0x38]
- self.i2c.write( self.slaveaddr, myaddr, mystop)
-
- return
diff --git a/packages/PCA9539PW.py b/packages/PCA9539PW.py
deleted file mode 100644
index b387b80..0000000
--- a/packages/PCA9539PW.py
+++ /dev/null
@@ -1,94 +0,0 @@
-# -*- coding: utf-8 -*-
-import uhal
-from packages.I2CuHal import I2CCore
-
-
-class PCA9539PW:
- #Class to configure the expander modules
-
- def __init__(self, i2c, slaveaddr=0x74):
- self.i2c = i2c
- self.slaveaddr = slaveaddr
-
-
- def writeReg(self, regN, regContent, verbose=False):
- #Basic functionality to write to register.
- if (regN < 0) | (regN > 7):
- print("PCA9539PW - ERROR: register number should be in range [0:7]")
- return
- regContent= regContent & 0xFF
- mystop=True
- cmd= [regN, regContent]
- self.i2c.write( self.slaveaddr, cmd, mystop)
-
-
- def readReg(self, regN, nwords, verbose=False):
- #Basic functionality to read from register.
- if (regN < 0) | (regN > 7):
- print("PCA9539PW - ERROR: register number should be in range [0:7]")
- return
- mystop=False
- self.i2c.write( self.slaveaddr, [regN], mystop)
- res= self.i2c.read( self.slaveaddr, nwords)
- return res
-
-
- def setInvertReg(self, regN, polarity= 0x00):
- #Set the content of register 4 or 5 which determine the polarity of the
- #ports (0= normal, 1= inverted).
- if (regN < 0) | (regN > 1):
- print("PCA9539PW - ERROR: regN should be 0 or 1")
- return
- polarity = polarity & 0xFF
- self.writeReg(regN+4, polarity)
-
- def getInvertReg(self, regN):
- #Read the content of register 4 or 5 which determine the polarity of the
- #ports (0= normal, 1= inverted).
- if (regN < 0) | (regN > 1):
- print("PCA9539PW - ERROR: regN should be 0 or 1")
- return
- res= self.readReg(regN+4, 1)
- return res
-
- def setIOReg(self, regN, direction= 0xFF):
- #Set the content of register 6 or 7 which determine the direction of the
- #ports (0= output, 1= input).
- if (regN < 0) | (regN > 1):
- print("PCA9539PW - ERROR: regN should be 0 or 1")
- return
- direction = direction & 0xFF
- self.writeReg(regN+6, direction)
-
- def getIOReg(self, regN):
- #Read the content of register 6 or 7 which determine the polarity of the
- #ports (0= normal, 1= inverted).
- if (regN < 0) | (regN > 1):
- print("PCA9539PW - ERROR: regN should be 0 or 1")
- return
- res= self.readReg(regN+6, 1)
- return res
-
- def getInputs(self, bank):
- #Read the incoming values of the pins for one of the two 8-bit banks.
- if (bank < 0) | (bank > 1):
- print("PCA9539PW - ERROR: bank should be 0 or 1")
- return
- res= self.readReg(bank, 1)
- return res
-
- def setOutputs(self, bank, values= 0x00):
- #Set the content of the output flip-flops.
- if (bank < 0) | (bank > 1):
- print("PCA9539PW - ERROR: bank should be 0 or 1")
- return
- values = values & 0xFF
- self.writeReg(bank+2, values)
-
- def getOutputs(self, bank):
- #Read the state of the outputs (i.e. what value is being written to them)
- if (bank < 0) | (bank > 1):
- print("PCA9539PW - ERROR: bank should be 0 or 1")
- return
- res= self.readReg(bank+2, 1)
- return res
diff --git a/packages/PCA9548ADW.py b/packages/PCA9548ADW.py
deleted file mode 100644
index adb6742..0000000
--- a/packages/PCA9548ADW.py
+++ /dev/null
@@ -1,51 +0,0 @@
-# -*- coding: utf-8 -*-
-import uhal
-from I2CuHal import I2CCore
-import StringIO
-
-
-class PCA9548ADW:
- #Class to configure the I2C multiplexer
-
- def __init__(self, i2c, slaveaddr=0x74):
- self.i2c = i2c
- self.slaveaddr = slaveaddr
-
- def disableAllChannels(self, verbose=False):
- #Disable all channels so that none of the MUX outputs is visible
- # to the upstream I2C bus
- mystop=True
- cmd= [0x0]
- self.i2c.write( self.slaveaddr, cmd, mystop)
-
- def getChannelStatus(self, verbose=False):
- #Basic functionality to read the status of the control register and determine
- # which channel is currently enabled.
- mystop=False
- cmd= []
- self.i2c.write( self.slaveaddr, cmd, mystop)
- res= self.i2c.read( self.slaveaddr, 1)
- return res[0]
-
- def setActiveChannel(self, channel, verbose=False):
- #Basic functionality to activate one channel
- # In principle multiple channels can be active at the same time (see
- # function "setMultipleChannels")
- if (channel < 0) | (channel > 7):
- print "PCA9539PW - ERROR: channel number should be in range [0:7]"
- return
- mystop=True
- cmd= [0x1 << channel]
- #print "\tChannel is ", channel, "we write ", cmd
- self.i2c.write( self.slaveaddr, cmd, mystop)
-
- def setMultipleChannels(self, channels, verbose=False):
- #Basic functionality to activate multiple channels
- # channels is a byte: each bit set to one will set the corresponding channels
- # as active. The slave connected to that channel will be visible on the I2C bus.
- # NOTE: this can lead to address clashes!
- channels = channels & 0xFF
- mystop=True
- cmd= [channels]
- #print "\tChannel is ", channel, "we write ", cmd
- self.i2c.write( self.slaveaddr, cmd, mystop)
diff --git a/packages/RawI2cAccess.py b/packages/RawI2cAccess.py
deleted file mode 100644
index 2846132..0000000
--- a/packages/RawI2cAccess.py
+++ /dev/null
@@ -1,261 +0,0 @@
-# Created on Sep 10, 2012
-# @author: Kristian Harder, based on code by Carl Jeske
-
-from I2cBusProperties import I2cBusProperties
-from ChipsBus import ChipsBus
-from ChipsLog import chipsLog
-from ChipsException import ChipsException
-
-
-class RawI2cAccess:
-
- def __init__(self, i2cBusProps, slaveAddr):
-
- # For performing read/writes over an OpenCores-compatible I2C bus master
- #
- # An instance of this class is required to communicate with each
- # I2C slave on the I2C bus.
- #
- # i2cBusProps: an instance of the class I2cBusProperties that contains
- # the relevant ChipsBus host and the I2C bus-master registers (if
- # they differ from the defaults specified by the I2cBusProperties
- # class).
- #
- #slaveAddr: The address of the I2C slave you wish to communicate with.
- #
-
- self._i2cProps = i2cBusProps # The I2C Bus Properties
- self._slaveAddr = 0x7f & slaveAddr # 7-bit slave address
-
-
- def resetI2cBus(self):
-
- # Resets the I2C bus
- #
- # This function does the following:
- # 1) Disables the I2C core
- # 2) Sets the clock prescale registers
- # 3) Enables the I2C core
- # 4) Sets all writable bus-master registers to default values
-
- try:
- self._chipsBus().queueWrite(self._i2cProps.ctrlReg, 0x00)
- #self._chipsBus().getNode(self._i2cProps.ctrlReg).write(0)
- self._chipsBus().queueWrite(self._i2cProps.preHiReg,
- self._i2cProps.preHiVal)
- self._chipsBus().queueWrite(self._i2cProps.preLoReg,
- self._i2cProps.preLoVal)
- self._chipsBus().queueWrite(self._i2cProps.ctrlReg, 0x80)
- self._chipsBus().queueWrite(self._i2cProps.txReg, 0x00)
- self._chipsBus().queueWrite(self._i2cProps.cmdReg, 0x00)
- self._chipsBus().queueRun()
- except ChipsException, err:
- raise ChipsException("I2C reset error:\n\t" + str(err))
-
-
- def read(self, numBytes):
-
- # Performs an I2C read. Returns the 8-bit read result(s).
- #
- # numBytes: number of bytes expected as response
- #
-
- try:
- result = self._privateRead(numBytes)
- except ChipsException, err:
- raise ChipsException("I2C read error:\n\t" + str(err))
- return result
-
-
- def write(self, listDataU8):
-
- # Performs an 8-bit I2C write.
- #
- # listDataU8: The 8-bit data values to be written.
- #
-
- try:
- self._privateWrite(listDataU8)
- except ChipsException, err:
- raise ChipsException("I2C write error:\n\t" + str(err))
- return
-
-
- def _chipsBus(self):
-
- # Returns the instance of the ChipsBus device that's hosting
- # the I2C bus master
-
- return self._i2cProps.chipsBus
-
-
- def _privateRead(self, numBytes):
-
- # I2C read implementation.
- #
- # Fast I2C read implementation,
- # i.e. done with the fewest packets possible.
-
-
- # transmit reg definitions
- # bits 7-1: 7-bit slave address during address transfer
- # or first 7 bits of byte during data transfer
- # bit 0: RW flag during address transfer or LSB during data transfer.
- # '1' = reading from slave
- # '0' = writing to slave
-
- # command reg definitions
- # bit 7: Generate start condition
- # bit 6: Generate stop condition
- # bit 5: Read from slave
- # bit 4: Write to slave
- # bit 3: 0 when acknowledgement is received
- # bit 2:1: Reserved
- # bit 0: Interrupt acknowledge. When set, clears a pending interrupt
-
- # Reset bus before beginning
- self.resetI2cBus()
-
- # Set slave address in bits 7:1, and set bit 0 to zero
- # (i.e. we're writing an address to the bus)
- self._chipsBus().queueWrite(self._i2cProps.txReg,
- (self._slaveAddr << 1) | 0x01)
- # Set start and write bit in command reg
- self._chipsBus().queueWrite(self._i2cProps.cmdReg, 0x90)
- # Run the queue
- self._chipsBus().queueRun()
- # Wait for transaction to finish.
- self._i2cWaitUntilFinished()
-
- result=[]
- for ibyte in range(numBytes):
- if ibyte==numBytes-1:
- stop_bit=0x40
- ack_bit=0x08
- else:
- stop_bit=0
- ack_bit=0
- pass
- # Set read bit, acknowledge and stop bit in command reg
- self._chipsBus().write(self._i2cProps.cmdReg, 0x20+ack_bit+stop_bit)
- # Wait for transaction to finish.
- # Don't expect an ACK, do expect bus free at finish.
- if stop_bit:
- self._i2cWaitUntilFinished(requireAcknowledgement = False,
- requireBusIdleAtEnd = True)
- else:
- self._i2cWaitUntilFinished(requireAcknowledgement = False,
- requireBusIdleAtEnd = False)
- pass
- result.append(self._chipsBus().read(self._i2cProps.rxReg))
-
- return result
-
-
- def _privateWrite(self, listDataU8):
-
- # I2C write implementation.
- #
- # Fast I2C write implementation,
- # i.e. done with the fewest packets possible.
-
- # transmit reg definitions
- # bits 7-1: 7-bit slave address during address transfer
- # or first 7 bits of byte during data transfer
- # bit 0: RW flag during address transfer or LSB during data transfer.
- # '1' = reading from slave
- # '0' = writing to slave
-
- # command reg definitions
- # bit 7: Generate start condition
- # bit 6: Generate stop condition
- # bit 5: Read from slave
- # bit 4: Write to slave
- # bit 3: 0 when acknowledgement is received
- # bit 2:1: Reserved
- # bit 0: Interrupt acknowledge. When set, clears a pending interrupt
- # Reset bus before beginning
- self.resetI2cBus()
-
- # Set slave address in bits 7:1, and set bit 0 to zero (i.e. "write mode")
- self._chipsBus().queueWrite(self._i2cProps.txReg,
- (self._slaveAddr << 1) & 0xfe)
- # Set start and write bit in command reg
- self._chipsBus().queueWrite(self._i2cProps.cmdReg, 0x90)
- # Run the queue
- self._chipsBus().queueRun()
- # Wait for transaction to finish.
- self._i2cWaitUntilFinished()
-
- for ibyte in range(len(listDataU8)):
- dataU8 = listDataU8[ibyte]
- if ibyte==len(listDataU8)-1:
- stop_bit=0x40
- else:
- stop_bit=0x00
- pass
- # Set data to be written in transmit reg
- self._chipsBus().queueWrite(self._i2cProps.txReg, (dataU8 & 0xff))
- # Set write and stop bit in command reg
- self._chipsBus().queueWrite(self._i2cProps.cmdReg, 0x10+stop_bit)
- # Run the queue
- self._chipsBus().queueRun()
- # Wait for transaction to finish.
- # Do expect an ACK and do expect bus to be free at finish
- if stop_bit:
- self._i2cWaitUntilFinished(requireAcknowledgement = True,
- requireBusIdleAtEnd = True)
- else:
- self._i2cWaitUntilFinished(requireAcknowledgement = True,
- requireBusIdleAtEnd = False)
- pass
- pass
-
- return
-
-
- def _i2cWaitUntilFinished(self, requireAcknowledgement = True,
- requireBusIdleAtEnd = False):
-
- # Ensures the current bus transaction has finished successfully
- # before allowing further I2C bus transactions
-
- # This method monitors the status register
- # and will not allow execution to continue until the
- # I2C bus has completed properly. It will throw an exception
- # if it picks up bus problems or a bus timeout occurs.
-
- maxRetry = 20
- attempt = 1
- while attempt <= maxRetry:
-
- # Get the status
- i2c_status = self._chipsBus().read(self._i2cProps.statusReg)
-
- receivedAcknowledge = not bool(i2c_status & 0x80)
- busy = bool(i2c_status & 0x40)
- arbitrationLost = bool(i2c_status & 0x20)
- transferInProgress = bool(i2c_status & 0x02)
- interruptFlag = bool(i2c_status & 0x01)
-
- if arbitrationLost: # This is an instant error at any time
- raise ChipsException("I2C error: Arbitration lost!")
-
- if not transferInProgress:
- break # The transfer looks to have completed successfully, pending further checks
-
- attempt += 1
-
- # At this point, we've either had too many retries, or the
- # Transfer in Progress (TIP) bit went low. If the TIP bit
- # did go low, then we do a couple of other checks to see if
- # the bus operated as expected:
-
- if attempt > maxRetry:
- raise ChipsException("I2C error: Transaction timeout - the 'Transfer in Progress' bit remained high for too long!")
-
- if requireAcknowledgement and not receivedAcknowledge:
- raise ChipsException("I2C error: No acknowledge received!")
-
- if requireBusIdleAtEnd and busy:
- raise ChipsException("I2C error: Transfer finished but bus still busy!")
diff --git a/packages/SFPI2C.py b/packages/SFPI2C.py
deleted file mode 100644
index 2dad8d4..0000000
--- a/packages/SFPI2C.py
+++ /dev/null
@@ -1,91 +0,0 @@
-# -*- coding: utf-8 -*-
-import uhal
-from I2CuHal import I2CCore
-import StringIO
-
-class SFPI2C:
- #Class to configure the EEPROM
-
- def __init__(self, i2c, slaveaddr=0x50):
- self.i2c = i2c
- self.slaveaddr = slaveaddr
-
- """def readEEPROM(self, startadd, nBytes):
- #Read EEPROM memory locations
- mystop= False
- myaddr= [startadd]#0xfa
- self.i2c.write( self.slaveaddr, [startadd], mystop)
- res= self.i2c.read( self.slaveaddr, nBytes)
- return res"""
-
- def _listToString(self, mylist):
- mystring= ""
- for iChar in mylist:
- mystring= mystring + str(unichr(iChar))
- return mystring
-
- def writeReg(self, regN, regContent, verbose=False):
- #Basic functionality to write to register.
- if (regN < 0) | (regN > 7):
- print "PCA9539PW - ERROR: register number should be in range [0:7]"
- return
- regContent= regContent & 0xFF
- mystop=True
- cmd= [regN, regContent]
- self.i2c.write( self.slaveaddr, cmd, mystop)
-
- def readReg(self, regN, nwords, verbose=False):
- #Basic functionality to read from register.
- mystop=False
- self.i2c.write( self.slaveaddr, [regN], mystop)
- res= self.i2c.read( self.slaveaddr, nwords)
- return res
-
- def getConnector(self):
- """Code for connector type (table 3.4)"""
- conntype= self.readReg(2, 1, False)[0]
- print "Connector type:", hex(conntype)
- return conntype
-
- def getDiagnosticsType(self):
- """Types of diagnostics available (table 3.9)"""
- diaType= self.readReg(92, 1, False)[0]
- print "Available Diagnostics:", hex(diaType)
- return diaType
-
- def getEncoding(self):
- encoding= self.readReg(11, 1, False)[0]
- print "Encoding", encoding
- return encoding
-
- def getEnhancedOpt(self):
- enOpt= self.readReg(93, 1, False)[0]
- print "Enhanced Options:", enOpt
- return enOpt
-
- def getTransceiver(self):
- res= self.readReg(3, 8, False)
- return res
-
- def getVendorId(self):
- """ Returns the OUI vendor id"""
- vendID= self.readReg(37, 3, False)
- return vendID
-
- def getVendorName(self):
- res= self.readReg( 20 , 16, False)
- mystring= self._listToString(res)
- return mystring
-
- def getVendorPN(self):
- """ Returns the part number defined by the vendor"""
- pn=[]
- mystring= ""
- res= self.readReg( 40 , 16, False)
- mystring= self._listToString(res)
- return mystring
-
- def scanI2C(self):
- mystop=True
- for iAddr in range (0, 128):
- self.i2c.write( iAddr, [], mystop)
diff --git a/packages/TLU_powermodule.py b/packages/TLU_powermodule.py
deleted file mode 100644
index 5eb9757..0000000
--- a/packages/TLU_powermodule.py
+++ /dev/null
@@ -1,339 +0,0 @@
-# -*- coding: utf-8 -*-
-import uhal
-from packages.I2CuHal import I2CCore
-#import StringIO
-from packages.AD5665R import AD5665R # Library for DAC
-from packages.PCA9539PW import PCA9539PW # Library for serial line expander
-import time
-
-class PWRLED:
- #Class to configure the EEPROM
-
- def __init__(self, i2ccore, DACaddr=0x1C, PMTmaxV= 1, Exp1Add= 0x76, Exp2Add= 0x77):
- print(" TLU POWERMODULE Initializing...")
- self.TLU_I2C = i2ccore
- self.pwraddr = DACaddr
- self.exp1addr= Exp1Add
- self.exp2addr= Exp2Add
- self.intRefOn= 0
- self.vCtrlMax= PMTmaxV
- self.verbose= True
-
- ## Identify the type of power board by trying to read the EEPROM (if fail, it is an old one):
- res= self.readEEPROM()
- if (len(res) != 0):
- self.bdType= 1
- else:
- self.bdType= 0
- print("\tPOWERMODULE type:", self.bdType)
- self.assignMapping()
-
-
- self.zeDAC_pwr=AD5665R(self.TLU_I2C, self.pwraddr)
- self.zeDAC_pwr.setIntRef(self.intRefOn, self.verbose)
- self.zeDAC_pwr.writeDAC(int(0), 7, self.verbose)
-
- self.ledExp1=PCA9539PW(self.TLU_I2C, self.exp1addr)
- self.ledExp1.setInvertReg(0, 0x00)# 0= normal, 1= inverted
- self.ledExp1.setIOReg(0, 0x00)# 0= output, 1= input
- self.ledExp1.setOutputs(0, 0xDA)# If output, set to XX
-
- self.ledExp1.setInvertReg(1, 0x00)# 0= normal, 1= inverted
- self.ledExp1.setIOReg(1, 0x00)# 0= output, 1= input
- self.ledExp1.setOutputs(1, 0xB6)# If output, set to XX
-
- self.ledExp2=PCA9539PW(self.TLU_I2C, self.exp2addr)
- self.ledExp2.setInvertReg(0, 0x00)# 0= normal, 1= inverted
- self.ledExp2.setIOReg(0, 0x00)# 0= output, 1= input
- self.ledExp2.setOutputs(0, 0x6D)# If output, set to XX
-
- self.ledExp2.setInvertReg(1, 0x00)# 0= normal, 1= inverted
- self.ledExp2.setIOReg(1, 0x00)# 0= output, 1= input
- self.ledExp2.setOutputs(1, 0xDB)# If output, set to XX
- print(" TLU POWERMODULE Ready")
- return
-
- def readEEPROM(self):
- ## Read content of EEPROM. New power modules host a 24AA025E48T, similar
- # to the one on the TLU but at address 0x50. Old modules will fail to ACKNOWLEDGE.
- eepromadd= 0x51
- bytes= 6
- startadd= 0xfa
- mystop= 1
- time.sleep(0.1)
- myaddr= [startadd]#0xfa
- self.TLU_I2C.write( eepromadd, [startadd], mystop)
- res= self.TLU_I2C.read( eepromadd, bytes)
- print(" POWERMODULE serial number (EEPROM):")
- result="\t"
- for iaddr in res:
- result+="%02x "%(iaddr)
- print(result)
- return res
-
- def assignMapping(self):
- ## Map indicator color based on their position on the expanders:
- # 0-15 are on expander 2
- # 16 to 31 on expander 1.
- # One indicator is missing the blue component, hence
- # the "-1" value.
- if (self.bdType==0):
- # Old board (with misplaced LED connection)
- self.indicatorXYZ= [(30, 29, 31), (27, 26, 28), (24, 23, 25), (21, 20, 22), (18, 17, 19), (15, 14, 16), (12, 11, 13), (9, 8, 10), (6, 5, 7), (3, 2, 4), (1, 0, -1)]
- else:
- # New board (with correct LED and EEPROM)
- self.indicatorXYZ= [(30, 29, 31), (27, 26, 28), (24, 23, 25), (21, 20, 22), (18, 17, -1), (15, 14, 16), (12, 11, 13), (9, 8, 10), (6, 5, 7), (3, 2, 4), (1, 0, 19)]
-
- def setVch(self, channel, voltage, verbose=False):
- # Note: the channel here is the DAC channel.
- # The mapping with the power module is not one-to-one
- if (verbose):
- print(" PWRModule: CONFIGURING VOLTAGE FOR PMT", channel+1)
- print("\tVcontrol=", voltage)
- if ((channel < 0) | (3 < channel )):
- print("\tPWRModule: channel should be comprised between 0 and 3")
- else:
- if (voltage < 0):
- print("\tPWRModule: voltage cannot be negative. Coherced to 0 V.")
- voltage = 0
- if (voltage > self.vCtrlMax):
- print("\tPWRModule: voltage cannot exceed vCtrlMax. Coherced to vCtrlMax.")
- print("\tPWRModule: vCtrlMax=", self.vCtrlMax, "V. See config file to change this value.")
- voltage = self.vCtrlMax
- dacValue= voltage*65535/self.vCtrlMax
- self.zeDAC_pwr.writeDAC(int(dacValue), channel, verbose)
- return
-
- def setIndicatorRGB(self, indicator, RGB=[0, 0, 0], verbose=False):
- # Indicator is one of the 11 LEDs on the front panels, labeled from 0 to 10
- # RGB allows to switch on (True) or off (False) the corresponding component for that Led
- # Note that one LED only has 2 components connected
- #print self.indicatorXYZ[indicator-1][2]
- if (1 <= indicator <= 11):
- nowStatus= []
- nowStatus.extend(self.ledExp1.getOutputs(0))
- nowStatus.extend(self.ledExp1.getOutputs(1))
- nowStatus.extend(self.ledExp2.getOutputs(0))
- nowStatus.extend(self.ledExp2.getOutputs(1))
- nowWrd= 0x00000000
- nowWrd= nowWrd | nowStatus[0]
- nowWrd= nowWrd | (nowStatus[1] << 8)
- nowWrd= nowWrd | (nowStatus[2] << 16)
- nowWrd= nowWrd | (nowStatus[3] << 24)
- nextWrd= nowWrd
- for iComp in range(0,3):
- indexComp= self.indicatorXYZ[indicator-1][iComp]
- valueComp= not bool(RGB[iComp])
- nextWrd= self._set_bit(nextWrd, indexComp, int(valueComp), False)
- if verbose:
- print("n=", iComp, "INDEX=", indexComp, "VALUE=", int(valueComp), "NEXTWORD=", bin(nextWrd))
- if verbose:
- print("NOW ", bin(nowWrd))
- print("NEXT ", bin(nextWrd))
- nextStatus= [0xFF & nextWrd, 0xFF & (nextWrd >> 8), 0xFF & (nextWrd >> 16), 0xFF & (nextWrd >> 24) ]
- #print " NOW", nowStatus
- #print " NEXT ", nextStatus
- if nowStatus[0] != nextStatus[0]:
- self.ledExp1.setOutputs(0, nextStatus[0])
- if nowStatus[1] != nextStatus[1]:
- self.ledExp1.setOutputs(1, nextStatus[1])
- if nowStatus[2] != nextStatus[2]:
- self.ledExp2.setOutputs(0, nextStatus[2])
- if nowStatus[3] != nextStatus[3]:
- self.ledExp2.setOutputs(1, nextStatus[3])
-
- return
-
-
- def _set_bit(self, v, index, x, verbose= False):
- """Set the index:th bit of v to 1 if x is truthy, else to 0, and return the new value."""
- if (index == -1):
- if (verbose):
- print(" SETBIT: Index= -1 will be ignored")
- else:
- mask = 1 << index # Compute mask, an integer with just bit 'index' set.
- v &= ~mask # Clear the bit indicated by the mask (if x is False)
- if x:
- v |= mask # If x was True, set the bit indicated by the mask.
- return v
-
- def allGreen(self):
- #self.setIndicatorRGB(1, [0, 1, 0])
- #self.setIndicatorRGB(2, [0, 1, 0])
- #self.setIndicatorRGB(3, [0, 1, 0])
- #self.setIndicatorRGB(4, [0, 1, 0])
- #self.setIndicatorRGB(5, [0, 1, 0])
- #self.setIndicatorRGB(6, [0, 1, 0])
- #self.setIndicatorRGB(7, [0, 1, 0])
- #self.setIndicatorRGB(8, [0, 1, 0])
- #self.setIndicatorRGB(9, [0, 1, 0])
- #self.setIndicatorRGB(10, [0, 1, 0])
- #self.setIndicatorRGB(11, [0, 1, 0])
- self.ledExp1.setOutputs(0, 218)
- self.ledExp1.setOutputs(1, 182)
- self.ledExp2.setOutputs(0, 109)
- self.ledExp2.setOutputs(1, 219)
-
- def allRed(self):
- self.ledExp1.setOutputs(0, 181)
- self.ledExp1.setOutputs(1, 109)
- self.ledExp2.setOutputs(0, 219)
- self.ledExp2.setOutputs(1, 182)
-
- def allBlue(self):
- self.ledExp1.setOutputs(0, 111)
- self.ledExp1.setOutputs(1, 219)
- self.ledExp2.setOutputs(0, 182)
- self.ledExp2.setOutputs(1, 109)
-
- def allBlack(self):
- self.ledExp1.setOutputs(0, 255)
- self.ledExp1.setOutputs(1, 255)
- self.ledExp2.setOutputs(0, 255)
- self.ledExp2.setOutputs(1, 255)
-
- def allWhite(self):
- self.ledExp1.setOutputs(0, 0)
- self.ledExp1.setOutputs(1, 0)
- self.ledExp2.setOutputs(0, 0)
- self.ledExp2.setOutputs(1, 0)
-
- def kitt(self):
- self.allBlack()
- print("\tWait while LEDs are tested...")
- self.setIndicatorRGB(1, [1, 0, 0])
- self.setIndicatorRGB(2, [0, 0, 0])
-
- self.setIndicatorRGB(1, [1, 0, 0])
- self.setIndicatorRGB(2, [1, 0, 0])
-
- self.setIndicatorRGB(1, [0, 0, 0])
- #self.setIndicatorRGB(2, [1, 0, 0])
- self.setIndicatorRGB(3, [1, 0, 0])
-
- self.setIndicatorRGB(2, [0, 0, 0])
- #self.setIndicatorRGB(3, [1, 0, 0])
- self.setIndicatorRGB(4, [1, 0, 0])
-
- self.setIndicatorRGB(3, [0, 0, 0])
- #self.setIndicatorRGB(4, [1, 0, 0])
- self.setIndicatorRGB(5, [1, 0, 0])
-
- #self.setIndicatorRGB(3, [0, 0, 0])
- self.setIndicatorRGB(4, [1, 0, 0])
- #self.setIndicatorRGB(5, [1, 0, 0])
- self.setIndicatorRGB(6, [1, 0, 0])
-
- self.setIndicatorRGB(4, [0, 0, 0])
- #self.setIndicatorRGB(5, [1, 0, 0])
- #self.setIndicatorRGB(6, [1, 0, 0])
- self.setIndicatorRGB(7, [1, 0, 0])
-
- self.setIndicatorRGB(5, [0, 0, 0])
- #self.setIndicatorRGB(6, [1, 0, 0])
- #self.setIndicatorRGB(7, [1, 0, 0])
- self.setIndicatorRGB(8, [1, 0, 0])
-
- self.setIndicatorRGB(6, [0, 0, 0])
- #self.setIndicatorRGB(7, [1, 0, 0])
- #self.setIndicatorRGB(8, [1, 0, 0])
- self.setIndicatorRGB(9, [1, 0, 0])
-
- self.setIndicatorRGB(7, [0, 0, 0])
- #self.setIndicatorRGB(8, [1, 0, 0])
- #self.setIndicatorRGB(9, [1, 0, 0])
- self.setIndicatorRGB(10, [1, 0, 0])
-
- self.setIndicatorRGB(8, [0, 0, 0])
- #self.setIndicatorRGB(9, [1, 0, 0])
- #self.setIndicatorRGB(10, [1, 0, 0])
- self.setIndicatorRGB(11, [1, 0, 0])
-
- self.setIndicatorRGB(9, [0, 0, 0])
- #self.setIndicatorRGB(10, [1, 0, 0])
- self.setIndicatorRGB(11, [1, 0, 0])
-
- #mid point
- #self.setIndicatorRGB(9, [0, 0, 0])
- self.setIndicatorRGB(10, [0, 0, 0])
- self.setIndicatorRGB(11, [1, 0, 0])
-
- #self.setIndicatorRGB(9, [0, 0, 0])
- self.setIndicatorRGB(10, [1, 0, 0])
- self.setIndicatorRGB(11, [1, 0, 0])
-
- self.setIndicatorRGB(9, [1, 0, 0])
- #self.setIndicatorRGB(10, [1, 0, 0])
- self.setIndicatorRGB(11, [1, 0, 0])
-
- self.setIndicatorRGB(8, [1, 0, 0])
- #self.setIndicatorRGB(9, [1, 0, 0])
- #self.setIndicatorRGB(10, [1, 0, 0])
- self.setIndicatorRGB(11, [0, 0, 0])
-
- self.setIndicatorRGB(7, [1, 0, 0])
- #self.setIndicatorRGB(8, [1, 0, 0])
- #self.setIndicatorRGB(9, [1, 0, 0])
- self.setIndicatorRGB(10, [0, 0, 0])
-
- self.setIndicatorRGB(6, [1, 0, 0])
- #self.setIndicatorRGB(7, [1, 0, 0])
- #self.setIndicatorRGB(8, [1, 0, 0])
- self.setIndicatorRGB(9, [0, 0, 0])
-
- self.setIndicatorRGB(5, [1, 0, 0])
- #self.setIndicatorRGB(6, [1, 0, 0])
- #self.setIndicatorRGB(7, [1, 0, 0])
- self.setIndicatorRGB(8, [0, 0, 0])
-
- self.setIndicatorRGB(4, [1, 0, 0])
- #self.setIndicatorRGB(5, [1, 0, 0])
- #self.setIndicatorRGB(6, [1, 0, 0])
- self.setIndicatorRGB(7, [0, 0, 0])
-
- self.setIndicatorRGB(4, [1, 0, 0])
- #self.setIndicatorRGB(5, [1, 0, 0])
- self.setIndicatorRGB(6, [0, 0, 0])
-
- self.setIndicatorRGB(3, [1, 0, 0])
- #self.setIndicatorRGB(4, [1, 0, 0])
- self.setIndicatorRGB(5, [0, 0, 0])
-
- self.setIndicatorRGB(2, [1, 0, 0])
- #self.setIndicatorRGB(3, [1, 0, 0])
- self.setIndicatorRGB(4, [0, 0, 0])
-
- self.setIndicatorRGB(1, [1, 0, 0])
- #self.setIndicatorRGB(2, [1, 0, 0])
- self.setIndicatorRGB(3, [0, 0, 0])
-
- self.setIndicatorRGB(1, [1, 0, 0])
- self.setIndicatorRGB(2, [0, 0, 0])
-
- self.setIndicatorRGB(1, [1, 0, 0])
- self.setIndicatorRGB(2, [0, 0, 0])
- print("\tLED test completed")
-
- def test(self):
- print(" Testing the powermodule")
- self.allBlack()
- # loop over red
- for iLED in range(0, 12):
- self.setIndicatorRGB(iLED, [1, 0, 0])
- self.setIndicatorRGB(iLED-1, [0, 0, 0])
- time.sleep(0.1)
- self.allBlack()
- # loop over green
- for iLED in range(0, 12):
- self.setIndicatorRGB(iLED, [0, 1, 0])
- self.setIndicatorRGB(iLED-1, [0, 0, 0])
- time.sleep(0.1)
- self.allBlack()
- # loop over blue (one will be missing)
- for iLED in range(0, 12):
- self.setIndicatorRGB(iLED, [0, 0, 1])
- self.setIndicatorRGB(iLED-1, [0, 0, 0])
- time.sleep(0.1)
- self.allBlack()
- print(" Powermodule test done")
- return
diff --git a/packages/TLUaddrmap_BKP.xml b/packages/TLUaddrmap_BKP.xml
deleted file mode 100644
index 65fb534..0000000
--- a/packages/TLUaddrmap_BKP.xml
+++ /dev/null
@@ -1,105 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/packages/TLUconnection_BKP.xml b/packages/TLUconnection_BKP.xml
deleted file mode 100644
index fca67f5..0000000
--- a/packages/TLUconnection_BKP.xml
+++ /dev/null
@@ -1,6 +0,0 @@
-
-
-
-
-
diff --git a/packages/si5345.py b/packages/si5345.py
deleted file mode 100644
index eedf85d..0000000
--- a/packages/si5345.py
+++ /dev/null
@@ -1,152 +0,0 @@
-import time
-import uhal
-from packages.I2CuHal import I2CCore
-import io
-import csv
-import sys
-
-class si5345:
- #Class to configure the Si5344 clock generator
-
- def __init__(self, i2c, slaveaddr=0x68):
- self.i2c = i2c
- self.slaveaddr = slaveaddr
- #self.configList=
-
- #def writeReg(self, address, data):
-
- def readRegister(self, myaddr, nwords, verbose= False):
- ### Read a specific register on the Si5344 chip. There is not check on the validity of the address but
- ### the code sets the correct page before reading.
-
- #First make sure we are on the correct page
- currentPg= self.getPage()
- requirePg= (myaddr & 0xFF00) >> 8
- if verbose:
- print("REG", hex(myaddr), "CURR PG" , hex(currentPg[0]), "REQ PG", hex(requirePg))
- if currentPg[0] != requirePg:
- self.setPage(requirePg)
- #Now read from register.
- addr=[]
- addr.append(myaddr)
- mystop=False
- self.i2c.write( self.slaveaddr, addr, mystop)
- # time.sleep(0.1)
- res= self.i2c.read( self.slaveaddr, nwords)
- return res
-
- def writeRegister(self, myaddr, data, verbose=False):
- ### Write a specific register on the Si5344 chip. There is not check on the validity of the address but
- ### the code sets the correct page before reading.
- ### myaddr is an int
- ### data is a list of ints
-
- #First make sure we are on the correct page
- myaddr= myaddr & 0xFFFF
- currentPg= self.getPage()
- requirePg= (myaddr & 0xFF00) >> 8
- #print "REG", hex(myaddr), "CURR PG" , currentPg, "REQ PG", hex(requirePg)
- if currentPg[0] != requirePg:
- self.setPage(requirePg)
- #Now write to register.
- data.insert(0, myaddr)
- if verbose:
- print(" Writing: ")
- result="\t "
- for iaddr in data:
- result+="%#02x "%(iaddr)
- print(result)
- self.i2c.write( self.slaveaddr, data)
- #time.sleep(0.01)
-
- def setPage(self, page, verbose=False):
- #Configure the chip to perform operations on the specified address page.
- mystop=True
- myaddr= [0x01, page]
- self.i2c.write( self.slaveaddr, myaddr, mystop)
- #time.sleep(0.01)
- if verbose:
- print(" Si5345 Set Reg Page:", page)
-
- def getPage(self, verbose=False):
- #Read the current address page
- mystop=False
- myaddr= [0x01]
- self.i2c.write( self.slaveaddr, myaddr, mystop)
- rPage= self.i2c.read( self.slaveaddr, 1)
- #time.sleep(0.1)
- if verbose:
- print("\tPage read:", rPage)
- return rPage
-
- def getDeviceVersion(self):
- #Read registers containing chip information
- mystop=False
- nwords=2
- myaddr= [0x02 ]#0xfa
- self.setPage(0)
- self.i2c.write( self.slaveaddr, myaddr, mystop)
- #time.sleep(0.1)
- res= self.i2c.read( self.slaveaddr, nwords)
- print(" Si5345 EEPROM: ")
- result="\t"
- for iaddr in reversed(res):
- result+="%#02x "%(iaddr)
- print(result)
- return res
-
- def parse_clk(self, filename, verbose= False):
- #Parse the configuration file produced by Clockbuilder Pro (Silicon Labs)
- deletedcomments=""""""
- if verbose:
- print("\tParsing file", filename)
- with open(filename, 'r') as configfile:
- for i, line in enumerate(configfile):
- if not line[0] == '#' :
- if not line[0:3] == 'Add':
- deletedcomments+=line
- csvfile = io.StringIO(deletedcomments)
- cvr= csv.reader(csvfile, delimiter=',', quotechar='|')
- #print "\tN elements parser:", sum(1 for row in cvr)
- #return [addr_list,data_list]
- # for item in cvr:
- # print "rere"
- # regAddr= int(item[0], 16)
- # regData[0]= int(item[1], 16)
- # print "\t ", hex(regAddr), hex(regData[0])
- #self.configList= cvr
- regSettingList= list(cvr)
- if verbose:
- print("\t ", len(regSettingList), "elements")
- return regSettingList
-
- def writeConfiguration(self, regSettingList, verbose= 0):
- print(" Si5345 Writing configuration:")
- toolbar_width = 38
- if (verbose==1):
- sys.stdout.write(" [%s]" % (" " * toolbar_width))
- sys.stdout.flush()
- sys.stdout.write("\b" * (toolbar_width+1)) # return to start of line, after '['
- #regSettingList= list(regSettingCsv)
- counter=0
- for item in regSettingList:
- regAddr= int(item[0], 16)
- regData=[0]
- regData[0]= int(item[1], 16)
- if (verbose > 1):
- print("\t", counter, "Reg:", hex(regAddr), "Data:", regData)
- counter += 1
- self.writeRegister(regAddr, regData, False)
- if (not(counter % 10) and (verbose==1)):
- sys.stdout.write("-")
- sys.stdout.flush()
- sys.stdout.write("\n")
- print("\tSi5345 configuration done")
-
- def checkDesignID(self):
- regAddr= 0x026B
- res= self.readRegister(regAddr, 8)
- result= " Si5345 design Id:\n\t"
- for iaddr in res:
- result+=chr(iaddr)
- print(result)
diff --git a/setup.py b/setup.py
index 6b5577c..b14fb3a 100644
--- a/setup.py
+++ b/setup.py
@@ -1,19 +1,30 @@
from setuptools import setup
from setuptools import find_packages
-author = 'Christian Bespin'
-author_email = 'bespin@physik.uni-bonn.de'
+author = "Christian Bespin, Rasmus Partzsch"
+author_email = "bespin@physik.uni-bonn.de, rasmus.partzsch@uni-bonn.de"
# Requirements
-install_requires = ['']
+install_requires = [
+ "pytest",
+ "numpy",
+ "tables",
+ "coloredlogs",
+ "pyzmq",
+ "online_monitor",
+ "tqdm",
+]
+
+with open("VERSION") as version_file:
+ version = version_file.read().strip()
setup(
- name='aidatlu',
- version='0.1.0',
- description='Control software for AIDA-2020 TLU',
- url='https://github.com/Silab-Bonn/aidatlu',
- license='',
- long_description='',
+ name="aidatlu",
+ version=version,
+ description="Control software for AIDA-2020 TLU",
+ url="https://github.com/Silab-Bonn/aidatlu",
+ license="License AGPL-3.0 license",
+ long_description="Repository for controlling the AIDA-2020 Trigger Logic Unit (TLU) with Python using uHAL bindings from IPbus.",
author=author,
maintainer=author,
author_email=author_email,
@@ -22,5 +33,5 @@
python_requires=">=3.8",
packages=find_packages(),
include_package_data=True,
- platforms='posix',
+ platforms="posix",
)