diff --git a/aidatlu/hardware/trigger_controller.py b/aidatlu/hardware/trigger_controller.py index ef4f73b..922efe3 100644 --- a/aidatlu/hardware/trigger_controller.py +++ b/aidatlu/hardware/trigger_controller.py @@ -2,6 +2,7 @@ from aidatlu.hardware.utils import _pack_bits from aidatlu import logger + class TriggerLogic(object): def __init__(self, i2c: I2CCore) -> None: self.log = logger.setup_derived_logger("Trigger Controller") diff --git a/aidatlu/main/config_parser.py b/aidatlu/main/config_parser.py index 82520a1..5a4cb7a 100644 --- a/aidatlu/main/config_parser.py +++ b/aidatlu/main/config_parser.py @@ -31,6 +31,55 @@ def configure(self) -> None: self.tlu.set_enable_record_data(1) self.log.success("TLU configured") + def get_configuration_table(self) -> list: + """Creates the configuration list to save in the data files + + Returns: + list: configuration list + """ + conf = [ + ( + "internal_trigger_rate", + self.conf["internal_trigger"]["internal_trigger_rate"], + ), + ("DUT_1", self.conf["dut_module"]["dut_1"]["mode"]), + ("DUT_2", self.conf["dut_module"]["dut_2"]["mode"]), + ("DUT_3", self.conf["dut_module"]["dut_3"]["mode"]), + ("DUT_4", self.conf["dut_module"]["dut_4"]["mode"]), + ("threshold_1", self.conf["trigger_inputs"]["threshold"]["threshold_1"]), + ("threshold_2", self.conf["trigger_inputs"]["threshold"]["threshold_2"]), + ("threshold_3", self.conf["trigger_inputs"]["threshold"]["threshold_3"]), + ("threshold_4", self.conf["trigger_inputs"]["threshold"]["threshold_4"]), + ("threshold_5", self.conf["trigger_inputs"]["threshold"]["threshold_3"]), + ("threshold_6", self.conf["trigger_inputs"]["threshold"]["threshold_4"]), + ( + "trigger_inputs_logic", + "%s" % (self.conf["trigger_inputs"]["trigger_inputs_logic"]), + ), + ( + "trigger_signal_shape_stretch", + "%s" + % str(self.conf["trigger_inputs"]["trigger_signal_shape"]["stretch"]), + ), + ( + "trigger_signal_shape_delay", + "%s" + % str(self.conf["trigger_inputs"]["trigger_signal_shape"]["delay"]), + ), + ( + "enable_clock_lemo_output", + self.conf["clock_lemo"]["enable_clock_lemo_output"], + ), + ("pmt_control_1", self.conf["pmt_control"]["pmt_1"]), + ("pmt_control_2", self.conf["pmt_control"]["pmt_2"]), + ("pmt_control_3", self.conf["pmt_control"]["pmt_3"]), + ("pmt_control_4", self.conf["pmt_control"]["pmt_4"]), + ("save_data", self.conf["save_data"]), + ("output_data_path", self.conf["output_data_path"]), + ("zmq_connection", self.conf["zmq_connection"]), + ] + return conf + def get_data_handling(self) -> tuple: """Information about data handling. diff --git a/aidatlu/main/data_parser.py b/aidatlu/main/data_parser.py index 35dad8a..5ffa803 100644 --- a/aidatlu/main/data_parser.py +++ b/aidatlu/main/data_parser.py @@ -65,7 +65,7 @@ def read_file(self, filepath: str) -> list: with tb.open_file(filepath, "r") as file: table = file.root.raw_data raw_data = np.array(table[:], dtype=data) - self.config = str(file.root.configuration).split(" ", 2)[2] + self.conf = np.array(file.root.conf[:]) return raw_data def _create_table(self, out_file, name, title, dtype): @@ -135,10 +135,22 @@ def write_data(self, filepath: str, data: np.array) -> None: data (table): raw data """ # filter_data = tb.Filters(complib='blosc', complevel=5) + config = np.dtype( + [ + ("attribute", "S32"), + ("value", "S32"), + ] + ) with tb.open_file(filepath, mode="w", title="TLU_interpreted") as h5_file: data_table = self._create_table( h5_file, name="interpreted_data", title="data", dtype=self.features ) # data_table = h5_file.create_table(h5_file.root, name='interpreted_data', description=features , title='data', filters=filter_data) data_table.append(data) - h5_file.create_group(h5_file.root, "configuration", self.config) + config_table = h5_file.create_table( + h5_file.root, + name="conf", + description=config, + ) + config_table.append(self.conf) + # h5_file.create_group(h5_file.root, "configuration", self.config) diff --git a/aidatlu/main/tlu.py b/aidatlu/main/tlu.py index 649d4c1..8416572 100644 --- a/aidatlu/main/tlu.py +++ b/aidatlu/main/tlu.py @@ -45,6 +45,7 @@ def __init__(self, hw, config_path, clock_config_path) -> None: def configure(self) -> None: """loads the conf.yaml and configures the TLU accordingly.""" self.config_parser.configure() + self.conf_list = self.config_parser.get_configuration_table() self.get_event_fifo_fill_level() self.get_event_fifo_csr() self.get_scalar() @@ -297,6 +298,14 @@ def init_raw_data_table(self) -> None: ("w5", "u4"), ] ) + + config = np.dtype( + [ + ("attribute", "S32"), + ("value", "S32"), + ] + ) + self.filter_data = tb.Filters(complib="blosc", complevel=5) self.h5_file = tb.open_file(self.raw_data_path, mode="w", title="TLU") self.data_table = self.h5_file.create_table( @@ -306,10 +315,17 @@ def init_raw_data_table(self) -> None: title="data", filters=self.filter_data, ) - self.h5_file.create_group( - self.h5_file.root, "configuration", self.config_parser.conf + # self.h5_file.create_group( + # self.h5_file.root, "configuration", self.config_parser.conf + # ) + config_table = self.h5_file.create_table( + self.h5_file.root, + name="conf", + description=config, + filters=self.filter_data, ) self.buffer = [] + config_table.append(self.conf_list) def log_sent_status(self, time: int) -> None: """Logs the status of the TLU run with trigger number, runtime usw. @@ -411,6 +427,8 @@ def run(self) -> None: self.path = self.config_parser.get_output_data_path() if self.path == None: self.path = "tlu_data/" + if __name__ == "__main__": + self.path = "../tlu_data/" self.raw_data_path = self.path + "tlu_raw_run%s_%s.h5" % ( self.run_number, datetime.now().strftime("%Y_%m_%d_%H_%M_%S"), diff --git a/aidatlu/test/hardware_test.py b/aidatlu/test/hardware_test.py index 90a5cf8..d71f087 100644 --- a/aidatlu/test/hardware_test.py +++ b/aidatlu/test/hardware_test.py @@ -1,4 +1,3 @@ - from aidatlu.main.tlu import AidaTLU from aidatlu.hardware.i2c import I2CCore from aidatlu.hardware.ioexpander_controller import IOControl @@ -11,7 +10,6 @@ import uhal import time import numpy as np -import uhal class Test_IOCControl: diff --git a/aidatlu/test/interpreted_data.h5 b/aidatlu/test/interpreted_data.h5 index 0a9dd38..1932c58 100644 Binary files a/aidatlu/test/interpreted_data.h5 and b/aidatlu/test/interpreted_data.h5 differ diff --git a/aidatlu/test/raw_data_test.h5 b/aidatlu/test/raw_data_test.h5 index 942141f..98a6195 100644 Binary files a/aidatlu/test/raw_data_test.h5 and b/aidatlu/test/raw_data_test.h5 differ diff --git a/aidatlu/test/software_test.py b/aidatlu/test/software_test.py index 2858c9b..21cf0ea 100644 --- a/aidatlu/test/software_test.py +++ b/aidatlu/test/software_test.py @@ -1,4 +1,3 @@ - import yaml import numpy as np import tables as tb diff --git a/aidatlu/test/test.py b/aidatlu/test/test.py index 65b2c2c..1a492cc 100644 --- a/aidatlu/test/test.py +++ b/aidatlu/test/test.py @@ -1,4 +1,3 @@ - from aidatlu.main.tlu import AidaTLU from aidatlu.hardware.i2c import I2CCore from aidatlu.hardware.utils import _set_bit