From 0502d09889e4055fcd1f322d57de4d20b373290a Mon Sep 17 00:00:00 2001 From: Anzooooo Date: Fri, 29 Nov 2024 13:17:46 +0800 Subject: [PATCH] feat(LoadPipe): let 128bitReq be accessed at 128-bit aligned granularity --- .../scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala b/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala index cbd4877b13..e1df398570 100644 --- a/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala +++ b/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala @@ -131,9 +131,10 @@ class LoadPipe(id: Int)(implicit p: Parameters) extends DCacheModule with HasPer io.tag_read.valid := io.lsu.req.fire && !io.nack val s0_valid = io.lsu.req.fire - val s0_req = io.lsu.req.bits + val s0_req = WireInit(io.lsu.req.bits) + s0_req.vaddr := Mux(io.load128Req, Cat(io.lsu.req.bits.vaddr(io.lsu.req.bits.vaddr.getWidth - 1, 4), 0.U(4.W)), io.lsu.req.bits.vaddr) val s0_fire = s0_valid && s1_ready - val s0_vaddr = s0_req.vaddr + val s0_vaddr = Mux(io.load128Req, Cat(s0_req.vaddr(s0_req.vaddr.getWidth - 1, 4), 0.U(4.W)), s0_req.vaddr) val s0_replayCarry = s0_req.replayCarry val s0_load128Req = io.load128Req val s0_bank_oh_64 = UIntToOH(addr_to_dcache_bank(s0_vaddr)) @@ -179,7 +180,8 @@ class LoadPipe(id: Int)(implicit p: Parameters) extends DCacheModule with HasPer val s1_load128Req = RegEnable(s0_load128Req, s0_fire) val s1_is_prefetch = s1_req.instrtype === DCACHE_PREFETCH_SOURCE.U // LSU may update the address from io.lsu.s1_paddr, which affects the bank read enable only. - val s1_vaddr = Cat(s1_req.vaddr(VAddrBits - 1, blockOffBits), io.lsu.s1_paddr_dup_lsu(blockOffBits - 1, 0)) + val s1_vaddr_update = Cat(s1_req.vaddr(VAddrBits - 1, blockOffBits), io.lsu.s1_paddr_dup_lsu(blockOffBits - 1, 0)) + val s1_vaddr = Mux(s1_load128Req, Cat(s1_vaddr_update(VAddrBits - 1, 4), 0.U(4.W)), s1_vaddr_update) val s1_bank_oh = RegEnable(s0_bank_oh, s0_fire) val s1_nack = RegNext(io.nack) val s1_fire = s1_valid && s2_ready