From ddf3803c458833227a1250d160c3a81607e01ec8 Mon Sep 17 00:00:00 2001 From: Anzooooo Date: Tue, 3 Dec 2024 13:02:38 +0800 Subject: [PATCH] fix(LSU): `rfwen` should not be set when `WakeUp` is cancelled or not need `WakeUp` --- src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala | 1 + src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala | 2 ++ 2 files changed, 3 insertions(+) diff --git a/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala b/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala index 3c9999c5b4..3371b8597a 100644 --- a/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala +++ b/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala @@ -548,6 +548,7 @@ class LoadMisalignBuffer(implicit p: Parameters) extends XSModule io.writeBack.bits.uop := req.uop io.writeBack.bits.uop.exceptionVec := DontCare LduCfg.exceptionOut.map(no => io.writeBack.bits.uop.exceptionVec(no) := (globalMMIO || globalException) && exceptionVec(no)) + io.writeBack.bits.uop.rfWen := !globalException && !globalMMIO && req.uop.rfWen io.writeBack.bits.uop.fuType := FuType.ldu.U io.writeBack.bits.uop.flushPipe := false.B io.writeBack.bits.uop.replayInst := false.B diff --git a/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala b/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala index ba14340e99..d71471c3f5 100644 --- a/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala +++ b/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala @@ -1729,6 +1729,8 @@ class LoadUnit(implicit p: Parameters) extends XSModule (s3_out.valid && !s3_vecout.isvec && !s3_mis_align && !s3_frm_mabuf)) io.ldout.bits.uop.exceptionVec := ExceptionNO.selectByFu(s3_ld_wb_meta.uop.exceptionVec, LduCfg) io.ldout.bits.isFromLoadUnit := true.B + // TODO vector? + io.ldout.bits.uop.rfWen := !io.ldCancel.ld2Cancel && s3_ld_wb_meta.uop.rfWen io.ldout.bits.uop.fuType := Mux( s3_valid && s3_isvec, FuType.vldu.U,