From d00cf7264ca53b33edf971eb6a0ff0aff18971ae Mon Sep 17 00:00:00 2001 From: klin02 Date: Sat, 14 Dec 2024 02:47:02 +0800 Subject: [PATCH] submodule(utility), transforms: collect XSLogs to SimTop.LogPerfEndpoint XSLog depends on LogPerfCtrl declared at Top Module. Previous we annotate such signal as dontTouch, and accessed through Hierarchical name like SimTop.xx by dummy LogPerfHelper. However, as XSLog is called in many spaces in DUT, which are not visible to each other, especailly some in WhenContext. XS will generate thousands of LogPerfHelper to get same LogPerfCtrl. Too many module instantiations greately slow down compilation speed, especailly in Palladium (more than 5 times slower than same DUT without Log). This change collect all XSLog to SimTop.LogPerfEndpoint, with LogPerfCtrl directly passed by IO. Some tips as follows: 1. Not call XSLog inside whenContext. To collect XSLogs, we should access Cond and Data from other module, but data in WhenContext is not accessible even through tap. Use XSLog(cond, pable) instead of when(cond) {XSLog(pable)}. We also add chisel Internal API currentWhen to check that. 2. Generate Hierarchical Module path through FIRRTL transforms. Sometimes we want to append module path for better debugging. XSCompatibility add a hacky way to use Chisel internal API to get tag of current Module. Then we will replace these tag with path during ChiselStage. Note path can only be acessed after circuit elaboration. 3. Register and invoke caller of XSPerf and related object. As XSPerf depends on LogPerfCtrl such as dump. We should deferred apply() until collect. So we regirster collect() method when firstly apply XSLog, then XSLog will automatically call XSPerf.collect() method during collection. Note deferred apply is called in another module, so original module tag should be recorded for path generation. 4. Concat XSLogs with same condition. Too many fwrites in same module will cause UPOPTTHREADS warning with 16-threads Verilator. Consider many XSLogs have same condition (especailly XSPerfs), we reuse same condition and concat their printables to reduce fwrites. Note we also limit size of concatation to 1000 to avoid segmentation fault caused by too long printf. --- src/main/scala/xiangshan/transforms/PrintModuleName.scala | 4 +++- src/test/scala/top/SimTop.scala | 7 ++----- utility | 2 +- 3 files changed, 6 insertions(+), 7 deletions(-) diff --git a/src/main/scala/xiangshan/transforms/PrintModuleName.scala b/src/main/scala/xiangshan/transforms/PrintModuleName.scala index ad31f786a6..37b12c9010 100644 --- a/src/main/scala/xiangshan/transforms/PrintModuleName.scala +++ b/src/main/scala/xiangshan/transforms/PrintModuleName.scala @@ -17,6 +17,8 @@ package xiangshan.transforms +import utility.XSLog + class PrintModuleName extends firrtl.options.Phase { override def invalidates(a: firrtl.options.Phase) = false @@ -33,7 +35,7 @@ class PrintModuleName extends firrtl.options.Phase { def onStmt(s: firrtl.ir.Statement): firrtl.ir.Statement = s match { case firrtl.ir.Print(info, firrtl.ir.StringLit(string), args, clk, en) => - firrtl.ir.Print(info, firrtl.ir.StringLit(string.replace(utility.XSLog.MagicStr, "%m")), args, clk, en) + firrtl.ir.Print(info, firrtl.ir.StringLit(XSLog.replaceFIRStr(string)), args, clk, en) case other: firrtl.ir.Statement => other.mapStmt(onStmt) } diff --git a/src/test/scala/top/SimTop.scala b/src/test/scala/top/SimTop.scala index 029a206944..e1631d7fd6 100644 --- a/src/test/scala/top/SimTop.scala +++ b/src/test/scala/top/SimTop.scala @@ -26,7 +26,7 @@ import difftest._ import freechips.rocketchip.amba.axi4.AXI4Bundle import freechips.rocketchip.diplomacy.{DisableMonitors, LazyModule} import freechips.rocketchip.util.HeterogeneousBag -import utility.{ChiselDB, Constantin, FileRegisters, GTimer} +import utility.{ChiselDB, Constantin, FileRegisters, GTimer, XSLog} import xiangshan.DebugOptionsKey import system.SoCParamsKey @@ -100,10 +100,7 @@ class SimTop(implicit p: Parameters) extends Module { val clean = if (hasPerf) WireDefault(difftest.perfCtrl.clean) else WireDefault(false.B) val dump = if (hasPerf) WireDefault(difftest.perfCtrl.dump) else WireDefault(false.B) - dontTouch(timer) - dontTouch(logEnable) - dontTouch(clean) - dontTouch(dump) + XSLog.collect(timer, logEnable, clean, dump) } object SimTop extends App { diff --git a/utility b/utility index 5a95832549..5e51b63ead 160000 --- a/utility +++ b/utility @@ -1 +1 @@ -Subproject commit 5a958325499d570f442278357b559286e851bcf5 +Subproject commit 5e51b63ead2c659059cc11d21073114ca4db3226