From c537b7250ac3a96db9ca773d1f2abf1fefdce97a Mon Sep 17 00:00:00 2001 From: Muzi Date: Wed, 27 Nov 2024 20:18:59 +0800 Subject: [PATCH] feat(frontend): add Pc class for frontend, in which the least significant bit is hardwired to zero to save area --- src/main/scala/xiangshan/frontend/Pc.scala | 59 ++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 src/main/scala/xiangshan/frontend/Pc.scala diff --git a/src/main/scala/xiangshan/frontend/Pc.scala b/src/main/scala/xiangshan/frontend/Pc.scala new file mode 100644 index 00000000000..dc89d02fdb6 --- /dev/null +++ b/src/main/scala/xiangshan/frontend/Pc.scala @@ -0,0 +1,59 @@ +/*************************************************************************************** + * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences + * Copyright (c) 2020-2021 Peng Cheng Laboratory + * + * XiangShan is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * + * See the Mulan PSL v2 for more details. + ***************************************************************************************/ + +package xiangshan.frontend + +import chisel3._ +import chisel3.util._ + +class Pc(width: Int) extends Bundle { + val pc: UInt = UInt((width - 1).W) + + def apply(): UInt = Cat(pc, 0.U(1.W)) + + def apply(x: Int): Bool = apply()(x) + + def apply(x: Int, y: Int): UInt = apply()(x, y) + + def :=(x: UInt): Unit = { + assert(width == x.getWidth) + pc := x(width - 1, 1) + } + + def +(offset: UInt): UInt = apply() + offset + + def ===(that: Pc): Bool = { + assert(width == that.width) + pc === that.pc + } + + def =/=(that: Pc): Bool = { // scalastyle:ignore method.name + assert(width == that.width) + pc =/= that.pc + } +} + +object Pc { + def apply(width: Int): Pc = new Pc(width) +} + +object PcInit { + def apply(fullPc: UInt): Pc = { + val pc = Wire(new Pc(fullPc.getWidth)) + pc := fullPc + pc + } +}