diff --git a/src/main/scala/top/Top.scala b/src/main/scala/top/Top.scala index 363382c73e..56d025db8c 100644 --- a/src/main/scala/top/Top.scala +++ b/src/main/scala/top/Top.scala @@ -311,8 +311,17 @@ class XSTop()(implicit p: Parameters) extends BaseXSSoc() with HasSoCParameter core.module.io.clintTime := misc.module.clintTime io.riscv_halt(i) := core.module.io.cpu_halt io.riscv_critical_error(i) := core.module.io.cpu_crtical_error - io.traceCoreInterface(i).toEncoder := core.module.io.traceCoreInterface.toEncoder - core.module.io.traceCoreInterface.fromEncoder := io.traceCoreInterface(i).fromEncoder + // trace Interface + val traceInterface = core.module.io.traceCoreInterface + traceInterface.fromEncoder := io.traceCoreInterface(i).fromEncoder + io.traceCoreInterface(i).toEncoder.priv := traceInterface.toEncoder.priv + io.traceCoreInterface(i).toEncoder.cause := traceInterface.toEncoder.trap.cause + io.traceCoreInterface(i).toEncoder.tval := traceInterface.toEncoder.trap.tval + io.traceCoreInterface(i).toEncoder.iaddr := VecInit(traceInterface.toEncoder.groups.map(_.bits.iaddr)).asUInt + io.traceCoreInterface(i).toEncoder.itype := VecInit(traceInterface.toEncoder.groups.map(_.bits.itype)).asUInt + io.traceCoreInterface(i).toEncoder.iretire := VecInit(traceInterface.toEncoder.groups.map(_.bits.iretire)).asUInt + io.traceCoreInterface(i).toEncoder.ilastsize := VecInit(traceInterface.toEncoder.groups.map(_.bits.ilastsize)).asUInt + core.module.io.reset_vector := io.riscv_rst_vec(i) } diff --git a/src/main/scala/top/XSNoCTop.scala b/src/main/scala/top/XSNoCTop.scala index 6e4a0205ed..34189ced58 100644 --- a/src/main/scala/top/XSNoCTop.scala +++ b/src/main/scala/top/XSNoCTop.scala @@ -165,8 +165,16 @@ class XSNoCTop()(implicit p: Parameters) extends BaseXSSoc with HasSoCParameter io.riscv_critical_error := core_with_l2.module.io.cpu_crtical_error io.hartIsInReset := core_with_l2.module.io.hartIsInReset core_with_l2.module.io.reset_vector := io.riscv_rst_vec - io.traceCoreInterface.toEncoder := core_with_l2.module.io.traceCoreInterface.toEncoder - core_with_l2.module.io.traceCoreInterface.fromEncoder := io.traceCoreInterface.fromEncoder + // trace Interface + val traceInterface = core_with_l2.module.io.traceCoreInterface + traceInterface.fromEncoder := io.traceCoreInterface.fromEncoder + io.traceCoreInterface.toEncoder.priv := traceInterface.toEncoder.priv + io.traceCoreInterface.toEncoder.cause := traceInterface.toEncoder.trap.cause + io.traceCoreInterface.toEncoder.tval := traceInterface.toEncoder.trap.tval + io.traceCoreInterface.toEncoder.iaddr := VecInit(traceInterface.toEncoder.groups.map(_.bits.iaddr)).asUInt + io.traceCoreInterface.toEncoder.itype := VecInit(traceInterface.toEncoder.groups.map(_.bits.itype)).asUInt + io.traceCoreInterface.toEncoder.iretire := VecInit(traceInterface.toEncoder.groups.map(_.bits.iretire)).asUInt + io.traceCoreInterface.toEncoder.ilastsize := VecInit(traceInterface.toEncoder.groups.map(_.bits.ilastsize)).asUInt EnableClintAsyncBridge match { case Some(param) => diff --git a/src/main/scala/xiangshan/L2Top.scala b/src/main/scala/xiangshan/L2Top.scala index 3d2e97d375..b42821f641 100644 --- a/src/main/scala/xiangshan/L2Top.scala +++ b/src/main/scala/xiangshan/L2Top.scala @@ -33,7 +33,7 @@ import top.BusPerfMonitor import utility._ import xiangshan.cache.mmu.TlbRequestIO import xiangshan.backend.fu.PMPRespBundle -import xiangshan.backend.trace.TraceCoreInterface +import xiangshan.backend.trace.{Itype, TraceCoreInterface} class L1BusErrorUnitInfo(implicit val p: Parameters) extends Bundle with HasSoCParameter { val ecc_error = Valid(UInt(soc.PAddrBits.W)) @@ -189,7 +189,32 @@ class L2TopInlined()(implicit p: Parameters) extends LazyModule io.hartId.toCore := io.hartId.fromTile io.cpu_halt.toTile := io.cpu_halt.fromCore io.cpu_critical_error.toTile := io.cpu_critical_error.fromCore - io.traceCoreInterface.toTile <> io.traceCoreInterface.fromCore + // trace interface + val traceToTile = io.traceCoreInterface.toTile + val traceFromCore = io.traceCoreInterface.fromCore + traceFromCore.fromEncoder := RegNext(traceToTile.fromEncoder) + traceToTile.toEncoder.trap := RegEnable( + traceFromCore.toEncoder.trap, + traceFromCore.toEncoder.groups(0).valid && Itype.isTrap(traceFromCore.toEncoder.groups(0).bits.itype) + ) + traceToTile.toEncoder.priv := RegEnable( + traceFromCore.toEncoder.priv, + traceFromCore.toEncoder.groups(0).valid + ) + (0 until TraceGroupNum).foreach{ i => + traceToTile.toEncoder.groups(i).valid := RegNext(traceFromCore.toEncoder.groups(i).valid) + traceToTile.toEncoder.groups(i).bits.iretire := RegNext(traceFromCore.toEncoder.groups(i).bits.iretire) + traceToTile.toEncoder.groups(i).bits.itype := RegNext(traceFromCore.toEncoder.groups(i).bits.itype) + traceToTile.toEncoder.groups(i).bits.ilastsize := RegEnable( + traceFromCore.toEncoder.groups(i).bits.ilastsize, + traceFromCore.toEncoder.groups(i).valid + ) + traceToTile.toEncoder.groups(i).bits.iaddr := RegEnable( + traceFromCore.toEncoder.groups(i).bits.iaddr, + traceFromCore.toEncoder.groups(i).valid + ) + } + dontTouch(io.hartId) dontTouch(io.cpu_halt) dontTouch(io.cpu_critical_error) diff --git a/src/main/scala/xiangshan/XSCore.scala b/src/main/scala/xiangshan/XSCore.scala index 1e2ab9e067..11196085d0 100644 --- a/src/main/scala/xiangshan/XSCore.scala +++ b/src/main/scala/xiangshan/XSCore.scala @@ -242,7 +242,6 @@ class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer) io.cpu_halt := memBlock.io.outer_cpu_halt io.cpu_critical_error := memBlock.io.outer_cpu_critical_error - io.traceCoreInterface <> backend.io.traceCoreInterface io.beu_errors.icache <> memBlock.io.outer_beu_errors_icache io.beu_errors.dcache <> memBlock.io.error.bits.toL1BusErrorUnitInfo(memBlock.io.error.valid) io.beu_errors.l2 <> DontCare diff --git a/src/main/scala/xiangshan/backend/CtrlBlock.scala b/src/main/scala/xiangshan/backend/CtrlBlock.scala index 71ce25f59f..91af136cd3 100644 --- a/src/main/scala/xiangshan/backend/CtrlBlock.scala +++ b/src/main/scala/xiangshan/backend/CtrlBlock.scala @@ -262,14 +262,16 @@ class CtrlBlockImp( io.fromCSR.traceCSR.lastPriv, io.fromCSR.traceCSR.currentPriv ) - io.traceCoreInterface.toEncoder.cause := io.fromCSR.traceCSR.cause.asUInt - io.traceCoreInterface.toEncoder.tval := io.fromCSR.traceCSR.tval.asUInt - io.traceCoreInterface.toEncoder.priv := tracePriv - io.traceCoreInterface.toEncoder.iaddr := VecInit(trace.io.out.toEncoder.blocks.map(_.bits.iaddr.get)).asUInt - io.traceCoreInterface.toEncoder.itype := VecInit(trace.io.out.toEncoder.blocks.map(_.bits.tracePipe.itype)).asUInt - io.traceCoreInterface.toEncoder.iretire := VecInit(trace.io.out.toEncoder.blocks.map(_.bits.tracePipe.iretire)).asUInt - io.traceCoreInterface.toEncoder.ilastsize := VecInit(trace.io.out.toEncoder.blocks.map(_.bits.tracePipe.ilastsize)).asUInt - + io.traceCoreInterface.toEncoder.trap.cause := io.fromCSR.traceCSR.cause.asUInt + io.traceCoreInterface.toEncoder.trap.tval := io.fromCSR.traceCSR.tval.asUInt + io.traceCoreInterface.toEncoder.priv := tracePriv + (0 until TraceGroupNum).foreach(i => { + io.traceCoreInterface.toEncoder.groups(i).valid := trace.io.out.toEncoder.blocks(i).valid + io.traceCoreInterface.toEncoder.groups(i).bits.iaddr := trace.io.out.toEncoder.blocks(i).bits.iaddr.getOrElse(0.U) + io.traceCoreInterface.toEncoder.groups(i).bits.itype := trace.io.out.toEncoder.blocks(i).bits.tracePipe.itype + io.traceCoreInterface.toEncoder.groups(i).bits.iretire := trace.io.out.toEncoder.blocks(i).bits.tracePipe.iretire + io.traceCoreInterface.toEncoder.groups(i).bits.ilastsize := trace.io.out.toEncoder.blocks(i).bits.tracePipe.ilastsize + }) /** * trace end */ diff --git a/src/main/scala/xiangshan/backend/MemBlock.scala b/src/main/scala/xiangshan/backend/MemBlock.scala index a40b292d90..86b109fcd4 100644 --- a/src/main/scala/xiangshan/backend/MemBlock.scala +++ b/src/main/scala/xiangshan/backend/MemBlock.scala @@ -46,7 +46,7 @@ import xiangshan.backend.datapath.NewPipelineConnect import system.SoCParamsKey import xiangshan.backend.fu.NewCSR.TriggerUtil import xiangshan.ExceptionNO._ -import xiangshan.backend.trace.TraceCoreInterface +import xiangshan.backend.trace.{Itype, TraceCoreInterface} trait HasMemBlockParameters extends HasXSParameter { // number of memory units @@ -1886,7 +1886,32 @@ class MemBlockInlinedImp(outer: MemBlockInlined) extends LazyModuleImp(outer) io.reset_backend := DontCare } io.resetInFrontendBypass.toL2Top := io.resetInFrontendBypass.fromFrontend - io.traceCoreInterfaceBypass.toL2Top <> io.traceCoreInterfaceBypass.fromBackend + // trace interface + val traceToL2Top = io.traceCoreInterfaceBypass.toL2Top + val traceFromBackend = io.traceCoreInterfaceBypass.fromBackend + traceFromBackend.fromEncoder := RegNext(traceToL2Top.fromEncoder) + traceToL2Top.toEncoder.trap := RegEnable( + traceFromBackend.toEncoder.trap, + traceFromBackend.toEncoder.groups(0).valid && Itype.isTrap(traceFromBackend.toEncoder.groups(0).bits.itype) + ) + traceToL2Top.toEncoder.priv := RegEnable( + traceFromBackend.toEncoder.priv, + traceFromBackend.toEncoder.groups(0).valid + ) + (0 until TraceGroupNum).foreach{ i => + traceToL2Top.toEncoder.groups(i).valid := RegNext(traceFromBackend.toEncoder.groups(i).valid) + traceToL2Top.toEncoder.groups(i).bits.iretire := RegNext(traceFromBackend.toEncoder.groups(i).bits.iretire) + traceToL2Top.toEncoder.groups(i).bits.itype := RegNext(traceFromBackend.toEncoder.groups(i).bits.itype) + traceToL2Top.toEncoder.groups(i).bits.ilastsize := RegEnable( + traceFromBackend.toEncoder.groups(i).bits.ilastsize, + traceFromBackend.toEncoder.groups(i).valid + ) + traceToL2Top.toEncoder.groups(i).bits.iaddr := RegEnable( + traceFromBackend.toEncoder.groups(i).bits.iaddr, + traceFromBackend.toEncoder.groups(i).valid + ) + } + io.mem_to_ooo.storeDebugInfo := DontCare // store event difftest information diff --git a/src/main/scala/xiangshan/backend/trace/Interface.scala b/src/main/scala/xiangshan/backend/trace/Interface.scala index 66336a7850..e80066ee34 100644 --- a/src/main/scala/xiangshan/backend/trace/Interface.scala +++ b/src/main/scala/xiangshan/backend/trace/Interface.scala @@ -41,14 +41,18 @@ class TraceCoreInterface(implicit val p: Parameters) extends Bundle with HasXSPa val enable = Bool() val stall = Bool() }) - val toEncoder = Output(new Bundle { - val cause = UInt(CauseWidth.W) - val tval = UInt(TvalWidth.W) - val priv = UInt(PrivWidth.W) - val iaddr = UInt((TraceGroupNum * IaddrWidth).W) - val itype = UInt((TraceGroupNum * ItypeWidth).W) - val iretire = UInt((TraceGroupNum * IretireWidthCompressed).W) - val ilastsize = UInt((TraceGroupNum * IlastsizeWidth).W) + val toEncoder = Output(new Bundle { + val priv = Priv() + val trap = new Bundle{ + val cause = UInt(CauseWidth.W) + val tval = UInt(TvalWidth.W) + } + val groups = Vec(TraceGroupNum, ValidIO(new Bundle{ + val iaddr = UInt(IaddrWidth.W) + val itype = UInt(ItypeWidth.W) + val iretire = UInt(IretireWidthCompressed.W) + val ilastsize = UInt(IlastsizeWidth.W) + })) }) } diff --git a/src/main/scala/xiangshan/backend/trace/Trace.scala b/src/main/scala/xiangshan/backend/trace/Trace.scala index 6940263289..49a6f0086b 100644 --- a/src/main/scala/xiangshan/backend/trace/Trace.scala +++ b/src/main/scala/xiangshan/backend/trace/Trace.scala @@ -71,4 +71,4 @@ class Trace(implicit val p: Parameters) extends Module with HasXSParameter { if(backendParams.debugEn) { dontTouch(io.out.toEncoder) } -} \ No newline at end of file +} diff --git a/src/main/scala/xiangshan/backend/trace/TraceBuffer.scala b/src/main/scala/xiangshan/backend/trace/TraceBuffer.scala index 91137129f4..e7e7337ae2 100644 --- a/src/main/scala/xiangshan/backend/trace/TraceBuffer.scala +++ b/src/main/scala/xiangshan/backend/trace/TraceBuffer.scala @@ -108,4 +108,4 @@ object TracePtr { ptr.value := v ptr } -} \ No newline at end of file +}