diff --git a/difftest b/difftest index 89c67e1d9d..8aa927533d 160000 --- a/difftest +++ b/difftest @@ -1 +1 @@ -Subproject commit 89c67e1d9d9f3bc442ec5de529d7ab69b18ba4d7 +Subproject commit 8aa927533dd9724e6479416ebb80439f4c4afa65 diff --git a/huancun b/huancun index 1ce17a778c..ac74ebc3ec 160000 --- a/huancun +++ b/huancun @@ -1 +1 @@ -Subproject commit 1ce17a778c3a8b5205a56e88fbae3dcbe88cc12e +Subproject commit ac74ebc3ec6c7c9c146d8c850d4e5599336be52e diff --git a/src/main/scala/xiangshan/backend/Scheduler.scala b/src/main/scala/xiangshan/backend/Scheduler.scala index afd98bb97c..28cfbc32f2 100644 --- a/src/main/scala/xiangshan/backend/Scheduler.scala +++ b/src/main/scala/xiangshan/backend/Scheduler.scala @@ -529,13 +529,11 @@ class SchedulerImp(outer: Scheduler) extends LazyModuleImp(outer) with HasXSPara if ((env.AlwaysBasicDiff || env.EnableDifftest) && intRfConfig._1) { val difftest = DifftestModule(new DiffArchIntRegState, delay = 2) - difftest.clock := clock difftest.coreid := io.hartId difftest.value := VecInit(intRfReadData.takeRight(32)) } if ((env.AlwaysBasicDiff || env.EnableDifftest) && fpRfConfig._1) { val difftest = DifftestModule(new DiffArchFpRegState, delay = 2) - difftest.clock := clock difftest.coreid := io.hartId difftest.value := VecInit(fpRfReadData.takeRight(32)) } diff --git a/src/main/scala/xiangshan/backend/exu/WbArbiter.scala b/src/main/scala/xiangshan/backend/exu/WbArbiter.scala index 3bd097b01d..e9ca61ec8d 100644 --- a/src/main/scala/xiangshan/backend/exu/WbArbiter.scala +++ b/src/main/scala/xiangshan/backend/exu/WbArbiter.scala @@ -307,7 +307,6 @@ class WbArbiterWrapper( if (env.EnableDifftest || env.AlwaysBasicDiff) { intArbiter.module.io.out.foreach(out => { val difftest = DifftestModule(new DiffIntWriteback(NRPhyRegs)) - difftest.clock := clock difftest.coreid := io.hartId difftest.valid := out.valid && out.bits.uop.ctrl.rfWen difftest.address := out.bits.uop.pdest @@ -328,7 +327,6 @@ class WbArbiterWrapper( if (env.EnableDifftest || env.AlwaysBasicDiff) { fpArbiter.module.io.out.foreach(out => { val difftest = DifftestModule(new DiffFpWriteback(NRPhyRegs)) - difftest.clock := clock difftest.coreid := io.hartId difftest.valid := out.valid // all fp instr will write fp rf difftest.address := out.bits.uop.pdest diff --git a/src/main/scala/xiangshan/backend/fu/CSR.scala b/src/main/scala/xiangshan/backend/fu/CSR.scala index f7db2ce86f..963a596a01 100644 --- a/src/main/scala/xiangshan/backend/fu/CSR.scala +++ b/src/main/scala/xiangshan/backend/fu/CSR.scala @@ -1208,7 +1208,6 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMP // Always instantiate basic difftest modules. if (env.AlwaysBasicDiff || env.EnableDifftest) { val difftest = DifftestModule(new DiffArchEvent, delay = 3, dontCare = true) - difftest.clock := clock difftest.coreid := csrio.hartId difftest.valid := csrio.exception.valid difftest.interrupt := Mux(raiseIntr, causeNO, 0.U) @@ -1222,7 +1221,6 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMP // Always instantiate basic difftest modules. if (env.AlwaysBasicDiff || env.EnableDifftest) { val difftest = DifftestModule(new DiffCSRState) - difftest.clock := clock difftest.coreid := csrio.hartId difftest.priviledgeMode := priviledgeMode difftest.mstatus := mstatus @@ -1246,7 +1244,6 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMP if(env.AlwaysBasicDiff || env.EnableDifftest) { val difftest = DifftestModule(new DiffDebugMode) - difftest.clock := clock difftest.coreid := csrio.hartId difftest.debugMode := debugMode difftest.dcsr := dcsr diff --git a/src/main/scala/xiangshan/backend/rob/Rob.scala b/src/main/scala/xiangshan/backend/rob/Rob.scala index 60d87aaff1..7c67857b14 100644 --- a/src/main/scala/xiangshan/backend/rob/Rob.scala +++ b/src/main/scala/xiangshan/backend/rob/Rob.scala @@ -1280,7 +1280,6 @@ class RobImp(outer: Rob)(implicit p: Parameters) extends LazyModuleImp(outer) val isRVC = dt_isRVC(ptr) val difftest = DifftestModule(new DiffInstrCommit(NRPhyRegs), delay = 3, dontCare = true) - difftest.clock := clock difftest.coreid := io.hartId difftest.index := i.U difftest.valid := io.commits.commitValid(i) && io.commits.isCommit @@ -1308,7 +1307,6 @@ class RobImp(outer: Rob)(implicit p: Parameters) extends LazyModuleImp(outer) if (env.EnableDifftest) { for (i <- 0 until CommitWidth) { val difftest = DifftestModule(new DiffLoadEvent, delay = 3) - difftest.clock := clock difftest.coreid := io.hartId difftest.index := i.U @@ -1334,7 +1332,6 @@ class RobImp(outer: Rob)(implicit p: Parameters) extends LazyModuleImp(outer) } val hitTrap = trapVec.reduce(_||_) val difftest = DifftestModule(new DiffTrapEvent, dontCare = true) - difftest.clock := clock difftest.coreid := io.hartId difftest.hasTrap := hitTrap difftest.cycleCnt := timer diff --git a/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala b/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala index b11cec7920..d974318e16 100644 --- a/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala +++ b/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala @@ -1053,8 +1053,7 @@ class MissQueue(edge: TLEdgeOut)(implicit p: Parameters) extends DCacheModule wi // Difftest if (env.EnableDifftest) { - val difftest = DifftestModule(new DiffRefillEvent) - difftest.clock := clock + val difftest = DifftestModule(new DiffRefillEvent, dontCare = true) difftest.coreid := io.hartId difftest.index := 1.U difftest.valid := io.refill_to_ldq.valid && io.refill_to_ldq.bits.hasdata && io.refill_to_ldq.bits.refill_done diff --git a/src/main/scala/xiangshan/cache/mmu/L2TLB.scala b/src/main/scala/xiangshan/cache/mmu/L2TLB.scala index 7aedab6868..647baff1ff 100644 --- a/src/main/scala/xiangshan/cache/mmu/L2TLB.scala +++ b/src/main/scala/xiangshan/cache/mmu/L2TLB.scala @@ -310,8 +310,7 @@ class L2TLBImp(outer: L2TLB)(implicit p: Parameters) extends PtwModule(outer) wi difftest_ptw_addr(mem.a.bits.source) := mem.a.bits.address } - val difftest = DifftestModule(new DiffRefillEvent) - difftest.clock := clock + val difftest = DifftestModule(new DiffRefillEvent, dontCare = true) difftest.coreid := p(XSCoreParamsKey).HartId.asUInt difftest.index := 2.U difftest.valid := cache.io.refill.valid @@ -322,7 +321,6 @@ class L2TLBImp(outer: L2TLB)(implicit p: Parameters) extends PtwModule(outer) wi if (env.EnableDifftest) { for (i <- 0 until PtwWidth) { val difftest = DifftestModule(new DiffL2TLBEvent) - difftest.clock := clock difftest.coreid := p(XSCoreParamsKey).HartId.asUInt difftest.valid := io.tlb(i).resp.fire && !io.tlb(i).resp.bits.af difftest.index := i.U diff --git a/src/main/scala/xiangshan/cache/mmu/TLB.scala b/src/main/scala/xiangshan/cache/mmu/TLB.scala index 1899558fad..c56ea80997 100644 --- a/src/main/scala/xiangshan/cache/mmu/TLB.scala +++ b/src/main/scala/xiangshan/cache/mmu/TLB.scala @@ -314,7 +314,6 @@ class TLB(Width: Int, nRespDups: Int = 1, Block: Seq[Boolean], q: TLBParameters) val pf = io.requestor(i).resp.bits.excp(0).pf.instr || io.requestor(i).resp.bits.excp(0).pf.st || io.requestor(i).resp.bits.excp(0).pf.ld val af = io.requestor(i).resp.bits.excp(0).af.instr || io.requestor(i).resp.bits.excp(0).af.st || io.requestor(i).resp.bits.excp(0).af.ld val difftest = DifftestModule(new DiffL1TLBEvent) - difftest.clock := clock difftest.coreid := p(XSCoreParamsKey).HartId.asUInt difftest.valid := RegNext(io.requestor(i).req.fire) && !RegNext(io.requestor(i).req_kill) && io.requestor(i).resp.fire && !io.requestor(i).resp.bits.miss && !pf && !af && portTranslateEnable(i) if (!Seq("itlb", "ldtlb", "sttlb").contains(q.name)) { diff --git a/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala b/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala index bad6cc0fa1..fe9206506d 100644 --- a/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala +++ b/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala @@ -359,8 +359,7 @@ class ICacheMainPipe(implicit p: Parameters) extends ICacheModule if (env.EnableDifftest) { (0 until PortNumber).foreach { i => - val diffPIQ = DifftestModule(new DiffRefillEvent) - diffPIQ.clock := clock + val diffPIQ = DifftestModule(new DiffRefillEvent, dontCare = true) diffPIQ.coreid := io.hartId diffPIQ.index := (i + 7).U if (i == 0) diffPIQ.valid := s1_fire && !s1_port_hit(i) && !s1_ipf_hit_latch(i) && s1_piq_hit_latch(i) && !tlbExcp(0) @@ -818,8 +817,7 @@ class ICacheMainPipe(implicit p: Parameters) extends ICacheModule discard } (0 until PortNumber).map { i => - val diffMainPipeOut = DifftestModule(new DiffRefillEvent) - diffMainPipeOut.clock := clock + val diffMainPipeOut = DifftestModule(new DiffRefillEvent, dontCare = true) diffMainPipeOut.coreid := io.hartId diffMainPipeOut.index := (4 + i).U if (i == 0) diffMainPipeOut.valid := s2_fire && !discards(0) diff --git a/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala b/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala index 8a6139094c..025359014b 100644 --- a/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala +++ b/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala @@ -278,8 +278,7 @@ class ICacheMissUnit(edge: TLEdgeOut)(implicit p: Parameters) extends ICacheMiss io.data_write <> refill_arb.io.out if (env.EnableDifftest) { - val difftest = DifftestModule(new DiffRefillEvent) - difftest.clock := clock + val difftest = DifftestModule(new DiffRefillEvent, dontCare = true) difftest.coreid := io.hartId difftest.index := 0.U difftest.valid := refill_arb.io.out.valid diff --git a/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala b/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala index 80ed717ee7..9332c6f8c3 100644 --- a/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala +++ b/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala @@ -247,8 +247,7 @@ class PrefetchBuffer(implicit p: Parameters) extends IPrefetchModule XSPerfAccumulate("fdip_fencei_cycle", io.fencei) if (env.EnableDifftest) { - val difftest = DifftestModule(new DiffRefillEvent) - difftest.clock := clock + val difftest = DifftestModule(new DiffRefillEvent, dontCare = true) difftest.coreid := io.hartId difftest.index := 6.U difftest.valid := toICacheData.fire @@ -846,8 +845,7 @@ class PrefetchQueue(edge: TLEdgeOut)(implicit p: Parameters) extends IPrefetchMo } if (env.EnableDifftest) { - val diffipfrefill = DifftestModule(new DiffRefillEvent) - diffipfrefill.clock := clock + val diffipfrefill = DifftestModule(new DiffRefillEvent, dontCare = true) diffipfrefill.coreid := io.hartId diffipfrefill.index := 3.U diffipfrefill.valid := handleEntry.valid && handleEntry.finish diff --git a/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala b/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala index 886f67a1a2..b8da8bf98b 100644 --- a/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala +++ b/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala @@ -767,7 +767,6 @@ class StoreQueue(implicit p: Parameters) extends XSModule val wdata = sbufferData & MaskExpand(sbufferMask) val difftest = DifftestModule(new DiffStoreEvent, delay = 2) - difftest.clock := clock difftest.coreid := io.hartId difftest.index := i.U difftest.valid := storeCommit diff --git a/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala b/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala index 68c58988fb..6d7a0cadd8 100644 --- a/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala +++ b/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala @@ -435,7 +435,6 @@ class AtomicsUnit(implicit p: Parameters) extends XSModule with MemoryOpConstant if (env.EnableDifftest) { val difftest = DifftestModule(new DiffAtomicEvent) - difftest.clock := clock difftest.coreid := io.hartId difftest.valid := state === s_cache_resp_latch difftest.addr := paddr_reg @@ -448,7 +447,6 @@ class AtomicsUnit(implicit p: Parameters) extends XSModule with MemoryOpConstant if (env.EnableDifftest || env.AlwaysBasicDiff) { val uop = io.out.bits.uop val difftest = DifftestModule(new DiffLrScEvent) - difftest.clock := clock difftest.coreid := io.hartId difftest.valid := io.out.fire && (uop.ctrl.fuOpType === LSUOpType.sc_d || uop.ctrl.fuOpType === LSUOpType.sc_w) diff --git a/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala b/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala index 05ce562bf8..e4bdbdaa40 100644 --- a/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala +++ b/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala @@ -746,7 +746,6 @@ class Sbuffer(implicit p: Parameters) extends DCacheModule with HasSbufferConst io.dcache.hit_resps.zipWithIndex.map{case (resp, index) => { val difftest = DifftestModule(new DiffSbufferEvent, delay = 1) val dcache_resp_id = resp.bits.id - difftest.clock := clock difftest.coreid := io.hartId difftest.index := index.U difftest.valid := resp.fire() diff --git a/utility b/utility index c2a0383650..241035e7e5 160000 --- a/utility +++ b/utility @@ -1 +1 @@ -Subproject commit c2a03836503e6b62e48ab4bedbf6a29b21c634f9 +Subproject commit 241035e7e5e5d517b6b5de8415b80a2a46b509ad