From 9c13e9625dd5ed5520c98b7b287a5c1bfa21f5be Mon Sep 17 00:00:00 2001
From: lin zhida <linzhida@open104.bosccluster.com>
Date: Thu, 7 Nov 2024 16:16:38 +0800
Subject: [PATCH] fix(aes): fix exception check for aes64ks1i.

rnum of aes64ks1i must be in the range 0x0..0xA. The values 0xB..0xF are reserved.
---
 src/main/scala/xiangshan/backend/decode/DecodeUnit.scala | 7 ++++++-
 .../backend/decode/isa/bitfield/RiscvInst.scala          | 9 +++++++++
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala b/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
index 384e997388..c410385a44 100644
--- a/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
+++ b/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
@@ -868,6 +868,10 @@ class DecodeUnit(implicit p: Parameters) extends XSModule with DecodeUnitConstan
   private val isCboInval = CBO_INVAL === io.enq.ctrlFlow.instr
   private val isCboZero  = CBO_ZERO  === io.enq.ctrlFlow.instr
 
+  // Note that rnum of aes64ks1i must be in the range 0x0..0xA. The values 0xB..0xF are reserved.
+  private val isAes64ks1iIllegal =
+    FuType.FuTypeOrR(decodedInst.fuType, FuType.bku) && (decodedInst.fuOpType === BKUOpType.aes64ks1i) && inst.isRnumIllegal
+
   private val exceptionII =
     decodedInst.selImm === SelImm.INVALID_INSTR ||
     vecException.io.illegalInst ||
@@ -889,7 +893,8 @@ class DecodeUnit(implicit p: Parameters) extends XSModule with DecodeUnitConstan
     (decodedInst.needFrm.vectorNeedFrm || FuType.isVectorNeedFrm(decodedInst.fuType)) && io.fromCSR.illegalInst.frm ||
     io.fromCSR.illegalInst.cboZ       && isCboZero ||
     io.fromCSR.illegalInst.cboCF      && (isCboClean || isCboFlush) ||
-    io.fromCSR.illegalInst.cboI       && isCboInval
+    io.fromCSR.illegalInst.cboI       && isCboInval ||
+    isAes64ks1iIllegal
 
   private val exceptionVI =
     io.fromCSR.virtualInst.sfenceVMA  && FuType.FuTypeOrR(decodedInst.fuType, FuType.fence) && decodedInst.fuOpType === FenceOpType.sfence ||
diff --git a/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala b/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala
index 735bbf9e78..61b2bece3b 100644
--- a/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala
+++ b/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala
@@ -117,12 +117,21 @@ trait BitFieldsVec { this: Riscv32BitInst =>
   }
 }
 
+trait BitFieldsRVK { this: Riscv32BitInst =>
+  def RNUM          : UInt = inst(23, 20)
+
+  def isRnumIllegal = {
+    this.RNUM > 0xA.U
+  }
+}
+
 class XSInstBitFields extends Riscv32BitInst
   with BitFieldsI
   with BitFieldsS
   with BitFieldsCSR
   with BitFieldsFp
   with BitFieldsVec
+  with BitFieldsRVK
 
 class InstVType extends Bundle {
   val reserved = UInt(3.W)