From 81ed4161509e46e879d638ecd13ea7089c3ed75f Mon Sep 17 00:00:00 2001 From: Jiuyue Ma Date: Wed, 11 Dec 2024 15:46:12 +0800 Subject: [PATCH] fix(frontend,cache): fix warning of read-only return value of `.asTypeOf` (#4005) Signed-off-by: Jiuyue Ma Co-authored-by: Easton Man --- .../xiangshan/cache/mmu/PageTableWalker.scala | 4 ++-- .../scala/xiangshan/frontend/ITTAGE.scala | 18 ++++++++++-------- src/main/scala/xiangshan/frontend/Tage.scala | 19 ++++++++++--------- 3 files changed, 22 insertions(+), 19 deletions(-) diff --git a/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala b/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala index 9ced77ca97..766dd4a0fd 100644 --- a/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala +++ b/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala @@ -177,13 +177,13 @@ class PTW()(implicit p: Parameters) extends XSModule with HasPtwConst with HasPe val gvpn_gpf = !(hptw_pageFault || hptw_accessFault ) && Mux(s2xlate && io.csr.hgatp.mode === Sv39x4, full_gvpn(ptePPNLen - 1, GPAddrBitsSv39x4 - offLen) =/= 0.U, Mux(s2xlate && io.csr.hgatp.mode === Sv48x4, full_gvpn(ptePPNLen - 1, GPAddrBitsSv48x4 - offLen) =/= 0.U, false.B)) val guestFault = hptw_pageFault || hptw_accessFault || gvpn_gpf val hpaddr = Cat(hptw_resp.genPPNS2(get_pn(gpaddr)), get_off(gpaddr)) - val fake_h_resp = 0.U.asTypeOf(new HptwResp) + val fake_h_resp = WireInit(0.U.asTypeOf(new HptwResp)) fake_h_resp.entry.tag := get_pn(gpaddr) fake_h_resp.entry.vmid.map(_ := io.csr.hgatp.vmid) fake_h_resp.gpf := true.B val pte_valid = RegInit(false.B) // avoid l1tlb pf from stage1 when gpf happens in the first s2xlate in PTW - val fake_pte = 0.U.asTypeOf(new PteBundle()) + val fake_pte = WireInit(0.U.asTypeOf(new PteBundle())) fake_pte.perm.v := false.B // tell L1TLB this is fake pte fake_pte.ppn := ppn(ppnLen - 1, 0) fake_pte.ppn_high := ppn(ptePPNLen - 1, ppnLen) diff --git a/src/main/scala/xiangshan/frontend/ITTAGE.scala b/src/main/scala/xiangshan/frontend/ITTAGE.scala index b99b9b5965..1c89eabaaa 100644 --- a/src/main/scala/xiangshan/frontend/ITTAGE.scala +++ b/src/main/scala/xiangshan/frontend/ITTAGE.scala @@ -504,29 +504,34 @@ class ITTage(implicit p: Parameters) extends BaseITTage { val update = Wire(new BranchPredictionUpdate) update := RegEnable(io.update.bits, io.update.valid) + // meta is splited by composer + val updateMeta = Wire(new ITTageMeta) + update.meta := updateMeta.asUInt + // The pc register has been moved outside of predictor, pc field of update bundle and other update data are not in the same stage // so io.update.bits.pc is used directly here val update_pc = io.update.bits.pc // To improve Clock Gating Efficiency val u_meta = io.update.bits.meta.asTypeOf(new ITTageMeta) - update.meta.asTypeOf(new ITTageMeta).provider.bits := RegEnable( + updateMeta := RegEnable(u_meta, io.update.valid) + updateMeta.provider.bits := RegEnable( u_meta.provider.bits, io.update.valid && u_meta.provider.valid ) - update.meta.asTypeOf(new ITTageMeta).providerTarget := RegEnable( + updateMeta.providerTarget := RegEnable( u_meta.providerTarget, io.update.valid && u_meta.provider.valid ) - update.meta.asTypeOf(new ITTageMeta).allocate.bits := RegEnable( + updateMeta.allocate.bits := RegEnable( u_meta.allocate.bits, io.update.valid && u_meta.allocate.valid ) - update.meta.asTypeOf(new ITTageMeta).altProvider.bits := RegEnable( + updateMeta.altProvider.bits := RegEnable( u_meta.altProvider.bits, io.update.valid && u_meta.altProvider.valid ) - update.meta.asTypeOf(new ITTageMeta).altProviderTarget := RegEnable( + updateMeta.altProviderTarget := RegEnable( u_meta.altProviderTarget, io.update.valid && u_meta.provider.valid && u_meta.altProvider.valid && u_meta.providerCtr === 0.U ) @@ -543,9 +548,6 @@ class ITTage(implicit p: Parameters) extends BaseITTage { numBr - 1 ) - // meta is splited by composer - val updateMeta = update.meta.asTypeOf(new ITTageMeta) - val updateMask = WireInit(0.U.asTypeOf(Vec(ITTageNTables, Bool()))) val updateUMask = WireInit(0.U.asTypeOf(Vec(ITTageNTables, Bool()))) val updateResetU = WireInit(false.B) diff --git a/src/main/scala/xiangshan/frontend/Tage.scala b/src/main/scala/xiangshan/frontend/Tage.scala index 81459b15e7..bd5b092027 100644 --- a/src/main/scala/xiangshan/frontend/Tage.scala +++ b/src/main/scala/xiangshan/frontend/Tage.scala @@ -682,29 +682,32 @@ class Tage(implicit p: Parameters) extends BaseTage { VecInit((0 until TageBanks).map(w => io.update.bits.ftb_entry.brValids(w) && io.update.valid )) // io.update.bits.ftb_entry.always_taken has timing issues(FTQEntryGen) - val u_meta = io.update.bits.meta.asTypeOf(new TageMeta) + val u_meta = io.update.bits.meta.asTypeOf(new TageMeta) + val updateMeta = Wire(new TageMeta) + update.meta := updateMeta.asUInt + updateMeta := RegEnable(u_meta, io.update.valid) for (i <- 0 until numBr) { - update.meta.asTypeOf(new TageMeta).providers(i).bits := RegEnable( + updateMeta.providers(i).bits := RegEnable( u_meta.providers(i).bits, u_meta.providers(i).valid && u_valids_for_cge(i) ) - update.meta.asTypeOf(new TageMeta).providerResps(i) := RegEnable( + updateMeta.providerResps(i) := RegEnable( u_meta.providerResps(i), u_meta.providers(i).valid && u_valids_for_cge(i) ) - update.meta.asTypeOf(new TageMeta).altUsed(i) := RegEnable(u_meta.altUsed(i), u_valids_for_cge(i)) - update.meta.asTypeOf(new TageMeta).allocates(i) := RegEnable( + updateMeta.altUsed(i) := RegEnable(u_meta.altUsed(i), u_valids_for_cge(i)) + updateMeta.allocates(i) := RegEnable( u_meta.allocates(i), io.update.valid && io.update.bits.mispred_mask(i) ) } if (EnableSC) { for (w <- 0 until TageBanks) { - update.meta.asTypeOf(new TageMeta).scMeta.get.scPreds(w) := RegEnable( + updateMeta.scMeta.get.scPreds(w) := RegEnable( u_meta.scMeta.get.scPreds(w), u_valids_for_cge(w) && u_meta.providers(w).valid ) - update.meta.asTypeOf(new TageMeta).scMeta.get.ctrs(w) := RegEnable( + updateMeta.scMeta.get.ctrs(w) := RegEnable( u_meta.scMeta.get.ctrs(w), u_valids_for_cge(w) && u_meta.providers(w).valid ) @@ -717,8 +720,6 @@ class Tage(implicit p: Parameters) extends BaseTage { !(PriorityEncoder(update.br_taken_mask) < w.U) )) - val updateMeta = update.meta.asTypeOf(new TageMeta) - val updateMask = WireInit(0.U.asTypeOf(Vec(numBr, Vec(TageNTables, Bool())))) val updateUMask = WireInit(0.U.asTypeOf(Vec(numBr, Vec(TageNTables, Bool())))) val updateResetU = WireInit(0.U.asTypeOf(Vec(numBr, Bool()))) // per predictor