From 80147fa58493b44d5f602217d45fd3e97f137799 Mon Sep 17 00:00:00 2001 From: Anzooooo Date: Sun, 1 Dec 2024 15:55:38 +0800 Subject: [PATCH] fix(LoadQueueReplay): use more precise conditions for unblocking `forwarding fault` It is not necessary to check whether the storequeue entry pointed to by sqidx is complete, because this entry is the store that follows this load. --- src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala b/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala index f81ab9b0ae..9eab647d8d 100644 --- a/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala +++ b/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala @@ -305,8 +305,8 @@ class LoadQueueReplay(implicit p: Parameters) extends XSModule for (i <- 0 until LoadQueueReplaySize) { // dequeue // FIXME: store*Ptr is not accurate - dataNotBlockVec(i) := isAfter(io.stDataReadySqPtr, blockSqIdx(i)) || stDataReadyVec(blockSqIdx(i).value) || io.sqEmpty // for better timing - addrNotBlockVec(i) := isAfter(io.stAddrReadySqPtr, blockSqIdx(i)) || !strict(i) && stAddrReadyVec(blockSqIdx(i).value) || io.sqEmpty // for better timing + dataNotBlockVec(i) := isNotBefore(io.stDataReadySqPtr, blockSqIdx(i)) || stDataReadyVec(blockSqIdx(i).value) || io.sqEmpty // for better timing + addrNotBlockVec(i) := isNotBefore(io.stAddrReadySqPtr, blockSqIdx(i)) || !strict(i) && stAddrReadyVec(blockSqIdx(i).value) || io.sqEmpty // for better timing // store address execute storeAddrInSameCycleVec(i) := VecInit((0 until StorePipelineWidth).map(w => { io.storeAddrIn(w).valid &&