From 5da510bf45f1c96427e209fa7eccb34b1cc8affd Mon Sep 17 00:00:00 2001
From: klin02 <youkunlin20@mails.ucas.ac.cn>
Date: Sat, 14 Dec 2024 03:38:39 +0800
Subject: [PATCH] feat(XSLog): move all XSLog outside WhenContext for
 collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
WhenContext. For example, when(cond1){XSDebug(cond2, pable)} to
XSDebug(cond1 && cond2, pable)
---
 src/main/scala/device/AXI4SlaveModule.scala   |  40 +-
 src/main/scala/device/TLTimer.scala           |   6 +-
 src/main/scala/utils/DebugIdentityNode.scala  |  10 +-
 src/main/scala/utils/TLDump.scala             | 542 ++++--------------
 .../scala/xiangshan/backend/CtrlBlock.scala   |  21 +-
 .../xiangshan/backend/dispatch/Dispatch.scala |  18 +-
 .../xiangshan/backend/issue/DataArray.scala   |   4 +-
 .../xiangshan/backend/rename/Snapshot.scala   |   3 +-
 .../scala/xiangshan/backend/rob/Rob.scala     |  27 +-
 .../backend/rob/RobDeqPtrWrapper.scala        |   5 +-
 .../cache/dcache/DCacheWrapper.scala          |  32 +-
 .../xiangshan/cache/dcache/Uncache.scala      |  13 +-
 .../cache/dcache/data/AbstractDataArray.scala |  25 +-
 .../cache/dcache/data/BankedDataArray.scala   |  84 ++-
 .../dcache/data/DuplicatedDataArray.scala     |   5 +-
 .../cache/dcache/loadpipe/LoadPipe.scala      |  14 +-
 .../dcache/mainpipe/AtomicsReplayUnit.scala   |   4 +-
 .../cache/dcache/mainpipe/MainPipe.scala      |   1 -
 .../cache/dcache/mainpipe/Probe.scala         |  26 +-
 .../dcache/mainpipe/WritebackQueue.scala      |  34 +-
 .../cache/dcache/meta/LegacyMetaArray.scala   |  28 +-
 .../xiangshan/cache/mmu/PageTableCache.scala  | 216 ++++---
 .../cache/prefetch/BestOffsetPrefetch.scala   |  20 +-
 .../cache/prefetch/StreamPrefetch.scala       |  18 +-
 .../scala/xiangshan/frontend/Frontend.scala   |  70 ++-
 .../scala/xiangshan/frontend/IBuffer.scala    |  10 +-
 src/main/scala/xiangshan/frontend/IFU.scala   |  17 +-
 .../scala/xiangshan/frontend/ITTAGE.scala     |  24 +-
 .../scala/xiangshan/frontend/NewFtq.scala     |  22 +-
 src/main/scala/xiangshan/frontend/SC.scala    |  71 ++-
 .../scala/xiangshan/frontend/newRAS.scala     |  10 +-
 .../xiangshan/mem/lsqueue/LoadQueueRAR.scala  |   7 +-
 .../xiangshan/mem/lsqueue/LoadQueueRAW.scala  |   5 +-
 .../mem/lsqueue/LoadQueueReplay.scala         |  23 +-
 .../mem/lsqueue/LoadQueueUncache.scala        |  49 +-
 .../xiangshan/mem/lsqueue/StoreQueue.scala    |  83 +--
 .../mem/lsqueue/VirtualLoadQueue.scala        |  54 +-
 .../scala/xiangshan/mem/mdp/StoreSet.scala    |   6 +-
 .../scala/xiangshan/mem/mdp/WaitTable.scala   |   4 +-
 .../xiangshan/mem/pipeline/AtomicsUnit.scala  |   7 +-
 .../xiangshan/mem/pipeline/LoadUnit.scala     |   5 +-
 .../scala/xiangshan/mem/sbuffer/Sbuffer.scala |  37 +-
 .../xiangshan/mem/vector/VSegmentUnit.scala   |   4 +-
 43 files changed, 689 insertions(+), 1015 deletions(-)

diff --git a/src/main/scala/device/AXI4SlaveModule.scala b/src/main/scala/device/AXI4SlaveModule.scala
index 58b0e2fdd1..aeaf2330e3 100644
--- a/src/main/scala/device/AXI4SlaveModule.scala
+++ b/src/main/scala/device/AXI4SlaveModule.scala
@@ -62,27 +62,25 @@ class AXI4SlaveModuleImp[T<:Data](outer: AXI4SlaveModule[T])
 
 
 //  val timer = GTimer()
-  when(in.ar.fire){
-    XSDebug(p"[ar] addr: ${Hexadecimal(in.ar.bits.addr)} " +
-      p"arlen:${in.ar.bits.len} arsize:${in.ar.bits.size} " +
-      p"id: ${in.ar.bits.id}\n"
-    )
-  }
-  when(in.aw.fire){
-    XSDebug(p"[aw] addr: ${Hexadecimal(in.aw.bits.addr)} " +
-      p"awlen:${in.aw.bits.len} awsize:${in.aw.bits.size} " +
-      p"id: ${in.aw.bits.id}\n"
-    )
-  }
-  when(in.w.fire){
-    XSDebug(p"[w] wmask: ${Binary(in.w.bits.strb)} last:${in.w.bits.last} data:${Hexadecimal(in.w.bits.data)}\n")
-  }
-  when(in.b.fire){
-    XSDebug(p"[b] id: ${in.b.bits.id}\n")
-  }
-  when(in.r.fire){
-    XSDebug(p"[r] id: ${in.r.bits.id} data: ${Hexadecimal(in.r.bits.data)}\n")
-  }
+  XSDebug(in.ar.fire,
+    p"[ar] addr: ${Hexadecimal(in.ar.bits.addr)} " +
+    p"arlen:${in.ar.bits.len} arsize:${in.ar.bits.size} " +
+    p"id: ${in.ar.bits.id}\n"
+  )
+  XSDebug(in.aw.fire,
+    p"[aw] addr: ${Hexadecimal(in.aw.bits.addr)} " +
+    p"awlen:${in.aw.bits.len} awsize:${in.aw.bits.size} " +
+    p"id: ${in.aw.bits.id}\n"
+  )
+  XSDebug(in.w.fire,
+    p"[w] wmask: ${Binary(in.w.bits.strb)} last:${in.w.bits.last} data:${Hexadecimal(in.w.bits.data)}\n"
+  )
+  XSDebug(in.b.fire,
+    p"[b] id: ${in.b.bits.id}\n"
+  )
+  XSDebug(in.r.fire,
+    p"[r] id: ${in.r.bits.id} data: ${Hexadecimal(in.r.bits.data)}\n"
+  )
 
   when(in.aw.fire){
     assert(in.aw.bits.burst === AXI4Parameters.BURST_INCR, "only support busrt ince!")
diff --git a/src/main/scala/device/TLTimer.scala b/src/main/scala/device/TLTimer.scala
index 80672b176b..931dbc22cb 100644
--- a/src/main/scala/device/TLTimer.scala
+++ b/src/main/scala/device/TLTimer.scala
@@ -65,10 +65,8 @@ class TLTimer(address: Seq[AddressSet], sim: Boolean, numCores: Int)(implicit p:
     node.regmap( mapping = clintMapping:_* )
 
     val in = node.in.head._1
-    when(in.a.valid){
-      XSDebug("[A] channel valid ready=%d ", in.a.ready)
-      in.a.bits.dump
-    }
+    XSDebug(in.a.valid, "[A] channel valid ready=%d ", in.a.ready)
+    in.a.bits.dump(in.a.valid)
 
     for (i <- 0 until numCores) {
       io.mtip(i) := RegNext(mtime >= mtimecmp(i))
diff --git a/src/main/scala/utils/DebugIdentityNode.scala b/src/main/scala/utils/DebugIdentityNode.scala
index f3c8aaa01c..dc63aff086 100644
--- a/src/main/scala/utils/DebugIdentityNode.scala
+++ b/src/main/scala/utils/DebugIdentityNode.scala
@@ -40,12 +40,10 @@ class DebugIdentityNode()(implicit p: Parameters) extends LazyModule  {
     def debug(t: TLBundle, valid: Boolean = false): Unit ={
       def fire[T <: Data](x: DecoupledIO[T]) = if(valid) x.valid else x.fire
       val channels = Seq(t.a, t.b, t.c, t.d, t.e)
-      channels.foreach(c =>
-        when(fire(c)){
-          XSDebug(" isFire:%d ",c.fire)
-          c.bits.dump
-        }
-      )
+      channels.foreach { c =>
+        XSDebug(fire(c), " isFire:%d ", c.fire)
+        c.bits.dump(fire(c))
+      }
     }
     debug(in, false)
   }
diff --git a/src/main/scala/utils/TLDump.scala b/src/main/scala/utils/TLDump.scala
index e05320ba9c..aaa190c03a 100644
--- a/src/main/scala/utils/TLDump.scala
+++ b/src/main/scala/utils/TLDump.scala
@@ -29,454 +29,154 @@ trait HasTLDump {
   implicit val p: Parameters
 
   implicit class TLDump(channel: TLChannel) {
-    def dump = channel match {
+    def dump(cond: Bool) = channel match {
       case a: TLBundleA =>
-        printChannelA(a)
+        printChannelA(a, cond)
       case b: TLBundleB =>
-        printChannelB(b)
+        printChannelB(b, cond)
       case c: TLBundleC =>
-        printChannelC(c)
+        printChannelC(c, cond)
       case d: TLBundleD =>
-        printChannelD(d)
+        printChannelD(d, cond)
       case e: TLBundleE =>
-        printChannelE(e)
+        printChannelE(e, cond)
     }
   }
 
-  def printChannelA(a: TLBundleA): Unit = {
-    switch(a.opcode) {
-      is(PutFullData) {
-        XSDebug(false, true.B,
-          a.channelName + " PutFullData param: %x size: %x source: %d address: %x mask: %x data: %x corrupt: %b\n",
-          a.param, a.size, a.source, a.address, a.mask, a.data, a.corrupt
-        )
-      }
-
-      is(PutPartialData) {
-        XSDebug(false, true.B,
-          a.channelName + " PutPartialData param: %x size: %x source: %d address: %x mask: %x data: %x corrupt: %b\n",
-          a.param, a.size, a.source, a.address, a.mask, a.data, a.corrupt
-        )
-      }
-
-      is(ArithmeticData) {
-        XSDebug(false, true.B,
-          a.channelName + " ArithmeticData param: %x size: %x source: %d address: %x mask: %x data: %x corrupt: %b\n",
-          a.param, a.size, a.source, a.address, a.mask, a.data, a.corrupt
-        )
-      }
-
-      is(LogicalData) {
-        XSDebug(false, true.B,
-          a.channelName + " LogicalData param: %x size: %x source: %d address: %x mask: %x data: %x corrupt: %b\n",
-          a.param, a.size, a.source, a.address, a.mask, a.data, a.corrupt
-        )
-      }
-
-      is(Get) {
-        XSDebug(false, true.B,
-          a.channelName + " Get param: %x size: %x source: %d address: %x mask: %x data: %x corrupt: %b\n",
-          a.param, a.size, a.source, a.address, a.mask, a.data, a.corrupt
-        )
-      }
-
-      is(Hint) {
-        XSDebug(false, true.B,
-          a.channelName + " Intent param: %x size: %x source: %d address: %x mask: %x data: %x corrupt: %b\n",
-          a.param, a.size, a.source, a.address, a.mask, a.data, a.corrupt
-        )
-      }
-
-      is(AcquireBlock) {
-        switch(a.param) {
-          is(NtoB) {
-            XSDebug(false, true.B,
-              a.channelName + " AcquireBlock NtoB size: %x source: %d address: %x mask: %x data: %x corrupt: %b\n",
-              a.size, a.source, a.address, a.mask, a.data, a.corrupt
-            )
-          }
-          is(NtoT) {
-            XSDebug(false, true.B,
-              a.channelName + " AcquireBlock NtoT size: %x source: %d address: %x mask: %x data: %x corrupt: %b\n",
-              a.size, a.source, a.address, a.mask, a.data, a.corrupt
-            )
-          }
-          is(BtoT) {
-            XSDebug(false, true.B,
-              a.channelName + " AcquireBlock BtoT size: %x source: %d address: %x mask: %x data: %x corrupt: %b\n",
-              a.size, a.source, a.address, a.mask, a.data, a.corrupt
-            )
-          }
-        }
-      }
-
-      is(AcquirePerm) {
-        switch(a.param) {
-          is(NtoB) {
-            XSDebug(false, true.B,
-              a.channelName + " AcquirePerm NtoB size: %x source: %d address: %x mask: %x data: %x corrupt: %b\n",
-              a.size, a.source, a.address, a.mask, a.data, a.corrupt
-            )
-          }
-          is(NtoT) {
-            XSDebug(false, true.B,
-              a.channelName + " AcquirePerm NtoT size: %x source: %d address: %x mask: %x data: %x corrupt: %b\n",
-              a.size, a.source, a.address, a.mask, a.data, a.corrupt
-            )
-          }
-          is(BtoT) {
-            XSDebug(false, true.B,
-              a.channelName + " AcquirePerm BtoT size: %x source: %d address: %x mask: %x data: %x corrupt: %b\n",
-              a.size, a.source, a.address, a.mask, a.data, a.corrupt
-            )
-          }
-        }
-      }
-
+  def printChannelA(a: TLBundleA, cond: Bool): Unit = {
+    def APrintable(opStr: String, paramStr: String = ""): Printable = {
+      a.channelName + " " + opStr + " " +
+        (if (paramStr != "") paramStr else Printable.pack("param: %x", a.param)) +
+        Printable.pack(" size: %x source: %d address: %x mask: %x data: %x corrupt: %b\n",
+          a.size, a.source, a.address, a.mask, a.data, a.corrupt)
     }
-  }
-
-  def printChannelB(b: TLBundleB): Unit = {
-    switch(b.opcode) {
-      is(PutFullData) {
-        XSDebug(false, true.B,
-          b.channelName + " PutFullData param: %x size: %x source: %d address: %x mask: %x data: %x corrupt: %b\n",
-          b.param, b.size, b.source, b.address, b.mask, b.data, b.corrupt
-        )
-      }
-
-      is(PutPartialData) {
-        XSDebug(false, true.B,
-          b.channelName + " PutPartialData param: %x size: %x source: %d address: %x mask: %x data: %x corrupt: %b\n",
-          b.param, b.size, b.source, b.address, b.mask, b.data, b.corrupt
-        )
-      }
-
-      is(ArithmeticData) {
-        XSDebug(false, true.B,
-          b.channelName + " ArithmeticData param: %x size: %x source: %d address: %x mask: %x data: %x corrupt: %b\n",
-          b.param, b.size, b.source, b.address, b.mask, b.data, b.corrupt
-        )
-      }
-
-      is(LogicalData) {
-        XSDebug(false, true.B,
-          b.channelName + " LogicalData param: %x size: %x source: %d address: %x mask: %x data: %x corrupt: %b\n",
-          b.param, b.size, b.source, b.address, b.mask, b.data, b.corrupt
-        )
-      }
-
-      is(Get) {
-        XSDebug(false, true.B,
-          b.channelName + " Get param: %x size: %x source: %d address: %x mask: %x data: %x corrupt: %b\n",
-          b.param, b.size, b.source, b.address, b.mask, b.data, b.corrupt
-        )
-      }
-
-      is(Hint) {
-        XSDebug(false, true.B,
-          b.channelName + " Intent param: %x size: %x source: %d address: %x mask: %x data: %x corrupt: %b\n",
-          b.param, b.size, b.source, b.address, b.mask, b.data, b.corrupt
-        )
-      }
-
-      is(Probe) {
-        switch(b.param) {
-          is(toN) {
-            XSDebug(false, true.B,
-              b.channelName + " Probe toN size: %x source: %d address: %x mask: %x data: %x corrupt: %b\n",
-              b.size, b.source, b.address, b.mask, b.data, b.corrupt
-            )
-          }
-          is(toB) {
-            XSDebug(false, true.B,
-              b.channelName + " Probe toB size: %x source: %d address: %x mask: %x data: %x corrupt: %b\n",
-              b.size, b.source, b.address, b.mask, b.data, b.corrupt
-            )
-          }
-          is(toT) {
-            XSDebug(false, true.B,
-              b.channelName + " Probe toT size: %x source: %d address: %x mask: %x data: %x corrupt: %b\n",
-              b.size, b.source, b.address, b.mask, b.data, b.corrupt
-            )
-          }
-        }
-      }
-
+    def ACond(opCode: UInt, param: Option[UInt] = None): Bool = {
+      // skip param compare if not passed
+      val paramComp = if (param.isDefined) a.param === param.get else true.B
+      cond && a.opcode === opCode && paramComp
     }
-  }
-
-  def printChannelC(c: TLBundleC): Unit = {
-    switch(c.opcode) {
-      is(AccessAck) {
-        XSDebug(false, true.B,
-          c.channelName + " AccessAck param: %x size: %x source: %d address: %x data: %x corrupt: %b\n",
-          c.param, c.size, c.source, c.address, c.data, c.corrupt
-        )
-      }
 
-      is(AccessAckData) {
-        XSDebug(false, true.B,
-          c.channelName + " AccessAckData param: %x size: %x source: %d address: %x data: %x corrupt: %b\n",
-          c.param, c.size, c.source, c.address, c.data, c.corrupt
-        )
-      }
+    XSDebug(false, ACond(PutFullData), APrintable("PutFullData"))
+    XSDebug(false, ACond(PutPartialData), APrintable("PutPartialData"))
+    XSDebug(false, ACond(ArithmeticData), APrintable("ArithmeticData"))
+    XSDebug(false, ACond(LogicalData), APrintable("LogicalData"))
+    XSDebug(false, ACond(Get), APrintable("Get"))
+    XSDebug(false, ACond(Hint), APrintable("Intent"))
 
-      is(HintAck) {
-        XSDebug(false, true.B,
-          c.channelName + " HintAck param: %x size: %x source: %d address: %x data: %x corrupt: %b\n",
-          c.param, c.size, c.source, c.address, c.data, c.corrupt
-        )
-      }
+    XSDebug(false, ACond(AcquireBlock, Some(NtoB)), APrintable("AcquireBlock", "NtoB"))
+    XSDebug(false, ACond(AcquireBlock, Some(NtoT)), APrintable("AcquireBlock", "NtoT"))
+    XSDebug(false, ACond(AcquireBlock, Some(BtoT)), APrintable("AcquireBlock", "BtoT"))
 
-      is(ProbeAck) {
-        switch(c.param) {
-          is(TtoB) {
-            XSDebug(false, true.B,
-              c.channelName + " ProbeAck TtoB size: %x source: %d address: %x data: %x corrupt: %b\n",
-              c.size, c.source, c.address, c.data, c.corrupt
-            )
-          }
-          is(TtoN) {
-            XSDebug(false, true.B,
-              c.channelName + " ProbeAck TtoN size: %x source: %d address: %x data: %x corrupt: %b\n",
-              c.size, c.source, c.address, c.data, c.corrupt
-            )
-          }
-          is(BtoN) {
-            XSDebug(false, true.B,
-              c.channelName + " ProbeAck BtoN size: %x source: %d address: %x data: %x corrupt: %b\n",
-              c.size, c.source, c.address, c.data, c.corrupt
-            )
-          }
-          is(TtoT) {
-            XSDebug(false, true.B,
-              c.channelName + " ProbeAck TtoT size: %x source: %d address: %x data: %x corrupt: %b\n",
-              c.size, c.source, c.address, c.data, c.corrupt
-            )
-          }
-          is(BtoB) {
-            XSDebug(false, true.B,
-              c.channelName + " ProbeAck BtoB size: %x source: %d address: %x data: %x corrupt: %b\n",
-              c.size, c.source, c.address, c.data, c.corrupt
-            )
-          }
-          is(NtoN) {
-            XSDebug(false, true.B,
-              c.channelName + " ProbeAck NtoN size: %x source: %d address: %x data: %x corrupt: %b\n",
-              c.size, c.source, c.address, c.data, c.corrupt
-            )
-          }
-        }
-      }
+    XSDebug(false, ACond(AcquirePerm, Some(NtoB)), APrintable("AcquirePerm", "NtoB"))
+    XSDebug(false, ACond(AcquirePerm, Some(NtoT)), APrintable("AcquirePerm", "NtoT"))
+    XSDebug(false, ACond(AcquirePerm, Some(BtoT)), APrintable("AcquirePerm", "BtoT"))
+  }
 
-      is(ProbeAckData) {
-        switch(c.param) {
-          is(TtoB) {
-            XSDebug(false, true.B,
-              c.channelName + " ProbeAckData TtoB size: %x source: %d address: %x data: %x corrupt: %b\n",
-              c.size, c.source, c.address, c.data, c.corrupt
-            )
-          }
-          is(TtoN) {
-            XSDebug(false, true.B,
-              c.channelName + " ProbeAckData TtoN size: %x source: %d address: %x data: %x corrupt: %b\n",
-              c.size, c.source, c.address, c.data, c.corrupt
-            )
-          }
-          is(BtoN) {
-            XSDebug(false, true.B,
-              c.channelName + " ProbeAckData BtoN size: %x source: %d address: %x data: %x corrupt: %b\n",
-              c.size, c.source, c.address, c.data, c.corrupt
-            )
-          }
-          is(TtoT) {
-            XSDebug(false, true.B,
-              c.channelName + " ProbeAckData TtoT size: %x source: %d address: %x data: %x corrupt: %b\n",
-              c.size, c.source, c.address, c.data, c.corrupt
-            )
-          }
-          is(BtoB) {
-            XSDebug(false, true.B,
-              c.channelName + " ProbeAckData BtoB size: %x source: %d address: %x data: %x corrupt: %b\n",
-              c.size, c.source, c.address, c.data, c.corrupt
-            )
-          }
-          is(NtoN) {
-            XSDebug(false, true.B,
-              c.channelName + " ProbeAckData NtoN size: %x source: %d address: %x data: %x corrupt: %b\n",
-              c.size, c.source, c.address, c.data, c.corrupt
-            )
-          }
-        }
-      }
+  def printChannelB(b: TLBundleB, cond: Bool): Unit = {
+    def BPrintable(opStr: String, paramStr: String = ""): Printable = {
+      b.channelName + " " + opStr + " " +
+        (if (paramStr != "") paramStr else Printable.pack("param: %x", b.param)) +
+        Printable.pack(" size: %x source: %d address: %x mask: %x data: %x corrupt: %b\n",
+          b.size, b.source, b.address, b.mask, b.data, b.corrupt)
+    }
+    def BCond(opCode: UInt, param: Option[UInt] = None): Bool = {
+      // skip param compare if not passed
+      val paramComp = if (param.isDefined) b.param === param.get else true.B
+      cond && b.opcode === opCode && paramComp
+    }
 
-      is(Release) {
-        switch(c.param) {
-          is(TtoB) {
-            XSDebug(false, true.B,
-              c.channelName + " Release TtoB size: %x source: %d address: %x data: %x corrupt: %b\n",
-              c.size, c.source, c.address, c.data, c.corrupt
-            )
-          }
-          is(TtoN) {
-            XSDebug(false, true.B,
-              c.channelName + " Release TtoN size: %x source: %d address: %x data: %x corrupt: %b\n",
-              c.size, c.source, c.address, c.data, c.corrupt
-            )
-          }
-          is(BtoN) {
-            XSDebug(false, true.B,
-              c.channelName + " Release BtoN size: %x source: %d address: %x data: %x corrupt: %b\n",
-              c.size, c.source, c.address, c.data, c.corrupt
-            )
-          }
-          is(TtoT) {
-            XSDebug(false, true.B,
-              c.channelName + " Release TtoT size: %x source: %d address: %x data: %x corrupt: %b\n",
-              c.size, c.source, c.address, c.data, c.corrupt
-            )
-          }
-          is(BtoB) {
-            XSDebug(false, true.B,
-              c.channelName + " Release BtoB size: %x source: %d address: %x data: %x corrupt: %b\n",
-              c.size, c.source, c.address, c.data, c.corrupt
-            )
-          }
-          is(NtoN) {
-            XSDebug(false, true.B,
-              c.channelName + " Release NtoN size: %x source: %d address: %x data: %x corrupt: %b\n",
-              c.size, c.source, c.address, c.data, c.corrupt
-            )
-          }
-        }
-      }
+    XSDebug(false, BCond(PutFullData), BPrintable("PutFullData"))
+    XSDebug(false, BCond(PutPartialData), BPrintable("PutPartialData"))
+    XSDebug(false, BCond(ArithmeticData), BPrintable("ArithmeticData"))
+    XSDebug(false, BCond(LogicalData), BPrintable("LogicalData"))
+    XSDebug(false, BCond(Get), BPrintable("Get"))
+    XSDebug(false, BCond(Hint), BPrintable("Intent"))
 
-      is(ReleaseData) {
-        switch(c.param) {
-          is(TtoB) {
-            XSDebug(false, true.B,
-              c.channelName + " ReleaseData TtoB size: %x source: %d address: %x data: %x corrupt: %b\n",
-              c.size, c.source, c.address, c.data, c.corrupt
-            )
-          }
-          is(TtoN) {
-            XSDebug(false, true.B,
-              c.channelName + " ReleaseData TtoN size: %x source: %d address: %x data: %x corrupt: %b\n",
-              c.size, c.source, c.address, c.data, c.corrupt
-            )
-          }
-          is(BtoN) {
-            XSDebug(false, true.B,
-              c.channelName + " ReleaseData BtoN size: %x source: %d address: %x data: %x corrupt: %b\n",
-              c.size, c.source, c.address, c.data, c.corrupt
-            )
-          }
-          is(TtoT) {
-            XSDebug(false, true.B,
-              c.channelName + " ReleaseData TtoT size: %x source: %d address: %x data: %x corrupt: %b\n",
-              c.size, c.source, c.address, c.data, c.corrupt
-            )
-          }
-          is(BtoB) {
-            XSDebug(false, true.B,
-              c.channelName + " ReleaseData BtoB size: %x source: %d address: %x data: %x corrupt: %b\n",
-              c.size, c.source, c.address, c.data, c.corrupt
-            )
-          }
-          is(NtoN) {
-            XSDebug(false, true.B,
-              c.channelName + " ReleaseData NtoN size: %x source: %d address: %x data: %x corrupt: %b\n",
-              c.size, c.source, c.address, c.data, c.corrupt
-            )
-          }
-        }
-      }
+    XSDebug(false, BCond(Probe, Some(toN)), BPrintable("Probe", "toN"))
+    XSDebug(false, BCond(Probe, Some(toB)), BPrintable("Probe", "toB"))
+    XSDebug(false, BCond(Probe, Some(toT)), BPrintable("Probe", "toT"))
+  }
 
+  def printChannelC(c: TLBundleC, cond: Bool): Unit = {
+    def CPrintable(opStr: String, paramStr: String = ""): Printable = {
+      c.channelName + " " + opStr + " " +
+        (if (paramStr != "") paramStr else Printable.pack("param: %x", c.param)) +
+        Printable.pack(" size: %x source: %d address: %x data: %x corrupt: %b\n",
+          c.size, c.source, c.address, c.data, c.corrupt)
+    }
+    def CCond(opCode: UInt, param: Option[UInt] = None): Bool = {
+      // skip param compare if not passed
+      val paramComp = if (param.isDefined) c.param === param.get else true.B
+      cond && c.opcode === opCode && paramComp
     }
-  }
 
-  def printChannelD(d: TLBundleD): Unit = {
-    switch(d.opcode) {
-      is(AccessAck) {
-        XSDebug(false, true.B,
-          d.channelName + " AccessAck param: %x size: %x source: %d sink: %d denied: %b data: %x corrupt: %b\n",
-          d.param, d.size, d.source, d.sink, d.denied, d.data, d.corrupt
-        )
-      }
+    XSDebug(false, CCond(AccessAck), CPrintable("AccessAck"))
+    XSDebug(false, CCond(AccessAckData), CPrintable("AccessAckData"))
+    XSDebug(false, CCond(HintAck), CPrintable("HintAck"))
+
+    XSDebug(false, CCond(ProbeAck, Some(TtoB)), CPrintable("ProbeAck", "TtoB"))
+    XSDebug(false, CCond(ProbeAck, Some(TtoN)), CPrintable("ProbeAck", "TtoN"))
+    XSDebug(false, CCond(ProbeAck, Some(BtoN)), CPrintable("ProbeAck", "BtoN"))
+    XSDebug(false, CCond(ProbeAck, Some(TtoT)), CPrintable("ProbeAck", "TtoT"))
+    XSDebug(false, CCond(ProbeAck, Some(BtoB)), CPrintable("ProbeAck", "BtoB"))
+    XSDebug(false, CCond(ProbeAck, Some(NtoN)), CPrintable("ProbeAck", "NtoN"))
+
+    XSDebug(false, CCond(ProbeAckData, Some(TtoB)), CPrintable("ProbeAckData", "TtoB"))
+    XSDebug(false, CCond(ProbeAckData, Some(TtoN)), CPrintable("ProbeAckData", "TtoN"))
+    XSDebug(false, CCond(ProbeAckData, Some(BtoN)), CPrintable("ProbeAckData", "BtoN"))
+    XSDebug(false, CCond(ProbeAckData, Some(TtoT)), CPrintable("ProbeAckData", "TtoT"))
+    XSDebug(false, CCond(ProbeAckData, Some(BtoB)), CPrintable("ProbeAckData", "BtoB"))
+    XSDebug(false, CCond(ProbeAckData, Some(NtoN)), CPrintable("ProbeAckData", "NtoN"))
+
+    XSDebug(false, CCond(Release, Some(TtoB)), CPrintable("Release", "TtoB"))
+    XSDebug(false, CCond(Release, Some(TtoN)), CPrintable("Release", "TtoN"))
+    XSDebug(false, CCond(Release, Some(BtoN)), CPrintable("Release", "BtoN"))
+    XSDebug(false, CCond(Release, Some(TtoT)), CPrintable("Release", "TtoT"))
+    XSDebug(false, CCond(Release, Some(BtoB)), CPrintable("Release", "BtoB"))
+    XSDebug(false, CCond(Release, Some(NtoN)), CPrintable("Release", "NtoN"))
+
+    XSDebug(false, CCond(ReleaseData, Some(TtoB)), CPrintable("ReleaseData", "TtoB"))
+    XSDebug(false, CCond(ReleaseData, Some(TtoN)), CPrintable("ReleaseData", "TtoN"))
+    XSDebug(false, CCond(ReleaseData, Some(BtoN)), CPrintable("ReleaseData", "BtoN"))
+    XSDebug(false, CCond(ReleaseData, Some(TtoT)), CPrintable("ReleaseData", "TtoT"))
+    XSDebug(false, CCond(ReleaseData, Some(BtoB)), CPrintable("ReleaseData", "BtoB"))
+    XSDebug(false, CCond(ReleaseData, Some(NtoN)), CPrintable("ReleaseData", "NtoN"))
+  }
 
-      is(AccessAckData) {
-        XSDebug(false, true.B,
-          d.channelName + " AccessAckData param: %x size: %x source: %d sink: %d denied: %b data: %x corrupt: %b\n",
-          d.param, d.size, d.source, d.sink, d.denied, d.data, d.corrupt
-        )
-      }
+  def printChannelD(d: TLBundleD, cond: Bool): Unit = {
+    def DPrintable(opStr: String, paramStr: String = ""): Printable = {
+      d.channelName + " " + opStr + " " +
+        (if (paramStr != "") paramStr else Printable.pack("param: %x", d.param)) +
+        Printable.pack(" size: %x source: %d sink: %d denied: %b data: %x corrupt: %b\n",
+          d.size, d.source, d.sink, d.denied, d.data, d.corrupt)
+    }
+    def DCond(opCode: UInt, param: Option[UInt] = None): Bool = {
+      // skip param compare if not passed
+      val paramComp = if (param.isDefined) d.param === param.get else true.B
+      cond && d.opcode === opCode && paramComp
+    }
 
-      is(HintAck) {
-        XSDebug(false, true.B,
-          d.channelName + " HintAck param: %x size: %x source: %d sink: %d denied: %b data: %x corrupt: %b\n",
-          d.param, d.size, d.source, d.sink, d.denied, d.data, d.corrupt
-        )
-      }
+    XSDebug(false, DCond(AccessAck), DPrintable("AccessAck"))
+    XSDebug(false, DCond(AccessAckData), DPrintable("AccessAckData"))
+    XSDebug(false, DCond(HintAck), DPrintable("HintAck"))
 
-      is(Grant) {
-        switch(d.param) {
-          is(toT) {
-            XSDebug(false, true.B,
-              d.channelName + " Grant toT size: %x source: %d sink: %d denied: %b data: %x corrupt: %b\n",
-              d.size, d.source, d.sink, d.denied, d.data, d.corrupt
-            )
-          }
-          is(toB) {
-            XSDebug(false, true.B,
-              d.channelName + " Grant toB size: %x source: %d sink: %d denied: %b data: %x corrupt: %b\n",
-              d.size, d.source, d.sink, d.denied, d.data, d.corrupt
-            )
-          }
-          is(toN) {
-            XSDebug(false, true.B,
-              d.channelName + " Grant toN size: %x source: %d sink: %d denied: %b data: %x corrupt: %b\n",
-              d.size, d.source, d.sink, d.denied, d.data, d.corrupt
-            )
-          }
-        }
-      }
+    XSDebug(false, DCond(Grant, Some(toT)), DPrintable("Grant", "toT"))
+    XSDebug(false, DCond(Grant, Some(toB)), DPrintable("Grant", "toB"))
+    XSDebug(false, DCond(Grant, Some(toN)), DPrintable("Grant", "toN"))
 
-      is(GrantData) {
-        switch(d.param) {
-          is(toT) {
-            XSDebug(false, true.B,
-              d.channelName + " GrantData toT size: %x source: %d sink: %d denied: %b data: %x corrupt: %b\n",
-              d.size, d.source, d.sink, d.denied, d.data, d.corrupt
-            )
-          }
-          is(toB) {
-            XSDebug(false, true.B,
-              d.channelName + " GrantData toB size: %x source: %d sink: %d denied: %b data: %x corrupt: %b\n",
-              d.size, d.source, d.sink, d.denied, d.data, d.corrupt
-            )
-          }
-          is(toN) {
-            XSDebug(false, true.B,
-              d.channelName + " GrantData toN size: %x source: %d sink: %d denied: %b data: %x corrupt: %b\n",
-              d.size, d.source, d.sink, d.denied, d.data, d.corrupt
-            )
-          }
-        }
-      }
+    XSDebug(false, DCond(GrantData, Some(toT)), DPrintable("GrantData", "toT"))
+    XSDebug(false, DCond(GrantData, Some(toB)), DPrintable("GrantData", "toB"))
+    XSDebug(false, DCond(GrantData, Some(toN)), DPrintable("GrantData", "toN"))
 
-      is(ReleaseAck) {
-        XSDebug(false, true.B,
-          d.channelName + " ReleaseAck param: %x size: %x source: %d sink: %d denied: %b data: %x corrupt: %b\n",
-          d.param, d.size, d.source, d.sink, d.denied, d.data, d.corrupt
-        )
-      }
+    XSDebug(false, DCond(GrantData, Some(toT)), DPrintable("GrantData", "toT"))
+    XSDebug(false, DCond(GrantData, Some(toB)), DPrintable("GrantData", "toB"))
+    XSDebug(false, DCond(GrantData, Some(toN)), DPrintable("GrantData", "toN"))
 
-    }
+    XSDebug(false, DCond(ReleaseAck), DPrintable("ReleaseAck"))
   }
 
-  def printChannelE(e: TLBundleE): Unit = {
-    XSDebug(false, true.B, e.channelName + "GrantAck sink: %d\n", e.sink)
+  def printChannelE(e: TLBundleE, cond: Bool): Unit = {
+    XSDebug(false, cond, e.channelName + "GrantAck sink: %d\n", e.sink)
   }
 
 }
diff --git a/src/main/scala/xiangshan/backend/CtrlBlock.scala b/src/main/scala/xiangshan/backend/CtrlBlock.scala
index 5afe7e1d81..b835517028 100644
--- a/src/main/scala/xiangshan/backend/CtrlBlock.scala
+++ b/src/main/scala/xiangshan/backend/CtrlBlock.scala
@@ -481,21 +481,20 @@ class CtrlBlockImp(
 
     // update the first RenameWidth - 1 instructions
     decode.io.fusion(i) := fusionDecoder.io.out(i).valid && rename.io.out(i).fire
+    // TODO: remove this dirty code for ftq update
+    val sameFtqPtr = rename.io.in(i).bits.ftqPtr.value === rename.io.in(i + 1).bits.ftqPtr.value
+    val ftqOffset0 = rename.io.in(i).bits.ftqOffset
+    val ftqOffset1 = rename.io.in(i + 1).bits.ftqOffset
+    val ftqOffsetDiff = ftqOffset1 - ftqOffset0
+    val cond1 = sameFtqPtr && ftqOffsetDiff === 1.U
+    val cond2 = sameFtqPtr && ftqOffsetDiff === 2.U
+    val cond3 = !sameFtqPtr && ftqOffset1 === 0.U
+    val cond4 = !sameFtqPtr && ftqOffset1 === 1.U
     when (fusionDecoder.io.out(i).valid) {
       fusionDecoder.io.out(i).bits.update(rename.io.in(i).bits)
-      // TODO: remove this dirty code for ftq update
-      val sameFtqPtr = rename.io.in(i).bits.ftqPtr.value === rename.io.in(i + 1).bits.ftqPtr.value
-      val ftqOffset0 = rename.io.in(i).bits.ftqOffset
-      val ftqOffset1 = rename.io.in(i + 1).bits.ftqOffset
-      val ftqOffsetDiff = ftqOffset1 - ftqOffset0
-      val cond1 = sameFtqPtr && ftqOffsetDiff === 1.U
-      val cond2 = sameFtqPtr && ftqOffsetDiff === 2.U
-      val cond3 = !sameFtqPtr && ftqOffset1 === 0.U
-      val cond4 = !sameFtqPtr && ftqOffset1 === 1.U
       rename.io.in(i).bits.commitType := Mux(cond1, 4.U, Mux(cond2, 5.U, Mux(cond3, 6.U, 7.U)))
-      XSError(!cond1 && !cond2 && !cond3 && !cond4, p"new condition $sameFtqPtr $ftqOffset0 $ftqOffset1\n")
     }
-
+    XSError(fusionDecoder.io.out(i).valid && !cond1 && !cond2 && !cond3 && !cond4, p"new condition $sameFtqPtr $ftqOffset0 $ftqOffset1\n")
   }
 
   // memory dependency predict
diff --git a/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala b/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
index 8e301c9325..3c119b2a72 100644
--- a/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
+++ b/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
@@ -195,23 +195,23 @@ class Dispatch(implicit p: Parameters) extends XSModule with HasPerfEvents {
   val isAMO    = VecInit(io.fromRename.map(req => FuType.isAMO(req.bits.fuType)))
   val isBlockBackward  = VecInit(io.fromRename.map(x => x.valid && x.bits.blockBackward))
   val isWaitForward    = VecInit(io.fromRename.map(x => x.valid && x.bits.waitForward))
-  
+
   // Singlestep should only commit one machine instruction after dret, and then hart enter debugMode according to singlestep exception.
   val s_holdRobidx :: s_updateRobidx :: Nil = Enum(2)
   val singleStepState = RegInit(s_updateRobidx)
-  
+
   val robidxStepHold  = WireInit(0.U.asTypeOf(io.fromRename(0).bits.robIdx))
   val robidxStepReg   = RegInit(0.U.asTypeOf(io.fromRename(0).bits.robIdx))
   val robidxCanCommitStepping = WireInit(0.U.asTypeOf(io.fromRename(0).bits.robIdx))
   robidxStepReg := robidxCanCommitStepping
-  
+
   when(!io.singleStep) {
     singleStepState := s_updateRobidx
   }.elsewhen(io.singleStep && io.fromRename(0).fire && io.enqRob.req(0).valid) {
     singleStepState := s_holdRobidx
     robidxStepHold := io.fromRename(0).bits.robIdx
   }
-  
+
   when(singleStepState === s_updateRobidx) {
     robidxCanCommitStepping := robidxStepHold
   }.elsewhen(singleStepState === s_holdRobidx) {
@@ -252,10 +252,12 @@ class Dispatch(implicit p: Parameters) extends XSModule with HasPerfEvents {
     }
     // update singleStep, singleStep exception only enable in next machine instruction.
     updatedUop(i).singleStep := io.singleStep && (io.fromRename(i).bits.robIdx =/= robidxCanCommitStepping)
-    when (io.fromRename(i).fire) {
-      XSDebug(TriggerAction.isDmode(updatedUop(i).trigger) || updatedUop(i).exceptionVec(breakPoint), s"Debug Mode: inst ${i} has frontend trigger exception\n")
-      XSDebug(updatedUop(i).singleStep, s"Debug Mode: inst ${i} has single step exception\n")
-    }
+    XSDebug(io.fromRename(i).fire &&
+              (TriggerAction.isDmode(updatedUop(i).trigger) || updatedUop(i).exceptionVec(breakPoint)),
+            s"Debug Mode: inst ${i} has frontend trigger exception\n")
+    XSDebug(io.fromRename(i).fire &&
+              updatedUop(i).singleStep,
+            s"Debug Mode: inst ${i} has single step exception\n")
     if (env.EnableDifftest) {
       // debug runahead hint
       val debug_runahead_checkpoint_id = Wire(checkpoint_id.cloneType)
diff --git a/src/main/scala/xiangshan/backend/issue/DataArray.scala b/src/main/scala/xiangshan/backend/issue/DataArray.scala
index 52c2d4ff55..50e231640f 100644
--- a/src/main/scala/xiangshan/backend/issue/DataArray.scala
+++ b/src/main/scala/xiangshan/backend/issue/DataArray.scala
@@ -41,8 +41,6 @@ class DataArray[T <: Data](gen: T, numRead: Int, numWrite: Int, numEntries: Int)
   for (i <- 0 until numEntries) {
     val wCnt = VecInit(io.write.indices.map(j => dataModule.io.wen(j) && dataModule.io.wvec(j)(i)))
     XSError(RegNext(PopCount(wCnt) > 1.U), s"why not OH $i?")
-    when(PopCount(wCnt) > 1.U) {
-      XSDebug("ERROR: IssueQueue DataArray write overlap!\n")
-    }
+    XSDebug(PopCount(wCnt) > 1.U, "ERROR: IssueQueue DataArray write overlap!\n")
   }
 }
diff --git a/src/main/scala/xiangshan/backend/rename/Snapshot.scala b/src/main/scala/xiangshan/backend/rename/Snapshot.scala
index c4fdbdd218..7c4358114f 100644
--- a/src/main/scala/xiangshan/backend/rename/Snapshot.scala
+++ b/src/main/scala/xiangshan/backend/rename/Snapshot.scala
@@ -58,8 +58,9 @@ class SnapshotGenerator[T <: Data](dataType: T)(implicit p: Parameters) extends
   when(!io.redirect && io.deq) {
     snptValids(snptDeqPtr.value) := false.B
     snptDeqPtr := snptDeqPtr + 1.U
-    XSError(isEmpty(snptEnqPtr, snptDeqPtr), "snapshots should not be empty when dequeue!\n")
   }
+  XSError(!io.redirect && io.deq && isEmpty(snptEnqPtr, snptDeqPtr), "snapshots should not be empty when dequeue!\n")
+
   snptValids.zip(io.flushVec).foreach { case (valid, flush) =>
     when(flush) { valid := false.B }
   }
diff --git a/src/main/scala/xiangshan/backend/rob/Rob.scala b/src/main/scala/xiangshan/backend/rob/Rob.scala
index 4ef7252587..7a53dc0c6e 100644
--- a/src/main/scala/xiangshan/backend/rob/Rob.scala
+++ b/src/main/scala/xiangshan/backend/rob/Rob.scala
@@ -242,7 +242,7 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP
       connectCommitEntry(robDeqGroup(i), robBanksRdataNextLineUpdate(i))
     }
   }
-  
+
   // In each robentry, the ftqIdx and ftqOffset belong to the first instruction that was compressed,
   // That is Necessary when exceptions happen.
   // Update the ftqOffset to correctly notify the frontend which instructions have been committed.
@@ -517,8 +517,9 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP
    * Writeback (from execution units)
    */
   for (wb <- exuWBs) {
+    val wbIdx = wb.bits.robIdx.value
+    val debug_Uop = debug_microOp(wbIdx)
     when(wb.valid) {
-      val wbIdx = wb.bits.robIdx.value
       debug_exuData(wbIdx) := wb.bits.data(0)
       debug_exuDebug(wbIdx) := wb.bits.debug
       debug_microOp(wbIdx).debugInfo.enqRsTime := wb.bits.debugInfo.enqRsTime
@@ -529,14 +530,12 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP
       // debug for lqidx and sqidx
       debug_microOp(wbIdx).lqIdx := wb.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr))
       debug_microOp(wbIdx).sqIdx := wb.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr))
-
-      val debug_Uop = debug_microOp(wbIdx)
-      XSInfo(true.B,
-        p"writebacked pc 0x${Hexadecimal(debug_Uop.pc)} wen ${debug_Uop.rfWen} " +
-          p"data 0x${Hexadecimal(wb.bits.data(0))} ldst ${debug_Uop.ldest} pdst ${debug_Uop.pdest} " +
-          p"skip ${wb.bits.debug.isSkipDiff} robIdx: ${wb.bits.robIdx}\n"
-      )
     }
+    XSInfo(wb.valid,
+      p"writebacked pc 0x${Hexadecimal(debug_Uop.pc)} wen ${debug_Uop.rfWen} " +
+        p"data 0x${Hexadecimal(wb.bits.data(0))} ldst ${debug_Uop.ldest} pdst ${debug_Uop.pdest} " +
+        p"skip ${wb.bits.debug.isSkipDiff} robIdx: ${wb.bits.robIdx}\n"
+    )
   }
 
   val writebackNum = PopCount(exuWBs.map(_.valid))
@@ -769,11 +768,11 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP
     io.commits.robIdx(i) := deqPtrVec(i)
 
     io.commits.walkValid(i) := shouldWalkVec(i)
-    when(state === s_walk) {
-      when(io.commits.isWalk && state === s_walk && shouldWalkVec(i)) {
-        XSError(!walk_v(i), s"The walking entry($i) should be valid\n")
-      }
-    }
+    XSError(
+      state === s_walk &&
+      io.commits.isWalk && state === s_walk && shouldWalkVec(i) &&
+      !walk_v(i),
+      s"The walking entry($i) should be valid\n")
 
     XSInfo(io.commits.isCommit && io.commits.commitValid(i),
       "retired pc %x wen %d ldest %d pdest %x data %x fflags: %b vxsat: %b\n",
diff --git a/src/main/scala/xiangshan/backend/rob/RobDeqPtrWrapper.scala b/src/main/scala/xiangshan/backend/rob/RobDeqPtrWrapper.scala
index 095e854f92..dbd89e521b 100644
--- a/src/main/scala/xiangshan/backend/rob/RobDeqPtrWrapper.scala
+++ b/src/main/scala/xiangshan/backend/rob/RobDeqPtrWrapper.scala
@@ -99,9 +99,8 @@ class NewRobDeqPtrWrapper(implicit p: Parameters) extends XSModule with HasCircu
   io.commitCnt := commitCnt
   io.commitEn := io.state === 0.U && !redirectOutValid && !io.blockCommit
 
-  when (io.state === 0.U) {
-    XSInfo(io.state === 0.U && commitCnt > 0.U, "retired %d insts\n", commitCnt)
-  }
+  XSInfo(io.state === 0.U && commitCnt > 0.U, "retired %d insts\n", commitCnt)
+
   if(backendParams.debugEn){
     dontTouch(commitDeqPtrVec)
     dontTouch(commitDeqPtrAll)
diff --git a/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala b/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
index 7e406f190a..916230dd1f 100644
--- a/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
+++ b/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
@@ -371,8 +371,8 @@ class DCacheWordReq(implicit p: Parameters) extends DCacheBundle
   val lqIdx = new LqPtr
 
   val debug_robIdx = UInt(log2Ceil(RobSize).W)
-  def dump() = {
-    XSDebug("DCacheWordReq: cmd: %x vaddr: %x data: %x mask: %x id: %d\n",
+  def dump(cond: Bool) = {
+    XSDebug(cond, "DCacheWordReq: cmd: %x vaddr: %x data: %x mask: %x id: %d\n",
       cmd, vaddr, data, mask, id)
   }
 }
@@ -386,8 +386,8 @@ class DCacheLineReq(implicit p: Parameters) extends DCacheBundle
   val data   = UInt((cfg.blockBytes * 8).W)
   val mask   = UInt(cfg.blockBytes.W)
   val id     = UInt(reqIdWidth.W)
-  def dump() = {
-    XSDebug("DCacheLineReq: cmd: %x addr: %x data: %x mask: %x id: %d\n",
+  def dump(cond: Bool) = {
+    XSDebug(cond, "DCacheLineReq: cmd: %x addr: %x data: %x mask: %x id: %d\n",
       cmd, addr, data, mask, id)
   }
   def idx: UInt = get_idx(vaddr)
@@ -438,8 +438,8 @@ class BaseDCacheWordResp(implicit p: Parameters) extends DCacheBundle
   val mshr_id = UInt(log2Up(cfg.nMissEntries).W)
 
   val debug_robIdx = UInt(log2Ceil(RobSize).W)
-  def dump() = {
-    XSDebug("DCacheWordResp: data: %x id: %d miss: %b replay: %b\n",
+  def dump(cond: Bool) = {
+    XSDebug(cond, "DCacheWordResp: data: %x id: %d miss: %b replay: %b\n",
       data, id, miss, replay)
   }
 }
@@ -476,8 +476,8 @@ class DCacheLineResp(implicit p: Parameters) extends DCacheBundle
   // cache req nacked, replay it later
   val replay = Bool()
   val id     = UInt(reqIdWidth.W)
-  def dump() = {
-    XSDebug("DCacheLineResp: data: %x id: %d miss: %b replay: %b\n",
+  def dump(cond: Bool) = {
+    XSDebug(cond, "DCacheLineResp: data: %x id: %d miss: %b replay: %b\n",
       data, id, miss, replay)
   }
 }
@@ -491,8 +491,8 @@ class Refill(implicit p: Parameters) extends DCacheBundle
   val data_raw = UInt((cfg.blockBytes * 8).W)
   val hasdata = Bool()
   val refill_done = Bool()
-  def dump() = {
-    XSDebug("Refill: addr: %x data: %x\n", addr, data)
+  def dump(cond: Bool) = {
+    XSDebug(cond, "Refill: addr: %x data: %x\n", addr, data)
   }
   val id     = UInt(log2Up(cfg.nMissEntries).W)
 }
@@ -500,8 +500,8 @@ class Refill(implicit p: Parameters) extends DCacheBundle
 class Release(implicit p: Parameters) extends DCacheBundle
 {
   val paddr  = UInt(PAddrBits.W)
-  def dump() = {
-    XSDebug("Release: paddr: %x\n", paddr(PAddrBits-1, DCacheTagOffset))
+  def dump(cond: Bool) = {
+    XSDebug(cond, "Release: paddr: %x\n", paddr(PAddrBits-1, DCacheTagOffset))
   }
 }
 
@@ -526,8 +526,8 @@ class UncacheWordReq(implicit p: Parameters) extends DCacheBundle
   val isFirstIssue = Bool()
   val replayCarry = new ReplayCarry(nWays)
 
-  def dump() = {
-    XSDebug("UncacheWordReq: cmd: %x addr: %x data: %x mask: %x id: %d\n",
+  def dump(cond: Bool) = {
+    XSDebug(cond, "UncacheWordReq: cmd: %x addr: %x data: %x mask: %x id: %d\n",
       cmd, addr, data, mask, id)
   }
 }
@@ -548,8 +548,8 @@ class UncacheWordResp(implicit p: Parameters) extends DCacheBundle
   val mshr_id = UInt(log2Up(cfg.nMissEntries).W)  // FIXME: why uncacheWordResp is not merged to baseDcacheResp
 
   val debug_robIdx = UInt(log2Ceil(RobSize).W)
-  def dump() = {
-    XSDebug("UncacheWordResp: data: %x id: %d miss: %b replay: %b, tag_error: %b, error: %b\n",
+  def dump(cond: Bool) = {
+    XSDebug(cond, "UncacheWordResp: data: %x id: %d miss: %b replay: %b, tag_error: %b, error: %b\n",
       data, id, miss, replay, tag_error, error)
   }
 }
diff --git a/src/main/scala/xiangshan/cache/dcache/Uncache.scala b/src/main/scala/xiangshan/cache/dcache/Uncache.scala
index 0bc016b34f..cadc3e6a12 100644
--- a/src/main/scala/xiangshan/cache/dcache/Uncache.scala
+++ b/src/main/scala/xiangshan/cache/dcache/Uncache.scala
@@ -482,14 +482,11 @@ class UncacheImp(outer: Uncache)extends LazyModuleImp(outer)
     req.bits.cmd, req.bits.addr, req.bits.data, req.bits.mask)
   XSDebug(resp.fire, "data: %x\n", req.bits.data)
   // print tilelink messages
-  when(mem_acquire.valid){
-    XSDebug("mem_acquire valid, ready=%d ", mem_acquire.ready)
-    mem_acquire.bits.dump
-  }
-  when (mem_grant.fire) {
-    XSDebug("mem_grant fire ")
-    mem_grant.bits.dump
-  }
+  XSDebug(mem_acquire.valid, "mem_acquire valid, ready=%d ", mem_acquire.ready)
+  mem_acquire.bits.dump(mem_acquire.valid)
+
+  XSDebug(mem_grant.fire, "mem_grant fire ")
+  mem_grant.bits.dump(mem_grant.fire)
 
   /* Performance Counters */
   XSPerfAccumulate("uncache_mmio_store", io.lsq.req.fire && isStore(io.lsq.req.bits.cmd) && !io.lsq.req.bits.nc)
diff --git a/src/main/scala/xiangshan/cache/dcache/data/AbstractDataArray.scala b/src/main/scala/xiangshan/cache/dcache/data/AbstractDataArray.scala
index a7d5e4da04..36c6e91733 100644
--- a/src/main/scala/xiangshan/cache/dcache/data/AbstractDataArray.scala
+++ b/src/main/scala/xiangshan/cache/dcache/data/AbstractDataArray.scala
@@ -53,22 +53,21 @@ abstract class AbstractDataArray(implicit p: Parameters) extends DCacheModule {
 
   def dumpRead = {
     (0 until 3) map { w =>
-      when(io.read(w).valid) {
-        XSDebug(s"DataArray Read channel: $w valid way_en: %x addr: %x\n",
-          io.read(w).bits.way_en, io.read(w).bits.addr)
-      }
+      XSDebug(io.read(w).valid,
+        s"DataArray Read channel: $w valid way_en: %x addr: %x\n",
+        io.read(w).bits.way_en, io.read(w).bits.addr)
     }
   }
 
   def dumpWrite = {
-    when(io.write.valid) {
-      XSDebug(s"DataArray Write valid way_en: %x addr: %x\n",
-        io.write.bits.way_en, io.write.bits.addr)
+    XSDebug(io.write.valid,
+      s"DataArray Write valid way_en: %x addr: %x\n",
+      io.write.bits.way_en, io.write.bits.addr)
 
-      (0 until blockRows) map { r =>
-        XSDebug(s"cycle: $r data: %x wmask: %x\n",
-          io.write.bits.data(r), io.write.bits.wmask(r))
-      }
+    (0 until blockRows) map { r =>
+      XSDebug(io.write.valid,
+        s"cycle: $r data: %x wmask: %x\n",
+        io.write.bits.data(r), io.write.bits.wmask(r))
     }
   }
 
@@ -83,9 +82,7 @@ abstract class AbstractDataArray(implicit p: Parameters) extends DCacheModule {
 
   def dumpNack = {
     (0 until 3) map { w =>
-      when(io.nacks(w)) {
-        XSDebug(s"DataArray NACK channel: $w\n")
-      }
+      XSDebug(io.nacks(w), s"DataArray NACK channel: $w\n")
     }
   }
 
diff --git a/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala b/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
index 46b3ba6aef..8b870e2f6e 100644
--- a/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
+++ b/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
@@ -131,25 +131,23 @@ class DataSRAM(bankIdx: Int, wayIdx: Int)(implicit p: Parameters) extends DCache
   XSPerfAccumulate("part_data_read_counter", data_sram.io.r.req.valid)
 
   def dump_r() = {
-    when(RegNext(io.r.en)) {
-      XSDebug("bank read set %x bank %x way %x data %x\n",
-        RegEnable(io.r.addr, io.r.en),
-        bankIdx.U,
-        wayIdx.U,
-        io.r.data
-      )
-    }
+    XSDebug(RegNext(io.r.en),
+      "bank read set %x bank %x way %x data %x\n",
+      RegEnable(io.r.addr, io.r.en),
+      bankIdx.U,
+      wayIdx.U,
+      io.r.data
+    )
   }
 
   def dump_w() = {
-    when(io.w.en) {
-      XSDebug("bank write set %x bank %x way %x data %x\n",
-        io.w.addr,
-        bankIdx.U,
-        wayIdx.U,
-        io.w.data
-      )
-    }
+    XSDebug(io.w.en,
+      "bank write set %x bank %x way %x data %x\n",
+      io.w.addr,
+      bankIdx.U,
+      wayIdx.U,
+      io.w.data
+    )
   }
 
   def dump() = {
@@ -205,22 +203,20 @@ class DataSRAMBank(index: Int)(implicit p: Parameters) extends DCacheModule {
   io.r.data := data_bank.map(_.io.r.resp.data(0))
 
   def dump_r() = {
-    when(RegNext(io.r.en)) {
-      XSDebug("bank read addr %x data %x\n",
-        RegEnable(io.r.addr, io.r.en),
-        io.r.data.asUInt
-      )
-    }
+    XSDebug(RegNext(io.r.en),
+      "bank read addr %x data %x\n",
+      RegEnable(io.r.addr, io.r.en),
+      io.r.data.asUInt
+    )
   }
 
   def dump_w() = {
-    when(io.w.en) {
-      XSDebug("bank write addr %x way_en %x data %x\n",
-        io.w.addr,
-        io.w.way_en,
-        io.w.data
-      )
-    }
+    XSDebug(io.w.en,
+      "bank write addr %x way_en %x data %x\n",
+      io.w.addr,
+      io.w.way_en,
+      io.w.data
+    )
   }
 
   def dump() = {
@@ -293,26 +289,24 @@ abstract class AbstractBankedDataArray(implicit p: Parameters) extends DCacheMod
 
   def dumpRead = {
     (0 until LoadPipelineWidth) map { w =>
-      when(io.read(w).valid) {
-        XSDebug(s"DataArray Read channel: $w valid way_en: %x addr: %x\n",
-          io.read(w).bits.way_en, io.read(w).bits.addr)
-      }
-    }
-    when(io.readline.valid) {
-      XSDebug(s"DataArray Read Line, valid way_en: %x addr: %x rmask %x\n",
-        io.readline.bits.way_en, io.readline.bits.addr, io.readline.bits.rmask)
+      XSDebug(io.read(w).valid,
+        s"DataArray Read channel: $w valid way_en: %x addr: %x\n",
+        io.read(w).bits.way_en, io.read(w).bits.addr)
     }
+    XSDebug(io.readline.valid,
+      s"DataArray Read Line, valid way_en: %x addr: %x rmask %x\n",
+      io.readline.bits.way_en, io.readline.bits.addr, io.readline.bits.rmask)
   }
 
   def dumpWrite = {
-    when(io.write.valid) {
-      XSDebug(s"DataArray Write valid way_en: %x addr: %x\n",
-        io.write.bits.way_en, io.write.bits.addr)
-
-      (0 until DCacheBanks) map { r =>
-        XSDebug(s"cycle: $r data: %x wmask: %x\n",
-          io.write.bits.data(r), io.write.bits.wmask(r))
-      }
+    XSDebug(io.write.valid,
+      s"DataArray Write valid way_en: %x addr: %x\n",
+      io.write.bits.way_en, io.write.bits.addr)
+
+    (0 until DCacheBanks) map { r =>
+      XSDebug(io.write.valid,
+        s"cycle: $r data: %x wmask: %x\n",
+        io.write.bits.data(r), io.write.bits.wmask(r))
     }
   }
 
diff --git a/src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala b/src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala
index 964e76caa5..f7b329b24b 100644
--- a/src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala
+++ b/src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala
@@ -128,9 +128,8 @@ class DuplicatedDataArray(implicit p: Parameters) extends AbstractDataArray {
         data = getECCFromRow(io.write.bits.data(r)),
         waymask = io.write.bits.way_en
       )
-      when(ecc_array.io.w.req.valid) {
-        XSDebug(p"write in ecc sram ${j.U} row ${r.U}: setIdx=${Hexadecimal(ecc_array.io.w.req.bits.setIdx)} ecc(0)=${Hexadecimal(getECCFromRow(io.write.bits.data(r))(0))} ecc(1)=${Hexadecimal(getECCFromRow(io.write.bits.data(r))(1))} waymask=${Hexadecimal(io.write.bits.way_en)}\n")
-      }
+      XSDebug(ecc_array.io.w.req.valid,
+        p"write in ecc sram ${j.U} row ${r.U}: setIdx=${Hexadecimal(ecc_array.io.w.req.bits.setIdx)} ecc(0)=${Hexadecimal(getECCFromRow(io.write.bits.data(r))(0))} ecc(1)=${Hexadecimal(getECCFromRow(io.write.bits.data(r))(1))} waymask=${Hexadecimal(io.write.bits.way_en)}\n")
       ecc_array.io.r.req.valid := io.read(j).valid && rmask(r)
       ecc_array.io.r.req.bits.apply(setIdx = raddr)
 
diff --git a/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala b/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
index 07e4b89b93..58b52a44f2 100644
--- a/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
+++ b/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
@@ -485,9 +485,7 @@ class LoadPipe(id: Int)(implicit p: Parameters) extends DCacheModule with HasPer
   io.lsu.resp.bits := resp.bits
   assert(RegNext(!(resp.valid && !io.lsu.resp.ready)), "lsu should be ready in s2")
 
-  when (resp.valid) {
-    resp.bits.dump()
-  }
+  resp.bits.dump(resp.valid)
 
   io.lsu.debug_s1_hit_way := s1_tag_match_way_dup_dc
   io.lsu.s1_disable_fast_wakeup := io.disable_ld_fast_wakeup
@@ -567,16 +565,12 @@ class LoadPipe(id: Int)(implicit p: Parameters) extends DCacheModule with HasPer
   // Debug logging functions
   def dump_pipeline_reqs(pipeline_stage_name: String, valid: Bool,
     req: DCacheWordReq ) = {
-      when (valid) {
-        XSDebug(s"$pipeline_stage_name: ")
-        req.dump()
-      }
+      XSDebug(valid, s"$pipeline_stage_name: ")
+      req.dump(valid)
   }
 
   def dump_pipeline_valids(pipeline_stage_name: String, signal_name: String, valid: Bool) = {
-    when (valid) {
-      XSDebug(s"$pipeline_stage_name $signal_name\n")
-    }
+    XSDebug(valid, s"$pipeline_stage_name $signal_name\n")
   }
 
   val load_trace = Wire(new LoadPfDbBundle)
diff --git a/src/main/scala/xiangshan/cache/dcache/mainpipe/AtomicsReplayUnit.scala b/src/main/scala/xiangshan/cache/dcache/mainpipe/AtomicsReplayUnit.scala
index 557182767c..86dedd2136 100644
--- a/src/main/scala/xiangshan/cache/dcache/mainpipe/AtomicsReplayUnit.scala
+++ b/src/main/scala/xiangshan/cache/dcache/mainpipe/AtomicsReplayUnit.scala
@@ -49,9 +49,7 @@ class AtomicsReplayEntry(implicit p: Parameters) extends DCacheModule
   io.block_addr.bits  := req.addr
 
 
-  when (state =/= s_invalid) {
-    XSDebug("AtomicsReplayEntry: state: %d block_addr: %x\n", state, io.block_addr.bits)
-  }
+  XSDebug(state =/= s_invalid, "AtomicsReplayEntry: state: %d block_addr: %x\n", state, io.block_addr.bits)
 
   // --------------------------------------------
   // s_invalid: receive requests
diff --git a/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala b/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
index 35a84dec19..331451aadc 100644
--- a/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
+++ b/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
@@ -636,7 +636,6 @@ class MainPipe(implicit p: Parameters) extends DCacheModule with HasPerfEvents w
       when (s3_sc_fail) {
         debug_sc_fail_addr := s3_req_addr_dup(2)
         debug_sc_fail_cnt  := 1.U
-        XSWarn(s3_sc_fail === 100.U, p"L1DCache failed too many SCs in a row 0x${Hexadecimal(debug_sc_fail_addr)}, check if sth went wrong\n")
       }
     }
   }
diff --git a/src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala b/src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala
index 70a456ac0d..c09ca5781a 100644
--- a/src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala
+++ b/src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala
@@ -35,8 +35,8 @@ class ProbeReq(implicit p: Parameters) extends DCacheBundle
   // probe queue entry ID
   val id = UInt(log2Up(cfg.nProbeEntries).W)
 
-  def dump() = {
-    XSDebug("ProbeReq source: %d opcode: %d addr: %x param: %d\n",
+  def dump(cond: Bool) = {
+    XSDebug(cond, "ProbeReq source: %d opcode: %d addr: %x param: %d\n",
       source, opcode, addr, param)
   }
 }
@@ -72,13 +72,9 @@ class ProbeEntry(implicit p: Parameters) extends DCacheModule {
   io.block_addr.valid := state =/= s_invalid
   io.block_addr.bits  := req.addr
 
-  when (state =/= s_invalid) {
-    XSDebug("state: %d\n", state)
-  }
+  XSDebug(state =/= s_invalid, "state: %d\n", state)
 
-  when (state =/= s_invalid) {
-    XSDebug("ProbeEntry: state: %d block_addr: %x\n", state, io.block_addr.bits)
-  }
+  XSDebug(state =/= s_invalid, "ProbeEntry: state: %d block_addr: %x\n", state, io.block_addr.bits)
 
   when (state === s_invalid) {
     io.req.ready := true.B
@@ -219,18 +215,12 @@ class ProbeQueue(edge: TLEdgeOut)(implicit p: Parameters) extends DCacheModule w
   }
 
   // debug output
-  when (io.mem_probe.fire) {
-    XSDebug("mem_probe: ")
-    io.mem_probe.bits.dump
-  }
+  XSDebug(io.mem_probe.fire, "mem_probe: ")
+  io.mem_probe.bits.dump(io.mem_probe.fire)
 
-//  when (io.pipe_req.fire) {
-//    io.pipe_req.bits.dump()
-//  }
+// io.pipe_req.bits.dump(io.pipe_req.fire)
 
-  when (io.lrsc_locked_block.valid) {
-    XSDebug("lrsc_locked_block: %x\n", io.lrsc_locked_block.bits)
-  }
+  XSDebug(io.lrsc_locked_block.valid, "lrsc_locked_block: %x\n", io.lrsc_locked_block.bits)
   XSPerfAccumulate("ProbeL1DCache", io.mem_probe.fire)
 
   val perfValidCount = RegNext(PopCount(entries.map(e => e.io.block_addr.valid)))
diff --git a/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala b/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala
index f573b42711..c30dc95646 100644
--- a/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala
+++ b/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala
@@ -38,8 +38,8 @@ class WritebackReqCtrl(implicit p: Parameters) extends DCacheBundle {
 class WritebackReqWodata(implicit p: Parameters) extends WritebackReqCtrl {
   val addr = UInt(PAddrBits.W)
 
-  def dump() = {
-    XSDebug("WritebackReq addr: %x param: %d voluntary: %b hasData: %b\n",
+  def dump(cond: Bool) = {
+    XSDebug(cond, "WritebackReq addr: %x param: %d voluntary: %b hasData: %b\n",
       addr, param, voluntary, hasData)
   }
 }
@@ -51,8 +51,8 @@ class WritebackReqData(implicit p: Parameters) extends DCacheBundle {
 class WritebackReq(implicit p: Parameters) extends WritebackReqWodata {
   val data = UInt((cfg.blockBytes * 8).W)
 
-  override def dump() = {
-    XSDebug("WritebackReq addr: %x param: %d voluntary: %b hasData: %b data: %x\n",
+  override def dump(cond: Bool) = {
+    XSDebug(cond, "WritebackReq addr: %x param: %d voluntary: %b hasData: %b data: %x\n",
       addr, param, voluntary, hasData, data)
   }
 
@@ -187,10 +187,7 @@ class WritebackEntry(edge: TLEdgeOut)(implicit p: Parameters) extends DCacheModu
   s_data_override := true.B // data_override takes only 1 cycle
   //s_data_merge := true.B // data_merge takes only 1 cycle
 
-  when (state =/= s_invalid) {
-    XSDebug("WritebackEntry: %d state: %d block_addr: %x\n", io.id, state, io.block_addr.bits)
-  }
-
+  XSDebug(state =/= s_invalid, "WritebackEntry: %d state: %d block_addr: %x\n", io.id, state, io.block_addr.bits)
 
   // --------------------------------------------------------------------------------
   // s_invalid: receive requests
@@ -205,7 +202,7 @@ class WritebackEntry(edge: TLEdgeOut)(implicit p: Parameters) extends DCacheModu
     paddr_dup_0 := io.req.bits.addr
     paddr_dup_1 := io.req.bits.addr
     paddr_dup_2 := io.req.bits.addr
-  
+
     remain_set := Mux(io.req.bits.hasData, ~0.U(refillCycles.W), 1.U(refillCycles.W))
     state      := s_release_req
     state_dup_0 := s_release_req
@@ -386,21 +383,12 @@ class WritebackQueue(edge: TLEdgeOut)(implicit p: Parameters) extends DCacheModu
   // sanity check
   // print all input/output requests for debug purpose
   // print req
-  when(io.req.fire) {
-    io.req.bits.dump()
-  }
-
-  when(io.mem_release.fire){
-    io.mem_grant.bits.dump
-  }
+  io.req.bits.dump(io.req.fire)
 
-  // when (io.miss_req.valid) {
-  //   XSDebug("miss_req: addr: %x\n", io.miss_req.bits)
-  // }
+  io.mem_grant.bits.dump(io.mem_release.fire)
 
-  // when (io.block_miss_req) {
-  //   XSDebug("block_miss_req\n")
-  // }
+  // XSDebug(io.miss_req.valid, "miss_req: addr: %x\n", io.miss_req.bits)
+  // XSDebug(io.block_miss_req, "block_miss_req\n")
 
   // performance counters
   XSPerfAccumulate("wb_req", io.req.fire)
@@ -413,6 +401,6 @@ class WritebackQueue(edge: TLEdgeOut)(implicit p: Parameters) extends DCacheModu
     ("dcache_wbq_3_4_valid", (perfValidCount > (cfg.nReleaseEntries.U/2.U)) & (perfValidCount <= (cfg.nReleaseEntries.U*3.U/4.U))),
     ("dcache_wbq_4_4_valid", (perfValidCount > (cfg.nReleaseEntries.U*3.U/4.U))),
   )
-  generatePerfEvent()  
+  generatePerfEvent()
 
 }
\ No newline at end of file
diff --git a/src/main/scala/xiangshan/cache/dcache/meta/LegacyMetaArray.scala b/src/main/scala/xiangshan/cache/dcache/meta/LegacyMetaArray.scala
index 04105810a4..211c85280e 100644
--- a/src/main/scala/xiangshan/cache/dcache/meta/LegacyMetaArray.scala
+++ b/src/main/scala/xiangshan/cache/dcache/meta/LegacyMetaArray.scala
@@ -97,17 +97,15 @@ class L1MetadataArray(onReset: () => L1Metadata)(implicit p: Parameters) extends
   io.read.ready := !wen
 
   def dumpRead = {
-    when(io.read.fire) {
-      XSDebug("MetaArray Read: idx: %d way_en: %x tag: %x\n",
-        io.read.bits.idx, io.read.bits.way_en, io.read.bits.tag)
-    }
+    XSDebug(io.read.fire,
+      "MetaArray Read: idx: %d way_en: %x tag: %x\n",
+      io.read.bits.idx, io.read.bits.way_en, io.read.bits.tag)
   }
 
   def dumpWrite = {
-    when(io.write.fire) {
-      XSDebug("MetaArray Write: idx: %d way_en: %x tag: %x new_tag: %x new_coh: %x\n",
-        io.write.bits.idx, io.write.bits.way_en, io.write.bits.tag, io.write.bits.data.tag, io.write.bits.data.coh.state)
-    }
+    XSDebug(io.write.fire,
+      "MetaArray Write: idx: %d way_en: %x tag: %x new_tag: %x new_coh: %x\n",
+      io.write.bits.idx, io.write.bits.way_en, io.write.bits.tag, io.write.bits.data.tag, io.write.bits.data.coh.state)
   }
 
   // def dumpResp() = {
@@ -153,18 +151,16 @@ class DuplicatedMetaArray(numReadPorts: Int)(implicit p: Parameters) extends DCa
 
   def dumpRead = {
     (0 until numReadPorts) map { w =>
-      when(io.read(w).fire) {
-        XSDebug(s"MetaArray Read channel: $w idx: %d way_en: %x tag: %x\n",
-          io.read(w).bits.idx, io.read(w).bits.way_en, io.read(w).bits.tag)
-      }
+      XSDebug(io.read(w).fire,
+        s"MetaArray Read channel: $w idx: %d way_en: %x tag: %x\n",
+        io.read(w).bits.idx, io.read(w).bits.way_en, io.read(w).bits.tag)
     }
   }
 
   def dumpWrite = {
-    when(io.write.fire) {
-      XSDebug("MetaArray Write: idx: %d way_en: %x tag: %x new_tag: %x new_coh: %x\n",
-        io.write.bits.idx, io.write.bits.way_en, io.write.bits.tag, io.write.bits.data.tag, io.write.bits.data.coh.state)
-    }
+    XSDebug(io.write.fire,
+      "MetaArray Write: idx: %d way_en: %x tag: %x new_tag: %x new_coh: %x\n",
+      io.write.bits.idx, io.write.bits.way_en, io.write.bits.tag, io.write.bits.data.tag, io.write.bits.data.coh.state)
   }
 
   // def dumpResp() = {
diff --git a/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala b/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
index df8e08366a..b3ca0b29f6 100644
--- a/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
+++ b/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
@@ -685,16 +685,15 @@ class PtwCache()(implicit p: Parameters) extends XSModule with HasPtwConst with
 
   // TODO: handle sfenceLatch outsize
   if (EnableSv48) {
-    when (
+    val l3Refill =
       !flush_dup(2) &&
       refill.levelOH.l3.get &&
       !memPte(2).isLeaf() &&
       memPte(2).canRefill(refill.level_dup(2), refill.req_info_dup(2).s2xlate, pbmte, io.csr_dup(2).vsatp.mode)
-    ) {
-      val refillIdx = replaceWrapper(l3v.get, ptwl3replace.get.way)
-      refillIdx.suggestName(s"Ptwl3RefillIdx")
-      val rfOH = UIntToOH(refillIdx)
-      l3.get(refillIdx).refill(
+    val l3RefillIdx = replaceWrapper(l3v.get, ptwl3replace.get.way).suggestName(s"l3_refillIdx")
+    val l3RfOH = UIntToOH(l3RefillIdx).asUInt.suggestName(s"l3_rfOH")
+    when (l3Refill) {
+      l3.get(l3RefillIdx).refill(
         refill.req_info_dup(2).vpn,
         Mux(refill.req_info_dup(2).s2xlate =/= noS2xlate, io.csr_dup(2).vsatp.asid, io.csr_dup(2).satp.asid),
         io.csr_dup(2).hgatp.vmid,
@@ -702,34 +701,31 @@ class PtwCache()(implicit p: Parameters) extends XSModule with HasPtwConst with
         3.U,
         refill_prefetch_dup(2)
       )
-      ptwl2replace.access(refillIdx)
-      l3v.get := l3v.get | rfOH
-      l3g.get := (l3g.get & ~rfOH) | Mux(memPte(2).perm.g, rfOH, 0.U)
-      l3h.get(refillIdx) := refill_h(2)
+      ptwl2replace.access(l3RefillIdx)
+      l3v.get := l3v.get | l3RfOH
+      l3g.get := (l3g.get & ~l3RfOH) | Mux(memPte(2).perm.g, l3RfOH, 0.U)
+      l3h.get(l3RefillIdx) := refill_h(2)
 
       for (i <- 0 until l2tlbParams.l3Size) {
-        l3RefillPerf.get(i) := i.U === refillIdx
+        l3RefillPerf.get(i) := i.U === l3RefillIdx
       }
-
-      XSDebug(p"[l3 refill] refillIdx:${refillIdx} refillEntry:${l3.get(refillIdx).genPtwEntry(refill.req_info_dup(2).vpn, Mux(refill.req_info_dup(2).s2xlate =/= noS2xlate, io.csr_dup(2).vsatp.asid, io.csr_dup(2).satp.asid), memSelData(2), 0.U, prefetch = refill_prefetch_dup(2))}\n")
-      XSDebug(p"[l3 refill] l3v:${Binary(l3v.get)}->${Binary(l3v.get | rfOH)} l3g:${Binary(l3g.get)}->${Binary((l3g.get & ~rfOH) | Mux(memPte(2).perm.g, rfOH, 0.U))}\n")
-
-      refillIdx.suggestName(s"l3_refillIdx")
-      rfOH.suggestName(s"l3_rfOH")
     }
+    XSDebug(l3Refill, p"[l3 refill] refillIdx:${l3RefillIdx} refillEntry:${l3.get(l3RefillIdx).genPtwEntry(refill.req_info_dup(2).vpn, Mux(refill.req_info_dup(2).s2xlate =/= noS2xlate, io.csr_dup(2).vsatp.asid, io.csr_dup(2).satp.asid), memSelData(2), 0.U, prefetch = refill_prefetch_dup(2))}\n")
+    XSDebug(l3Refill, p"[l3 refill] l3v:${Binary(l3v.get)}->${Binary(l3v.get | l3RfOH)} l3g:${Binary(l3g.get)}->${Binary((l3g.get & ~l3RfOH) | Mux(memPte(2).perm.g, l3RfOH, 0.U))}\n")
   }
 
   // L2 refill
-  when (
+  val l2Refill =
     !flush_dup(2) &&
     refill.levelOH.l2 &&
     !memPte(2).isLeaf() &&
     memPte(2).canRefill(refill.level_dup(2), refill.req_info_dup(2).s2xlate, pbmte, io.csr_dup(2).vsatp.mode)
+  val l2RefillIdx = replaceWrapper(l2v, ptwl2replace.way).suggestName(s"l2_refillIdx")
+  val l2RfOH = UIntToOH(l2RefillIdx).asUInt.suggestName(s"l2_rfOH")
+  when (
+    l2Refill
   ) {
-    val refillIdx = replaceWrapper(l2v, ptwl2replace.way)
-    refillIdx.suggestName(s"Ptwl2RefillIdx")
-    val rfOH = UIntToOH(refillIdx)
-    l2(refillIdx).refill(
+    l2(l2RefillIdx).refill(
       refill.req_info_dup(2).vpn,
       Mux(refill.req_info_dup(2).s2xlate =/= noS2xlate, io.csr_dup(2).vsatp.asid, io.csr_dup(2).satp.asid),
       io.csr_dup(2).hgatp.vmid,
@@ -737,121 +733,107 @@ class PtwCache()(implicit p: Parameters) extends XSModule with HasPtwConst with
       2.U,
       refill_prefetch_dup(2)
     )
-    ptwl2replace.access(refillIdx)
-    l2v := l2v | rfOH
-    l2g := (l2g & ~rfOH) | Mux(memPte(2).perm.g, rfOH, 0.U)
-    l2h(refillIdx) := refill_h(2)
+    ptwl2replace.access(l2RefillIdx)
+    l2v := l2v | l2RfOH
+    l2g := (l2g & ~l2RfOH) | Mux(memPte(2).perm.g, l2RfOH, 0.U)
+    l2h(l2RefillIdx) := refill_h(2)
 
     for (i <- 0 until l2tlbParams.l2Size) {
-      l2RefillPerf(i) := i.U === refillIdx
+      l2RefillPerf(i) := i.U === l2RefillIdx
     }
-
-    XSDebug(p"[l2 refill] refillIdx:${refillIdx} refillEntry:${l2(refillIdx).genPtwEntry(refill.req_info_dup(2).vpn, Mux(refill.req_info_dup(2).s2xlate =/= noS2xlate, io.csr_dup(2).vsatp.asid, io.csr_dup(2).satp.asid), memSelData(2), 0.U, prefetch = refill_prefetch_dup(2))}\n")
-    XSDebug(p"[l2 refill] l2v:${Binary(l2v)}->${Binary(l2v | rfOH)} l2g:${Binary(l2g)}->${Binary((l2g & ~rfOH) | Mux(memPte(2).perm.g, rfOH, 0.U))}\n")
-
-    refillIdx.suggestName(s"l2_refillIdx")
-    rfOH.suggestName(s"l2_rfOH")
   }
+  XSDebug(l2Refill, p"[l2 refill] refillIdx:${l2RefillIdx} refillEntry:${l2(l2RefillIdx).genPtwEntry(refill.req_info_dup(2).vpn, Mux(refill.req_info_dup(2).s2xlate =/= noS2xlate, io.csr_dup(2).vsatp.asid, io.csr_dup(2).satp.asid), memSelData(2), 0.U, prefetch = refill_prefetch_dup(2))}\n")
+  XSDebug(l2Refill, p"[l2 refill] l2v:${Binary(l2v)}->${Binary(l2v | l2RfOH)} l2g:${Binary(l2g)}->${Binary((l2g & ~l2RfOH) | Mux(memPte(2).perm.g, l2RfOH, 0.U))}\n")
 
   // L1 refill
-  when (!flush_dup(1) && refill.levelOH.l1) {
-    val refillIdx = genPtwL1SetIdx(refill.req_info_dup(1).vpn)
-    val victimWay = replaceWrapper(getl1vSet(refill.req_info_dup(1).vpn), ptwl1replace.way(refillIdx))
-    val victimWayOH = UIntToOH(victimWay)
-    val rfvOH = UIntToOH(Cat(refillIdx, victimWay))
-    val wdata = Wire(l1EntryType)
-    wdata.gen(
-      vpn = refill.req_info_dup(1).vpn,
-      asid = Mux(refill.req_info_dup(1).s2xlate =/= noS2xlate, io.csr_dup(1).vsatp.asid, io.csr_dup(1).satp.asid),
-      vmid = io.csr_dup(1).hgatp.vmid,
-      data = memRdata,
-      levelUInt = 1.U,
-      refill_prefetch_dup(1),
-      refill.req_info_dup(1).s2xlate,
-      pbmte,
-      io.csr_dup(1).vsatp.mode
-    )
+  val l1Refill = !flush_dup(1) && refill.levelOH.l1
+  val l1RefillIdx = genPtwL1SetIdx(refill.req_info_dup(1).vpn).suggestName(s"l1_refillIdx")
+  val l1VictimWay = replaceWrapper(getl1vSet(refill.req_info_dup(1).vpn), ptwl1replace.way(l1RefillIdx)).suggestName(s"l1_victimWay")
+  val l1VictimWayOH = UIntToOH(l1VictimWay).suggestName(s"l1_victimWayOH")
+  val l1RfvOH = UIntToOH(Cat(l1RefillIdx, l1VictimWay)).asUInt.suggestName(s"l1_rfvOH")
+  val l1Wdata = Wire(l1EntryType)
+  l1Wdata.gen(
+    vpn = refill.req_info_dup(1).vpn,
+    asid = Mux(refill.req_info_dup(1).s2xlate =/= noS2xlate, io.csr_dup(1).vsatp.asid, io.csr_dup(1).satp.asid),
+    vmid = io.csr_dup(1).hgatp.vmid,
+    data = memRdata,
+    levelUInt = 1.U,
+    refill_prefetch_dup(1),
+    refill.req_info_dup(1).s2xlate,
+    pbmte,
+    io.csr_dup(1).vsatp.mode
+  )
+  when (l1Refill) {
     l1.io.w.apply(
       valid = true.B,
-      setIdx = refillIdx,
-      data = wdata,
-      waymask = victimWayOH
+      setIdx = l1RefillIdx,
+      data = l1Wdata,
+      waymask = l1VictimWayOH
     )
-    ptwl1replace.access(refillIdx, victimWay)
-    l1v := l1v | rfvOH
-    l1g := l1g & ~rfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, rfvOH, 0.U)
-    l1h(refillIdx)(victimWay) := refill_h(1)
+    ptwl1replace.access(l1RefillIdx, l1VictimWay)
+    l1v := l1v | l1RfvOH
+    l1g := l1g & ~l1RfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, l1RfvOH, 0.U)
+    l1h(l1RefillIdx)(l1VictimWay) := refill_h(1)
 
     for (i <- 0 until l2tlbParams.l1nWays) {
-      l1RefillPerf(i) := i.U === victimWay
+      l1RefillPerf(i) := i.U === l1VictimWay
     }
-
-    XSDebug(p"[l1 refill] refillIdx:0x${Hexadecimal(refillIdx)} victimWay:${victimWay} victimWayOH:${Binary(victimWayOH)} rfvOH(in UInt):${Cat(refillIdx, victimWay)}\n")
-    XSDebug(p"[l1 refill] refilldata:0x${wdata}\n")
-    XSDebug(p"[l1 refill] l1v:${Binary(l1v)} -> ${Binary(l1v | rfvOH)}\n")
-    XSDebug(p"[l1 refill] l1g:${Binary(l1g)} -> ${Binary(l1g & ~rfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, rfvOH, 0.U))}\n")
-
-    refillIdx.suggestName(s"l1_refillIdx")
-    victimWay.suggestName(s"l1_victimWay")
-    victimWayOH.suggestName(s"l1_victimWayOH")
-    rfvOH.suggestName(s"l1_rfvOH")
   }
+  XSDebug(l1Refill, p"[l1 refill] refillIdx:0x${Hexadecimal(l1RefillIdx)} victimWay:${l1VictimWay} victimWayOH:${Binary(l1VictimWayOH)} rfvOH(in UInt):${Cat(l1RefillIdx, l1VictimWay)}\n")
+  XSDebug(l1Refill, p"[l1 refill] refilldata:0x${l1Wdata}\n")
+  XSDebug(l1Refill, p"[l1 refill] l1v:${Binary(l1v)} -> ${Binary(l1v | l1RfvOH)}\n")
+  XSDebug(l1Refill, p"[l1 refill] l1g:${Binary(l1g)} -> ${Binary(l1g & ~l1RfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, l1RfvOH, 0.U))}\n")
 
   // L0 refill
-  when (!flush_dup(0) && refill.levelOH.l0) {
-    val refillIdx = genPtwL0SetIdx(refill.req_info_dup(0).vpn)
-    val victimWay = replaceWrapper(getl0vSet(refill.req_info_dup(0).vpn), ptwl0replace.way(refillIdx))
-    val victimWayOH = UIntToOH(victimWay)
-    val rfvOH = UIntToOH(Cat(refillIdx, victimWay))
-    val wdata = Wire(l0EntryType)
-    wdata.gen(
-      vpn =  refill.req_info_dup(0).vpn,
-      asid = Mux(refill.req_info_dup(0).s2xlate =/= noS2xlate, io.csr_dup(0).vsatp.asid, io.csr_dup(0).satp.asid),
-      vmid = io.csr_dup(0).hgatp.vmid,
-      data = memRdata,
-      levelUInt = 0.U,
-      refill_prefetch_dup(0),
-      refill.req_info_dup(0).s2xlate,
-      pbmte,
-      io.csr_dup(0).vsatp.mode
-    )
+  val l0Refill = !flush_dup(0) && refill.levelOH.l0
+  val l0RefillIdx = genPtwL0SetIdx(refill.req_info_dup(0).vpn).suggestName(s"l0_refillIdx")
+  val l0VictimWay = replaceWrapper(getl0vSet(refill.req_info_dup(0).vpn), ptwl0replace.way(l0RefillIdx)).suggestName(s"l0_victimWay")
+  val l0VictimWayOH = UIntToOH(l0VictimWay).asUInt.suggestName(s"l0_victimWayOH")
+  val l0RfvOH = UIntToOH(Cat(l0RefillIdx, l0VictimWay)).suggestName(s"l0_rfvOH")
+  val l0Wdata = Wire(l0EntryType)
+  l0Wdata.gen(
+    vpn = refill.req_info_dup(0).vpn,
+    asid = Mux(refill.req_info_dup(0).s2xlate =/= noS2xlate, io.csr_dup(0).vsatp.asid, io.csr_dup(0).satp.asid),
+    vmid = io.csr_dup(0).hgatp.vmid,
+    data = memRdata,
+    levelUInt = 0.U,
+    refill_prefetch_dup(0),
+    refill.req_info_dup(0).s2xlate,
+    pbmte,
+    io.csr_dup(0).vsatp.mode
+  )
+  when (l0Refill) {
     l0.io.w.apply(
       valid = true.B,
-      setIdx = refillIdx,
-      data = wdata,
-      waymask = victimWayOH
+      setIdx = l0RefillIdx,
+      data = l0Wdata,
+      waymask = l0VictimWayOH
     )
-    ptwl0replace.access(refillIdx, victimWay)
-    l0v := l0v | rfvOH
-    l0g := l0g & ~rfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, rfvOH, 0.U)
-    l0h(refillIdx)(victimWay) := refill_h(0)
+    ptwl0replace.access(l0RefillIdx, l0VictimWay)
+    l0v := l0v | l0RfvOH
+    l0g := l0g & ~l0RfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, l0RfvOH, 0.U)
+    l0h(l0RefillIdx)(l0VictimWay) := refill_h(0)
 
     for (i <- 0 until l2tlbParams.l0nWays) {
-      l0RefillPerf(i) := i.U === victimWay
+      l0RefillPerf(i) := i.U === l0VictimWay
     }
-
-    XSDebug(p"[l0 refill] refillIdx:0x${Hexadecimal(refillIdx)} victimWay:${victimWay} victimWayOH:${Binary(victimWayOH)} rfvOH(in UInt):${Cat(refillIdx, victimWay)}\n")
-    XSDebug(p"[l0 refill] refilldata:0x${wdata}\n")
-    XSDebug(p"[l0 refill] l0v:${Binary(l0v)} -> ${Binary(l0v | rfvOH)}\n")
-    XSDebug(p"[l0 refill] l0g:${Binary(l0g)} -> ${Binary(l0g & ~rfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, rfvOH, 0.U))}\n")
-
-    refillIdx.suggestName(s"l0_refillIdx")
-    victimWay.suggestName(s"l0_victimWay")
-    victimWayOH.suggestName(s"l0_victimWayOH")
-    rfvOH.suggestName(s"l0_rfvOH")
   }
+  XSDebug(l0Refill, p"[l0 refill] refillIdx:0x${Hexadecimal(l0RefillIdx)} victimWay:${l0VictimWay} victimWayOH:${Binary(l0VictimWayOH)} rfvOH(in UInt):${Cat(l0RefillIdx, l0VictimWay)}\n")
+  XSDebug(l0Refill, p"[l0 refill] refilldata:0x${l0Wdata}\n")
+  XSDebug(l0Refill, p"[l0 refill] l0v:${Binary(l0v)} -> ${Binary(l0v | l0RfvOH)}\n")
+  XSDebug(l0Refill, p"[l0 refill] l0g:${Binary(l0g)} -> ${Binary(l0g & ~l0RfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, l0RfvOH, 0.U))}\n")
 
 
   // misc entries: super & invalid
-  when (
+  val spRefill =
     !flush_dup(0) &&
     refill.levelOH.sp &&
     ((memPte(0).isLeaf() && memPte(0).canRefill(refill.level_dup(0), refill.req_info_dup(0).s2xlate, pbmte, io.csr_dup(0).vsatp.mode)) ||
     memPte(0).onlyPf(refill.level_dup(0), refill.req_info_dup(0).s2xlate, pbmte))
-  ) {
-    val refillIdx = spreplace.way// LFSR64()(log2Up(l2tlbParams.spSize)-1,0) // TODO: may be LRU
-    val rfOH = UIntToOH(refillIdx)
-    sp(refillIdx).refill(
+  val spRefillIdx = spreplace.way.suggestName(s"sp_refillIdx") // LFSR64()(log2Up(l2tlbParams.spSize)-1,0) // TODO: may be LRU
+  val spRfOH = UIntToOH(spRefillIdx).asUInt.suggestName(s"sp_rfOH")
+  when (spRefill) {
+    sp(spRefillIdx).refill(
       refill.req_info_dup(0).vpn,
       Mux(refill.req_info_dup(0).s2xlate =/= noS2xlate, io.csr_dup(0).vsatp.asid, io.csr_dup(0).satp.asid),
       io.csr_dup(0).hgatp.vmid,
@@ -860,21 +842,17 @@ class PtwCache()(implicit p: Parameters) extends XSModule with HasPtwConst with
       refill_prefetch_dup(0),
       !memPte(0).onlyPf(refill.level_dup(0), refill.req_info_dup(0).s2xlate, pbmte)
     )
-    spreplace.access(refillIdx)
-    spv := spv | rfOH
-    spg := spg & ~rfOH | Mux(memPte(0).perm.g, rfOH, 0.U)
-    sph(refillIdx) := refill_h(0)
+    spreplace.access(spRefillIdx)
+    spv := spv | spRfOH
+    spg := spg & ~spRfOH | Mux(memPte(0).perm.g, spRfOH, 0.U)
+    sph(spRefillIdx) := refill_h(0)
 
     for (i <- 0 until l2tlbParams.spSize) {
-      spRefillPerf(i) := i.U === refillIdx
+      spRefillPerf(i) := i.U === spRefillIdx
     }
-
-    XSDebug(p"[sp refill] refillIdx:${refillIdx} refillEntry:${sp(refillIdx).genPtwEntry(refill.req_info_dup(0).vpn, Mux(refill.req_info_dup(0).s2xlate =/= noS2xlate, io.csr_dup(0).vsatp.asid, io.csr_dup(0).satp.asid), memSelData(0), refill.level_dup(0), refill_prefetch_dup(0))}\n")
-    XSDebug(p"[sp refill] spv:${Binary(spv)}->${Binary(spv | rfOH)} spg:${Binary(spg)}->${Binary(spg & ~rfOH | Mux(memPte(0).perm.g, rfOH, 0.U))}\n")
-
-    refillIdx.suggestName(s"sp_refillIdx")
-    rfOH.suggestName(s"sp_rfOH")
   }
+  XSDebug(spRefill, p"[sp refill] refillIdx:${spRefillIdx} refillEntry:${sp(spRefillIdx).genPtwEntry(refill.req_info_dup(0).vpn, Mux(refill.req_info_dup(0).s2xlate =/= noS2xlate, io.csr_dup(0).vsatp.asid, io.csr_dup(0).satp.asid), memSelData(0), refill.level_dup(0), refill_prefetch_dup(0))}\n")
+  XSDebug(spRefill, p"[sp refill] spv:${Binary(spv)}->${Binary(spv | spRfOH)} spg:${Binary(spg)}->${Binary(spg & ~spRfOH | Mux(memPte(0).perm.g, spRfOH, 0.U))}\n")
 
   val l1eccFlush = resp_res.l1.ecc && stageResp_valid_1cycle_dup(0) // RegNext(l1eccError, init = false.B)
   val l0eccFlush = resp_res.l0.ecc && stageResp_valid_1cycle_dup(1) // RegNext(l0eccError, init = false.B)
diff --git a/src/main/scala/xiangshan/cache/prefetch/BestOffsetPrefetch.scala b/src/main/scala/xiangshan/cache/prefetch/BestOffsetPrefetch.scala
index 1d08884b92..56d39d1c0e 100644
--- a/src/main/scala/xiangshan/cache/prefetch/BestOffsetPrefetch.scala
+++ b/src/main/scala/xiangshan/cache/prefetch/BestOffsetPrefetch.scala
@@ -257,37 +257,35 @@ class OffsetScoreTable(implicit p: Parameters) extends PrefetchModule {
   // The current learning phase finishes at the end of a round when:
   // (1) one of the score equals SCOREMAX, or
   // (2) the number of rounds equals ROUNDMAX.
+  val oldEntry = st(io.test.resp.bits.ptr)
+  val oldScore = oldEntry.score
+  val newScore = oldScore + 1.U
+  val offset = oldEntry.offset
   when (state === s_learn) {
     when (io.test.req.fire) {
       val roundFinish = ptr === (scores - 1).U
       ptr := Mux(roundFinish, 0.U, ptr + 1.U)
       round := Mux(roundFinish, round + 1.U, round)
-
-      XSDebug(p"test offset ${testOffset} req fire\n")
     }
 
     // (2) the number of rounds equals ROUNDMAX.
     when (round >= roundMax.U) {
       state := s_idle
-      XSDebug(p"round reaches roundMax(${roundMax.U})\n")
     }
 
     when (io.test.resp.fire && io.test.resp.bits.hit) {
-      val oldEntry = st(io.test.resp.bits.ptr)
-      val oldScore = oldEntry.score
-      val newScore = oldScore + 1.U
-      val offset = oldEntry.offset
       st(io.test.resp.bits.ptr).score := newScore
       bestOffset := winner((new ScoreTableEntry).apply(offset, newScore), bestOffset)
       // (1) one of the score equals SCOREMAX
       when (newScore >= scoreMax.U) {
         state := s_idle
-        XSDebug(p"newScore reaches scoreMax(${scoreMax.U})\n")
       }
-
-      XSDebug(p"test offset ${offset} resp fire and hit. score ${oldScore} -> ${newScore}\n")
     }
   }
+  XSDebug(state === s_learn && io.test.req.fire, p"test offset ${testOffset} req fire\n")
+  XSDebug(state === s_learn && round >= roundMax.U, p"round reaches roundMax(${roundMax.U})\n")
+  XSDebug(state === s_learn && io.test.resp.fire && io.test.resp.bits.hit && newScore >= scoreMax.U, p"newScore reaches scoreMax(${scoreMax.U})\n")
+  XSDebug(state === s_learn && io.test.resp.fire && io.test.resp.bits.hit, p"test offset ${offset} resp fire and hit. score ${oldScore} -> ${newScore}\n")
 
   io.req.ready := true.B
   io.prefetchOffset := prefetchOffset
@@ -338,9 +336,9 @@ class BestOffsetPrefetchEntry(implicit p: Parameters) extends PrefetchModule wit
       req.addr := nextAddr
       req.write := io.pft.train.bits.write
       baseAddr := getBlockAddr(io.pft.train.bits.addr)
-      XSDebug(crossPage, p"prefetch addr 0x${nextAddr} cross page, ignore this!\n")
     }
   }
+  XSDebug(state === s_idle && io.pft.train.valid && crossPage, p"prefetch addr 0x${nextAddr} cross page, ignore this!\n")
 
   when (state === s_req) {
     when (io.pft.req.fire) {
diff --git a/src/main/scala/xiangshan/cache/prefetch/StreamPrefetch.scala b/src/main/scala/xiangshan/cache/prefetch/StreamPrefetch.scala
index 8b05f43980..435a3642f6 100644
--- a/src/main/scala/xiangshan/cache/prefetch/StreamPrefetch.scala
+++ b/src/main/scala/xiangshan/cache/prefetch/StreamPrefetch.scala
@@ -139,9 +139,10 @@ class StreamBuffer(implicit p: Parameters) extends PrefetchModule with HasTlbCon
 
   // dequeue
   val hitIdx = io.update.bits.hitIdx
-  when (io.update.valid && !empty && (isPrefetching(hitIdx) || valid(hitIdx))) {
-    val headBeforehitIdx = head <= hitIdx && (hitIdx < tail || tail <= head)
-    val hitIdxBeforeHead = hitIdx < tail && tail <= head
+  val dequeue = io.update.valid && !empty && (isPrefetching(hitIdx) || valid(hitIdx))
+  val headBeforehitIdx = head <= hitIdx && (hitIdx < tail || tail <= head)
+  val hitIdxBeforeHead = hitIdx < tail && tail <= head
+  when (dequeue) {
     when (headBeforehitIdx) {
       (0 until streamSize).foreach(i => deqLater(i) := Mux(i.U >= head && i.U <= hitIdx, true.B, deqLater(i)))
     }
@@ -149,9 +150,8 @@ class StreamBuffer(implicit p: Parameters) extends PrefetchModule with HasTlbCon
     when (hitIdxBeforeHead) {
       (0 until streamSize).foreach(i => deqLater(i) := Mux(i.U >= head || i.U <= hitIdx, true.B, deqLater(i)))
     }
-
-    XSDebug(io.update.valid && !empty && (isPrefetching(hitIdx) || valid(hitIdx)), p"hitIdx=${hitIdx} headBeforehitIdx=${headBeforehitIdx} hitIdxBeforeHead=${hitIdxBeforeHead}\n")
   }
+  XSDebug(dequeue, p"hitIdx=${hitIdx} headBeforehitIdx=${headBeforehitIdx} hitIdxBeforeHead=${hitIdxBeforeHead}\n")
 
   val deqValid = WireInit(VecInit(Seq.fill(streamSize)(false.B)))
   deqValid(head) := deqLater(head) && !isPrefetching(head)
@@ -180,17 +180,17 @@ class StreamBuffer(implicit p: Parameters) extends PrefetchModule with HasTlbCon
 
   // enqueue
   val nextAddrCrossPage = getPageNum(baseReq.bits.addr) =/= getPageNum(nextReq.addr)
-  when (!full && baseReq.valid && !needRealloc) {
+  val enqueue = !full && baseReq.valid && !needRealloc
+  when (enqueue) {
     when (!nextAddrCrossPage) {
       state(tail) := s_req
       tail := tail + 1.U
       buf(tail) := nextReq
       nextReq.addr := nextReq.addr + blockBytes.U
-      XSDebug(p"enqueue 0x${nextReq.addr}\n")
-    }.otherwise {
-      XSDebug(p"addr 0x${nextReq.addr} could not enqueue for crossing pages\n")
     }
   }
+  XSDebug(enqueue && !nextAddrCrossPage, p"enqueue 0x${nextReq.addr}\n")
+  XSDebug(enqueue && nextAddrCrossPage, p"addr 0x${nextReq.addr} could not enqueue for crossing pages\n")
 
   val reqs = Wire(Vec(streamSize, Decoupled(new StreamPrefetchReq)))
   val resps = Wire(Vec(streamSize, Decoupled(new StreamPrefetchResp)))
diff --git a/src/main/scala/xiangshan/frontend/Frontend.scala b/src/main/scala/xiangshan/frontend/Frontend.scala
index e28b44c50a..0728a0a371 100644
--- a/src/main/scala/xiangshan/frontend/Frontend.scala
+++ b/src/main/scala/xiangshan/frontend/Frontend.scala
@@ -221,13 +221,19 @@ class FrontendInlinedImp(outer: FrontendInlined) extends LazyModuleImp(outer)
       when(ibuffer.io.out(i).fire && ibuffer.io.out(i).bits.pd.isBr) {
         when(ibuffer.io.out(i + 1).fire) {
           // not last br, check now
-          XSError(checkTargetIdx(i) =/= checkTargetIdx(i + 1), "not-taken br should have same ftqPtr\n")
+          // call XSError below
         }.otherwise {
           // last br, record its info
           prevNotTakenValid  := true.B
           prevNotTakenFtqIdx := checkTargetIdx(i)
         }
       }
+      XSError(
+        ibuffer.io.out(i).fire && ibuffer.io.out(i).bits.pd.isBr &&
+          ibuffer.io.out(i + 1).fire &&
+          checkTargetIdx(i) =/= checkTargetIdx(i + 1),
+        "not-taken br should have same ftqPtr\n"
+      )
     }
     when(ibuffer.io.out(DecodeWidth - 1).fire && ibuffer.io.out(DecodeWidth - 1).bits.pd.isBr) {
       // last instr is a br, record its info
@@ -235,9 +241,14 @@ class FrontendInlinedImp(outer: FrontendInlined) extends LazyModuleImp(outer)
       prevNotTakenFtqIdx := checkTargetIdx(DecodeWidth - 1)
     }
     when(prevNotTakenValid && ibuffer.io.out(0).fire) {
-      XSError(prevNotTakenFtqIdx =/= checkTargetIdx(0), "not-taken br should have same ftqPtr\n")
       prevNotTakenValid := false.B
     }
+    XSError(
+      prevNotTakenValid && ibuffer.io.out(0).fire &&
+        prevNotTakenFtqIdx =/= checkTargetIdx(0),
+      "not-taken br should have same ftqPtr\n"
+    )
+
     when(needFlush) {
       prevNotTakenValid := false.B
     }
@@ -252,13 +263,18 @@ class FrontendInlinedImp(outer: FrontendInlined) extends LazyModuleImp(outer)
       when(ibuffer.io.out(i).fire && ibuffer.io.out(i).bits.pd.isBr && ibuffer.io.out(i).bits.pred_taken) {
         when(ibuffer.io.out(i + 1).fire) {
           // not last br, check now
-          XSError(checkTargetIdx(i) + 1.U =/= checkTargetIdx(i + 1), "taken br should have consecutive ftqPtr\n")
         }.otherwise {
           // last br, record its info
           prevTakenValid  := true.B
           prevTakenFtqIdx := checkTargetIdx(i)
         }
       }
+      XSError(
+        ibuffer.io.out(i).fire && ibuffer.io.out(i).bits.pd.isBr && ibuffer.io.out(i).bits.pred_taken &&
+          ibuffer.io.out(i + 1).fire &&
+          checkTargetIdx(i) + 1.U =/= checkTargetIdx(i + 1),
+        "taken br should have consecutive ftqPtr\n"
+      )
     }
     when(ibuffer.io.out(DecodeWidth - 1).fire && ibuffer.io.out(DecodeWidth - 1).bits.pd.isBr && ibuffer.io.out(
       DecodeWidth - 1
@@ -268,9 +284,13 @@ class FrontendInlinedImp(outer: FrontendInlined) extends LazyModuleImp(outer)
       prevTakenFtqIdx := checkTargetIdx(DecodeWidth - 1)
     }
     when(prevTakenValid && ibuffer.io.out(0).fire) {
-      XSError(prevTakenFtqIdx + 1.U =/= checkTargetIdx(0), "taken br should have consecutive ftqPtr\n")
       prevTakenValid := false.B
     }
+    XSError(
+      prevTakenValid && ibuffer.io.out(0).fire &&
+        prevTakenFtqIdx + 1.U =/= checkTargetIdx(0),
+      "taken br should have consecutive ftqPtr\n"
+    )
     when(needFlush) {
       prevTakenValid := false.B
     }
@@ -283,19 +303,20 @@ class FrontendInlinedImp(outer: FrontendInlined) extends LazyModuleImp(outer)
 
     for (i <- 0 until DecodeWidth - 1) {
       when(ibuffer.io.out(i).fire && ibuffer.io.out(i).bits.pd.isBr && !ibuffer.io.out(i).bits.pred_taken) {
-        when(ibuffer.io.out(i + 1).fire) {
-          XSError(
-            ibuffer.io.out(i).bits.pc + Mux(ibuffer.io.out(i).bits.pd.isRVC, 2.U, 4.U) =/= ibuffer.io.out(
-              i + 1
-            ).bits.pc,
-            "not-taken br should have consecutive pc\n"
-          )
-        }.otherwise {
+        when(ibuffer.io.out(i + 1).fire) {}.otherwise {
           prevNotTakenValid := true.B
           prevIsRVC         := ibuffer.io.out(i).bits.pd.isRVC
           prevNotTakenPC    := ibuffer.io.out(i).bits.pc
         }
       }
+      XSError(
+        ibuffer.io.out(i).fire && ibuffer.io.out(i).bits.pd.isBr && !ibuffer.io.out(i).bits.pred_taken &&
+          ibuffer.io.out(i + 1).fire &&
+          ibuffer.io.out(i).bits.pc + Mux(ibuffer.io.out(i).bits.pd.isRVC, 2.U, 4.U) =/= ibuffer.io.out(
+            i + 1
+          ).bits.pc,
+        "not-taken br should have consecutive pc\n"
+      )
     }
     when(ibuffer.io.out(DecodeWidth - 1).fire && ibuffer.io.out(DecodeWidth - 1).bits.pd.isBr && !ibuffer.io.out(
       DecodeWidth - 1
@@ -305,12 +326,13 @@ class FrontendInlinedImp(outer: FrontendInlined) extends LazyModuleImp(outer)
       prevNotTakenPC    := ibuffer.io.out(DecodeWidth - 1).bits.pc
     }
     when(prevNotTakenValid && ibuffer.io.out(0).fire) {
-      XSError(
-        prevNotTakenPC + Mux(prevIsRVC, 2.U, 4.U) =/= ibuffer.io.out(0).bits.pc,
-        "not-taken br should have same pc\n"
-      )
       prevNotTakenValid := false.B
     }
+    XSError(
+      prevNotTakenValid && ibuffer.io.out(0).fire &&
+        prevNotTakenPC + Mux(prevIsRVC, 2.U, 4.U) =/= ibuffer.io.out(0).bits.pc,
+      "not-taken br should have same pc\n"
+    )
     when(needFlush) {
       prevNotTakenValid := false.B
     }
@@ -324,13 +346,17 @@ class FrontendInlinedImp(outer: FrontendInlined) extends LazyModuleImp(outer)
 
     for (i <- 0 until DecodeWidth - 1) {
       when(ibuffer.io.out(i).fire && !ibuffer.io.out(i).bits.pd.notCFI && ibuffer.io.out(i).bits.pred_taken) {
-        when(ibuffer.io.out(i + 1).fire) {
-          XSError(checkTarget(i) =/= ibuffer.io.out(i + 1).bits.pc, "taken instr should follow target pc\n")
-        }.otherwise {
+        when(ibuffer.io.out(i + 1).fire) {}.otherwise {
           prevTakenValid  := true.B
           prevTakenFtqIdx := checkTargetIdx(i)
         }
       }
+      XSError(
+        ibuffer.io.out(i).fire && !ibuffer.io.out(i).bits.pd.notCFI && ibuffer.io.out(i).bits.pred_taken &&
+          ibuffer.io.out(i + 1).fire &&
+          checkTarget(i) =/= ibuffer.io.out(i + 1).bits.pc,
+        "taken instr should follow target pc\n"
+      )
     }
     when(ibuffer.io.out(DecodeWidth - 1).fire && !ibuffer.io.out(DecodeWidth - 1).bits.pd.notCFI && ibuffer.io.out(
       DecodeWidth - 1
@@ -339,9 +365,13 @@ class FrontendInlinedImp(outer: FrontendInlined) extends LazyModuleImp(outer)
       prevTakenFtqIdx := checkTargetIdx(DecodeWidth - 1)
     }
     when(prevTakenValid && ibuffer.io.out(0).fire) {
-      XSError(prevTakenTarget =/= ibuffer.io.out(0).bits.pc, "taken instr should follow target pc\n")
       prevTakenValid := false.B
     }
+    XSError(
+      prevTakenValid && ibuffer.io.out(0).fire &&
+        prevTakenTarget =/= ibuffer.io.out(0).bits.pc,
+      "taken instr should follow target pc\n"
+    )
     when(needFlush) {
       prevTakenValid := false.B
     }
diff --git a/src/main/scala/xiangshan/frontend/IBuffer.scala b/src/main/scala/xiangshan/frontend/IBuffer.scala
index 87f50addf7..c33c3bfb24 100644
--- a/src/main/scala/xiangshan/frontend/IBuffer.scala
+++ b/src/main/scala/xiangshan/frontend/IBuffer.scala
@@ -441,12 +441,10 @@ class IBuffer(implicit p: Parameters) extends XSModule with HasCircularQueuePtrH
 
   XSDebug(io.flush, "IBuffer Flushed\n")
 
-  when(io.in.fire) {
-    XSDebug("Enque:\n")
-    XSDebug(p"MASK=${Binary(io.in.bits.valid)}\n")
-    for (i <- 0 until PredictWidth) {
-      XSDebug(p"PC=${Hexadecimal(io.in.bits.pc(i))} ${Hexadecimal(io.in.bits.instrs(i))}\n")
-    }
+  XSDebug(io.in.fire, "Enque:\n")
+  XSDebug(io.in.fire, p"MASK=${Binary(io.in.bits.valid)}\n")
+  for (i <- 0 until PredictWidth) {
+    XSDebug(io.in.fire, p"PC=${Hexadecimal(io.in.bits.pc(i))} ${Hexadecimal(io.in.bits.instrs(i))}\n")
   }
 
   for (i <- 0 until DecodeWidth) {
diff --git a/src/main/scala/xiangshan/frontend/IFU.scala b/src/main/scala/xiangshan/frontend/IFU.scala
index 7175703af7..3ed597f227 100644
--- a/src/main/scala/xiangshan/frontend/IFU.scala
+++ b/src/main/scala/xiangshan/frontend/IFU.scala
@@ -1121,15 +1121,14 @@ class NewIFU(implicit p: Parameters) extends XSModule
   XSPerfAccumulate("predecode_flush_notCFIFault", checkNotCFIFault)
   XSPerfAccumulate("predecode_flush_incalidTakenFault", checkInvalidTaken)
 
-  when(checkRetFault) {
-    XSDebug(
-      "startAddr:%x  nextstartAddr:%x  taken:%d    takenIdx:%d\n",
-      wb_ftq_req.startAddr,
-      wb_ftq_req.nextStartAddr,
-      wb_ftq_req.ftqOffset.valid,
-      wb_ftq_req.ftqOffset.bits
-    )
-  }
+  XSDebug(
+    checkRetFault,
+    "startAddr:%x  nextstartAddr:%x  taken:%d    takenIdx:%d\n",
+    wb_ftq_req.startAddr,
+    wb_ftq_req.nextStartAddr,
+    wb_ftq_req.ftqOffset.valid,
+    wb_ftq_req.ftqOffset.bits
+  )
 
   /** performance counter */
   val f3_perf_info = RegEnable(f2_perf_info, f2_fire)
diff --git a/src/main/scala/xiangshan/frontend/ITTAGE.scala b/src/main/scala/xiangshan/frontend/ITTAGE.scala
index 1c89eabaaa..ec1a11e442 100644
--- a/src/main/scala/xiangshan/frontend/ITTAGE.scala
+++ b/src/main/scala/xiangshan/frontend/ITTAGE.scala
@@ -685,15 +685,12 @@ class ITTage(implicit p: Parameters) extends BaseITTage {
   metaAltProviderTargetOffset.pointer     := rTable.io.update_pointer(1)
   metaAltProviderTargetOffset.usePCRegion := !rTable.io.update_hit(1)
 
+  val provider    = updateMeta.provider.bits
+  val altProvider = updateMeta.altProvider.bits
+  val usedAltpred = updateMeta.altProvider.valid && updateMeta.providerCtr === 0.U
   when(updateValid) {
     when(updateMeta.provider.valid) {
-      val provider = updateMeta.provider.bits
-      XSDebug(true.B, p"update provider $provider, pred cycle ${updateMeta.pred_cycle.getOrElse(0.U)}\n")
-      val altProvider = updateMeta.altProvider.bits
-      val usedAltpred = updateMeta.altProvider.valid && updateMeta.providerCtr === 0.U
       when(usedAltpred && updateMisPred) { // update altpred if used as pred
-        XSDebug(true.B, p"update altprovider $altProvider, pred cycle ${updateMeta.pred_cycle.getOrElse(0.U)}\n")
-
         updateMask(altProvider)            := true.B
         updateUMask(altProvider)           := false.B
         updateCorrect(altProvider)         := false.B
@@ -718,16 +715,23 @@ class ITTage(implicit p: Parameters) extends BaseITTage {
       updateOldTargetOffset(provider) := metaProviderTargetOffset
     }
   }
+  XSDebug(
+    updateValid && updateMeta.provider.valid,
+    p"update provider $provider, pred cycle ${updateMeta.pred_cycle.getOrElse(0.U)}\n"
+  )
+  XSDebug(
+    updateValid && updateMeta.provider.valid && usedAltpred && updateMisPred,
+    p"update altprovider $altProvider, pred cycle ${updateMeta.pred_cycle.getOrElse(0.U)}\n"
+  )
 
   // if mispredicted and not the case that
   // provider offered correct target but used altpred due to unconfident
   val providerCorrect = updateMeta.provider.valid && updateMeta.providerTarget === updateRealTarget
   val providerUnconf  = updateMeta.providerCtr === 0.U
+  val allocate        = updateMeta.allocate
   when(updateValid && updateMisPred && !(providerCorrect && providerUnconf)) {
-    val allocate = updateMeta.allocate
     tickCtr := satUpdate(tickCtr, TickWidth, !allocate.valid)
     when(allocate.valid) {
-      XSDebug(true.B, p"allocate new table entry, pred cycle ${updateMeta.pred_cycle.getOrElse(0.U)}\n")
       updateMask(allocate.bits)         := true.B
       updateCorrect(allocate.bits)      := true.B // useless for alloc
       updateAlloc(allocate.bits)        := true.B
@@ -736,6 +740,10 @@ class ITTage(implicit p: Parameters) extends BaseITTage {
       updateTargetOffset(allocate.bits) := updateRealTargetOffset
     }
   }
+  XSDebug(
+    updateValid && updateMisPred && !(providerCorrect && providerUnconf) && allocate.valid,
+    p"allocate new table entry, pred cycle ${updateMeta.pred_cycle.getOrElse(0.U)}\n"
+  )
 
   when(tickCtr === ((1 << TickWidth) - 1).U) {
     tickCtr      := 0.U
diff --git a/src/main/scala/xiangshan/frontend/NewFtq.scala b/src/main/scala/xiangshan/frontend/NewFtq.scala
index c140a51ae1..13bc31c3f0 100644
--- a/src/main/scala/xiangshan/frontend/NewFtq.scala
+++ b/src/main/scala/xiangshan/frontend/NewFtq.scala
@@ -942,13 +942,13 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
       entry_hit_status(ifuPtr.value) := h_false_hit
       // XSError(true.B, "FTB false hit by fallThroughError, startAddr: %x, fallTHru: %x\n", io.toIfu.req.bits.startAddr, io.toIfu.req.bits.nextStartAddr)
     }
-    XSDebug(
-      true.B,
-      "fallThruError! start:%x, fallThru:%x\n",
-      io.toIfu.req.bits.startAddr,
-      io.toIfu.req.bits.nextStartAddr
-    )
   }
+  XSDebug(
+    toIfuPcBundle.fallThruError && entry_hit_status(ifuPtr.value) === h_hit,
+    "fallThruError! start:%x, fallThru:%x\n",
+    io.toIfu.req.bits.startAddr,
+    io.toIfu.req.bits.nextStartAddr
+  )
 
   XSPerfAccumulate(
     f"fall_through_error_to_ifu",
@@ -1030,10 +1030,13 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
         (pred_ftb_entry.isRet && !(jmp_pd.valid && jmp_pd.isRet)))
 
     has_false_hit := br_false_hit || jal_false_hit || hit_pd_mispred_reg
-    XSDebug(has_false_hit, "FTB false hit by br or jal or hit_pd, startAddr: %x\n", pdWb.bits.pc(0))
-
     // assert(!has_false_hit)
   }
+  XSDebug(
+    RegNext(hit_pd_valid) && has_false_hit,
+    "FTB false hit by br or jal or hit_pd, startAddr: %x\n",
+    pdWb.bits.pc(0)
+  )
 
   when(has_false_hit) {
     entry_hit_status(wb_idx_reg) := h_false_hit
@@ -1445,9 +1448,10 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
       bpu_ftb_update_stall := 0.U
     }
     is(3.U) {
-      XSError(true.B, "bpu_ftb_update_stall should be 0, 1 or 2")
+      // XSError below
     }
   }
+  XSError(bpu_ftb_update_stall === 3.U, "bpu_ftb_update_stall should be 0, 1 or 2")
 
   // TODO: remove this
   XSError(do_commit && diff_commit_target =/= commit_target, "\ncommit target should be the same as update target\n")
diff --git a/src/main/scala/xiangshan/frontend/SC.scala b/src/main/scala/xiangshan/frontend/SC.scala
index 8e043c5225..a319606a9a 100644
--- a/src/main/scala/xiangshan/frontend/SC.scala
+++ b/src/main/scala/xiangshan/frontend/SC.scala
@@ -346,22 +346,25 @@ trait HasSC extends HasSCParameter with HasPerfEvents { this: Tage =>
       scMeta.scPreds(w) := RegEnable(s2_scPreds(s2_chooseBit), io.s2_fire(3))
       scMeta.ctrs(w)    := RegEnable(s2_scCtrs, io.s2_fire(3))
 
+      val pred     = s2_scPreds(s2_chooseBit)
+      val debug_pc = Cat(debug_pc_s2, w.U, 0.U(instOffsetBits.W))
       when(s2_provideds(w)) {
         s2_sc_used(w) := true.B
         s2_unconf(w)  := !s2_sumAboveThresholds(s2_chooseBit)
         s2_conf(w)    := s2_sumAboveThresholds(s2_chooseBit)
         // Use prediction from Statistical Corrector
-        XSDebug(p"---------tage_bank_${w} provided so that sc used---------\n")
         when(s2_sumAboveThresholds(s2_chooseBit)) {
-          val pred     = s2_scPreds(s2_chooseBit)
-          val debug_pc = Cat(debug_pc_s2, w.U, 0.U(instOffsetBits.W))
           s2_agree(w)    := s2_tageTakens_dup(3)(w) === pred
           s2_disagree(w) := s2_tageTakens_dup(3)(w) =/= pred
           // fit to always-taken condition
           // io.out.s2.full_pred.br_taken_mask(w) := pred
-          XSDebug(p"pc(${Hexadecimal(debug_pc)}) SC(${w.U}) overriden pred to ${pred}\n")
         }
       }
+      XSDebug(s2_provideds(w), p"---------tage_bank_${w} provided so that sc used---------\n")
+      XSDebug(
+        s2_provideds(w) && s2_sumAboveThresholds(s2_chooseBit),
+        p"pc(${Hexadecimal(debug_pc)}) SC(${w.U}) overriden pred to ${pred}\n"
+      )
 
       val s3_pred_dup   = io.s2_fire.map(f => RegEnable(s2_pred, f))
       val sc_enable_dup = dup(RegNext(io.ctrl.sc_enable))
@@ -374,17 +377,19 @@ trait HasSC extends HasSCParameter with HasPerfEvents { this: Tage =>
         }
       }
 
-      val updateTageMeta = updateMeta
+      val updateTageMeta    = updateMeta
+      val scPred            = updateSCMeta.scPreds(w)
+      val tagePred          = updateTageMeta.takens(w)
+      val taken             = update.br_taken_mask(w)
+      val scOldCtrs         = updateSCMeta.ctrs(w)
+      val pvdrCtr           = updateTageMeta.providerResps(w).ctr
+      val tableSum          = ParallelSingedExpandingAdd(scOldCtrs.map(getCentered))
+      val totalSumAbs       = (tableSum +& getPvdrCentered(pvdrCtr)).abs.asUInt
+      val updateThres       = updateThresholds(w)
+      val sumAboveThreshold = aboveThreshold(tableSum, getPvdrCentered(pvdrCtr), updateThres)
+      val thres             = useThresholds(w)
+      val newThres          = scThresholds(w).update(scPred =/= taken)
       when(updateValids(w) && updateTageMeta.providers(w).valid) {
-        val scPred            = updateSCMeta.scPreds(w)
-        val tagePred          = updateTageMeta.takens(w)
-        val taken             = update.br_taken_mask(w)
-        val scOldCtrs         = updateSCMeta.ctrs(w)
-        val pvdrCtr           = updateTageMeta.providerResps(w).ctr
-        val tableSum          = ParallelSingedExpandingAdd(scOldCtrs.map(getCentered))
-        val totalSumAbs       = (tableSum +& getPvdrCentered(pvdrCtr)).abs.asUInt
-        val updateThres       = updateThresholds(w)
-        val sumAboveThreshold = aboveThreshold(tableSum, getPvdrCentered(pvdrCtr), updateThres)
         scUpdateTagePreds(w) := tagePred
         scUpdateTakens(w)    := taken
         (scUpdateOldCtrs(w) zip scOldCtrs).foreach { case (t, c) => t := c }
@@ -397,30 +402,40 @@ trait HasSC extends HasSCParameter with HasPerfEvents { this: Tage =>
         sc_corr_tage_misp(w) := scPred === taken && tagePred =/= taken && update_conf(w)
         sc_misp_tage_corr(w) := scPred =/= taken && tagePred === taken && update_conf(w)
 
-        val thres = useThresholds(w)
         when(scPred =/= tagePred && totalSumAbs >= thres - 4.U && totalSumAbs <= thres - 2.U) {
-          val newThres = scThresholds(w).update(scPred =/= taken)
           scThresholds(w) := newThres
-          XSDebug(p"scThres $w update: old ${useThresholds(w)} --> new ${newThres.thres}\n")
         }
 
         when(scPred =/= taken || !sumAboveThreshold) {
           scUpdateMask(w).foreach(_ := true.B)
-          XSDebug(
-            tableSum < 0.S,
-            p"scUpdate: bank(${w}), scPred(${scPred}), tagePred(${tagePred}), " +
-              p"scSum(-${tableSum.abs}), mispred: sc(${scPred =/= taken}), tage(${updateMisPreds(w)})\n"
-          )
-          XSDebug(
-            tableSum >= 0.S,
-            p"scUpdate: bank(${w}), scPred(${scPred}), tagePred(${tagePred}), " +
-              p"scSum(+${tableSum.abs}), mispred: sc(${scPred =/= taken}), tage(${updateMisPreds(w)})\n"
-          )
-          XSDebug(p"bank(${w}), update: sc: ${updateSCMeta}\n")
           update_on_mispred(w) := scPred =/= taken
           update_on_unconf(w)  := scPred === taken
         }
       }
+      XSDebug(
+        updateValids(w) && updateTageMeta.providers(w).valid &&
+          scPred =/= tagePred && totalSumAbs >= thres - 4.U && totalSumAbs <= thres - 2.U,
+        p"scThres $w update: old ${useThresholds(w)} --> new ${newThres.thres}\n"
+      )
+      XSDebug(
+        updateValids(w) && updateTageMeta.providers(w).valid &&
+          (scPred =/= taken || !sumAboveThreshold) &&
+          tableSum < 0.S,
+        p"scUpdate: bank(${w}), scPred(${scPred}), tagePred(${tagePred}), " +
+          p"scSum(-${tableSum.abs}), mispred: sc(${scPred =/= taken}), tage(${updateMisPreds(w)})\n"
+      )
+      XSDebug(
+        updateValids(w) && updateTageMeta.providers(w).valid &&
+          (scPred =/= taken || !sumAboveThreshold) &&
+          tableSum >= 0.S,
+        p"scUpdate: bank(${w}), scPred(${scPred}), tagePred(${tagePred}), " +
+          p"scSum(+${tableSum.abs}), mispred: sc(${scPred =/= taken}), tage(${updateMisPreds(w)})\n"
+      )
+      XSDebug(
+        updateValids(w) && updateTageMeta.providers(w).valid &&
+          (scPred =/= taken || !sumAboveThreshold),
+        p"bank(${w}), update: sc: ${updateSCMeta}\n"
+      )
     }
 
     val realWens = scUpdateMask.transpose.map(v => v.reduce(_ | _))
diff --git a/src/main/scala/xiangshan/frontend/newRAS.scala b/src/main/scala/xiangshan/frontend/newRAS.scala
index 799d45d330..60d924ff40 100644
--- a/src/main/scala/xiangshan/frontend/newRAS.scala
+++ b/src/main/scala/xiangshan/frontend/newRAS.scala
@@ -765,9 +765,9 @@ class RAS(implicit p: Parameters) extends BasePredictor {
       spec_debug.spec_queue(i).ctr,
       spec_debug.spec_nos(i).value
     )
-    when(i.U === stack.TOSW.value)(XSDebug(io.s2_fire(2), "   <----TOSW"))
-    when(i.U === stack.TOSR.value)(XSDebug(io.s2_fire(2), "   <----TOSR"))
-    when(i.U === stack.BOS.value)(XSDebug(io.s2_fire(2), "   <----BOS"))
+    XSDebug(io.s2_fire(2) && i.U === stack.TOSW.value, "   <----TOSW")
+    XSDebug(io.s2_fire(2) && i.U === stack.TOSR.value, "   <----TOSR")
+    XSDebug(io.s2_fire(2) && i.U === stack.BOS.value, "   <----BOS")
     XSDebug(io.s2_fire(2), "\n")
   }
   XSDebug(io.s2_fire(2), "  index       addr           ctr   (committed part)\n")
@@ -779,8 +779,8 @@ class RAS(implicit p: Parameters) extends BasePredictor {
       spec_debug.commit_stack(i).retAddr,
       spec_debug.commit_stack(i).ctr
     )
-    when(i.U === stack.ssp)(XSDebug(io.s2_fire(2), "   <----ssp"))
-    when(i.U === stack.nsp)(XSDebug(io.s2_fire(2), "   <----nsp"))
+    XSDebug(io.s2_fire(2) && i.U === stack.ssp, "   <----ssp")
+    XSDebug(io.s2_fire(2) && i.U === stack.nsp, "   <----nsp")
     XSDebug(io.s2_fire(2), "\n")
   }
   /*
diff --git a/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala b/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
index 8aa976ea58..3eb3e8344d 100644
--- a/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
+++ b/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
@@ -158,9 +158,6 @@ class LoadQueueRAR(implicit p: Parameters) extends XSModule
     when (needEnqueue(w) && enq.ready) {
       acceptedVec(w) := true.B
 
-      val debug_robIdx = enq.bits.uop.robIdx.asUInt
-      XSError(allocated(enqIndex), p"LoadQueueRAR: You can not write an valid entry! check: ldu $w, robIdx $debug_robIdx")
-
       freeList.io.doAllocate(w) := true.B
       //  Allocate new entry
       allocated(enqIndex) := true.B
@@ -182,6 +179,10 @@ class LoadQueueRAR(implicit p: Parameters) extends XSModule
         enq.bits.paddr(PAddrBits-1, DCacheLineOffset) === release1Cycle.bits.paddr(PAddrBits-1, DCacheLineOffset))
       )
     }
+    val debug_robIdx = enq.bits.uop.robIdx.asUInt
+    XSError(
+      needEnqueue(w) && enq.ready && allocated(enqIndex),
+      p"LoadQueueRAR: You can not write an valid entry! check: ldu $w, robIdx $debug_robIdx")
   }
 
   //  LoadQueueRAR deallocate
diff --git a/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala b/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
index 59cbb5a095..05cc854010 100644
--- a/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
+++ b/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
@@ -141,9 +141,6 @@ class LoadQueueRAW(implicit p: Parameters) extends XSModule
     when (needEnqueue(w) && enq.ready) {
       acceptedVec(w) := true.B
 
-      val debug_robIdx = enq.bits.uop.robIdx.asUInt
-      XSError(allocated(enqIndex), p"LoadQueueRAW: You can not write an valid entry! check: ldu $w, robIdx $debug_robIdx")
-
       freeList.io.doAllocate(w) := true.B
 
       //  Allocate new entry
@@ -163,6 +160,8 @@ class LoadQueueRAW(implicit p: Parameters) extends XSModule
       uop(enqIndex) := enq.bits.uop
       datavalid(enqIndex) := enq.bits.data_valid
     }
+    val debug_robIdx = enq.bits.uop.robIdx.asUInt
+    XSError(needEnqueue(w) && enq.ready && allocated(enqIndex), p"LoadQueueRAW: You can not write an valid entry! check: ldu $w, robIdx $debug_robIdx")
   }
 
   for ((query, w) <- io.query.map(_.resp).zipWithIndex) {
diff --git a/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala b/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
index 9eab647d8d..7ed3040b9a 100644
--- a/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
+++ b/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
@@ -568,9 +568,7 @@ class LoadQueueReplay(implicit p: Parameters) extends XSModule
     replay_req(i).bits.schedIndex   := s2_oldestSel(i).bits
     replay_req(i).bits.uop.loadWaitStrict := false.B
 
-    when (replay_req(i).fire) {
-      XSError(!allocated(s2_oldestSel(i).bits), p"LoadQueueReplay: why replay an invalid entry ${s2_oldestSel(i).bits} ?")
-    }
+    XSError(replay_req(i).fire && !allocated(s2_oldestSel(i).bits), p"LoadQueueReplay: why replay an invalid entry ${s2_oldestSel(i).bits} ?")
   }
 
   val EnableHybridUnitReplay = Constantin.createRecord("EnableHybridUnitReplay", true)
@@ -599,9 +597,8 @@ class LoadQueueReplay(implicit p: Parameters) extends XSModule
     }
   }
 
- // when(io.refill.valid) {
- //   XSDebug("miss resp: paddr:0x%x data %x\n", io.refill.bits.addr, io.refill.bits.data)
- // }
+  // XSDebug(io.refill.valid, "miss resp: paddr:0x%x data %x\n", io.refill.bits.addr, io.refill.bits.data)
+
 
   // init
   freeMaskVec.map(e => e := false.B)
@@ -628,12 +625,16 @@ class LoadQueueReplay(implicit p: Parameters) extends XSModule
     enqIndexOH(w) := UIntToOH(enqIndex)
     enq.ready := true.B
 
+    val debug_robIdx = enq.bits.uop.robIdx.asUInt
+    XSError(
+      needEnqueue(w) && enq.ready &&
+      allocated(enqIndex) && !enq.bits.isLoadReplay,
+      p"LoadQueueReplay: can not accept more load, check: ldu $w, robIdx $debug_robIdx!")
+    XSError(
+      needEnqueue(w) && enq.ready &&
+      hasExceptions(w),
+      p"LoadQueueReplay: The instruction has exception, it can not be replay, check: ldu $w, robIdx $debug_robIdx!")
     when (needEnqueue(w) && enq.ready) {
-
-      val debug_robIdx = enq.bits.uop.robIdx.asUInt
-      XSError(allocated(enqIndex) && !enq.bits.isLoadReplay, p"LoadQueueReplay: can not accept more load, check: ldu $w, robIdx $debug_robIdx!")
-      XSError(hasExceptions(w), p"LoadQueueReplay: The instruction has exception, it can not be replay, check: ldu $w, robIdx $debug_robIdx!")
-
       freeList.io.doAllocate(w) := !enq.bits.isLoadReplay
 
       //  Allocate new entry
diff --git a/src/main/scala/xiangshan/mem/lsqueue/LoadQueueUncache.scala b/src/main/scala/xiangshan/mem/lsqueue/LoadQueueUncache.scala
index 0378c59d1d..3b23572700 100644
--- a/src/main/scala/xiangshan/mem/lsqueue/LoadQueueUncache.scala
+++ b/src/main/scala/xiangshan/mem/lsqueue/LoadQueueUncache.scala
@@ -88,13 +88,13 @@ class UncacheEntry(entryIndex: Int)(implicit p: Parameters) extends XSModule
   when (flush) {
     req_valid := false.B
   } .elsewhen (io.req.valid) {
-    XSError(req_valid, p"LoadQueueUncache: You can not write an valid entry: $entryIndex")
     req_valid := true.B
     req := io.req.bits
     nderr := false.B
   } .elsewhen (writeback) {
     req_valid := false.B
   }
+  XSError(!flush && io.req.valid && req_valid, p"LoadQueueUncache: You can not write an valid entry: $entryIndex")
 
   /**
     * Memory mapped IO / NC operations
@@ -224,31 +224,28 @@ class UncacheEntry(entryIndex: Int)(implicit p: Parameters) extends XSModule
   io.exception.bits.uop.exceptionVec(loadAccessFault) := nderr
 
   /* debug log */
-  when (io.uncache.req.fire) {
-    XSDebug("uncache req: pc %x addr %x data %x op %x mask %x\n",
-      req.uop.pc,
-      io.uncache.req.bits.addr,
-      io.uncache.req.bits.data,
-      io.uncache.req.bits.cmd,
-      io.uncache.req.bits.mask
-    )
-  }
-  when(io.ncOut.fire) {
-    XSInfo("int load miss write to cbd robidx %d lqidx %d pc 0x%x mmio %x\n",
-      io.ncOut.bits.uop.robIdx.asUInt,
-      io.ncOut.bits.uop.lqIdx.asUInt,
-      io.ncOut.bits.uop.pc,
-      true.B
-    )
-  }
-  when(io.mmioOut.fire) {
-    XSInfo("int load miss write to cbd robidx %d lqidx %d pc 0x%x mmio %x\n",
-      io.mmioOut.bits.uop.robIdx.asUInt,
-      io.mmioOut.bits.uop.lqIdx.asUInt,
-      io.mmioOut.bits.uop.pc,
-      true.B
-    )
-  }
+  XSDebug(io.uncache.req.fire,
+    "uncache req: pc %x addr %x data %x op %x mask %x\n",
+    req.uop.pc,
+    io.uncache.req.bits.addr,
+    io.uncache.req.bits.data,
+    io.uncache.req.bits.cmd,
+    io.uncache.req.bits.mask
+  )
+  XSInfo(io.ncOut.fire,
+    "int load miss write to cbd robidx %d lqidx %d pc 0x%x mmio %x\n",
+    io.ncOut.bits.uop.robIdx.asUInt,
+    io.ncOut.bits.uop.lqIdx.asUInt,
+    io.ncOut.bits.uop.pc,
+    true.B
+  )
+  XSInfo(io.mmioOut.fire,
+    "int load miss write to cbd robidx %d lqidx %d pc 0x%x mmio %x\n",
+    io.mmioOut.bits.uop.robIdx.asUInt,
+    io.mmioOut.bits.uop.lqIdx.asUInt,
+    io.mmioOut.bits.uop.pc,
+    true.B
+  )
 
 }
 
diff --git a/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala b/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
index f05c4b830a..60e5d3e51a 100644
--- a/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
+++ b/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
@@ -387,11 +387,18 @@ class StoreQueue(implicit p: Parameters) extends XSModule
           vecDataValid((index + j.U).value) := false.B
           hasException((index + j.U).value) := false.B
           waitStoreS2((index + j.U).value) := true.B
-          XSError(!io.enq.canAccept || !io.enq.lqCanAccept, s"must accept $i\n")
-          XSError(index.value =/= sqIdx.value, s"must be the same entry $i\n")
         }
       }
     }
+    val cond = VecInit.tabulate(VecMemLSQEnqIteratorNumberSeq(i)){j => j.U < validVStoreOffset(i)}.asUInt.orR
+    XSError(
+      canEnqueue(i) && !enqCancel(i) && cond &&
+        (!io.enq.canAccept || !io.enq.lqCanAccept),
+      s"must accept $i\n")
+    XSError(
+      canEnqueue(i) && !enqCancel(i) && cond &&
+      index.value =/= sqIdx.value,
+      s"must be the same entry $i\n")
     io.enq.resp(i) := sqIdx
   }
   XSDebug(p"(ready, valid): ${io.enq.canAccept}, ${Binary(Cat(io.enq.req.map(_.valid)))}\n")
@@ -505,21 +512,21 @@ class StoreQueue(implicit p: Parameters) extends XSModule
       debug_paddr(paddrModule.io.waddr(i)) := paddrModule.io.wdata(i)
 
       // mmio(stWbIndex) := io.storeAddrIn(i).bits.mmio
-
-      XSInfo("store addr write to sq idx %d pc 0x%x miss:%d vaddr %x paddr %x mmio %x isvec %x\n",
-        io.storeAddrIn(i).bits.uop.sqIdx.value,
-        io.storeAddrIn(i).bits.uop.pc,
-        io.storeAddrIn(i).bits.miss,
-        io.storeAddrIn(i).bits.vaddr,
-        io.storeAddrIn(i).bits.paddr,
-        io.storeAddrIn(i).bits.mmio,
-        io.storeAddrIn(i).bits.isvec
-      )
     }
     when (io.storeAddrIn(i).fire) {
       uop(stWbIndex) := io.storeAddrIn(i).bits.uop
       uop(stWbIndex).debugInfo := io.storeAddrIn(i).bits.uop.debugInfo
     }
+    XSInfo(io.storeAddrIn(i).fire && !io.storeAddrIn(i).bits.isFrmMisAlignBuf,
+      "store addr write to sq idx %d pc 0x%x miss:%d vaddr %x paddr %x mmio %x isvec %x\n",
+      io.storeAddrIn(i).bits.uop.sqIdx.value,
+      io.storeAddrIn(i).bits.uop.pc,
+      io.storeAddrIn(i).bits.miss,
+      io.storeAddrIn(i).bits.vaddr,
+      io.storeAddrIn(i).bits.paddr,
+      io.storeAddrIn(i).bits.mmio,
+      io.storeAddrIn(i).bits.isvec
+    )
 
     // re-replinish mmio, for pma/pmp will get mmio one cycle later
     val storeAddrInFireReg = RegNext(io.storeAddrIn(i).fire && !io.storeAddrIn(i).bits.miss) && io.storeAddrInRe(i).updateAddrValid
@@ -570,14 +577,14 @@ class StoreQueue(implicit p: Parameters) extends XSModule
       dataModule.io.data.wen(i) := true.B
 
       debug_data(dataModule.io.data.waddr(i)) := dataModule.io.data.wdata(i)
-
-      XSInfo("store data write to sq idx %d pc 0x%x data %x -> %x\n",
-        io.storeDataIn(i).bits.uop.sqIdx.value,
-        io.storeDataIn(i).bits.uop.pc,
-        io.storeDataIn(i).bits.data,
-        dataModule.io.data.wdata(i)
-      )
     }
+    XSInfo(io.storeDataIn(i).fire,
+      "store data write to sq idx %d pc 0x%x data %x -> %x\n",
+      io.storeDataIn(i).bits.uop.sqIdx.value,
+      io.storeDataIn(i).bits.uop.pc,
+      io.storeDataIn(i).bits.data,
+      dataModule.io.data.wdata(i)
+    )
     // sq data write s1
     val lastStWbIndex = RegEnable(stWbIndex, io.storeDataIn(i).fire)
     when (
@@ -658,13 +665,12 @@ class StoreQueue(implicit p: Parameters) extends XSModule
       GatedRegNext(addrRealValidVec.asUInt)
     ) =/= 0.U
     val vaddrMatchFailed = vpmaskNotEqual && RegNext(io.forward(i).valid)
-    when (vaddrMatchFailed) {
-      XSInfo("vaddrMatchFailed: pc %x pmask %x vmask %x\n",
-        RegEnable(io.forward(i).uop.pc, io.forward(i).valid),
-        RegEnable(needForward & paddrModule.io.forwardMmask(i).asUInt, io.forward(i).valid),
-        RegEnable(needForward & vaddrModule.io.forwardMmask(i).asUInt, io.forward(i).valid)
-      );
-    }
+    XSInfo(vaddrMatchFailed,
+      "vaddrMatchFailed: pc %x pmask %x vmask %x\n",
+      RegEnable(io.forward(i).uop.pc, io.forward(i).valid),
+      RegEnable(needForward & paddrModule.io.forwardMmask(i).asUInt, io.forward(i).valid),
+      RegEnable(needForward & vaddrModule.io.forwardMmask(i).asUInt, io.forward(i).valid)
+    );
     XSPerfAccumulate("vaddr_match_failed", vpmaskNotEqual)
     XSPerfAccumulate("vaddr_match_really_failed", vaddrMatchFailed)
 
@@ -943,15 +949,15 @@ class StoreQueue(implicit p: Parameters) extends XSModule
   when(mmioDoReq){
     // mmio store should not be committed until uncache req is sent
     pending(deqPtr) := false.B
-
-    XSDebug(
-      p"uncache mmio req: pc ${Hexadecimal(uop(deqPtr).pc)} " +
-      p"addr ${Hexadecimal(io.uncache.req.bits.addr)} " +
-      p"data ${Hexadecimal(io.uncache.req.bits.data)} " +
-      p"op ${Hexadecimal(io.uncache.req.bits.cmd)} " +
-      p"mask ${Hexadecimal(io.uncache.req.bits.mask)}\n"
-    )
   }
+  XSDebug(
+    mmioDoReq,
+    p"uncache req: pc ${Hexadecimal(uop(deqPtr).pc)} " +
+    p"addr ${Hexadecimal(io.uncache.req.bits.addr)} " +
+    p"data ${Hexadecimal(io.uncache.req.bits.data)} " +
+    p"op ${Hexadecimal(io.uncache.req.bits.cmd)} " +
+    p"mask ${Hexadecimal(io.uncache.req.bits.mask)}\n"
+  )
 
   // (3) response from uncache channel: mark as datavalid
   io.uncache.resp.ready := true.B
@@ -1231,8 +1237,8 @@ class StoreQueue(implicit p: Parameters) extends XSModule
     val ptr = dataBuffer.io.deq(i).bits.sqPtr.value
     when (RegNext(io.sbuffer(i).fire && io.sbuffer(i).bits.sqNeedDeq)) {
       allocated(RegEnable(ptr, io.sbuffer(i).fire)) := false.B
-      XSDebug("sbuffer "+i+" fire: ptr %d\n", ptr)
     }
+    XSDebug(RegNext(io.sbuffer(i).fire && io.sbuffer(i).bits.sqNeedDeq), "sbuffer "+i+" fire: ptr %d\n", ptr)
   }
 
   // All vector instruction uop normally dequeue, but the Uop after the exception is raised does not write to the 'sbuffer'.
@@ -1453,11 +1459,8 @@ class StoreQueue(implicit p: Parameters) extends XSModule
   XSDebug("enqPtrExt %d:%d deqPtrExt %d:%d\n", enqPtrExt(0).flag, enqPtr, deqPtrExt(0).flag, deqPtr)
 
   def PrintFlag(flag: Bool, name: String): Unit = {
-    when(flag) {
-      XSDebug(false, true.B, name)
-    }.otherwise {
-      XSDebug(false, true.B, " ")
-    }
+    XSDebug(false, flag, name) // when(flag)
+    XSDebug(false, !flag, " ") // otherwirse
   }
 
   for (i <- 0 until StoreQueueSize) {
diff --git a/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala b/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
index 13e4451287..6383516bda 100644
--- a/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
+++ b/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
@@ -183,12 +183,18 @@ class VirtualLoadQueue(implicit p: Parameters) extends XSModule
 
           debug_mmio((index + j.U).value) := false.B
           debug_paddr((index + j.U).value) := 0.U
-
-          XSError(!io.enq.canAccept || !io.enq.sqCanAccept, s"must accept $i\n")
-          XSError(index.value =/= lqIdx.value, s"must be the same entry $i\n")
         }
       }
     }
+    val cond = VecInit.tabulate(VecMemLSQEnqIteratorNumberSeq(i)){j => j.U < validVLoadOffset(i)}.asUInt.orR
+    XSError(
+      canEnqueue(i) && !enqCancel(i) && cond &&
+        (!io.enq.canAccept || !io.enq.sqCanAccept),
+      s"must accept $i\n")
+    XSError(
+      canEnqueue(i) && !enqCancel(i) && cond &&
+      index.value =/= lqIdx.value,
+      s"must be the same entry $i\n")
     io.enq.resp(i) := lqIdx
   }
 
@@ -200,8 +206,8 @@ class VirtualLoadQueue(implicit p: Parameters) extends XSModule
   (0 until DeqPtrMoveStride).map(i => {
     when (commitCount > i.U) {
       allocated((deqPtr+i.U).value) := false.B
-      XSError(!allocated((deqPtr+i.U).value), s"why commit invalid entry $i?\n")
     }
+    XSError(commitCount > i.U && !allocated((deqPtr+i.U).value), s"why commit invalid entry $i?\n")
   })
 
   // vector commit or replay
@@ -242,11 +248,10 @@ class VirtualLoadQueue(implicit p: Parameters) extends XSModule
     io.ldin(i).ready := true.B
     val loadWbIndex = io.ldin(i).bits.uop.lqIdx.value
 
+    val hasExceptions = ExceptionNO.selectByFu(io.ldin(i).bits.uop.exceptionVec, LduCfg).asUInt.orR
+    val need_rep = io.ldin(i).bits.rep_info.need_rep
+    val need_valid = io.ldin(i).bits.updateAddrValid
     when (io.ldin(i).valid) {
-      val hasExceptions = ExceptionNO.selectByFu(io.ldin(i).bits.uop.exceptionVec, LduCfg).asUInt.orR
-      val need_rep = io.ldin(i).bits.rep_info.need_rep
-      val need_valid = io.ldin(i).bits.updateAddrValid
-
       when (!need_rep && need_valid) {
       // update control flag
         addrvalid(loadWbIndex) := hasExceptions || !io.ldin(i).bits.tlbMiss || io.ldin(i).bits.isSWPrefetch
@@ -276,21 +281,21 @@ class VirtualLoadQueue(implicit p: Parameters) extends XSModule
         //  Debug info
         debug_mmio(loadWbIndex) := io.ldin(i).bits.mmio
         debug_paddr(loadWbIndex) := io.ldin(i).bits.paddr
-
-        XSInfo(io.ldin(i).valid,
-          "load hit write to lq idx %d pc 0x%x vaddr %x paddr %x mask %x forwardData %x forwardMask: %x mmio %x isvec %x\n",
-          io.ldin(i).bits.uop.lqIdx.asUInt,
-          io.ldin(i).bits.uop.pc,
-          io.ldin(i).bits.vaddr,
-          io.ldin(i).bits.paddr,
-          io.ldin(i).bits.mask,
-          io.ldin(i).bits.forwardData.asUInt,
-          io.ldin(i).bits.forwardMask.asUInt,
-          io.ldin(i).bits.mmio,
-          io.ldin(i).bits.isvec
-        )
       }
     }
+
+    XSInfo(io.ldin(i).valid && !need_rep && need_valid,
+      "load hit write to lq idx %d pc 0x%x vaddr %x paddr %x mask %x forwardData %x forwardMask: %x mmio %x isvec %x\n",
+      io.ldin(i).bits.uop.lqIdx.asUInt,
+      io.ldin(i).bits.uop.pc,
+      io.ldin(i).bits.vaddr,
+      io.ldin(i).bits.paddr,
+      io.ldin(i).bits.mask,
+      io.ldin(i).bits.forwardData.asUInt,
+      io.ldin(i).bits.forwardMask.asUInt,
+      io.ldin(i).bits.mmio,
+      io.ldin(i).bits.isvec
+    )
   }
 
   //  perf counter
@@ -305,11 +310,8 @@ class VirtualLoadQueue(implicit p: Parameters) extends XSModule
   XSDebug("enqPtrExt %d:%d deqPtrExt %d:%d\n", enqPtrExt(0).flag, enqPtr, deqPtr.flag, deqPtr.value)
 
   def PrintFlag(flag: Bool, name: String): Unit = {
-    when(flag) {
-      XSDebug(false, true.B, name)
-    }.otherwise {
-      XSDebug(false, true.B, " ")
-    }
+    XSDebug(false, flag, name) // when(flag)
+    XSDebug(false, !flag, " ") // otherwise
   }
 
   for (i <- 0 until VirtualLoadQueueSize) {
diff --git a/src/main/scala/xiangshan/mem/mdp/StoreSet.scala b/src/main/scala/xiangshan/mem/mdp/StoreSet.scala
index 9249d7d9c4..4772527c0d 100644
--- a/src/main/scala/xiangshan/mem/mdp/StoreSet.scala
+++ b/src/main/scala/xiangshan/mem/mdp/StoreSet.scala
@@ -319,10 +319,8 @@ class SSIT(implicit p: Parameters) extends XSModule {
   ) // should be zero
 
   // debug
-  when (s2_mempred_update_req.valid) {
-    XSDebug("%d: SSIT update: load pc %x store pc %x\n", GTimer(), s2_mempred_update_req.ldpc, s2_mempred_update_req.stpc)
-    XSDebug("%d: SSIT update: load valid %b ssid %x  store valid %b ssid %x\n", GTimer(), s2_loadAssigned, s2_loadOldSSID, s2_storeAssigned, s2_storeOldSSID)
-  }
+  XSDebug(s2_mempred_update_req.valid, "%d: SSIT update: load pc %x store pc %x\n", GTimer(), s2_mempred_update_req.ldpc, s2_mempred_update_req.stpc)
+  XSDebug(s2_mempred_update_req.valid, "%d: SSIT update: load valid %b ssid %x  store valid %b ssid %x\n", GTimer(), s2_loadAssigned, s2_loadOldSSID, s2_storeAssigned, s2_storeOldSSID)
 }
 
 
diff --git a/src/main/scala/xiangshan/mem/mdp/WaitTable.scala b/src/main/scala/xiangshan/mem/mdp/WaitTable.scala
index eea6007c13..5f63dc9039 100644
--- a/src/main/scala/xiangshan/mem/mdp/WaitTable.scala
+++ b/src/main/scala/xiangshan/mem/mdp/WaitTable.scala
@@ -65,9 +65,7 @@ class WaitTable(implicit p: Parameters) extends XSModule {
   }
 
   // debug
-  when (io.update.valid) {
-    XSDebug("%d: waittable update: pc %x data: %x\n", GTimer(), io.update.waddr, io.update.wdata)
-  }
+  XSDebug(io.update.valid, "%d: waittable update: pc %x data: %x\n", GTimer(), io.update.waddr, io.update.wdata)
 
   XSPerfAccumulate("wait_table_bit_set", PopCount(data.map(d => d(1))))
 }
diff --git a/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala b/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
index d236b06a19..ec15044fcb 100644
--- a/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
+++ b/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
@@ -230,7 +230,7 @@ class AtomicsUnit(implicit p: Parameters) extends XSModule
   TriggerUtil.triggerActionGen(triggerAction, backendTriggerCanFireVec, actionVec, triggerCanRaiseBpExp)
   val triggerDebugMode = TriggerAction.isDmode(triggerAction)
   val triggerBreakpoint = TriggerAction.isExp(triggerAction)
-  
+
   // tlb translation, manipulating signals && deal with exception
   // at the same time, flush sbuffer
   when (state === s_tlb_and_flush_sbuffer_req) {
@@ -258,7 +258,7 @@ class AtomicsUnit(implicit p: Parameters) extends XSModule
       exceptionVec(loadAccessFault)     := io.dtlb.resp.bits.excp(0).af.ld
       exceptionVec(storeGuestPageFault) := io.dtlb.resp.bits.excp(0).gpf.st
       exceptionVec(loadGuestPageFault)  := io.dtlb.resp.bits.excp(0).gpf.ld
-      
+
       exceptionVec(breakPoint) := triggerBreakpoint
       trigger                  := triggerAction
 
@@ -407,6 +407,7 @@ class AtomicsUnit(implicit p: Parameters) extends XSModule
       }
     }
   }
+  XSDebug(io.out.fire, "atomics writeback: pc %x data %x\n", io.out.bits.uop.pc, io.dcache.resp.bits.data)
 
   when (state === s_finish2) {
     when (io.out.fire) {
@@ -528,7 +529,7 @@ class AtomicsUnit(implicit p: Parameters) extends XSModule
   pipe_req.amo_data := genWdataAMO(rs2, uop.fuOpType)
   pipe_req.amo_mask := genWmaskAMO(paddr, uop.fuOpType)
   pipe_req.amo_cmp  := genWdataAMO(rd, uop.fuOpType)
-  
+
   if (env.EnableDifftest) {
     val difftest = DifftestModule(new DiffAtomicEvent)
     val en = io.dcache.req.fire
diff --git a/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala b/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
index d71471c3f5..7fa3ea6e0f 100644
--- a/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
+++ b/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
@@ -1924,10 +1924,6 @@ class LoadUnit(implicit p: Parameters) extends XSModule
   )
   generatePerfEvent()
 
-  when(io.ldout.fire){
-    XSDebug("ldout %x\n", io.ldout.bits.uop.pc)
-  }
-
   if (backendParams.debugEn){
     dontTouch(s0_src_valid_vec)
     dontTouch(s0_src_ready_vec)
@@ -1939,5 +1935,6 @@ class LoadUnit(implicit p: Parameters) extends XSModule
     s3_picked_data_frm_pipe.map(x=> dontTouch(x))
   }
 
+  XSDebug(io.ldout.fire, "ldout %x\n", io.ldout.bits.uop.pc)
   // end
 }
diff --git a/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala b/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
index bd18c9627c..caccd82eb3 100644
--- a/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
+++ b/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
@@ -456,15 +456,17 @@ class Sbuffer(implicit p: Parameters)
         // missqReplayCount(entryIdx) := 0.U
         // check if vtag is the same, if not, trigger sbuffer flush
         when(reqvtag =/= vtag(entryIdx)) {
-          XSDebug("reqvtag =/= sbufvtag req(vtag %x ptag %x) sbuffer(vtag %x ptag %x)\n",
-            reqvtag << OffsetWidth,
-            reqptag << OffsetWidth,
-            vtag(entryIdx) << OffsetWidth,
-            ptag(entryIdx) << OffsetWidth
-          )
           merge_need_uarch_drain := true.B
         }
       }
+      XSDebug(
+        mergeVec(entryIdx) && reqvtag =/= vtag(entryIdx),
+        "reqvtag =/= sbufvtag req(vtag %x ptag %x) sbuffer(vtag %x ptag %x)\n",
+        reqvtag << OffsetWidth,
+        reqptag << OffsetWidth,
+        vtag(entryIdx) << OffsetWidth,
+        ptag(entryIdx) << OffsetWidth
+      )
     })
   }
 
@@ -481,15 +483,16 @@ class Sbuffer(implicit p: Parameters)
     val accessValid = in.fire && in.bits.vecValid
     accessIdx(i).valid := RegNext(accessValid)
     accessIdx(i).bits := RegEnable(Mux(canMerge(i), mergeIdx(i), insertIdx), accessValid)
+
+    XSDebug(accessValid && canMerge(i), p"merge req $i to line [${mergeIdx(i)}]\n")
+    XSDebug(accessValid && !canMerge(i), p"insert req $i to line[$insertIdx]\n")
     when(accessValid){
       when(canMerge(i)){
         writeReq(i).bits.wvec := mergeVec(i)
         mergeWordReq(in.bits, inptags(i), invtags(i), mergeIdx(i), mergeVec(i), vwordOffset)
-        XSDebug(p"merge req $i to line [${mergeIdx(i)}]\n")
       }.otherwise({
         writeReq(i).bits.wvec := insertVec
         wordReqToBufLine(in.bits, inptags(i), invtags(i), insertIdx, insertVec, vwordOffset)
-        XSDebug(p"insert req $i to line[$insertIdx]\n")
         assert(debug_insertIdx === insertIdx)
       })
     }
@@ -660,8 +663,8 @@ class Sbuffer(implicit p: Parameters)
     stateVec(sbuffer_out_s0_evictionIdx).state_inflight := true.B
     stateVec(sbuffer_out_s0_evictionIdx).w_timeout := false.B
     // stateVec(sbuffer_out_s0_evictionIdx).s_pipe_req := true.B
-    XSDebug(p"$sbuffer_out_s0_evictionIdx will be sent to Dcache\n")
   }
+  XSDebug(sbuffer_out_s0_fire, p"$sbuffer_out_s0_evictionIdx will be sent to Dcache\n")
 
   XSDebug(p"need drain:$need_drain cohHasTimeOut: $cohHasTimeOut need replace:$need_replace\n")
   XSDebug(p"drainIdx:$drainIdx tIdx:$cohTimeOutIdx replIdx:$replaceIdx " +
@@ -776,14 +779,16 @@ class Sbuffer(implicit p: Parameters)
     )).asUInt.orR
     mismatch(i) := tag_mismatch
     when (tag_mismatch) {
-      XSDebug("forward tag mismatch: pmatch %x vmatch %x vaddr %x paddr %x\n",
-        RegNext(ptag_matches.asUInt),
-        RegNext(vtag_matches.asUInt),
-        RegNext(forward.vaddr),
-        RegNext(forward.paddr)
-      )
       forward_need_uarch_drain := true.B
     }
+    XSDebug(
+      tag_mismatch,
+      "forward tag mismatch: pmatch %x vmatch %x vaddr %x paddr %x\n",
+      RegNext(ptag_matches.asUInt),
+      RegNext(vtag_matches.asUInt),
+      RegNext(forward.vaddr),
+      RegNext(forward.paddr)
+    )
     val valid_tag_matches = widthMap(w => tag_matches(w) && activeMask(w))
     val inflight_tag_matches = widthMap(w => tag_matches(w) && inflightMask(w))
     val line_offset_mask = UIntToOH(getVWordOffset(forward.paddr))
@@ -844,7 +849,7 @@ class Sbuffer(implicit p: Parameters)
       stateVec(i).w_timeout
     )
   }
-  
+
   /*
   *
   **********************************************************
diff --git a/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala b/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
index ecb3f5a6c5..dbd94cec9b 100644
--- a/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
+++ b/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
@@ -347,10 +347,8 @@ class VSegmentUnit (implicit p: Parameters) extends VLSUModule
     )
   }.elsewhen(state === s_fof_fix_vl){ // writeback uop
     stateNext := Mux(!fofBufferValid, s_idle, s_fof_fix_vl)
-
-  }.otherwise{
+  }.otherwise{ // unknown state
     stateNext := s_idle
-    XSError(true.B, s"Unknown state!\n")
   }
 
   /*************************************************************************