From 4f296b3f70c46bcb0f7c347db0c364c1afaa1143 Mon Sep 17 00:00:00 2001 From: Easton Man Date: Mon, 9 Dec 2024 19:40:47 +0800 Subject: [PATCH] fix(bpu): fix reg increase when removing asTypeOf --- src/main/scala/xiangshan/frontend/ITTAGE.scala | 4 +++- src/main/scala/xiangshan/frontend/Tage.scala | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/main/scala/xiangshan/frontend/ITTAGE.scala b/src/main/scala/xiangshan/frontend/ITTAGE.scala index 77240a2d92c..197761c1bd5 100644 --- a/src/main/scala/xiangshan/frontend/ITTAGE.scala +++ b/src/main/scala/xiangshan/frontend/ITTAGE.scala @@ -505,7 +505,8 @@ class ITTage(implicit p: Parameters) extends BaseITTage { update := RegEnable(io.update.bits, io.update.valid) // meta is splited by composer - val updateMeta = WireInit(update.meta.asTypeOf(new ITTageMeta)) + val updateMeta = Wire(new ITTageMeta) + update.meta := updateMeta.asUInt // The pc register has been moved outside of predictor, pc field of update bundle and other update data are not in the same stage // so io.update.bits.pc is used directly here @@ -513,6 +514,7 @@ class ITTage(implicit p: Parameters) extends BaseITTage { // To improve Clock Gating Efficiency val u_meta = io.update.bits.meta.asTypeOf(new ITTageMeta) + updateMeta := RegNext(u_meta) updateMeta.provider.bits := RegEnable( u_meta.provider.bits, io.update.valid && u_meta.provider.valid diff --git a/src/main/scala/xiangshan/frontend/Tage.scala b/src/main/scala/xiangshan/frontend/Tage.scala index 44f85121d6d..9a3c3973c95 100644 --- a/src/main/scala/xiangshan/frontend/Tage.scala +++ b/src/main/scala/xiangshan/frontend/Tage.scala @@ -707,7 +707,9 @@ class Tage(implicit p: Parameters) extends BaseTage { io.update.bits.ftb_entry.brValids(w) && io.update.valid )) // io.update.bits.ftb_entry.always_taken has timing issues(FTQEntryGen) val u_meta = io.update.bits.meta.asTypeOf(new TageMeta) - val updateMeta = WireInit(update.meta.asTypeOf(new TageMeta)) + val updateMeta = Wire(new TageMeta) + update.meta := updateMeta.asUInt + updateMeta := RegNext(u_meta) for (i <- 0 until numBr) { updateMeta.providers(i).bits := RegEnable( u_meta.providers(i).bits,