From 43171c7a556b0816cbe36a0cb5f43ec9743fd1fd Mon Sep 17 00:00:00 2001 From: wakafa Date: Wed, 15 Nov 2023 19:27:03 +0800 Subject: [PATCH] csr: fix interrupt priority (#2480) --- .../scala/xiangshan/backend/fu/util/CSRConst.scala | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala b/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala index 7c7187a4beb..699c0e75c6f 100644 --- a/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala +++ b/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala @@ -203,17 +203,17 @@ trait HasCSRConst { def ModeS = 0x1.U def ModeU = 0x0.U - def IRQ_UEIP = 0 - def IRQ_SEIP = 1 - def IRQ_MEIP = 3 + def IRQ_USIP = 0 + def IRQ_SSIP = 1 + def IRQ_MSIP = 3 def IRQ_UTIP = 4 def IRQ_STIP = 5 def IRQ_MTIP = 7 - def IRQ_USIP = 8 - def IRQ_SSIP = 9 - def IRQ_MSIP = 11 + def IRQ_UEIP = 8 + def IRQ_SEIP = 9 + def IRQ_MEIP = 11 def IRQ_DEBUG = 12