fix(bpu): fix reg increase when removing asTypeOf

OpenXiangShan · Dec 11, 2024 · 2da0123 · 2da0123
1 parent aadcdaf
commit 2da0123
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Showing 2 changed files with 6 additions and 2 deletions.
diff --git a/src/main/scala/xiangshan/frontend/ITTAGE.scala b/src/main/scala/xiangshan/frontend/ITTAGE.scala
@@ -505,14 +505,16 @@ class ITTage(implicit p: Parameters) extends BaseITTage {
   update := RegEnable(io.update.bits, io.update.valid)
 
   // meta is splited by composer
-  val updateMeta = WireInit(update.meta.asTypeOf(new ITTageMeta))
+  val updateMeta = Wire(new ITTageMeta)
+  update.meta := updateMeta.asUInt
 
   // The pc register has been moved outside of predictor, pc field of update bundle and other update data are not in the same stage
   // so io.update.bits.pc is used directly here
   val update_pc = io.update.bits.pc
 
   // To improve Clock Gating Efficiency
   val u_meta = io.update.bits.meta.asTypeOf(new ITTageMeta)
+  updateMeta := RegEnable(u_meta, io.update.valid)
   updateMeta.provider.bits := RegEnable(
     u_meta.provider.bits,
     io.update.valid && u_meta.provider.valid

diff --git a/src/main/scala/xiangshan/frontend/Tage.scala b/src/main/scala/xiangshan/frontend/Tage.scala
@@ -707,7 +707,9 @@ class Tage(implicit p: Parameters) extends BaseTage {
       io.update.bits.ftb_entry.brValids(w) && io.update.valid
     )) // io.update.bits.ftb_entry.always_taken has timing issues(FTQEntryGen)
   val u_meta     = io.update.bits.meta.asTypeOf(new TageMeta)
-  val updateMeta = WireInit(update.meta.asTypeOf(new TageMeta))
+  val updateMeta = Wire(new TageMeta)
+  update.meta := updateMeta.asUInt
+  updateMeta  := RegEnable(u_meta, io.update.valid)
   for (i <- 0 until numBr) {
     updateMeta.providers(i).bits := RegEnable(
       u_meta.providers(i).bits,