From 049386d975ab9a2053bd6baae942b2a270d000eb Mon Sep 17 00:00:00 2001 From: Anzooooo Date: Mon, 9 Dec 2024 17:13:47 +0800 Subject: [PATCH] fix(selectOldest): use `===` instead of `isNotBefore` For instructions with vectors or other multiple `uop`, it is necessary to determine whether `robIdx` is the same before comparing `uopIdx`. Although there is no error if `isNotBefore` is used, we can use the clearer and more concise `===` to make the determination. --- .../scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala | 4 ++-- src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala b/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala index 11cc3a952f..d7e81036f1 100644 --- a/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala +++ b/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala @@ -81,7 +81,7 @@ class LqExceptionBuffer(implicit p: Parameters) extends XSModule with HasCircula } val oldest = Mux(valid(0) && valid(1), Mux(isAfter(bits(0).uop.robIdx, bits(1).uop.robIdx) || - (isNotBefore(bits(0).uop.robIdx, bits(1).uop.robIdx) && bits(0).uop.uopIdx > bits(1).uop.uopIdx), res(1), res(0)), + (bits(0).uop.robIdx === bits(1).uop.robIdx && bits(0).uop.uopIdx > bits(1).uop.uopIdx), res(1), res(0)), Mux(valid(0) && !valid(1), res(0), res(1))) (Seq(oldest.valid), Seq(oldest.bits)) } else { @@ -95,7 +95,7 @@ class LqExceptionBuffer(implicit p: Parameters) extends XSModule with HasCircula when (req_valid) { req := Mux( - reqSel._1(0) && (isAfter(req.uop.robIdx, reqSel._2(0).uop.robIdx) || (isNotBefore(req.uop.robIdx, reqSel._2(0).uop.robIdx) && req.uop.uopIdx > reqSel._2(0).uop.uopIdx)), + reqSel._1(0) && (isAfter(req.uop.robIdx, reqSel._2(0).uop.robIdx) || (req.uop.robIdx === reqSel._2(0).uop.robIdx && req.uop.uopIdx > reqSel._2(0).uop.uopIdx)), reqSel._2(0), req) } .elsewhen (s2_enqueue.asUInt.orR) { diff --git a/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala b/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala index e0115a3a04..81e599779d 100644 --- a/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala +++ b/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala @@ -123,7 +123,7 @@ class StoreExceptionBuffer(implicit p: Parameters) extends XSModule with HasCirc } val oldest = Mux(valid(0) && valid(1), Mux(isAfter(bits(0).uop.robIdx, bits(1).uop.robIdx) || - (isNotBefore(bits(0).uop.robIdx, bits(1).uop.robIdx) && bits(0).uop.uopIdx > bits(1).uop.uopIdx), res(1), res(0)), + (bits(0).uop.robIdx === bits(1).uop.robIdx && bits(0).uop.uopIdx > bits(1).uop.uopIdx), res(1), res(0)), Mux(valid(0) && !valid(1), res(0), res(1))) (Seq(oldest.valid), Seq(oldest.bits)) } else {