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Improving Xilinx Zynq-7000 support #5605
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This issue has been marked as a stale issue because it has been open (more than) 30 days with no activity. Remove the stale label or add a comment, otherwise this issue will automatically be closed in 5 days. Note, that you can always re-open a closed issue at any time. |
Keep-alive |
This issue has been marked as a stale issue because it has been open (more than) 30 days with no activity. Remove the stale label or add a comment, otherwise this issue will automatically be closed in 5 days. Note, that you can always re-open a closed issue at any time. |
Keep-alive |
This issue has been marked as a stale issue because it has been open (more than) 30 days with no activity. Remove the stale label or add a comment, otherwise this issue will automatically be closed in 5 days. Note, that you can always re-open a closed issue at any time. |
Keep-alive |
This issue has been marked as a stale issue because it has been open (more than) 30 days with no activity. Remove the stale label or add a comment, otherwise this issue will automatically be closed in 5 days. Note, that you can always re-open a closed issue at any time. |
Keep-alive. @jforissier can you add enhancement or such flag for this? |
@vesajaaskelainen sure, done. |
Hey guys, is the build system configured to automatically pull ZyncMPSoC Boot Firmware? [1] and [2] mention it is required. [1] https://optee.readthedocs.io/en/latest/building/devices/zynqmp.html |
This is to track merging of improved Xilinx Zynq-7000 support.
Current set of changes:
Now it seems to be feature complete so that:
xtest
is executed successfullyKnown missing features:
Currently this all works in our own hardware -- should be able to get most working with common Xilinx ZC702 devkit (expect FPGA bitstream related features as there is no common bitstream that could be shared between parties).
The text was updated successfully, but these errors were encountered: