From 281025adaf49e9005bcd206553e98d26bd588b07 Mon Sep 17 00:00:00 2001 From: nwdepatie Date: Fri, 23 Feb 2024 19:28:54 -0500 Subject: [PATCH 1/8] #9 Autogenerating ADC DMA implementation for 1 ADC --- CM4/Core/Src/main.c | 13 +++++++ CM7/Core/Inc/stm32h7xx_it.h | 1 + CM7/Core/Src/main.c | 27 ++++++++++--- CM7/Core/Src/stm32h7xx_hal_msp.c | 22 +++++++++++ CM7/Core/Src/stm32h7xx_it.c | 16 +++++++- Makefile/CM4/Makefile | 2 +- Makefile/CM7/Makefile | 2 +- proteus.ioc | 66 ++++++++++++++++++++++---------- 8 files changed, 119 insertions(+), 30 deletions(-) diff --git a/CM4/Core/Src/main.c b/CM4/Core/Src/main.c index e978b15..f98b747 100644 --- a/CM4/Core/Src/main.c +++ b/CM4/Core/Src/main.c @@ -69,6 +69,7 @@ const osThreadAttr_t defaultTask_attributes = { /* Private function prototypes -----------------------------------------------*/ static void MX_GPIO_Init(void); +static void MX_DMA_Init(void); static void MX_FDCAN1_Init(void); static void MX_QUADSPI_Init(void); static void MX_USB_OTG_FS_PCD_Init(void); @@ -124,6 +125,7 @@ int main(void) /* Initialize all configured peripherals */ MX_GPIO_Init(); + MX_DMA_Init(); MX_FDCAN1_Init(); MX_QUADSPI_Init(); MX_USB_OTG_FS_PCD_Init(); @@ -381,6 +383,17 @@ static void MX_USB_OTG_FS_PCD_Init(void) } +/** + * Enable DMA controller clock + */ +static void MX_DMA_Init(void) +{ + + /* DMA controller clock enable */ + __HAL_RCC_DMA1_CLK_ENABLE(); + +} + /** * @brief GPIO Initialization Function * @param None diff --git a/CM7/Core/Inc/stm32h7xx_it.h b/CM7/Core/Inc/stm32h7xx_it.h index 1137fad..03c091f 100644 --- a/CM7/Core/Inc/stm32h7xx_it.h +++ b/CM7/Core/Inc/stm32h7xx_it.h @@ -53,6 +53,7 @@ void BusFault_Handler(void); void UsageFault_Handler(void); void DebugMon_Handler(void); void SysTick_Handler(void); +void DMA1_Stream0_IRQHandler(void); /* USER CODE BEGIN EFP */ /* USER CODE END EFP */ diff --git a/CM7/Core/Src/main.c b/CM7/Core/Src/main.c index 7d60385..426bbf4 100644 --- a/CM7/Core/Src/main.c +++ b/CM7/Core/Src/main.c @@ -47,6 +47,7 @@ /* Private variables ---------------------------------------------------------*/ ADC_HandleTypeDef hadc1; ADC_HandleTypeDef hadc3; +DMA_HandleTypeDef hdma_adc1; CRC_HandleTypeDef hcrc; @@ -77,7 +78,7 @@ const osThreadAttr_t defaultTask_attributes = { void SystemClock_Config(void); void PeriphCommonClock_Config(void); static void MX_GPIO_Init(void); -static void MX_CRC_Init(void); +static void MX_DMA_Init(void); static void MX_ADC1_Init(void); static void MX_ADC3_Init(void); static void MX_SPI1_Init(void); @@ -88,6 +89,7 @@ static void MX_TIM1_Init(void); static void MX_TIM2_Init(void); static void MX_TIM4_Init(void); static void MX_TIM8_Init(void); +static void MX_CRC_Init(void); void StartDefaultTask(void *argument); /* USER CODE BEGIN PFP */ @@ -159,7 +161,7 @@ Error_Handler(); /* Initialize all configured peripherals */ MX_GPIO_Init(); - MX_CRC_Init(); + MX_DMA_Init(); MX_ADC1_Init(); MX_ADC3_Init(); MX_SPI1_Init(); @@ -170,6 +172,7 @@ Error_Handler(); MX_TIM2_Init(); MX_TIM4_Init(); MX_TIM8_Init(); + MX_CRC_Init(); /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ @@ -239,10 +242,6 @@ void SystemClock_Config(void) while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} - /** Macro to configure the PLL clock source - */ - __HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSI); - /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ @@ -966,6 +965,22 @@ static void MX_TIM8_Init(void) } +/** + * Enable DMA controller clock + */ +static void MX_DMA_Init(void) +{ + + /* DMA controller clock enable */ + __HAL_RCC_DMA1_CLK_ENABLE(); + + /* DMA interrupt init */ + /* DMA1_Stream0_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn); + +} + /** * @brief GPIO Initialization Function * @param None diff --git a/CM7/Core/Src/stm32h7xx_hal_msp.c b/CM7/Core/Src/stm32h7xx_hal_msp.c index fba8a9d..63d7120 100644 --- a/CM7/Core/Src/stm32h7xx_hal_msp.c +++ b/CM7/Core/Src/stm32h7xx_hal_msp.c @@ -24,6 +24,7 @@ /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ +extern DMA_HandleTypeDef hdma_adc1; /* Private typedef -----------------------------------------------------------*/ /* USER CODE BEGIN TD */ @@ -123,6 +124,25 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + /* ADC1 DMA Init */ + /* ADC1 Init */ + hdma_adc1.Instance = DMA1_Stream0; + hdma_adc1.Init.Request = DMA_REQUEST_ADC1; + hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; + hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; + hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; + hdma_adc1.Init.Mode = DMA_NORMAL; + hdma_adc1.Init.Priority = DMA_PRIORITY_HIGH; + hdma_adc1.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1); + /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ @@ -195,6 +215,8 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) HAL_GPIO_DeInit(GPIOB, GPIO_PIN_0|GPIO_PIN_1); + /* ADC1 DMA DeInit */ + HAL_DMA_DeInit(hadc->DMA_Handle); /* USER CODE BEGIN ADC1_MspDeInit 1 */ /* USER CODE END ADC1_MspDeInit 1 */ diff --git a/CM7/Core/Src/stm32h7xx_it.c b/CM7/Core/Src/stm32h7xx_it.c index 656fc4c..273abf6 100644 --- a/CM7/Core/Src/stm32h7xx_it.c +++ b/CM7/Core/Src/stm32h7xx_it.c @@ -57,7 +57,7 @@ /* USER CODE END 0 */ /* External variables --------------------------------------------------------*/ - +extern DMA_HandleTypeDef hdma_adc1; /* USER CODE BEGIN EV */ /* USER CODE END EV */ @@ -182,6 +182,20 @@ void SysTick_Handler(void) /* please refer to the startup file (startup_stm32h7xx.s). */ /******************************************************************************/ +/** + * @brief This function handles DMA1 stream0 global interrupt. + */ +void DMA1_Stream0_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */ + + /* USER CODE END DMA1_Stream0_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_adc1); + /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */ + + /* USER CODE END DMA1_Stream0_IRQn 1 */ +} + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/Makefile/CM4/Makefile b/Makefile/CM4/Makefile index 5903b05..eb940cd 100644 --- a/Makefile/CM4/Makefile +++ b/Makefile/CM4/Makefile @@ -1,5 +1,5 @@ ########################################################################################################################## -# File automatically-generated by tool: [projectgenerator] version: [4.2.0-B44] date: [Fri Feb 23 17:29:36 EST 2024] +# File automatically-generated by tool: [projectgenerator] version: [4.2.0-B44] date: [Fri Feb 23 17:55:52 EST 2024] ########################################################################################################################## # ------------------------------------------------ diff --git a/Makefile/CM7/Makefile b/Makefile/CM7/Makefile index 087956c..b2a2d0b 100644 --- a/Makefile/CM7/Makefile +++ b/Makefile/CM7/Makefile @@ -1,5 +1,5 @@ ########################################################################################################################## -# File automatically-generated by tool: [projectgenerator] version: [4.2.0-B44] date: [Fri Feb 23 17:29:36 EST 2024] +# File automatically-generated by tool: [projectgenerator] version: [4.2.0-B44] date: [Fri Feb 23 17:55:53 EST 2024] ########################################################################################################################## # ------------------------------------------------ diff --git a/proteus.ioc b/proteus.ioc index d536cfb..f16fdd8 100644 --- a/proteus.ioc +++ b/proteus.ioc @@ -19,6 +19,26 @@ CAD.pinconfig= CAD.provider= CortexM4.IPs=CORTEX_M4\:I,DEBUG,FATFS_M4\:I,FREERTOS_M4\:I,IWDG2\:I,OPENAMP_M4\:I,PDM2PCM_M4\:I,PWR,RCC,RESMGR_UTILITY,SYS_M4\:I,USB_DEVICE_M4\:I,USB_HOST_M4\:I,VREFBUF,WWDG2\:I,GPIO,DMA,BDMA,MDMA,NVIC2\:I,FDCAN1\:I,CRC,USB_OTG_FS\:I,QUADSPI\:I,UART4\:I CortexM7.IPs=CORTEX_M7\:I,DEBUG\:I,FATFS_M7\:I,FREERTOS_M7\:I,IWDG1\:I,OPENAMP_M7\:I,PDM2PCM_M7\:I,PWR\:I,RCC\:I,RESMGR_UTILITY\:I,SYS\:I,USB_DEVICE_M7\:I,USB_HOST_M7\:I,VREFBUF\:I,WWDG1\:I,GPIO\:I,DMA\:I,BDMA\:I,MDMA\:I,NVIC1\:I,FDCAN1,SPI1\:I,SPI2\:I,SPI4\:I,CRC\:I,TIM1\:I,TIM8\:I,TIM2\:I,TIM3\:I,TIM4\:I,ADC1\:I,SPI3\:I,ADC3\:I +Dma.ADC1.0.Direction=DMA_PERIPH_TO_MEMORY +Dma.ADC1.0.EventEnable=DISABLE +Dma.ADC1.0.FIFOMode=DMA_FIFOMODE_DISABLE +Dma.ADC1.0.Instance=DMA1_Stream0 +Dma.ADC1.0.MemDataAlignment=DMA_MDATAALIGN_HALFWORD +Dma.ADC1.0.MemInc=DMA_MINC_ENABLE +Dma.ADC1.0.Mode=DMA_NORMAL +Dma.ADC1.0.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD +Dma.ADC1.0.PeriphInc=DMA_PINC_DISABLE +Dma.ADC1.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING +Dma.ADC1.0.Priority=DMA_PRIORITY_HIGH +Dma.ADC1.0.RequestNumber=1 +Dma.ADC1.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber +Dma.ADC1.0.SignalID=NONE +Dma.ADC1.0.SyncEnable=DISABLE +Dma.ADC1.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT +Dma.ADC1.0.SyncRequestNumber=1 +Dma.ADC1.0.SyncSignalID=NONE +Dma.Request0=ADC1 +Dma.RequestsNb=1 FDCAN1.CalculateBaudRateNominal=625000 FDCAN1.CalculateTimeBitNominal=1600 FDCAN1.CalculateTimeQuantumNominal=320.0 @@ -37,30 +57,31 @@ Mcu.ContextNb=2 Mcu.Family=STM32H7 Mcu.IP0=ADC1 Mcu.IP1=ADC3 -Mcu.IP10=NVIC2 -Mcu.IP11=QUADSPI -Mcu.IP12=RCC -Mcu.IP13=SPI1 -Mcu.IP14=SPI2 -Mcu.IP15=SPI3 -Mcu.IP16=SPI4 -Mcu.IP17=SYS_M4 -Mcu.IP18=SYS -Mcu.IP19=TIM1 +Mcu.IP10=NVIC1 +Mcu.IP11=NVIC2 +Mcu.IP12=QUADSPI +Mcu.IP13=RCC +Mcu.IP14=SPI1 +Mcu.IP15=SPI2 +Mcu.IP16=SPI3 +Mcu.IP17=SPI4 +Mcu.IP18=SYS_M4 +Mcu.IP19=SYS Mcu.IP2=CORTEX_M4 -Mcu.IP20=TIM2 -Mcu.IP21=TIM4 -Mcu.IP22=TIM8 -Mcu.IP23=UART4 -Mcu.IP24=USB_OTG_FS +Mcu.IP20=TIM1 +Mcu.IP21=TIM2 +Mcu.IP22=TIM4 +Mcu.IP23=TIM8 +Mcu.IP24=UART4 +Mcu.IP25=USB_OTG_FS Mcu.IP3=CORTEX_M7 Mcu.IP4=CRC Mcu.IP5=DEBUG -Mcu.IP6=FDCAN1 -Mcu.IP7=FREERTOS_M4 -Mcu.IP8=FREERTOS_M7 -Mcu.IP9=NVIC1 -Mcu.IPNb=25 +Mcu.IP6=DMA +Mcu.IP7=FDCAN1 +Mcu.IP8=FREERTOS_M4 +Mcu.IP9=FREERTOS_M7 +Mcu.IPNb=26 Mcu.Name=STM32H745ZITx Mcu.Package=LQFP144 Mcu.Pin0=PE2 @@ -153,6 +174,7 @@ Mcu.UserName=STM32H745ZITx MxCube.Version=6.10.0 MxDb.Version=DB.6.0.100 NVIC1.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false +NVIC1.DMA1_Stream0_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true NVIC1.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false NVIC1.ForceEnableDMAVector=true NVIC1.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false @@ -531,7 +553,7 @@ ProjectManager.ToolChainLocation= ProjectManager.UAScriptAfterPath= ProjectManager.UAScriptBeforePath= ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false-CortexM7,2-MX_GPIO_Init-GPIO-false-HAL-true-CortexM7,3-MX_CRC_Init-CRC-false-HAL-true-CortexM7,4-MX_ADC1_Init-ADC1-false-HAL-true-CortexM7,5-MX_ADC3_Init-ADC3-false-HAL-true-CortexM7,6-MX_FDCAN1_Init-FDCAN1-true-HAL-false-CortexM7,7-MX_SPI1_Init-SPI1-false-HAL-true-CortexM7,8-MX_SPI2_Init-SPI2-false-HAL-true-CortexM7,9-MX_SPI3_Init-SPI3-false-HAL-true-CortexM7,10-MX_SPI4_Init-SPI4-false-HAL-true-CortexM7,11-MX_TIM1_Init-TIM1-false-HAL-true-CortexM7,12-MX_TIM2_Init-TIM2-false-HAL-true-CortexM7,13-MX_TIM4_Init-TIM4-false-HAL-true-CortexM7,14-MX_TIM8_Init-TIM8-false-HAL-true-CortexM7,15-MX_FREERTOS_Init-FREERTOS_M7-false-HAL-false-CortexM7,1-MX_GPIO_Init-GPIO-false-HAL-true-CortexM4,2-MX_CRC_Init-CRC-true-HAL-false-CortexM4,3-MX_FDCAN1_Init-FDCAN1-false-HAL-true-CortexM4,4-MX_QUADSPI_Init-QUADSPI-false-HAL-true-CortexM4,5-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true-CortexM4,6-MX_UART4_Init-UART4-false-HAL-true-CortexM4,7-MX_FREERTOS_Init-FREERTOS_M4-false-HAL-false-CortexM4,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true-CortexM7,0-MX_CORTEX_M4_Init-CORTEX_M4-false-HAL-true-CortexM4 +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false-CortexM7,2-MX_GPIO_Init-GPIO-false-HAL-true-CortexM7,3-MX_DMA_Init-DMA-false-HAL-true-CortexM7,4-MX_ADC1_Init-ADC1-false-HAL-true-CortexM7,5-MX_ADC3_Init-ADC3-false-HAL-true-CortexM7,6-MX_FDCAN1_Init-FDCAN1-true-HAL-false-CortexM7,7-MX_SPI1_Init-SPI1-false-HAL-true-CortexM7,8-MX_SPI2_Init-SPI2-false-HAL-true-CortexM7,9-MX_SPI3_Init-SPI3-false-HAL-true-CortexM7,10-MX_SPI4_Init-SPI4-false-HAL-true-CortexM7,11-MX_TIM1_Init-TIM1-false-HAL-true-CortexM7,12-MX_TIM2_Init-TIM2-false-HAL-true-CortexM7,13-MX_TIM4_Init-TIM4-false-HAL-true-CortexM7,14-MX_TIM8_Init-TIM8-false-HAL-true-CortexM7,15-MX_CRC_Init-CRC-false-HAL-true-CortexM7,16-MX_FREERTOS_Init-FREERTOS_M7-false-HAL-false-CortexM7,1-MX_GPIO_Init-GPIO-false-HAL-true-CortexM4,2-MX_DMA_Init-DMA-false-HAL-true-CortexM4,3-MX_FDCAN1_Init-FDCAN1-false-HAL-true-CortexM4,4-MX_QUADSPI_Init-QUADSPI-false-HAL-true-CortexM4,5-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true-CortexM4,6-MX_UART4_Init-UART4-false-HAL-true-CortexM4,7-MX_CRC_Init-CRC-true-HAL-false-CortexM4,8-MX_FREERTOS_Init-FREERTOS_M4-false-HAL-false-CortexM4,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true-CortexM7,0-MX_CORTEX_M4_Init-CORTEX_M4-false-HAL-true-CortexM4 RCC.ADCFreq_Value=37500000 RCC.AHB12Freq_Value=64000000 RCC.AHB4Freq_Value=64000000 @@ -698,3 +720,5 @@ VP_SYS_M4_VS_Systick.Signal=SYS_M4_VS_Systick VP_SYS_VS_Systick.Mode=SysTick VP_SYS_VS_Systick.Signal=SYS_VS_Systick board=custom +rtos.0.ip=FREERTOS_M4 +rtos.1.ip=FREERTOS_M7 From 540d22d2f53c27f7e616fa3ab4d9bc8112bf9e87 Mon Sep 17 00:00:00 2001 From: nwdepatie Date: Fri, 23 Feb 2024 19:29:19 -0500 Subject: [PATCH 2/8] (#9) Working in ADC DMA implementation to gate driver interface --- CM7/Core/Inc/gatedriver.h | 26 ++++++++++++++++------ CM7/Core/Src/gatedriver.c | 44 ++++++++++++++++++------------------- CM7/Core/Src/main.c | 2 ++ Common/Inc/proteus_config.h | 6 +++++ Makefile/CM4/Makefile | 1 + Makefile/CM7/Makefile | 1 + 6 files changed, 51 insertions(+), 29 deletions(-) create mode 100644 Common/Inc/proteus_config.h diff --git a/CM7/Core/Inc/gatedriver.h b/CM7/Core/Inc/gatedriver.h index 48508ea..5ce13cb 100644 --- a/CM7/Core/Inc/gatedriver.h +++ b/CM7/Core/Inc/gatedriver.h @@ -3,30 +3,42 @@ #include "cmsis_os.h" #include "stm32h7xx.h" +#include "stm32h7xx_hal.h" #include #include -enum phase{ - U, - V, - W +#define ADC_BUF_LEN 4 + +enum { + PHASE_U, + PHASE_V, + PHASE_W, + NUM_PHASES }; typedef struct { TIM_HandleTypeDef* tim; osMutexId_t* tim_mutex; TIM_OC_InitTypeDef* pPWMConfig; - uint32_t pulses[]; + uint32_t pulses[NUM_PHASES]; + + DMA_HandleTypeDef *hdma_adc; + SPI_HandleTypeDef *adc_spi; + uint32_t intern_adc_buffer[ADC_BUF_LEN]; + + osMutexId_t* tim_mutex_mutex; + osMutexAttr_t tim_mutex_attr; + osMutexId_t* ext_adc_mutex; + osMutexAttr_t ext_adc_mutex_attr; } gatedriver_t; -gatedriver_t* gatedrv_init(TIM_HandleTypeDef* tim); +gatedriver_t* gatedrv_init(TIM_HandleTypeDef* tim, DMA_HandleTypeDef *hdma_adc, SPI_HandleTypeDef *adc_spi); int16_t gatedrv_read_dc_voltage(gatedriver_t* drv); int16_t gatedrv_read_dc_current(gatedriver_t* drv); /* Note: This has to atomically write to ALL PWM registers */ -//TODO: mechanism for PWM synchronization int16_t gatedrv_write_pwm(gatedriver_t* drv, float duty_cycles[]); int16_t gatedrv_read_igbt_temp(gatedriver_t* drv); diff --git a/CM7/Core/Src/gatedriver.c b/CM7/Core/Src/gatedriver.c index a5647ff..dfa75d1 100644 --- a/CM7/Core/Src/gatedriver.c +++ b/CM7/Core/Src/gatedriver.c @@ -1,4 +1,3 @@ - #include "gatedriver.h" #include "stm32h7xx.h" #include @@ -7,19 +6,6 @@ #define PERIOD_VALUE (uint32_t)(2000 - 1) -const static osMutexAttr_t gatedrv_tim_mutex_attr; - -//TODO: Look up STM callback func pointer for ADCs -static void gatedrv_current_adc_cb(gatedriver_t* drv) -{ - -} - -static void gatedrv_voltage_adc_cb(gatedriver_t* drv) -{ - -} - static void gatedrv_ready_cb(gatedriver_t* drv) { @@ -35,10 +21,12 @@ static void gatedrv_fault_cb(gatedriver_t* drv) } -gatedriver_t* gatedrv_init(TIM_HandleTypeDef* tim) +gatedriver_t* gatedrv_init(TIM_HandleTypeDef* tim, DMA_HandleTypeDef *hdma_adc, SPI_HandleTypeDef *adc_spi) { /* Assert hardware params */ assert(tim); + assert(hdma_adc); + assert(adc_spi); /* Create MPU struct */ gatedriver_t* gatedriver = malloc(sizeof(gatedriver_t)); @@ -46,16 +34,16 @@ gatedriver_t* gatedrv_init(TIM_HandleTypeDef* tim) /* Set interfaces */ gatedriver->tim = tim; - + gatedriver->hdma_adc = hdma_adc; + gatedriver->adc_spi = adc_spi; + /* Init hardware */ tim->Init.Prescaler = 0; tim->Init.Period = PERIOD_VALUE; tim->Init.ClockDivision = 0; tim->Init.CounterMode = TIM_COUNTERMODE_UP; tim->Init.RepetitionCounter = 0; - if(HAL_TIM_PWM_Init(tim) != HAL_OK) { - // TODO: how to handle this error? - } + assert(HAL_TIM_PWM_Init(tim) != HAL_OK); /* Common configuration for all PWM channels */ TIM_OC_InitTypeDef PWMConfig; @@ -67,15 +55,27 @@ gatedriver_t* gatedrv_init(TIM_HandleTypeDef* tim) PWMConfig.OCFastMode = TIM_OCFAST_DISABLE; gatedriver->pPWMConfig = &PWMConfig; + /* Configure DMA */ + assert(HAL_ADC_Start_DMA(gatedriver->hdma_adc, &gatedriver->intern_adc_buffer, ADC_BUF_LEN)); + /* Create Mutexes */ - gatedriver->tim_mutex = osMutexNew(&gatedrv_tim_mutex_attr); + gatedriver->tim_mutex = osMutexNew(&gatedriver->tim_mutex_attr); assert(gatedriver->tim_mutex); - //TODO: Link interrupts to callbacks + gatedriver->ext_adc_mutex = osMutexNew(&gatedriver->ext_adc_mutex_attr); + assert(gatedriver->ext_adc_mutex); return gatedriver; } +void gatedrv_get_phase_currents(gatedriver_t* drv, int16_t current_buf[]) +{ + // TODO: Figure out what data is where in the DMA + // current_buf[U] = drv->mem[0] << X + // current_buf[V] = drv->mem + // current_buf[W] = drv->mem +} + int16_t gatedrv_read_dc_voltage(gatedriver_t* drv) { @@ -103,7 +103,7 @@ int16_t gatedrv_write_pwm(gatedriver_t* drv, float duty_cycles[]) /* Getting PWM channel config */ TIM_OC_InitTypeDef* config = drv->pPWMConfig; - + /* Attempting to set channel 1 */ config->Pulse = pulses[0]; if(HAL_TIM_PWM_ConfigChannel(drv->tim, config, TIM_CHANNEL_1) != HAL_OK) diff --git a/CM7/Core/Src/main.c b/CM7/Core/Src/main.c index 426bbf4..5753eb2 100644 --- a/CM7/Core/Src/main.c +++ b/CM7/Core/Src/main.c @@ -23,6 +23,8 @@ /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ +#include "proteus_config.h" + /* USER CODE END Includes */ /* Private typedef -----------------------------------------------------------*/ diff --git a/Common/Inc/proteus_config.h b/Common/Inc/proteus_config.h new file mode 100644 index 0000000..1aa6aa1 --- /dev/null +++ b/Common/Inc/proteus_config.h @@ -0,0 +1,6 @@ +#ifndef PROTEUS_CONFIG_H +#define PROTEUS_CONFIG_H + + + +#endif /* PROTEUS_CONFIG_H */ diff --git a/Makefile/CM4/Makefile b/Makefile/CM4/Makefile index eb940cd..31f0d5f 100644 --- a/Makefile/CM4/Makefile +++ b/Makefile/CM4/Makefile @@ -146,6 +146,7 @@ AS_INCLUDES = \ # C includes C_INCLUDES = \ -I../../CM4/Core/Inc \ +-I../../Common/Inc \ -I../../Drivers/STM32H7xx_HAL_Driver/Inc \ -I../../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy \ -I../../Middlewares/Third_Party/FreeRTOS/Source/include \ diff --git a/Makefile/CM7/Makefile b/Makefile/CM7/Makefile index b2a2d0b..c29ca83 100644 --- a/Makefile/CM7/Makefile +++ b/Makefile/CM7/Makefile @@ -147,6 +147,7 @@ AS_INCLUDES = \ # C includes C_INCLUDES = \ -I../../CM7/Core/Inc \ +-I../../Common/Inc \ -I../../Drivers/STM32H7xx_HAL_Driver/Inc \ -I../../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy \ -I../../Middlewares/Third_Party/FreeRTOS/Source/include \ From c73ef6e6da75503df334d4a99ae2658785704bbd Mon Sep 17 00:00:00 2001 From: nwdepatie Date: Wed, 13 Mar 2024 16:32:27 -0400 Subject: [PATCH 3/8] Changing DMA typedef to ADC typedef --- CM7/Core/Inc/gatedriver.h | 4 ++-- CM7/Core/Src/gatedriver.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/CM7/Core/Inc/gatedriver.h b/CM7/Core/Inc/gatedriver.h index 5ce13cb..8fbfae7 100644 --- a/CM7/Core/Inc/gatedriver.h +++ b/CM7/Core/Inc/gatedriver.h @@ -22,7 +22,7 @@ typedef struct { TIM_OC_InitTypeDef* pPWMConfig; uint32_t pulses[NUM_PHASES]; - DMA_HandleTypeDef *hdma_adc; + ADC_HandleTypeDef *hdma_adc; SPI_HandleTypeDef *adc_spi; uint32_t intern_adc_buffer[ADC_BUF_LEN]; @@ -32,7 +32,7 @@ typedef struct { osMutexAttr_t ext_adc_mutex_attr; } gatedriver_t; -gatedriver_t* gatedrv_init(TIM_HandleTypeDef* tim, DMA_HandleTypeDef *hdma_adc, SPI_HandleTypeDef *adc_spi); +gatedriver_t* gatedrv_init(TIM_HandleTypeDef* tim, ADC_HandleTypeDef *hdma_adc, SPI_HandleTypeDef *adc_spi); int16_t gatedrv_read_dc_voltage(gatedriver_t* drv); diff --git a/CM7/Core/Src/gatedriver.c b/CM7/Core/Src/gatedriver.c index dfa75d1..2924bef 100644 --- a/CM7/Core/Src/gatedriver.c +++ b/CM7/Core/Src/gatedriver.c @@ -21,7 +21,7 @@ static void gatedrv_fault_cb(gatedriver_t* drv) } -gatedriver_t* gatedrv_init(TIM_HandleTypeDef* tim, DMA_HandleTypeDef *hdma_adc, SPI_HandleTypeDef *adc_spi) +gatedriver_t* gatedrv_init(TIM_HandleTypeDef* tim, ADC_HandleTypeDef *hdma_adc, SPI_HandleTypeDef *adc_spi) { /* Assert hardware params */ assert(tim); From c226c3066595f7b57369391d5bf141c3aa7caa98 Mon Sep 17 00:00:00 2001 From: nwdepatie Date: Wed, 13 Mar 2024 17:13:22 -0400 Subject: [PATCH 4/8] Adding in actual ADC mappings --- CM7/Core/Inc/gatedriver.h | 6 +++--- CM7/Core/Src/gatedriver.c | 28 ++++++++++++++-------------- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/CM7/Core/Inc/gatedriver.h b/CM7/Core/Inc/gatedriver.h index 8fbfae7..65916b2 100644 --- a/CM7/Core/Inc/gatedriver.h +++ b/CM7/Core/Inc/gatedriver.h @@ -7,7 +7,7 @@ #include #include -#define ADC_BUF_LEN 4 +#define MAX_ADC_BUF 7 enum { PHASE_U, @@ -19,12 +19,12 @@ enum { typedef struct { TIM_HandleTypeDef* tim; osMutexId_t* tim_mutex; - TIM_OC_InitTypeDef* pPWMConfig; + TIM_OC_InitTypeDef* pwm_cfg; uint32_t pulses[NUM_PHASES]; ADC_HandleTypeDef *hdma_adc; SPI_HandleTypeDef *adc_spi; - uint32_t intern_adc_buffer[ADC_BUF_LEN]; + uint32_t intern_adc_buffer[MAX_ADC_BUF]; osMutexId_t* tim_mutex_mutex; osMutexAttr_t tim_mutex_attr; diff --git a/CM7/Core/Src/gatedriver.c b/CM7/Core/Src/gatedriver.c index 2924bef..c07b543 100644 --- a/CM7/Core/Src/gatedriver.c +++ b/CM7/Core/Src/gatedriver.c @@ -46,17 +46,17 @@ gatedriver_t* gatedrv_init(TIM_HandleTypeDef* tim, ADC_HandleTypeDef *hdma_adc, assert(HAL_TIM_PWM_Init(tim) != HAL_OK); /* Common configuration for all PWM channels */ - TIM_OC_InitTypeDef PWMConfig; - PWMConfig.OCMode = TIM_OCMODE_PWM1; - PWMConfig.OCPolarity = TIM_OCPOLARITY_HIGH; - PWMConfig.OCNPolarity = TIM_OCNPOLARITY_HIGH; - PWMConfig.OCIdleState = TIM_OCIDLESTATE_SET; - PWMConfig.OCNIdleState = TIM_OCNIDLESTATE_RESET; - PWMConfig.OCFastMode = TIM_OCFAST_DISABLE; - gatedriver->pPWMConfig = &PWMConfig; + TIM_OC_InitTypeDef pwm_cfg; + pwm_cfg.OCMode = TIM_OCMODE_PWM1; + pwm_cfg.OCPolarity = TIM_OCPOLARITY_HIGH; + pwm_cfg.OCNPolarity = TIM_OCNPOLARITY_HIGH; + pwm_cfg.OCIdleState = TIM_OCIDLESTATE_SET; + pwm_cfg.OCNIdleState = TIM_OCNIDLESTATE_RESET; + pwm_cfg.OCFastMode = TIM_OCFAST_DISABLE; + gatedriver->pwm_cfg = &pwm_cfg; /* Configure DMA */ - assert(HAL_ADC_Start_DMA(gatedriver->hdma_adc, &gatedriver->intern_adc_buffer, ADC_BUF_LEN)); + assert(HAL_ADC_Start_DMA(gatedriver->hdma_adc, gatedriver->intern_adc_buffer, MAX_ADC_BUF)); /* Create Mutexes */ gatedriver->tim_mutex = osMutexNew(&gatedriver->tim_mutex_attr); @@ -70,10 +70,10 @@ gatedriver_t* gatedrv_init(TIM_HandleTypeDef* tim, ADC_HandleTypeDef *hdma_adc, void gatedrv_get_phase_currents(gatedriver_t* drv, int16_t current_buf[]) { - // TODO: Figure out what data is where in the DMA - // current_buf[U] = drv->mem[0] << X - // current_buf[V] = drv->mem - // current_buf[W] = drv->mem + //TODO: Ensure the ADC DMA is mapped the same across boards + current_buf[PHASE_U] = drv->intern_adc_buffer[0]; + current_buf[PHASE_V] = drv->intern_adc_buffer[1]; + current_buf[PHASE_W] = drv->intern_adc_buffer[2]; } int16_t gatedrv_read_dc_voltage(gatedriver_t* drv) @@ -102,7 +102,7 @@ int16_t gatedrv_write_pwm(gatedriver_t* drv, float duty_cycles[]) pulses[2] = (uint32_t) (duty_cycles[2] * PERIOD_VALUE / 100); /* Getting PWM channel config */ - TIM_OC_InitTypeDef* config = drv->pPWMConfig; + TIM_OC_InitTypeDef* config = drv->pwm_cfg; /* Attempting to set channel 1 */ config->Pulse = pulses[0]; From e7759312b1fc356b8992ed4b940464907ae88f0f Mon Sep 17 00:00:00 2001 From: nwdepatie Date: Wed, 13 Mar 2024 17:14:38 -0400 Subject: [PATCH 5/8] Autogenerating STM code for ADC DMA --- CM7/Core/Inc/stm32h7xx_it.h | 1 + CM7/Core/Src/main.c | 111 +++++++++++++++++++++++++++++-- CM7/Core/Src/stm32h7xx_hal_msp.c | 23 +++++++ CM7/Core/Src/stm32h7xx_it.c | 15 +++++ Makefile/CM4/Makefile | 2 +- Makefile/CM7/Makefile | 2 +- proteus.ioc | 83 ++++++++++++++++++++++- 7 files changed, 228 insertions(+), 9 deletions(-) diff --git a/CM7/Core/Inc/stm32h7xx_it.h b/CM7/Core/Inc/stm32h7xx_it.h index 03c091f..ed65d7b 100644 --- a/CM7/Core/Inc/stm32h7xx_it.h +++ b/CM7/Core/Inc/stm32h7xx_it.h @@ -54,6 +54,7 @@ void UsageFault_Handler(void); void DebugMon_Handler(void); void SysTick_Handler(void); void DMA1_Stream0_IRQHandler(void); +void DMA1_Stream2_IRQHandler(void); /* USER CODE BEGIN EFP */ /* USER CODE END EFP */ diff --git a/CM7/Core/Src/main.c b/CM7/Core/Src/main.c index 5753eb2..42de874 100644 --- a/CM7/Core/Src/main.c +++ b/CM7/Core/Src/main.c @@ -50,6 +50,7 @@ ADC_HandleTypeDef hadc1; ADC_HandleTypeDef hadc3; DMA_HandleTypeDef hdma_adc1; +DMA_HandleTypeDef hdma_adc3; CRC_HandleTypeDef hcrc; @@ -335,11 +336,11 @@ static void MX_ADC1_Init(void) hadc1.Instance = ADC1; hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; hadc1.Init.Resolution = ADC_RESOLUTION_16B; - hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; + hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; hadc1.Init.LowPowerAutoWait = DISABLE; hadc1.Init.ContinuousConvMode = DISABLE; - hadc1.Init.NbrOfConversion = 1; + hadc1.Init.NbrOfConversion = 6; hadc1.Init.DiscontinuousConvMode = DISABLE; hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; @@ -373,6 +374,51 @@ static void MX_ADC1_Init(void) { Error_Handler(); } + + /** Configure Regular Channel + */ + sConfig.Channel = ADC_CHANNEL_4; + sConfig.Rank = ADC_REGULAR_RANK_2; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Regular Channel + */ + sConfig.Channel = ADC_CHANNEL_5; + sConfig.Rank = ADC_REGULAR_RANK_3; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Regular Channel + */ + sConfig.Channel = ADC_CHANNEL_7; + sConfig.Rank = ADC_REGULAR_RANK_4; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Regular Channel + */ + sConfig.Channel = ADC_CHANNEL_8; + sConfig.Rank = ADC_REGULAR_RANK_5; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Regular Channel + */ + sConfig.Channel = ADC_CHANNEL_9; + sConfig.Rank = ADC_REGULAR_RANK_6; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ @@ -401,11 +447,11 @@ static void MX_ADC3_Init(void) */ hadc3.Instance = ADC3; hadc3.Init.Resolution = ADC_RESOLUTION_16B; - hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE; + hadc3.Init.ScanConvMode = ADC_SCAN_ENABLE; hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV; hadc3.Init.LowPowerAutoWait = DISABLE; hadc3.Init.ContinuousConvMode = DISABLE; - hadc3.Init.NbrOfConversion = 1; + hadc3.Init.NbrOfConversion = 7; hadc3.Init.DiscontinuousConvMode = DISABLE; hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START; hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; @@ -431,6 +477,60 @@ static void MX_ADC3_Init(void) { Error_Handler(); } + + /** Configure Regular Channel + */ + sConfig.Channel = ADC_CHANNEL_2; + sConfig.Rank = ADC_REGULAR_RANK_2; + if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Regular Channel + */ + sConfig.Channel = ADC_CHANNEL_3; + sConfig.Rank = ADC_REGULAR_RANK_3; + if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Regular Channel + */ + sConfig.Channel = ADC_CHANNEL_7; + sConfig.Rank = ADC_REGULAR_RANK_4; + if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Regular Channel + */ + sConfig.Channel = ADC_CHANNEL_8; + sConfig.Rank = ADC_REGULAR_RANK_5; + if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Regular Channel + */ + sConfig.Channel = ADC_CHANNEL_10; + sConfig.Rank = ADC_REGULAR_RANK_6; + if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Regular Channel + */ + sConfig.Channel = ADC_CHANNEL_11; + sConfig.Rank = ADC_REGULAR_RANK_7; + if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) + { + Error_Handler(); + } /* USER CODE BEGIN ADC3_Init 2 */ /* USER CODE END ADC3_Init 2 */ @@ -980,6 +1080,9 @@ static void MX_DMA_Init(void) /* DMA1_Stream0_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0); HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn); + /* DMA1_Stream2_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn); } diff --git a/CM7/Core/Src/stm32h7xx_hal_msp.c b/CM7/Core/Src/stm32h7xx_hal_msp.c index 63d7120..a3cad01 100644 --- a/CM7/Core/Src/stm32h7xx_hal_msp.c +++ b/CM7/Core/Src/stm32h7xx_hal_msp.c @@ -26,6 +26,8 @@ /* USER CODE END Includes */ extern DMA_HandleTypeDef hdma_adc1; +extern DMA_HandleTypeDef hdma_adc3; + /* Private typedef -----------------------------------------------------------*/ /* USER CODE BEGIN TD */ @@ -178,6 +180,25 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PC3, SYSCFG_SWITCH_PC3_OPEN); + /* ADC3 DMA Init */ + /* ADC3 Init */ + hdma_adc3.Instance = DMA1_Stream2; + hdma_adc3.Init.Request = DMA_REQUEST_ADC3; + hdma_adc3.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_adc3.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_adc3.Init.MemInc = DMA_MINC_ENABLE; + hdma_adc3.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; + hdma_adc3.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; + hdma_adc3.Init.Mode = DMA_NORMAL; + hdma_adc3.Init.Priority = DMA_PRIORITY_HIGH; + hdma_adc3.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_adc3) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc3); + /* USER CODE BEGIN ADC3_MspInit 1 */ /* USER CODE END ADC3_MspInit 1 */ @@ -242,6 +263,8 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0|GPIO_PIN_1); + /* ADC3 DMA DeInit */ + HAL_DMA_DeInit(hadc->DMA_Handle); /* USER CODE BEGIN ADC3_MspDeInit 1 */ /* USER CODE END ADC3_MspDeInit 1 */ diff --git a/CM7/Core/Src/stm32h7xx_it.c b/CM7/Core/Src/stm32h7xx_it.c index 273abf6..15636eb 100644 --- a/CM7/Core/Src/stm32h7xx_it.c +++ b/CM7/Core/Src/stm32h7xx_it.c @@ -58,6 +58,7 @@ /* External variables --------------------------------------------------------*/ extern DMA_HandleTypeDef hdma_adc1; +extern DMA_HandleTypeDef hdma_adc3; /* USER CODE BEGIN EV */ /* USER CODE END EV */ @@ -196,6 +197,20 @@ void DMA1_Stream0_IRQHandler(void) /* USER CODE END DMA1_Stream0_IRQn 1 */ } +/** + * @brief This function handles DMA1 stream2 global interrupt. + */ +void DMA1_Stream2_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Stream2_IRQn 0 */ + + /* USER CODE END DMA1_Stream2_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_adc3); + /* USER CODE BEGIN DMA1_Stream2_IRQn 1 */ + + /* USER CODE END DMA1_Stream2_IRQn 1 */ +} + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/Makefile/CM4/Makefile b/Makefile/CM4/Makefile index 31f0d5f..979c53c 100644 --- a/Makefile/CM4/Makefile +++ b/Makefile/CM4/Makefile @@ -1,5 +1,5 @@ ########################################################################################################################## -# File automatically-generated by tool: [projectgenerator] version: [4.2.0-B44] date: [Fri Feb 23 17:55:52 EST 2024] +# File automatically-generated by tool: [projectgenerator] version: [4.2.0-B44] date: [Wed Mar 13 17:13:51 EDT 2024] ########################################################################################################################## # ------------------------------------------------ diff --git a/Makefile/CM7/Makefile b/Makefile/CM7/Makefile index c29ca83..531ceac 100644 --- a/Makefile/CM7/Makefile +++ b/Makefile/CM7/Makefile @@ -1,5 +1,5 @@ ########################################################################################################################## -# File automatically-generated by tool: [projectgenerator] version: [4.2.0-B44] date: [Fri Feb 23 17:55:53 EST 2024] +# File automatically-generated by tool: [projectgenerator] version: [4.2.0-B44] date: [Wed Mar 13 17:13:51 EDT 2024] ########################################################################################################################## # ------------------------------------------------ diff --git a/proteus.ioc b/proteus.ioc index f16fdd8..385ad5a 100644 --- a/proteus.ioc +++ b/proteus.ioc @@ -1,19 +1,76 @@ #MicroXplorer Configuration settings - do not modify ADC1.Channel-1\#ChannelRegularConversion=ADC_CHANNEL_3 -ADC1.IPParameters=Rank-1\#ChannelRegularConversion,Channel-1\#ChannelRegularConversion,SamplingTime-1\#ChannelRegularConversion,OffsetNumber-1\#ChannelRegularConversion,OffsetSignedSaturation-1\#ChannelRegularConversion,NbrOfConversionFlag,master +ADC1.Channel-2\#ChannelRegularConversion=ADC_CHANNEL_4 +ADC1.Channel-3\#ChannelRegularConversion=ADC_CHANNEL_5 +ADC1.Channel-4\#ChannelRegularConversion=ADC_CHANNEL_7 +ADC1.Channel-5\#ChannelRegularConversion=ADC_CHANNEL_8 +ADC1.Channel-6\#ChannelRegularConversion=ADC_CHANNEL_9 +ADC1.IPParameters=Rank-1\#ChannelRegularConversion,Channel-1\#ChannelRegularConversion,SamplingTime-1\#ChannelRegularConversion,OffsetNumber-1\#ChannelRegularConversion,OffsetSignedSaturation-1\#ChannelRegularConversion,NbrOfConversionFlag,master,Rank-2\#ChannelRegularConversion,Channel-2\#ChannelRegularConversion,SamplingTime-2\#ChannelRegularConversion,OffsetNumber-2\#ChannelRegularConversion,OffsetSignedSaturation-2\#ChannelRegularConversion,Rank-3\#ChannelRegularConversion,Channel-3\#ChannelRegularConversion,SamplingTime-3\#ChannelRegularConversion,OffsetNumber-3\#ChannelRegularConversion,OffsetSignedSaturation-3\#ChannelRegularConversion,NbrOfConversion,Rank-4\#ChannelRegularConversion,Channel-4\#ChannelRegularConversion,SamplingTime-4\#ChannelRegularConversion,OffsetNumber-4\#ChannelRegularConversion,OffsetSignedSaturation-4\#ChannelRegularConversion,Rank-5\#ChannelRegularConversion,Channel-5\#ChannelRegularConversion,SamplingTime-5\#ChannelRegularConversion,OffsetNumber-5\#ChannelRegularConversion,OffsetSignedSaturation-5\#ChannelRegularConversion,Rank-6\#ChannelRegularConversion,Channel-6\#ChannelRegularConversion,SamplingTime-6\#ChannelRegularConversion,OffsetNumber-6\#ChannelRegularConversion,OffsetSignedSaturation-6\#ChannelRegularConversion +ADC1.NbrOfConversion=6 ADC1.NbrOfConversionFlag=1 ADC1.OffsetNumber-1\#ChannelRegularConversion=ADC_OFFSET_NONE +ADC1.OffsetNumber-2\#ChannelRegularConversion=ADC_OFFSET_NONE +ADC1.OffsetNumber-3\#ChannelRegularConversion=ADC_OFFSET_NONE +ADC1.OffsetNumber-4\#ChannelRegularConversion=ADC_OFFSET_NONE +ADC1.OffsetNumber-5\#ChannelRegularConversion=ADC_OFFSET_NONE +ADC1.OffsetNumber-6\#ChannelRegularConversion=ADC_OFFSET_NONE ADC1.OffsetSignedSaturation-1\#ChannelRegularConversion=DISABLE +ADC1.OffsetSignedSaturation-2\#ChannelRegularConversion=DISABLE +ADC1.OffsetSignedSaturation-3\#ChannelRegularConversion=DISABLE +ADC1.OffsetSignedSaturation-4\#ChannelRegularConversion=DISABLE +ADC1.OffsetSignedSaturation-5\#ChannelRegularConversion=DISABLE +ADC1.OffsetSignedSaturation-6\#ChannelRegularConversion=DISABLE ADC1.Rank-1\#ChannelRegularConversion=1 +ADC1.Rank-2\#ChannelRegularConversion=2 +ADC1.Rank-3\#ChannelRegularConversion=3 +ADC1.Rank-4\#ChannelRegularConversion=4 +ADC1.Rank-5\#ChannelRegularConversion=5 +ADC1.Rank-6\#ChannelRegularConversion=6 ADC1.SamplingTime-1\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5 +ADC1.SamplingTime-2\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5 +ADC1.SamplingTime-3\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5 +ADC1.SamplingTime-4\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5 +ADC1.SamplingTime-5\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5 +ADC1.SamplingTime-6\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5 ADC1.master=1 ADC3.Channel-2\#ChannelRegularConversion=ADC_CHANNEL_1 -ADC3.IPParameters=Rank-2\#ChannelRegularConversion,Channel-2\#ChannelRegularConversion,SamplingTime-2\#ChannelRegularConversion,OffsetNumber-2\#ChannelRegularConversion,OffsetSignedSaturation-2\#ChannelRegularConversion,NbrOfConversionFlag +ADC3.Channel-3\#ChannelRegularConversion=ADC_CHANNEL_2 +ADC3.Channel-4\#ChannelRegularConversion=ADC_CHANNEL_3 +ADC3.Channel-5\#ChannelRegularConversion=ADC_CHANNEL_7 +ADC3.Channel-6\#ChannelRegularConversion=ADC_CHANNEL_8 +ADC3.Channel-7\#ChannelRegularConversion=ADC_CHANNEL_10 +ADC3.Channel-8\#ChannelRegularConversion=ADC_CHANNEL_11 +ADC3.IPParameters=Rank-2\#ChannelRegularConversion,Channel-2\#ChannelRegularConversion,SamplingTime-2\#ChannelRegularConversion,OffsetNumber-2\#ChannelRegularConversion,OffsetSignedSaturation-2\#ChannelRegularConversion,NbrOfConversionFlag,Rank-3\#ChannelRegularConversion,Channel-3\#ChannelRegularConversion,SamplingTime-3\#ChannelRegularConversion,OffsetNumber-3\#ChannelRegularConversion,OffsetSignedSaturation-3\#ChannelRegularConversion,Rank-4\#ChannelRegularConversion,Channel-4\#ChannelRegularConversion,SamplingTime-4\#ChannelRegularConversion,OffsetNumber-4\#ChannelRegularConversion,OffsetSignedSaturation-4\#ChannelRegularConversion,Rank-5\#ChannelRegularConversion,Channel-5\#ChannelRegularConversion,SamplingTime-5\#ChannelRegularConversion,OffsetNumber-5\#ChannelRegularConversion,OffsetSignedSaturation-5\#ChannelRegularConversion,Rank-6\#ChannelRegularConversion,Channel-6\#ChannelRegularConversion,SamplingTime-6\#ChannelRegularConversion,OffsetNumber-6\#ChannelRegularConversion,OffsetSignedSaturation-6\#ChannelRegularConversion,Rank-7\#ChannelRegularConversion,Channel-7\#ChannelRegularConversion,SamplingTime-7\#ChannelRegularConversion,OffsetNumber-7\#ChannelRegularConversion,OffsetSignedSaturation-7\#ChannelRegularConversion,NbrOfConversion,Rank-8\#ChannelRegularConversion,Channel-8\#ChannelRegularConversion,SamplingTime-8\#ChannelRegularConversion,OffsetNumber-8\#ChannelRegularConversion,OffsetSignedSaturation-8\#ChannelRegularConversion +ADC3.NbrOfConversion=7 ADC3.NbrOfConversionFlag=1 ADC3.OffsetNumber-2\#ChannelRegularConversion=ADC_OFFSET_NONE +ADC3.OffsetNumber-3\#ChannelRegularConversion=ADC_OFFSET_NONE +ADC3.OffsetNumber-4\#ChannelRegularConversion=ADC_OFFSET_NONE +ADC3.OffsetNumber-5\#ChannelRegularConversion=ADC_OFFSET_NONE +ADC3.OffsetNumber-6\#ChannelRegularConversion=ADC_OFFSET_NONE +ADC3.OffsetNumber-7\#ChannelRegularConversion=ADC_OFFSET_NONE +ADC3.OffsetNumber-8\#ChannelRegularConversion=ADC_OFFSET_NONE ADC3.OffsetSignedSaturation-2\#ChannelRegularConversion=DISABLE +ADC3.OffsetSignedSaturation-3\#ChannelRegularConversion=DISABLE +ADC3.OffsetSignedSaturation-4\#ChannelRegularConversion=DISABLE +ADC3.OffsetSignedSaturation-5\#ChannelRegularConversion=DISABLE +ADC3.OffsetSignedSaturation-6\#ChannelRegularConversion=DISABLE +ADC3.OffsetSignedSaturation-7\#ChannelRegularConversion=DISABLE +ADC3.OffsetSignedSaturation-8\#ChannelRegularConversion=DISABLE ADC3.Rank-2\#ChannelRegularConversion=1 +ADC3.Rank-3\#ChannelRegularConversion=2 +ADC3.Rank-4\#ChannelRegularConversion=3 +ADC3.Rank-5\#ChannelRegularConversion=4 +ADC3.Rank-6\#ChannelRegularConversion=5 +ADC3.Rank-7\#ChannelRegularConversion=6 +ADC3.Rank-8\#ChannelRegularConversion=7 ADC3.SamplingTime-2\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5 +ADC3.SamplingTime-3\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5 +ADC3.SamplingTime-4\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5 +ADC3.SamplingTime-5\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5 +ADC3.SamplingTime-6\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5 +ADC3.SamplingTime-7\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5 +ADC3.SamplingTime-8\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5 CAD.formats= CAD.pinconfig= CAD.provider= @@ -37,8 +94,27 @@ Dma.ADC1.0.SyncEnable=DISABLE Dma.ADC1.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT Dma.ADC1.0.SyncRequestNumber=1 Dma.ADC1.0.SyncSignalID=NONE +Dma.ADC3.1.Direction=DMA_PERIPH_TO_MEMORY +Dma.ADC3.1.EventEnable=DISABLE +Dma.ADC3.1.FIFOMode=DMA_FIFOMODE_DISABLE +Dma.ADC3.1.Instance=DMA1_Stream2 +Dma.ADC3.1.MemDataAlignment=DMA_MDATAALIGN_HALFWORD +Dma.ADC3.1.MemInc=DMA_MINC_ENABLE +Dma.ADC3.1.Mode=DMA_NORMAL +Dma.ADC3.1.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD +Dma.ADC3.1.PeriphInc=DMA_PINC_DISABLE +Dma.ADC3.1.Polarity=HAL_DMAMUX_REQ_GEN_RISING +Dma.ADC3.1.Priority=DMA_PRIORITY_HIGH +Dma.ADC3.1.RequestNumber=1 +Dma.ADC3.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber +Dma.ADC3.1.SignalID=NONE +Dma.ADC3.1.SyncEnable=DISABLE +Dma.ADC3.1.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT +Dma.ADC3.1.SyncRequestNumber=1 +Dma.ADC3.1.SyncSignalID=NONE Dma.Request0=ADC1 -Dma.RequestsNb=1 +Dma.Request1=ADC3 +Dma.RequestsNb=2 FDCAN1.CalculateBaudRateNominal=625000 FDCAN1.CalculateTimeBitNominal=1600 FDCAN1.CalculateTimeQuantumNominal=320.0 @@ -175,6 +251,7 @@ MxCube.Version=6.10.0 MxDb.Version=DB.6.0.100 NVIC1.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false NVIC1.DMA1_Stream0_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true +NVIC1.DMA1_Stream2_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true NVIC1.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false NVIC1.ForceEnableDMAVector=true NVIC1.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false From 1b543ff4def77ca37069294ac115d236fa5e1aa6 Mon Sep 17 00:00:00 2001 From: nwdepatie Date: Wed, 13 Mar 2024 17:18:50 -0400 Subject: [PATCH 6/8] Adding in initialization of gatedrivers in main --- CM7/Core/Src/main.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/CM7/Core/Src/main.c b/CM7/Core/Src/main.c index 42de874..dc40275 100644 --- a/CM7/Core/Src/main.c +++ b/CM7/Core/Src/main.c @@ -24,6 +24,7 @@ /* USER CODE BEGIN Includes */ #include "proteus_config.h" +#include "gatedriver.h" /* USER CODE END Includes */ @@ -184,7 +185,10 @@ Error_Handler(); osKernelInitialize(); /* USER CODE BEGIN RTOS_MUTEX */ - /* add mutexes, ... */ + //lmao we aren't adding mutexes here but need to init stuff after the kernel initializes + + gatedriver_t *gatedrv_left = gatedrv_init(&htim1, &hadc1, &hspi1); + gatedriver_t *gatedrv_right = gatedrv_init(&htim2, &hadc3, &hspi3); /* USER CODE END RTOS_MUTEX */ /* USER CODE BEGIN RTOS_SEMAPHORES */ From 51263a76e64e600cb6397582f4e09906a85d0724 Mon Sep 17 00:00:00 2001 From: nwdepatie Date: Wed, 13 Mar 2024 17:27:46 -0400 Subject: [PATCH 7/8] Modifying enums to follow ADC DMA indices --- CM7/Core/Inc/gatedriver.h | 30 ++++++++++++++++++++++++------ CM7/Core/Src/gatedriver.c | 11 +++++------ 2 files changed, 29 insertions(+), 12 deletions(-) diff --git a/CM7/Core/Inc/gatedriver.h b/CM7/Core/Inc/gatedriver.h index 65916b2..d462b38 100644 --- a/CM7/Core/Inc/gatedriver.h +++ b/CM7/Core/Inc/gatedriver.h @@ -9,22 +9,33 @@ #define MAX_ADC_BUF 7 +/* + * Note that these phases readings should ALWAYS be mapped to the corresponding indices + * Ensure the ADC DMA is mapped the same across boards + */ enum { - PHASE_U, - PHASE_V, - PHASE_W, - NUM_PHASES + GATEDRV_PHASE_U, + GATEDRV_PHASE_V, + GATEDRV_PHASE_W, + GATEDRV_NUM_PHASES }; +enum { + GATEDRV_DC_CURRENT = GATEDRV_NUM_PHASES, /* Keep index rolling from phase enum */ + GATEDRV_IGBT_TEMP, + SIZE_OF_ADC_DMA +}; + +/* Definition of gatedriver struct */ typedef struct { TIM_HandleTypeDef* tim; osMutexId_t* tim_mutex; TIM_OC_InitTypeDef* pwm_cfg; - uint32_t pulses[NUM_PHASES]; + uint32_t pulses[GATEDRV_NUM_PHASES]; ADC_HandleTypeDef *hdma_adc; SPI_HandleTypeDef *adc_spi; - uint32_t intern_adc_buffer[MAX_ADC_BUF]; + uint32_t intern_adc_buffer[SIZE_OF_ADC_DMA]; osMutexId_t* tim_mutex_mutex; osMutexAttr_t tim_mutex_attr; @@ -32,15 +43,22 @@ typedef struct { osMutexAttr_t ext_adc_mutex_attr; } gatedriver_t; +/* initialize a new gatedriver */ gatedriver_t* gatedrv_init(TIM_HandleTypeDef* tim, ADC_HandleTypeDef *hdma_adc, SPI_HandleTypeDef *adc_spi); +/* read the dc voltage (V) */ int16_t gatedrv_read_dc_voltage(gatedriver_t* drv); +/* read the dc current (A) */ int16_t gatedrv_read_dc_current(gatedriver_t* drv); /* Note: This has to atomically write to ALL PWM registers */ int16_t gatedrv_write_pwm(gatedriver_t* drv, float duty_cycles[]); +/* read the internal IGBT temp */ int16_t gatedrv_read_igbt_temp(gatedriver_t* drv); +/* read the currents of each phase */ +void gatedrv_get_phase_currents(gatedriver_t* drv, int16_t current_buf[GATEDRV_NUM_PHASES]); + #endif /* GATEDRIVER_H */ diff --git a/CM7/Core/Src/gatedriver.c b/CM7/Core/Src/gatedriver.c index c07b543..baf5c4e 100644 --- a/CM7/Core/Src/gatedriver.c +++ b/CM7/Core/Src/gatedriver.c @@ -68,12 +68,11 @@ gatedriver_t* gatedrv_init(TIM_HandleTypeDef* tim, ADC_HandleTypeDef *hdma_adc, return gatedriver; } -void gatedrv_get_phase_currents(gatedriver_t* drv, int16_t current_buf[]) +void gatedrv_get_phase_currents(gatedriver_t* drv, int16_t current_buf[GATEDRV_NUM_PHASES]) { - //TODO: Ensure the ADC DMA is mapped the same across boards - current_buf[PHASE_U] = drv->intern_adc_buffer[0]; - current_buf[PHASE_V] = drv->intern_adc_buffer[1]; - current_buf[PHASE_W] = drv->intern_adc_buffer[2]; + current_buf[GATEDRV_PHASE_U] = drv->intern_adc_buffer[GATEDRV_PHASE_U]; + current_buf[GATEDRV_PHASE_V] = drv->intern_adc_buffer[GATEDRV_PHASE_V]; + current_buf[GATEDRV_PHASE_W] = drv->intern_adc_buffer[GATEDRV_PHASE_W]; } int16_t gatedrv_read_dc_voltage(gatedriver_t* drv) @@ -87,7 +86,7 @@ int16_t gatedrv_read_dc_current(gatedriver_t* drv) } /* Note: This has to atomically write to ALL PWM registers */ -int16_t gatedrv_write_pwm(gatedriver_t* drv, float duty_cycles[]) +int16_t gatedrv_write_pwm(gatedriver_t* drv, float duty_cycles[GATEDRV_NUM_PHASES]) { /* Acquiring mutex lock */ osStatus_t mut_stat = osMutexAcquire(drv->tim_mutex, osWaitForever); From e045ccce34cf299a4a7248a35fa6940e3810412c Mon Sep 17 00:00:00 2001 From: nwdepatie Date: Wed, 13 Mar 2024 17:34:13 -0400 Subject: [PATCH 8/8] Removing unnecessary macro --- CM7/Core/Inc/gatedriver.h | 6 ++---- CM7/Core/Src/gatedriver.c | 2 +- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/CM7/Core/Inc/gatedriver.h b/CM7/Core/Inc/gatedriver.h index d462b38..96731a0 100644 --- a/CM7/Core/Inc/gatedriver.h +++ b/CM7/Core/Inc/gatedriver.h @@ -7,8 +7,6 @@ #include #include -#define MAX_ADC_BUF 7 - /* * Note that these phases readings should ALWAYS be mapped to the corresponding indices * Ensure the ADC DMA is mapped the same across boards @@ -23,7 +21,7 @@ enum { enum { GATEDRV_DC_CURRENT = GATEDRV_NUM_PHASES, /* Keep index rolling from phase enum */ GATEDRV_IGBT_TEMP, - SIZE_OF_ADC_DMA + GATEDRV_SIZE_OF_ADC_DMA }; /* Definition of gatedriver struct */ @@ -35,7 +33,7 @@ typedef struct { ADC_HandleTypeDef *hdma_adc; SPI_HandleTypeDef *adc_spi; - uint32_t intern_adc_buffer[SIZE_OF_ADC_DMA]; + uint32_t intern_adc_buffer[GATEDRV_SIZE_OF_ADC_DMA]; osMutexId_t* tim_mutex_mutex; osMutexAttr_t tim_mutex_attr; diff --git a/CM7/Core/Src/gatedriver.c b/CM7/Core/Src/gatedriver.c index baf5c4e..e34fd6d 100644 --- a/CM7/Core/Src/gatedriver.c +++ b/CM7/Core/Src/gatedriver.c @@ -56,7 +56,7 @@ gatedriver_t* gatedrv_init(TIM_HandleTypeDef* tim, ADC_HandleTypeDef *hdma_adc, gatedriver->pwm_cfg = &pwm_cfg; /* Configure DMA */ - assert(HAL_ADC_Start_DMA(gatedriver->hdma_adc, gatedriver->intern_adc_buffer, MAX_ADC_BUF)); + assert(HAL_ADC_Start_DMA(gatedriver->hdma_adc, gatedriver->intern_adc_buffer, GATEDRV_SIZE_OF_ADC_DMA)); /* Create Mutexes */ gatedriver->tim_mutex = osMutexNew(&gatedriver->tim_mutex_attr);