From dd56025b8a80a2b7ee13f73867191ee406068686 Mon Sep 17 00:00:00 2001 From: Kristopher King Date: Wed, 31 May 2017 12:28:09 -0500 Subject: [PATCH] Changes to support release 1.2.2 --- FAQs.md | 6 +- RELEASE_NOTES.md | 7 +- .../build/scripts/.critical_warnings | 2 +- .../cl_dram_dma/design/cl_dram_dma.sv | 4 +- .../cl_dram_dma/design/cl_dram_dma_defines.vh | 4 +- .../cl_dram_dma/verif/scripts/top.questa.f | 2 +- .../cl_dram_dma/verif/scripts/top.vcs.f | 2 +- .../cl_dram_dma/verif/scripts/top.vivado.f | 2 +- .../cl_hello_world/design/cl_hello_world.sv | 8 +- .../design/cl_hello_world_defines.vh | 4 +- .../build/scripts/aws_build_dcp_from_cl.sh | 10 +-- .../build/scripts/aws_clock_properties.tcl | 40 ++++++++++ .../build/scripts/aws_gen_clk_constraints.tcl | 36 +++++++++ .../new_cl_template/build/README.md | 6 +- hdk/docs/Programmer_View.md | 4 +- hdk/docs/clock_recipes.csv | 6 ++ hdk/hdk_version.txt | 2 +- sdk/README.md | 8 -- sdk/sdk_install.sh | 13 +++- sdk/userspace/fpga_libs/fpga_mgmt/Makefile | 5 +- .../fpga_libs/fpga_mgmt/fpga_mgmt_cmd.c | 2 +- sdk/userspace/fpga_libs/fpga_pci/fpga_pci.c | 9 ++- sdk/userspace/fpga_mgmt_tools/README.md | 4 +- .../fpga_mgmt_tools/src/fpga_local_cmd.c | 3 + sdk/userspace/install_fpga_mgmt_tools.sh | 73 ++++++++++++++++--- 25 files changed, 205 insertions(+), 57 deletions(-) diff --git a/FAQs.md b/FAQs.md index 9f7d92a0d..99fb836d0 100644 --- a/FAQs.md +++ b/FAQs.md @@ -204,7 +204,7 @@ We encourage you to use the [AWS FPGA Developer Forum](https://forums.aws.amazon The required AWS software is the [FPGA Management Tool set](./sdk/userspace/fpga_mgmt_tools). This software manages loading and clearing AFIs for the instance FPGAs. It also allows developers to retrieve FPGAs status from within the instance. Users will need to load the F1 AMI with the drivers and runtime libraries needed for their FPGA application. -Typically, you will not need the HDK nor any Xilinx Vivado tools on an F1 instance that is using prebuilt AFIs; unless, you want to do in-field debug using Vivado's ChipScope. +Typically, you will not need the HDK nor any Xilinx Vivado tools on an F1 instance that is using prebuilt AFIs; unless, you want to do in-field debug using Vivado's ChipScope (Virtual JTAG). ## Marketplace @@ -235,7 +235,7 @@ There are two types of interfaces from the instance host CPU to the FPGAs: The first is the FPGA Image Management Tools. These APIs are detailed in the [SDK portion](./sdk/userspace/fpga_mgmt_tools) of the GitHub repository. FPGA Image Management Tools include APIs to load, clear, and get status of the FPGA. -The second type of interface is direct address access to the Application PCIe Physical Functions (PF) of the FPGA. There is no API for this access. Rather, there is direct access to resources in the Custom Logic (CL) region or Shell that can be accessed by software written on the instance. For example, the ChipScope software uses address space in a PF to provide FPGA debug support. Developers can create any API to the resources in their CL. See the [Shell Interface Specification](./hdk/docs/AWS_Shell_Interface_Specification.md) for more details on the address space mapping as seen from the instance. +The second type of interface is direct address access to the Application PCIe Physical Functions (PF) of the FPGA. There is no API for this access. Rather, there is direct access to resources in the Custom Logic (CL) region or Shell that can be accessed by software written on the instance. For example, the ChipScope software (Virtual JTAG) uses address space in a PF to provide FPGA debug support. Developers can create any API to the resources in their CL. See the [Shell Interface Specification](./hdk/docs/AWS_Shell_Interface_Specification.md) for more details on the address space mapping as seen from the instance. @@ -379,7 +379,7 @@ Yes. The HDK includes a simulation model for the AWS shell. See the [HDK common **Q: What resources within the FPGA does the AWS Shell consume?** -The Shell consumes about 20% of the FPGA resources, and that includes the PCIe Gen3 X16, DMA engine, DRAM controller interface, ChipScope and other health monitoring and image loading logic. No modifications to the Shell or the partition pins between the Shell and the Custom Logic are possible by the FPGA developer. +The Shell consumes about 20% of the FPGA resources, and that includes the PCIe Gen3 X16, DMA engine, DRAM controller interface, ChipScope (Virtual JTAG) and other health monitoring and image loading logic. No modifications to the Shell or the partition pins between the Shell and the Custom Logic are possible by the FPGA developer. diff --git a/RELEASE_NOTES.md b/RELEASE_NOTES.md index 80c4b4529..8d2296c9e 100644 --- a/RELEASE_NOTES.md +++ b/RELEASE_NOTES.md @@ -26,12 +26,17 @@ * 1 DDR controller implemented in the SH (always available) * 3 DDR controllers implemented in the CL (configurable number of implemented controllers allowed) +# Release 1.2.1 + * Expanded [clock recipes](./hdk/docs/clock_recipes.csv) + * Virtual JTAG documentation updates + * Included encryption of .sv files for CL examples + # Release 1.2.1 * Updated CL example build scripts with Prohibit URAM sites * EDMA Performance improvments * Expanded EC2 Instance type support * CL Examples @250Mhz (Clock recipe A1) - * Option to exclude chipscope from building CL examples (DISABLE_CHIPSCOPE_DEBUG) + * Option to exclude Chipscope (Virtual JTAG) from building CL examples (DISABLE_VJTAG_DEBUG) # Release 1.2.0 diff --git a/hdk/cl/examples/cl_dram_dma/build/scripts/.critical_warnings b/hdk/cl/examples/cl_dram_dma/build/scripts/.critical_warnings index 2d73b5e3b..492dff089 100644 --- a/hdk/cl/examples/cl_dram_dma/build/scripts/.critical_warnings +++ b/hdk/cl/examples/cl_dram_dma/build/scripts/.critical_warnings @@ -1 +1 @@ -152 \ No newline at end of file +152 diff --git a/hdk/cl/examples/cl_dram_dma/design/cl_dram_dma.sv b/hdk/cl/examples/cl_dram_dma/design/cl_dram_dma.sv index 7d2b0d82f..2cb890206 100644 --- a/hdk/cl/examples/cl_dram_dma/design/cl_dram_dma.sv +++ b/hdk/cl/examples/cl_dram_dma/design/cl_dram_dma.sv @@ -720,7 +720,7 @@ cl_sda_slv CL_SDA_SLV ( //----------------------------------------- -`ifndef DISABLE_CHIPSCOPE_DEBUG +`ifndef DISABLE_VJTAG_DEBUG cl_ila CL_ILA ( @@ -751,7 +751,7 @@ cl_vio CL_VIO ( ); -`endif // `ifndef DISABLE_CHIPSCOPE_DEBUG +`endif // `ifndef DISABLE_VJTAG_DEBUG //----------------------------------------- // Virtual JATG ILA Debug core example diff --git a/hdk/cl/examples/cl_dram_dma/design/cl_dram_dma_defines.vh b/hdk/cl/examples/cl_dram_dma/design/cl_dram_dma_defines.vh index 034ee3a2e..7ce3610c2 100644 --- a/hdk/cl/examples/cl_dram_dma/design/cl_dram_dma_defines.vh +++ b/hdk/cl/examples/cl_dram_dma/design/cl_dram_dma_defines.vh @@ -27,8 +27,8 @@ //uncomment below to make SH and CL async `define SH_CL_ASYNC -// Uncomment to disable Chipscope -//`define DISABLE_CHIPSCOPE_DEBUG +// Uncomment to disable Virtual JTAG +//`define DISABLE_VJTAG_DEBUG `endif diff --git a/hdk/cl/examples/cl_dram_dma/verif/scripts/top.questa.f b/hdk/cl/examples/cl_dram_dma/verif/scripts/top.questa.f index e79efe8c2..be8ad0d85 100644 --- a/hdk/cl/examples/cl_dram_dma/verif/scripts/top.questa.f +++ b/hdk/cl/examples/cl_dram_dma/verif/scripts/top.questa.f @@ -49,7 +49,7 @@ ${SH_LIB_DIR}/bram_2rw.sv ${SH_LIB_DIR}/flop_fifo.sv -+define+DISABLE_CHIPSCOPE_DEBUG ++define+DISABLE_VJTAG_DEBUG ${CL_ROOT}/design/axil_slave.sv ${CL_ROOT}/design/cl_dram_dma_defines.vh ${CL_ROOT}/design/cl_tst_scrb.sv diff --git a/hdk/cl/examples/cl_dram_dma/verif/scripts/top.vcs.f b/hdk/cl/examples/cl_dram_dma/verif/scripts/top.vcs.f index d338530c2..7aa15d70b 100644 --- a/hdk/cl/examples/cl_dram_dma/verif/scripts/top.vcs.f +++ b/hdk/cl/examples/cl_dram_dma/verif/scripts/top.vcs.f @@ -45,7 +45,7 @@ ${SH_LIB_DIR}/../ip/axi_register_slice/sim/axi_register_slice.v ${SH_LIB_DIR}/../ip/axi_register_slice_light/sim/axi_register_slice_light.v -+define+DISABLE_CHIPSCOPE_DEBUG ++define+DISABLE_VJTAG_DEBUG ${CL_ROOT}/design/axil_slave.sv ${CL_ROOT}/design/cl_dram_dma_defines.vh ${CL_ROOT}/design/cl_tst_scrb.sv diff --git a/hdk/cl/examples/cl_dram_dma/verif/scripts/top.vivado.f b/hdk/cl/examples/cl_dram_dma/verif/scripts/top.vivado.f index 83b2b05ef..13a63aacb 100644 --- a/hdk/cl/examples/cl_dram_dma/verif/scripts/top.vivado.f +++ b/hdk/cl/examples/cl_dram_dma/verif/scripts/top.vivado.f @@ -47,7 +47,7 @@ ${SH_LIB_DIR}/../ip/axi_register_slice/sim/axi_register_slice.v ${SH_LIB_DIR}/../ip/axi_register_slice_light/sim/axi_register_slice_light.v ---define DISABLE_CHIPSCOPE_DEBUG +--define DISABLE_VJTAG_DEBUG ${CL_ROOT}/design/axil_slave.sv ${CL_ROOT}/design/cl_dram_dma_defines.vh ${CL_ROOT}/design/cl_tst_scrb.sv diff --git a/hdk/cl/examples/cl_hello_world/design/cl_hello_world.sv b/hdk/cl/examples/cl_hello_world/design/cl_hello_world.sv index da909788b..75c1ec223 100644 --- a/hdk/cl/examples/cl_hello_world/design/cl_hello_world.sv +++ b/hdk/cl/examples/cl_hello_world/design/cl_hello_world.sv @@ -328,9 +328,9 @@ assign pre_cl_sh_status_vled[15:0] = vled_q[15:0] & sh_cl_status_vdip_q2[15:0]; assign cl_sh_status1[31:0] = `CL_VERSION; //----------------------------------------------- -// Debug bridge, used if need chipscope +// Debug bridge, used if need Virtual JTAG //----------------------------------------------- -`ifndef DISABLE_CHIPSCOPE_DEBUG +`ifndef DISABLE_VJTAG_DEBUG // Flop for timing global clock counter logic[63:0] sh_cl_glcount0_q; @@ -381,7 +381,7 @@ always_ff @(posedge clk_main_a0) ); //----------------------------------------------- -// VIO Example - Needs Chipscope +// VIO Example - Needs Virtual JTAG //----------------------------------------------- // Counter running at 125MHz @@ -465,7 +465,7 @@ always_ff @(posedge clk_main_a0) .probe10 (vo_cnt_watermark_q) ); -`endif // `ifndef DISABLE_CHIPSCOPE_DEBUG +`endif // `ifndef DISABLE_VJTAG_DEBUG endmodule diff --git a/hdk/cl/examples/cl_hello_world/design/cl_hello_world_defines.vh b/hdk/cl/examples/cl_hello_world/design/cl_hello_world_defines.vh index 7b689be20..ca2cd2904 100644 --- a/hdk/cl/examples/cl_hello_world/design/cl_hello_world_defines.vh +++ b/hdk/cl/examples/cl_hello_world/design/cl_hello_world_defines.vh @@ -23,7 +23,7 @@ // FPGA flop init capability). This will help with routing resources. `define FPGA_LESS_RST -// Uncomment to disable Chipscope -//`define DISABLE_CHIPSCOPE_DEBUG +// Uncomment to disable Virtual JTAG +//`define DISABLE_VJTAG_DEBUG `endif diff --git a/hdk/common/shell_v04151701/build/scripts/aws_build_dcp_from_cl.sh b/hdk/common/shell_v04151701/build/scripts/aws_build_dcp_from_cl.sh index 0fd9e1a2c..59bc0757c 100755 --- a/hdk/common/shell_v04151701/build/scripts/aws_build_dcp_from_cl.sh +++ b/hdk/common/shell_v04151701/build/scripts/aws_build_dcp_from_cl.sh @@ -18,7 +18,7 @@ # Usage help function usage { - echo "usage: aws_build_dcp_from_cl.sh [ [-script ] | [-strategy BASIC | DEFAULT | EXPLORE | TIMING | CONGESTION] [-clock_recipe_a A0 | A1 | A2] [-clock_recipe_b B0 | B1] [-clock_recipe_c C0 | C1] [-foreground] [-notify] | [-h] | [-H] | [-help] | ]" + echo "usage: aws_build_dcp_from_cl.sh [ [-script ] | [-strategy BASIC | DEFAULT | EXPLORE | TIMING | CONGESTION] [-clock_recipe_a A0 | A1 | A2] [-clock_recipe_b B0 | B1 | B2 | B3 | B4 | B5] [-clock_recipe_c C0 | C1 | C2 | C3] [-foreground] [-notify] | [-h] | [-H] | [-help] | ]" echo " " echo "By default the build is run in the background using nohup so that the" echo "process will not be terminated if the terminal window is closed." @@ -123,15 +123,15 @@ fi # Check that clock_recipe_b is valid shopt -s extglob -if [[ $clock_recipe_b != @(B0|B1) ]]; then - err_msg "$clock_recipe_b isn't a valid Clock Group B recipe. Valid Clock Group B recipes are B0 and B1." +if [[ $clock_recipe_b != @(B0|B1|B2|B3|B4|B5) ]]; then + err_msg "$clock_recipe_b isn't a valid Clock Group B recipe. Valid Clock Group B recipes are B0, B1, B2, B3, B4, and B5." exit 1 fi # Check that clock_recipe_c is valid shopt -s extglob -if [[ $clock_recipe_c != @(C0|C1) ]]; then - err_msg "$clock_recipe_c isn't a valid Clock Group C recipe. Valid Clock Group C recipes are C0 and C1." +if [[ $clock_recipe_c != @(C0|C1|C2|C3) ]]; then + err_msg "$clock_recipe_c isn't a valid Clock Group C recipe. Valid Clock Group C recipes are C0, C1, C2, and C3." exit 1 fi diff --git a/hdk/common/shell_v04151701/build/scripts/aws_clock_properties.tcl b/hdk/common/shell_v04151701/build/scripts/aws_clock_properties.tcl index e5022a10d..95b6ca400 100755 --- a/hdk/common/shell_v04151701/build/scripts/aws_clock_properties.tcl +++ b/hdk/common/shell_v04151701/build/scripts/aws_clock_properties.tcl @@ -15,6 +15,8 @@ # Set Clock Group properties based on specified recipe # Clock Group A +set_property CLKFBOUT_MULT_F 6 [get_cells SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] +set_property DIVCLK_DIVIDE 1 [get_cells SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] if {[string compare $clock_recipe_a "A1"] == 0} { set_property CLKOUT0_DIVIDE_F 6 [get_cells SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] set_property CLKOUT1_DIVIDE 12 [get_cells SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] @@ -34,18 +36,56 @@ if {[string compare $clock_recipe_a "A1"] == 0} { # Clock Group B if {[string compare $clock_recipe_b "B1"] == 0} { + set_property CLKFBOUT_MULT_F 5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] + set_property DIVCLK_DIVIDE 1 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] set_property CLKOUT0_DIVIDE_F 10 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] set_property CLKOUT1_DIVIDE 20 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] +} elseif {[string compare $clock_recipe_b "B2"] == 0} { + set_property CLKFBOUT_MULT_F 18 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] + set_property DIVCLK_DIVIDE 5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] + set_property CLKOUT0_DIVIDE_F 2 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] + set_property CLKOUT1_DIVIDE 4 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] +} elseif {[string compare $clock_recipe_b "B3"] == 0} { + set_property CLKFBOUT_MULT_F 5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] + set_property DIVCLK_DIVIDE 1 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] + set_property CLKOUT0_DIVIDE_F 5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] + set_property CLKOUT1_DIVIDE 20 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] +} elseif {[string compare $clock_recipe_b "B4"] == 0} { + set_property CLKFBOUT_MULT_F 24 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] + set_property DIVCLK_DIVIDE 5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] + set_property CLKOUT0_DIVIDE_F 4 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] + set_property CLKOUT1_DIVIDE 16 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] +} elseif {[string compare $clock_recipe_b "B5"] == 0} { + set_property CLKFBOUT_MULT_F 24 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] + set_property DIVCLK_DIVIDE 5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] + set_property CLKOUT0_DIVIDE_F 3 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] + set_property CLKOUT1_DIVIDE 12 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] } else { #B0 + set_property CLKFBOUT_MULT_F 5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] + set_property DIVCLK_DIVIDE 1 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] set_property CLKOUT0_DIVIDE_F 5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] set_property CLKOUT1_DIVIDE 10 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] } # Clock Group C if {[string compare $clock_recipe_c "C1"] == 0} { + set_property CLKFBOUT_MULT_F 24 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] + set_property DIVCLK_DIVIDE 5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] set_property CLKOUT0_DIVIDE_F 8 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] set_property CLKOUT1_DIVIDE 6 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] +} elseif {[string compare $clock_recipe_c "C2"] == 0} { + set_property CLKFBOUT_MULT_F 24 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] + set_property DIVCLK_DIVIDE 5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] + set_property CLKOUT0_DIVIDE_F 16 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] + set_property CLKOUT1_DIVIDE 12 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] +} elseif {[string compare $clock_recipe_c "C3"] == 0} { + set_property CLKFBOUT_MULT_F 16 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] + set_property DIVCLK_DIVIDE 5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] + set_property CLKOUT0_DIVIDE_F 4 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] + set_property CLKOUT1_DIVIDE 3 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] } else { #C0 + set_property CLKFBOUT_MULT_F 24 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] + set_property DIVCLK_DIVIDE 5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] set_property CLKOUT0_DIVIDE_F 4 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] set_property CLKOUT1_DIVIDE 3 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst] } diff --git a/hdk/common/shell_v04151701/build/scripts/aws_gen_clk_constraints.tcl b/hdk/common/shell_v04151701/build/scripts/aws_gen_clk_constraints.tcl index 9fff7e122..415b93ef5 100755 --- a/hdk/common/shell_v04151701/build/scripts/aws_gen_clk_constraints.tcl +++ b/hdk/common/shell_v04151701/build/scripts/aws_gen_clk_constraints.tcl @@ -65,6 +65,30 @@ switch $clock_recipe_b { set clk_extra_b1_period 16 set clk_extra_b1_half_period 8 } + "B2" { + set clk_extra_b0_period 2.222 + set clk_extra_b0_half_period 1.111 + set clk_extra_b1_period 4.444 + set clk_extra_b1_half_period 2.222 + } + "B3" { + set clk_extra_b0_period 4 + set clk_extra_b0_half_period 2 + set clk_extra_b1_period 16 + set clk_extra_b1_half_period 8 + } + "B4" { + set clk_extra_b0_period 3.333 + set clk_extra_b0_half_period 1.667 + set clk_extra_b1_period 13.333 + set clk_extra_b1_half_period 6.667 + } + "B5" { + set clk_extra_b0_period 2.5 + set clk_extra_b0_half_period 1.25 + set clk_extra_b1_period 10 + set clk_extra_b1_half_period 5 + } default { puts "$clock_recipe_b is NOT a valid clock_recipe_b." } @@ -84,6 +108,18 @@ switch $clock_recipe_c { set clk_extra_c1_period 5 set clk_extra_c1_half_period 2.5 } + "C2" { + set clk_extra_c0_period 13.333 + set clk_extra_c0_half_period 6.667 + set clk_extra_c1_period 10 + set clk_extra_c1_half_period 5 + } + "C3" { + set clk_extra_c0_period 5 + set clk_extra_c0_half_period 2.5 + set clk_extra_c1_period 3.75 + set clk_extra_c1_half_period 1.875 + } default { puts "$clock_recipe_c is NOT a valid clock_recipe_c." } diff --git a/hdk/common/shell_v04151701/new_cl_template/build/README.md b/hdk/common/shell_v04151701/new_cl_template/build/README.md index ac28e7260..da72de8d4 100644 --- a/hdk/common/shell_v04151701/new_cl_template/build/README.md +++ b/hdk/common/shell_v04151701/new_cl_template/build/README.md @@ -5,7 +5,7 @@ 1. [Overview of AFI Build process](#buildoverview) 2. [Build procedure step by step](#stepbystep) 3. [Build strategies and parallel builds](#strategies) -4. [About Encrption during build process](#buildencryption) +4. [About Encryption during build process](#buildencryption) 5. [Advanced Notes](#buildadvanced_notes) 6. [Build Frequently Asked Questions](#buildfaq) @@ -61,7 +61,7 @@ The build script performs: #### Build Strategies -In order to help developers close timing goals and successfully build their designs efficiently, the build script provides the means to synthesize with different strategies. The different strategies alter the directives used by the synthesis tool. For example, some directives might specify additional optimizations to close timing, while others may specify less effort to minimize synthesis time for designs that can more easily close timing and area goals. Since every design is different, some strategies may provide better results than anothers. If a developer has trouble successfully building their design with one strategy it is encouraged that they try a different strategy, or run a few strategies in parallel using the FPGA Developer AMI. The strategies are described in more detail below. +In order to help developers close timing goals and successfully build their designs efficiently, the build script provides the means to synthesize with different strategies. The different strategies alter the directives used by the synthesis tool. For example, some directives might specify additional optimizations to close timing, while others may specify less effort to minimize synthesis time for designs that can more easily close timing and area goals. Since every design is different, some strategies may provide better results than another build strategies. If a developer has trouble successfully building their design with one strategy it is encouraged that they try a different strategy, or run a few strategies in parallel using the FPGA Developer AMI. The strategies are described in more detail below. Build script usage: @@ -96,7 +96,7 @@ Options: Strategy descriptions: * BASIC - * This is the basic flow in Vivado and contains the mandatory steps to be able to build a design. It is designed to provide a good balance betwwen runtime and Quality of Results (QOR). + * This is the basic flow in Vivado and contains the mandatory steps to be able to build a design. It is designed to provide a good balance between runtime and Quality of Results (QOR). * EXPLORE * This is a high-effort flow which is designed to give improved QOR results at the expense of runtime. diff --git a/hdk/docs/Programmer_View.md b/hdk/docs/Programmer_View.md index 1298237bb..0c4b1cf66 100644 --- a/hdk/docs/Programmer_View.md +++ b/hdk/docs/Programmer_View.md @@ -10,13 +10,13 @@ There are two parts required to work with AWS FPGA: Management and Runtime, and **\[A\]** As linux shell commands called [FPGA Management Tools](../../sdk/userspace/fpga_mgmt_tools/README.md). - **\[B\]** As a C-library called [FPGA Management Lib](../../sdk/userspace/lib/) to be compiled with the developer's C/C++ application. + **\[B\]** As a C-library called [FPGA Management Lib](../../sdk/userspace/fpga_libs/fpga_mgmt/) to be compiled with the developer's C/C++ application. **\[C\]** Pre-integrated with [OpenCL runtime library](../../sdk/SDAccel) 2. **Runtime code**: required for reading/writing from/to the Custom Logic, handling interrupts, and using the DMA. This is provided by: - **\[D\]** [FPGA PCIe Lib](../../sdk/runtime/lib/) is a C-library used to access the FPGA memory space behind the AppPF PCIe BARs, from Linux application space like reading/writing to register space or passing messages. This library can be compiled and linked with the developer's C/C++ application. + **\[D\]** [FPGA PCIe Lib](../../sdk/userspace/fpga_libs/fpga_pci/) is a C-library used to access the FPGA memory space behind the AppPF PCIe BARs, from Linux application space like reading/writing to register space or passing messages. This library can be compiled and linked with the developer's C/C++ application. **\[E\]** A [DMA Interface](../../sdk/linux_kernel_drivers/edma/edma_README.md) using standard POSIX API like open()/read()/write() to be used in any C/C++ application for data transfer using DMA. This DMA interface requires installing the [AWS EDMA kernel driver](../../sdk/linux_kernel_drivers/edma/edma_install.md) - marked as item **\[G\]**. diff --git a/hdk/docs/clock_recipes.csv b/hdk/docs/clock_recipes.csv index b92b6c95c..4f82247dd 100644 --- a/hdk/docs/clock_recipes.csv +++ b/hdk/docs/clock_recipes.csv @@ -8,9 +8,15 @@ Clock Group B,,,, Recipe Number,clk_extra_b0,clk_extra_b1,, B0,250,125,, B1,125,62.5,, +B2,450,225,, +B3,250,62.5,, +B4,300,75,, +B5,400,100,, ,,,, Clock Group C,,,, Recipe Number,clk_extra_c0,clk_extra_c1,, C0,300,400,, C1,150,200,, +C2,75,100,, +C3,200,266,, diff --git a/hdk/hdk_version.txt b/hdk/hdk_version.txt index 746dd1d88..2ba34f304 100644 --- a/hdk/hdk_version.txt +++ b/hdk/hdk_version.txt @@ -1 +1 @@ -HDK_VERSION=1.2.0 +HDK_VERSION=1.2.2 diff --git a/sdk/README.md b/sdk/README.md index 05216b511..bf430c098 100644 --- a/sdk/README.md +++ b/sdk/README.md @@ -33,11 +33,3 @@ To install gcc with apt-get, execute: $ sudo apt-get update $ sudo apt-get install build-essential ``` - -There is a known bug in the SDK install script for the fpga library (`libfpga_mgmt.so`). To get the tools running, after running `source sdk_setup.sh`, run the following commands to install the library: - -``` -$ cd $SDK_DIR -$ sudo cp userspace/lib/so/libfpga_mgmt.so /usr/local/lib -$ sudo ldconfig -v -``` diff --git a/sdk/sdk_install.sh b/sdk/sdk_install.sh index d7302ae94..11ad4feba 100755 --- a/sdk/sdk_install.sh +++ b/sdk/sdk_install.sh @@ -30,12 +30,21 @@ fi SDK_USERSPACE_DIR=$SDK_DIR/userspace -# Build and install the Amazon FPGA Image (AFI) Management Tools +# Build the Amazon FPGA Image (AFI) Management Tools +(cd $SDK_USERSPACE_DIR && ./mkall_fpga_mgmt_tools.sh) +RET=$? +if [ $RET != 0 ]; then + echo "Error: mkall_fpga_mgmt_tools.sh returned $RET" + exit $RET +fi +echo "Build complete." + +# Install the Amazon FPGA Image (AFI) Management Tools $SDK_USERSPACE_DIR/install_fpga_mgmt_tools.sh RET=$? if [ $RET != 0 ]; then echo "Error: install_fpga_mgmt_tools.sh returned $RET" - exit $RET + exit $RET fi echo "Done with SDK install." diff --git a/sdk/userspace/fpga_libs/fpga_mgmt/Makefile b/sdk/userspace/fpga_libs/fpga_mgmt/Makefile index d2e162521..f31351772 100644 --- a/sdk/userspace/fpga_libs/fpga_mgmt/Makefile +++ b/sdk/userspace/fpga_libs/fpga_mgmt/Makefile @@ -26,7 +26,7 @@ CFLAGS=$(OPT) -g -std=gnu99 -fPIC -Wall -Werror -W -Wno-parentheses -Wstrict-pro SRC = $(wildcard *.c) OBJ = $(SRC:.c=.o) -FPGAMGMTLIB_SO = $(LIB_SO_PATH)/libfpga_mgmt.so +FPGAMGMTLIB_SO = $(LIB_SO_PATH)/libfpga_mgmt.so.1.0.0 FPGAMGMTLIB = $(LIB_PATH)/libfpga_mgmt.a LDLIBS = -lrt -lpthread @@ -43,7 +43,8 @@ $(FPGAMGMTLIB): $(OBJ) $(FPGAMGMTLIB_SO): $(OBJ) mkdir -p $(LIB_SO_PATH) - $(CC) -o $(FPGAMGMTLIB_SO) -shared $(OBJ) -Wl,-soname,libfpga_mgmt.so -Wl,--whole-archive $(FPGAAUXLIBS) -Wl,--no-whole-archive $(LDLIBS) + $(CC) -o $(FPGAMGMTLIB_SO) -shared $(OBJ) -Wl,-soname,libfpga_mgmt.so.1 -Wl,--whole-archive $(FPGAAUXLIBS) -Wl,--no-whole-archive $(LDLIBS) + ln -sf libfpga_mgmt.so.1.0.0 $(LIB_SO_PATH)/libfpga_mgmt.so clean: rm -f *.o $(FPGAMGMTLIB) $(FPGAMGMTLIB_SO) diff --git a/sdk/userspace/fpga_libs/fpga_mgmt/fpga_mgmt_cmd.c b/sdk/userspace/fpga_libs/fpga_mgmt/fpga_mgmt_cmd.c index b2ef23b67..4912ffbb2 100644 --- a/sdk/userspace/fpga_libs/fpga_mgmt/fpga_mgmt_cmd.c +++ b/sdk/userspace/fpga_libs/fpga_mgmt/fpga_mgmt_cmd.c @@ -415,7 +415,7 @@ fpga_mgmt_send_cmd(int slot_id, ret = -EAGAIN; while (ret == -EAGAIN) { ret = fpga_hal_mbox_read(handle, (void *)rsp, len); - fail_on(ret = (ret) ? ETIMEDOUT : 0, err_code, "Error: operation timed out"); + fail_on(ret = (ret) ? (-ETIMEDOUT) : 0, err_code, "Error: operation timed out"); ret = fpga_mgmt_afi_validate_header(cmd, rsp, *len); fail_on(ret, err_code, CLI_INTERNAL_ERR_STR); diff --git a/sdk/userspace/fpga_libs/fpga_pci/fpga_pci.c b/sdk/userspace/fpga_libs/fpga_pci/fpga_pci.c index f965e3d6e..51d69ec28 100644 --- a/sdk/userspace/fpga_libs/fpga_pci/fpga_pci.c +++ b/sdk/userspace/fpga_libs/fpga_pci/fpga_pci.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -163,6 +164,7 @@ static int fpga_pci_bar_attach(struct fpga_slot_spec *spec, int pf_id, int bar_id, bool write_combining, int *handle) { + int fd = -1; log_debug("enter"); void *mem_base = NULL; @@ -227,12 +229,14 @@ fpga_pci_bar_attach(struct fpga_slot_spec *spec, int pf_id, int bar_id, log_debug("Opening sysfs_name=%s", sysfs_name); - int fd = open(sysfs_name, O_RDWR | O_SYNC); + fd = open(sysfs_name, O_RDWR | O_SYNC); fail_on(fd == -1, err, "open failed"); mem_base = mmap(0, map->resource_size[bar_id], PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0); fail_on(mem_base == MAP_FAILED, err, "mmap failed"); + close(fd); + fd = -1; /** Allocate a bar */ int tmp_handle = fpga_pci_bar_alloc(); @@ -253,6 +257,9 @@ fpga_pci_bar_attach(struct fpga_slot_spec *spec, int pf_id, int bar_id, fail_on(ret != 0, err, "munmap failed"); } err: + if (fd != -1) { + close(fd); + } errno = 0; return FPGA_ERR_FAIL; } diff --git a/sdk/userspace/fpga_mgmt_tools/README.md b/sdk/userspace/fpga_mgmt_tools/README.md index e5f4f54f2..d88ebd9ed 100644 --- a/sdk/userspace/fpga_mgmt_tools/README.md +++ b/sdk/userspace/fpga_mgmt_tools/README.md @@ -92,7 +92,7 @@ To load the AFI, use the FPGA slot number and Amazon Global FPGA Image ID parame #### Describing the AFI content loaded on a specific FPGA slot after load -Displays the current state for the given FPGA slot number. The output shows the FPGA in the “loaded” state after the FPGA image "load" operation. The "-R" option performs a PCI device remove and recan in order to expose the unique AFI Vendor and Device Id. +Displays the current state for the given FPGA slot number. The output shows the FPGA in the “loaded” state after the FPGA image "load" operation. **_The "-R" option performs a PCI device remove and recan in order to expose the unique AFI Vendor and Device Id._** $ sudo fpga-describe-local-image -S 0 -R -H @@ -109,7 +109,7 @@ The following command will clear the FPGA image, including internal and external #### Describing the AFI content loaded on a specific FPGA slot after clear -The following command displays the current state for the given FPGA slot number. It shows that the FPGA is in the “cleared” state after the FPGA image "clear" operation. The "-R" option performs a PCI device remove and recan in order to expose the default AFI Vendor and Device Id. +The following command displays the current state for the given FPGA slot number. It shows that the FPGA is in the “cleared” state after the FPGA image "clear" operation. **_The "-R" option performs a PCI device remove and recan in order to expose the default AFI Vendor and Device Id._** $ sudo fpga-describe-local-image -S 0 -R -H diff --git a/sdk/userspace/fpga_mgmt_tools/src/fpga_local_cmd.c b/sdk/userspace/fpga_mgmt_tools/src/fpga_local_cmd.c index df75c06a0..399eab9cb 100644 --- a/sdk/userspace/fpga_mgmt_tools/src/fpga_local_cmd.c +++ b/sdk/userspace/fpga_mgmt_tools/src/fpga_local_cmd.c @@ -115,6 +115,9 @@ cli_attach(void) ret = fpga_mgmt_init(); fail_on_internal(ret != 0, err, CLI_INTERNAL_ERR_STR); + fpga_mgmt_set_cmd_timeout(f1.mbox_timeout); + fpga_mgmt_set_cmd_delay_msec(f1.mbox_delay_msec); + out: return 0; err: diff --git a/sdk/userspace/install_fpga_mgmt_tools.sh b/sdk/userspace/install_fpga_mgmt_tools.sh index 35ee29cff..09b66feee 100755 --- a/sdk/userspace/install_fpga_mgmt_tools.sh +++ b/sdk/userspace/install_fpga_mgmt_tools.sh @@ -15,30 +15,79 @@ # permissions and limitations under the License. # -set -e if [ -z "$SDK_DIR" ]; then - echo "Error: SDK_DIR environment variable is not set. Please 'source sdk_setup.sh' from the aws-fpga directory first." - exit 1 -fi + echo "Error: SDK_DIR environment variable is not set. Please 'source sdk_setup.sh' from the aws-fpga directory first." + exit 1 +fi + +if [ $EUID != 0 ]; then + echo "" + echo "Root privileges are required to install. You may be asked for your password..." + sudo -E "$0" "$@" + exit $? +else + echo "Executing as root..." + echo "" +fi + +BASE_PATH=/usr/local + +# check to see if the /usr/local/bin is on the sudo PATH (is secure_path enabled?) +echo $PATH | grep "$BASE_PATH" +ret=$? +if [ $ret -ne "0" ]; then + BASE_PATH=/usr +fi SDK_MGMT_DIR=$SDK_DIR/userspace AFI_MGMT_TOOLS_SRC_DIR=$SDK_MGMT_DIR/fpga_mgmt_tools/src -AFI_MGMT_TOOLS_DST_DIR=/usr/bin +AFI_MGMT_TOOLS_DST_DIR=$BASE_PATH/bin AFI_MGMT_TOOLS_LIB_DIR=$SDK_MGMT_DIR/lib/so -AFI_MGMT_LIBS_DST_DIR=/usr/lib64 -# Build and install the Amazon FPGA Image (AFI) Management Tools -cd $SDK_MGMT_DIR -$SDK_MGMT_DIR/mkall_fpga_mgmt_tools.sh +# in order to accommodate different distributions, check several options for the user-libraries directory +if [ -d "/usr/local/lib64" ]; then + AFI_MGMT_LIBS_DST_DIR=/usr/local/lib64 +elif [ -d "/usr/local/lib" ]; then + AFI_MGMT_LIBS_DST_DIR=/usr/local/lib +elif [ -d "/usr/lib64" ]; then + AFI_MGMT_LIBS_DST_DIR=/usr/lib64 +elif [ -d "/usr/lib" ]; then + AFI_MGMT_LIBS_DST_DIR=/usr/lib +else + echo "Error: No directory for installing libraries." + exit 1 +fi if [ ! -d "$AFI_MGMT_TOOLS_DST_DIR" ]; then - mkdir -p $AFI_MGMT_TOOLS_DST_DIR + mkdir -p $AFI_MGMT_TOOLS_DST_DIR fi # /usr/bin requires sudo permissions echo "AWS FPGA: Copying Amazon FPGA Image (AFI) Management Tools to $AFI_MGMT_TOOLS_DST_DIR" -sudo cp -f $AFI_MGMT_TOOLS_SRC_DIR/fpga-* $AFI_MGMT_TOOLS_DST_DIR -sudo cp -f $AFI_MGMT_TOOLS_LIB_DIR/libfpga_mgmt.so $AFI_MGMT_LIBS_DST_DIR +cp -f $AFI_MGMT_TOOLS_SRC_DIR/fpga-* $AFI_MGMT_TOOLS_DST_DIR +cp -f $AFI_MGMT_TOOLS_LIB_DIR/libfpga_mgmt.so.1.0.0 $AFI_MGMT_LIBS_DST_DIR +ln -sf libfpga_mgmt.so.1 $AFI_MGMT_LIBS_DST_DIR/libfpga_mgmt.so + +echo "AWS FPGA: Installing shared library to $AFI_MGMT_LIBS_DST_DIR" +ld_conf_change="0" +while true; do + # update the dynamic linker cache + ldconfig + + # confirm that the linker cache stored the library we want + ldconfig -p | grep "libfpga_mgmt\.so\.1" + ret=$? + if [ $ret -ne "0" ]; then + if [ "$ld_conf_change" -eq "1" ]; then + echo "Error: Unable to automatically install the fpga_mgmt library." + exit 1 + fi + ld_conf_change="1" + echo "$AFI_MGMT_LIBS_DST_DIR" > /etc/ld.so.conf.d/fpga_mgmt-x86_64.conf + else + break + fi +done echo "AWS FPGA: Done with Amazon FPGA Image (AFI) Management Tools install."