From 4bfd3a2c2a6b35afc83e791168e249d6187de8fa Mon Sep 17 00:00:00 2001 From: sbarillet Date: Wed, 24 May 2017 17:16:46 +0200 Subject: [PATCH] fixed verilog file source parsing issue --- .../examples/cl_dram_dma/build/scripts/create_dcp_from_cl.tcl | 2 +- .../cl_hello_world/build/scripts/create_dcp_from_cl.tcl | 2 +- .../new_cl_template/build/scripts/create_dcp_from_cl.tcl | 2 +- .../new_cl_template/build/scripts/create_dcp_from_cl.tcl | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hdk/cl/examples/cl_dram_dma/build/scripts/create_dcp_from_cl.tcl b/hdk/cl/examples/cl_dram_dma/build/scripts/create_dcp_from_cl.tcl index 5273ab588..011caec35 100644 --- a/hdk/cl/examples/cl_dram_dma/build/scripts/create_dcp_from_cl.tcl +++ b/hdk/cl/examples/cl_dram_dma/build/scripts/create_dcp_from_cl.tcl @@ -238,7 +238,7 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Reading developer's # Reading the .sv and .v files, as proper designs would not require # reading .v, .vh, nor .inc files -read_verilog -sv [ glob $ENC_SRC_DIR/*.?v ] +read_verilog -sv [ glob $ENC_SRC_DIR/*.{v,sv} ] #---- End of section replaced by User ---- diff --git a/hdk/cl/examples/cl_hello_world/build/scripts/create_dcp_from_cl.tcl b/hdk/cl/examples/cl_hello_world/build/scripts/create_dcp_from_cl.tcl index 3f82daac9..8f717529b 100644 --- a/hdk/cl/examples/cl_hello_world/build/scripts/create_dcp_from_cl.tcl +++ b/hdk/cl/examples/cl_hello_world/build/scripts/create_dcp_from_cl.tcl @@ -180,7 +180,7 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Reading developer's # Reading the .sv and .v files, as proper designs would not require # reading .v, .vh, nor .inc files -read_verilog -sv [glob $ENC_SRC_DIR/*.?v] +read_verilog -sv [glob $ENC_SRC_DIR/*.{v,sv}] #---- End of section replaced by User ---- diff --git a/hdk/common/shell_v032117d7/new_cl_template/build/scripts/create_dcp_from_cl.tcl b/hdk/common/shell_v032117d7/new_cl_template/build/scripts/create_dcp_from_cl.tcl index 1345a724a..16bfdfd5a 100644 --- a/hdk/common/shell_v032117d7/new_cl_template/build/scripts/create_dcp_from_cl.tcl +++ b/hdk/common/shell_v032117d7/new_cl_template/build/scripts/create_dcp_from_cl.tcl @@ -112,7 +112,7 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Reading developer's # Reading the .sv and .v files, as proper designs would not require # reading .v, .vh, nor .inc files -read_verilog -sv [glob $ENC_SRC_DIR/*.?v] +read_verilog -sv [glob $ENC_SRC_DIR/*.{v,sv}] #---- End of section replaced by User ---- diff --git a/hdk/common/shell_v04151701/new_cl_template/build/scripts/create_dcp_from_cl.tcl b/hdk/common/shell_v04151701/new_cl_template/build/scripts/create_dcp_from_cl.tcl index ae00bf133..3258b45ef 100644 --- a/hdk/common/shell_v04151701/new_cl_template/build/scripts/create_dcp_from_cl.tcl +++ b/hdk/common/shell_v04151701/new_cl_template/build/scripts/create_dcp_from_cl.tcl @@ -173,7 +173,7 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Reading developer's # Reading the .sv and .v files, as proper designs would not require # reading .v, .vh, nor .inc files -read_verilog -sv [glob $ENC_SRC_DIR/*.?v] +read_verilog -sv [glob $ENC_SRC_DIR/*.{v,sv}] #---- End of section replaced by User ----