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AWS_Shell_V1.4_Migration_Guidelines.md

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Shell F1.X.1.4 Migration Document

This document describes the changes required when migrating your design from shell F1.X.1.3 to shell F1.X.1.4. The HDK build scripts have changed to reflect the new v1.4 shell’s floorplan and newer Vivado tools. It’s strongly recommended users move to these scripts. Users who have already customized v1.3 scripts should diff those with the v1.4 scripts and be sure to include all new parameters that have been added to v1.4 scripts.

  1. Upgrade Vivado Tools to version 2019.1 or later. Needs FPGA DEVELOPER AMI 1.4 or later

  2. The hierarchy for CL & SH modules have changed. Now they are instantiated in "WRAPPER_INST" Module. The paths in your Build scripts, constraints & verification components have to be updated.

F1.X.1.3 Shell F1.X.1.4 Shell
CL/blkA/sublockB/componentC/celld/signalX WRAPPER_INST/CL/blkA/sublockB/componentC/celld/signalX
SH/blkA/sublockB/componentC/celld/signalX WRAPPER_INST/SH/blkA/sublockB/componentC/celld/signalX
  1. The CL to Shell interface has the following additional signals. Please refer to v1.4 Shell Interface Specification for functionality.
Interface Signal Name Width Direction Recommended Tie-Off
dma_pcis interface (BAR4) cl_sh_dma_wr_full 1 output 1'b0
dma_pcis interface (BAR4) cl_sh_dma_rd_full 1 output 1'b0
DDR-C AXI4 CL to SH cl_sh_ddr_awburst 2 output 2'b01
DDR-C AXI4 CL to SH cl_sh_ddr_arburst 2 output 2'b01

NOTE: Only INCR burst mode is supported on AXI-4 buses between CL/Shell interface.

  1. If your CL is using "cl_axi_interconnect" IP which comes included with other shell IP, Please note the path changes for directory hierarchy. CL_AXI_INTERCONNECT IP can be found here.

  2. Upgrade to latest for SH_DDR IP .

  3. All Xilinx IP in your CL must to be upgraded to 2017.4 or later version. see vivado 2017.4 release notes for recommended version

  4. ILA cores need to be upgraded for 2017.4 or later Please refer to the cl_dram_dma example for ILA hookup on PCIS interface.

  5. Please use below information to update CL pblock constraints to optimize your design in Shell F1.X.1.4.

    • Shell F1.X.1.4 is slightly larger than Shell F1.X.1.3. CL floorplan may need to be tweaked to account for the larger shell. Please review pblock constriants of CL for conflicting regions.
    • Following are the interface placement changes between Shell F1.X.1.3 & F1.X.1.4
    INTERFACE Shell F1.X.1.3 SLR SHELL F1.X.1.4 SLR
    CL_SH_DDR MID/BOTTOM SLR MID SLR
    BAR1 MID SLR MID SLR
    PCIM MID SLR MID SLR
    PCIS BOTTOM SLR BOTTOM SLR
    OCL BOTTOM SLR BOTTOM SLR
    DDR STAT3 BOTTOM SLR BOTTOM SLR
    DDR STAT0 TOP SLR MID/BOTTOM SLR
    DDR STAT1 MID SLR MID/BOTTOM SLR
    SDA BOTTOM SLR MID/BOTTOM SLR

  6. The following parameter is required to be set before running CL placement & routing.

    set_param hd.clockRoutingWireReduction false

    This ensures that there are no contentions on clock nets for designs that have large number of clock nets. The included build script has this parameter included.