From 8424a5edd047d09a359fff6104db67a0a12a1e5b Mon Sep 17 00:00:00 2001 From: "ivan.ruzavin" Date: Mon, 18 Nov 2024 10:32:11 +0100 Subject: [PATCH 01/56] Initial commit --- cmake/utils.cmake | 5 +++++ hal/interface/CMakeLists.txt | 2 ++ targets/arm/mikroe/CMakeLists.txt | 2 ++ targets/arm/mikroe/common/CMakeLists.txt | 8 ++++++++ 4 files changed, 17 insertions(+) diff --git a/cmake/utils.cmake b/cmake/utils.cmake index 0038381b6..95b0ce82b 100644 --- a/cmake/utils.cmake +++ b/cmake/utils.cmake @@ -155,6 +155,9 @@ function(find_chip_vendor _chip_vendor) if(${MCU_NAME} MATCHES "^TM4C.*") set(${_chip_vendor} "tiva" PARENT_SCOPE) endif() + if(${MCU_NAME} MATCHES "^(AT)?SAM.*") + set(${_chip_vendor} "sam" PARENT_SCOPE) + endif() endfunction() ############################################################################# @@ -169,6 +172,8 @@ function(find_chip_architecture _chip_architecture) set(${_chip_architecture} "arm" PARENT_SCOPE) elseif(${MCU_NAME} MATCHES "^TM4C.*") set(${_chip_architecture} "arm" PARENT_SCOPE) + elseif(${MCU_NAME} MATCHES "^(AT)?SAM.*") + set(${_chip_architecture} "arm" PARENT_SCOPE) else() set(${_chip_architecture} "UNSUPPORTED_CHIP_SELECTED_FOR_FOLLOWING_IMPLEMENTATION" PARENT_SCOPE) endif() diff --git a/hal/interface/CMakeLists.txt b/hal/interface/CMakeLists.txt index ce8496bfd..0f59e0b2d 100644 --- a/hal/interface/CMakeLists.txt +++ b/hal/interface/CMakeLists.txt @@ -26,6 +26,8 @@ elseif(${MCU_NAME} MATCHES "(^PIC18(.+)$)") set(vendor_id "pic18") elseif(${MCU_NAME} MATCHES "(^GD32VF(.+)$)") set(vendor_id "gigadevice") +elseif(${MCU_NAME} MATCHES "^(AT)?SAM(.+)$") + set(vendor_id "sam") elseif(${MCU_NAME} MATCHES "AT") set(vendor_id "avr") elseif(${MCU_NAME} MATCHES "^(ds)?PIC(24|30|33).*") diff --git a/targets/arm/mikroe/CMakeLists.txt b/targets/arm/mikroe/CMakeLists.txt index 155f46662..904a304b7 100644 --- a/targets/arm/mikroe/CMakeLists.txt +++ b/targets/arm/mikroe/CMakeLists.txt @@ -6,6 +6,8 @@ elseif(${MCU_NAME} MATCHES "(^MK(.+)$)") elseif(${MCU_NAME} MATCHES "(^TM4C1(.+)$)") ## TIVA has only the 71 MCUs already implemented set(vendor_id "tiva") +elseif(${MCU_NAME} MATCHES "(^(AT)?SAM(.+)$)") + set(vendor_id "sam") else() set(vendor_id "__implementation_error__") endif() diff --git a/targets/arm/mikroe/common/CMakeLists.txt b/targets/arm/mikroe/common/CMakeLists.txt index c91b41018..169f26b92 100644 --- a/targets/arm/mikroe/common/CMakeLists.txt +++ b/targets/arm/mikroe/common/CMakeLists.txt @@ -29,6 +29,14 @@ elseif(${MCU_NAME} MATCHES "(^MK(.+)$)") else() set(architecture "NXP") endif() +elseif(${MCU_NAME} MATCHES "(^ATSAM(.+)$)") + set(architecture_macro "SAM") + set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_ID_}${_MSDK_PACKAGE_PIN_COUNT_}) + if(AI_GENERATED_SDK) + set(architecture "ai_generated/SAM") + else() + set(architecture "SAM") + endif() elseif(${MCU_NAME} MATCHES "(^TM4C1(.+)$)") set(architecture_macro "TIVA") set(architecture "TIVA") From 43e6734b470933b28392ba0d3ca20021ab77ae31 Mon Sep 17 00:00:00 2001 From: "ivan.ruzavin" Date: Mon, 18 Nov 2024 14:06:56 +0100 Subject: [PATCH 02/56] Building phase --- targets/arm/mikroe/common/CMakeLists.txt | 3 +- .../ATSAME70Q21B/LQFP144/mcu_definitions.h | 295 +++++ .../ATSAME70Q21B/LQFP144/mcu_reg_addresses.h | 53 + targets/arm/mikroe/core/CMakeLists.txt | 4 + .../mikroe/core/include/hal_ll_core_defines.h | 40 + .../mikroe/core/src/sam/m7/hal_ll_core_port.c | 94 ++ targets/arm/mikroe/sam/CMakeLists.txt | 39 + .../arm/mikroe/sam/include/gpio/hal_ll_gpio.h | 279 +++++ .../sam/include/gpio/hal_ll_gpio_port.h | 157 +++ .../hal_ll_gpio_constants.h | 153 +++ .../hal_ll_gpio_struct_type.h | 107 ++ .../hal_ll_gpio_struct_type.h.bak | 107 ++ .../arm/mikroe/sam/include/hal_ll_pin_names.h | 611 +++++++++ .../arm/mikroe/sam/include/hal_ll_target.h | 68 + .../mikroe/sam/include/hal_ll_target_names.h | 72 ++ .../sam/include/i2c/hal_ll_i2c_master.h | 241 ++++ .../hal_ll_i2c_pin_map.h | 94 ++ .../arm_gcc_clang_atsam_e70/hal_ll_pmc.h | 125 ++ .../include/spi_master/hal_ll_spi_master.h | 232 ++++ .../hal_ll_spi_master_pin_map.h | 101 ++ .../arm/mikroe/sam/include/tim/hal_ll_tim.h | 253 ++++ .../hal_ll_tim_pin_map.h | 116 ++ .../arm/mikroe/sam/include/uart/hal_ll_uart.h | 299 +++++ .../hal_ll_uart_pin_map.h | 110 ++ .../arm/mikroe/sam/src/gpio/CMakeLists.txt | 73 ++ targets/arm/mikroe/sam/src/gpio/hal_ll_gpio.c | 185 +++ .../arm_gcc_clang_atsam_e70/CMakeLists.cmake | 6 + .../hal_ll_gpio_port.c | 270 ++++ .../arm/mikroe/sam/src/hal_ll/CMakeLists.txt | 16 + targets/arm/mikroe/sam/src/i2c/CMakeLists.txt | 82 ++ .../arm_gcc_clang_atsam_e70/CMakeLists.cmake | 7 + .../hal_ll_i2c_master.c | 835 +++++++++++++ .../mikroe/sam/src/spi_master/CMakeLists.txt | 72 ++ .../arm_gcc_clang_atsam_e70/CMakeLists.cmake | 7 + .../hal_ll_spi_master.c | 668 ++++++++++ targets/arm/mikroe/sam/src/tim/CMakeLists.txt | 71 ++ .../arm_gcc_clang_atsam_e70/CMakeLists.cmake | 7 + .../arm_gcc_clang_atsam_e70/hal_ll_tim.c | 743 +++++++++++ .../arm/mikroe/sam/src/uart/CMakeLists.txt | 72 ++ .../arm_gcc_clang_atsam_e70/CMakeLists.cmake | 7 + .../CMakeLists.cmake.bak | 7 + .../arm_gcc_clang_atsam_e70/hal_ll_uart.c | 1103 +++++++++++++++++ 42 files changed, 7883 insertions(+), 1 deletion(-) create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21B/LQFP144/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q21B/LQFP144/mcu_reg_addresses.h create mode 100644 targets/arm/mikroe/core/src/sam/m7/hal_ll_core_port.c create mode 100644 targets/arm/mikroe/sam/CMakeLists.txt create mode 100644 targets/arm/mikroe/sam/include/gpio/hal_ll_gpio.h create mode 100644 targets/arm/mikroe/sam/include/gpio/hal_ll_gpio_port.h create mode 100644 targets/arm/mikroe/sam/include/gpio/implementations/arm_gcc_clang_atsam_e70/hal_ll_gpio_constants.h create mode 100644 targets/arm/mikroe/sam/include/gpio/implementations/arm_gcc_clang_atsam_e70/hal_ll_gpio_struct_type.h create mode 100644 targets/arm/mikroe/sam/include/gpio/implementations/arm_gcc_clang_atsam_e70/hal_ll_gpio_struct_type.h.bak create mode 100644 targets/arm/mikroe/sam/include/hal_ll_pin_names.h create mode 100644 targets/arm/mikroe/sam/include/hal_ll_target.h create mode 100644 targets/arm/mikroe/sam/include/hal_ll_target_names.h create mode 100644 targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_master.h create mode 100644 targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_pin_map/implementations/arm_gcc_clang_atsam_e70/hal_ll_i2c_pin_map.h create mode 100644 targets/arm/mikroe/sam/include/pmc/implementations/arm_gcc_clang_atsam_e70/hal_ll_pmc.h create mode 100644 targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master.h create mode 100644 targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master_pin_map/implementations/arm_gcc_clang_atsam_e70/hal_ll_spi_master_pin_map.h create mode 100644 targets/arm/mikroe/sam/include/tim/hal_ll_tim.h create mode 100644 targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/arm_gcc_clang_atsam_e70/hal_ll_tim_pin_map.h create mode 100644 targets/arm/mikroe/sam/include/uart/hal_ll_uart.h create mode 100644 targets/arm/mikroe/sam/include/uart/hal_ll_uart_pin_map/implementations/arm_gcc_clang_atsam_e70/hal_ll_uart_pin_map.h create mode 100644 targets/arm/mikroe/sam/src/gpio/CMakeLists.txt create mode 100644 targets/arm/mikroe/sam/src/gpio/hal_ll_gpio.c create mode 100644 targets/arm/mikroe/sam/src/gpio/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake create mode 100644 targets/arm/mikroe/sam/src/gpio/implementations/arm_gcc_clang_atsam_e70/hal_ll_gpio_port.c create mode 100644 targets/arm/mikroe/sam/src/hal_ll/CMakeLists.txt create mode 100644 targets/arm/mikroe/sam/src/i2c/CMakeLists.txt create mode 100644 targets/arm/mikroe/sam/src/i2c/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake create mode 100644 targets/arm/mikroe/sam/src/i2c/implementations/arm_gcc_clang_atsam_e70/hal_ll_i2c_master.c create mode 100644 targets/arm/mikroe/sam/src/spi_master/CMakeLists.txt create mode 100644 targets/arm/mikroe/sam/src/spi_master/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake create mode 100644 targets/arm/mikroe/sam/src/spi_master/implementations/arm_gcc_clang_atsam_e70/hal_ll_spi_master.c create mode 100644 targets/arm/mikroe/sam/src/tim/CMakeLists.txt create mode 100644 targets/arm/mikroe/sam/src/tim/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake create mode 100644 targets/arm/mikroe/sam/src/tim/implementations/arm_gcc_clang_atsam_e70/hal_ll_tim.c create mode 100644 targets/arm/mikroe/sam/src/uart/CMakeLists.txt create mode 100644 targets/arm/mikroe/sam/src/uart/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake create mode 100644 targets/arm/mikroe/sam/src/uart/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake.bak create mode 100644 targets/arm/mikroe/sam/src/uart/implementations/arm_gcc_clang_atsam_e70/hal_ll_uart.c diff --git a/targets/arm/mikroe/common/CMakeLists.txt b/targets/arm/mikroe/common/CMakeLists.txt index 169f26b92..810529ad2 100644 --- a/targets/arm/mikroe/common/CMakeLists.txt +++ b/targets/arm/mikroe/common/CMakeLists.txt @@ -31,7 +31,8 @@ elseif(${MCU_NAME} MATCHES "(^MK(.+)$)") endif() elseif(${MCU_NAME} MATCHES "(^ATSAM(.+)$)") set(architecture_macro "SAM") - set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_ID_}${_MSDK_PACKAGE_PIN_COUNT_}) + set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) + set(mcu_regs_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) if(AI_GENERATED_SDK) set(architecture "ai_generated/SAM") else() diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21B/LQFP144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21B/LQFP144/mcu_definitions.h new file mode 100644 index 000000000..6603608ec --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21B/LQFP144/mcu_definitions.h @@ -0,0 +1,295 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70Q21B_LQFP144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +//I2C +#define I2C0_SDA_PA3_AFA +#define I2C0_SCL_PA4_AFA +#define I2C1_SDA_PB4_AFA +#define I2C1_SCL_PB5_AFA +#define I2C2_SDA_PD27_AFC +#define I2C2_SCL_PD28_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +//EOF I2C + +//TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +//EOF TIM + +//USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFC +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +//EOF USART + +//UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (8) +//EOF UART + +//SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +//EOF SPI + +//GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +//EOF GPIO + +//IVT Table +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +//EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q21B/LQFP144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q21B/LQFP144/mcu_reg_addresses.h new file mode 100644 index 000000000..aac0a5f8b --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q21B/LQFP144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70Q21B register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70Q21B REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/core/CMakeLists.txt b/targets/arm/mikroe/core/CMakeLists.txt index f03d20394..b763c88f7 100644 --- a/targets/arm/mikroe/core/CMakeLists.txt +++ b/targets/arm/mikroe/core/CMakeLists.txt @@ -37,6 +37,10 @@ elseif(${MCU_NAME} MATCHES "^TM4C.*") set(chip_vendor "tiva") list(APPEND hal_ll_core_def_list ${chip_vendor}) set(hal_ll_core_source "m4") +elseif(${MCU_NAME} MATCHES "^ATSAM.*") + set(chip_vendor "sam") + list(APPEND hal_ll_core_def_list ${chip_vendor}) + set(hal_ll_core_source "m7") else() list(hal_ll_core_def_list __vendor_not_supported__) endif() diff --git a/targets/arm/mikroe/core/include/hal_ll_core_defines.h b/targets/arm/mikroe/core/include/hal_ll_core_defines.h index c800a5ac1..9db9ff31f 100644 --- a/targets/arm/mikroe/core/include/hal_ll_core_defines.h +++ b/targets/arm/mikroe/core/include/hal_ll_core_defines.h @@ -359,6 +359,46 @@ extern "C"{ #define HAL_LL_CORE_NVIC_SYS_PRI_1 (( uint32_t * )0xE000ED18) #define HAL_LL_CORE_NVIC_SYS_PRI_2 (( uint32_t * )0xE000ED1C) #define HAL_LL_CORE_NVIC_SYS_PRI_3 (( uint32_t * )0xE000ED20) +#elif defined (sam) + typedef enum + { + HAL_LL_IVT_PRIORITY_LEVEL_0 = 0, + HAL_LL_IVT_PRIORITY_LEVEL_1, + HAL_LL_IVT_PRIORITY_LEVEL_2, + HAL_LL_IVT_PRIORITY_LEVEL_3, + HAL_LL_IVT_PRIORITY_LEVEL_4, + HAL_LL_IVT_PRIORITY_LEVEL_5, + HAL_LL_IVT_PRIORITY_LEVEL_6, + HAL_LL_IVT_PRIORITY_LEVEL_7 + } hal_ll_core_irq_priority_levels; + + #define hal_ll_core_irq(irq_val) (irq_val-16) + + #define HAL_LL_CORE_IRQ_MASK 0x1F + #define HAL_LL_CORE_LOW_NIBBLE 0xFUL + #define HAL_LL_CORE_HIGH_NIBBLE 0xF0UL + #define HAL_LL_CORE_IVT_INT_MEM_MANAGE 4 + #define HAL_LL_CORE_IVT_INT_BUS_FAULT 5 + #define HAL_LL_CORE_IVT_INT_USAGE_FAULT 6 + #define HAL_LL_CORE_IVT_INT_SYS_TICK 15 + #define HAL_LL_CORE_IVT_TICKINT_BIT 1 + #define HAL_LL_CORE_IVT_MEMFAULTENA_BIT 16 + #define HAL_LL_CORE_IVT_BUSFAULTENA_BIT 17 + #define HAL_LL_CORE_IVT_USGFAULTENA_BIT 18 + #define HAL_LL_CORE_SCB_SHCRS (( uint32_t * )0xE000ED24) + #define HAL_LL_CORE_STK_CTRL (( uint32_t * )0xE000E010) + #define HAL_LL_CORE_NVIC_ISER_0 (( uint32_t * )0xE000E100) + #define HAL_LL_CORE_NVIC_ISER_1 (( uint32_t * )0xE000E104) + #define HAL_LL_CORE_NVIC_ISER_2 (( uint32_t * )0xE000E108) + #define HAL_LL_CORE_NVIC_ISER_3 (( uint32_t * )0xE000E10C) + #define HAL_LL_CORE_NVIC_ICER_0 (( uint32_t * )0xE000E180) + #define HAL_LL_CORE_NVIC_ICER_1 (( uint32_t * )0xE000E184) + #define HAL_LL_CORE_NVIC_ICER_2 (( uint32_t * )0xE000E188) + #define HAL_LL_CORE_NVIC_ICER_3 (( uint32_t * )0xE000E18C) + #define HAL_LL_CORE_NVIC_IPR_0 (( uint32_t * )0xE000E400) + #define HAL_LL_CORE_NVIC_SCB_SHPR1 (( uint32_t * )0xE000ED18) + #define HAL_LL_CORE_NVIC_SCB_SHPR2 (( uint32_t * )0xE000ED1C) + #define HAL_LL_CORE_NVIC_SCB_SHPR3 (( uint32_t * )0xE000ED20) #endif #ifdef __cplusplus diff --git a/targets/arm/mikroe/core/src/sam/m7/hal_ll_core_port.c b/targets/arm/mikroe/core/src/sam/m7/hal_ll_core_port.c new file mode 100644 index 000000000..f008614ab --- /dev/null +++ b/targets/arm/mikroe/core/src/sam/m7/hal_ll_core_port.c @@ -0,0 +1,94 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_core_port.c + * @brief This file contains all low level function definitions for chip specific core functionality. + * @note Refers to all M7 cortex chips. + */ + +#include "hal_ll_core_defines.h" +#include "hal_ll_bit_control.h" + +void hal_ll_core_port_nvic_enable_irq( uint8_t IRQn ) +{ + // General exceptions + if ( IRQn >= 64 ) + set_reg_bit( HAL_LL_CORE_NVIC_ISER_2, ( IRQn & HAL_LL_CORE_IRQ_MASK ) ); + else if ( IRQn >= 32) + set_reg_bit( HAL_LL_CORE_NVIC_ISER_1, ( IRQn & HAL_LL_CORE_IRQ_MASK ) ); + else if ( IRQn >= 0 ) + set_reg_bit( HAL_LL_CORE_NVIC_ISER_0, ( IRQn & HAL_LL_CORE_IRQ_MASK ) ); +} + +void hal_ll_core_port_nvic_disable_irq( uint8_t IRQn ) +{ + // General exceptions + if ( IRQn >= 64 ) + set_reg_bit( HAL_LL_CORE_NVIC_ICER_2, ( IRQn & HAL_LL_CORE_IRQ_MASK ) ); + else if ( IRQn >= 32) + set_reg_bit( HAL_LL_CORE_NVIC_ICER_1, ( IRQn & HAL_LL_CORE_IRQ_MASK ) ); + else if ( IRQn >= 0 ) + set_reg_bit( HAL_LL_CORE_NVIC_ICER_0, ( IRQn & HAL_LL_CORE_IRQ_MASK ) ); +} + +void hal_ll_core_port_nvic_set_priority_irq( uint8_t IRQn, uint8_t IRQn_priority ) +{ + uintptr_t *reg; + uint8_t tmp_shift; + + if ( IRQn > 15 ) + { + reg = HAL_LL_CORE_NVIC_IPR_0 + ( ( hal_ll_core_irq( IRQn ) ) >> 2 ); + tmp_shift = ( ( ( hal_ll_core_irq( IRQn ) ) % 4 ) << 3 ) + 4; + } else if ( ( IRQn > 3 ) & ( IRQn <= 15 ) ) { + reg = HAL_LL_CORE_NVIC_SCB_SHPR1 + ( IRQn / 4 ) - 1; + tmp_shift = ( ( IRQn % 4 ) << 3 ) + 4; + } else { + return; + } + + if ( IRQn_priority & HAL_LL_CORE_LOW_NIBBLE ) { + *reg &= ~( HAL_LL_CORE_LOW_NIBBLE << tmp_shift ); + *reg |= ( uint32_t )IRQn_priority << tmp_shift; + } else { + *reg &= ~( HAL_LL_CORE_LOW_NIBBLE << tmp_shift ); + *reg |= ( uint32_t )IRQn_priority << ( tmp_shift - 4 ); + } +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/sam/CMakeLists.txt b/targets/arm/mikroe/sam/CMakeLists.txt new file mode 100644 index 000000000..d0d3a2cba --- /dev/null +++ b/targets/arm/mikroe/sam/CMakeLists.txt @@ -0,0 +1,39 @@ +## ./targets/arm/mikroe/ai_generated/stm32/CMakeLists.txt +# ALL MODULES +add_subdirectory(src/hal_ll) + +# SEPARATE MODULES +set(module_list "") +set(module_list_supported "") +set_module_support(module_list module_list_supported ${MCU_NAME} "hal_ll_layer") + +if (msdk_adc IN_LIST module_list_supported) + # add_subdirectory(src/adc) +endif() +if (msdk_gpio_in IN_LIST module_list_supported) + add_subdirectory(src/gpio) +endif() +if (msdk_i2c_master IN_LIST module_list_supported) + add_subdirectory(src/i2c) +endif() +if (msdk_pwm IN_LIST module_list_supported) + add_subdirectory(src/tim) +endif() +if (msdk_spi_master IN_LIST module_list_supported) + add_subdirectory(src/spi_master) +endif() +if (msdk_uart IN_LIST module_list_supported) + add_subdirectory(src/uart) +endif() +if (msdk_onewire IN_LIST module_list_supported) + # add_subdirectory(src/one_wire) +endif() +if (msdk_can IN_LIST module_list_supported) + # add_subdirectory(src/can) +endif() +if (msdk_dma IN_LIST module_list_supported) + # add_subdirectory(src/dma) +endif() +if (msdk_rtc IN_LIST module_list_supported) + # add_subdirectory(src/rtc) +endif() diff --git a/targets/arm/mikroe/sam/include/gpio/hal_ll_gpio.h b/targets/arm/mikroe/sam/include/gpio/hal_ll_gpio.h new file mode 100644 index 000000000..d67b30360 --- /dev/null +++ b/targets/arm/mikroe/sam/include/gpio/hal_ll_gpio.h @@ -0,0 +1,279 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio.h + * @brief This file contains all the functions prototypes for the GPIO library. + */ + +#ifndef _HAL_LL_GPIO_H_ +#define _HAL_LL_GPIO_H_ + +#include "hal_ll_gpio_port.h" + +#ifdef __cplusplus +extern "C"{ +#endif + +/** + * @brief Function configures pin. + * + * Configures pin to digital output or digital input. + * Sets only the pin defined by pin mask in + * hal_ll_gpio_pin_t structure. + * + * @param *pin Pin object context. + * Configured during this functions process. + * @param name Pin name -- PA0, PA1... + * @param direction Pin direction. + * HAL_LL_GPIO_DIGITAL_INPUT + * HAL_LL_GPIO_DIGITAL_OUTPUT + * + * @return None. + */ +void hal_ll_gpio_configure_pin(hal_ll_gpio_pin_t *pin, hal_ll_pin_name_t name, hal_ll_gpio_direction_t direction); + +/** + * @brief Read pin input. + * + * Checks pin data input register value and + * returns logical state. + * + * @param *pin Pin object context. + * Configured during hal_ll_gpio_configure_pin. + * + * @return uint8_t Pin logical state. + * 1/true -- pin high state -- 1.8V or more detected + * 0/false -- pin low state -- 1.8V or less detected + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_read_pin_input(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base) == 0) ? \ + (0) : (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->signal.pin_status & ((hal_ll_gpio_pin_t *)_handle)->mask) ? \ + (1) : (0)) +#else +uint8_t hal_ll_gpio_read_pin_input(hal_ll_gpio_pin_t *pin); +#endif + +/** + * @brief Read pin output. + * + * Checks pin data output register value and + * returns logical state. + * + * @param *pin Pin object context. + * Configured during hal_ll_gpio_configure_pin. + * + * @return uint8_t Pin logical state. + * 1/true -- pin high state -- 1.8V or more detected + * 0/false -- pin low state -- 1.8V or less detected + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_read_pin_output(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base) == 0) ? \ + (0) : (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->signal.pin_status & ((hal_ll_gpio_pin_t *)_handle)->mask) ? \ + (1) : (0)) +#else +uint8_t hal_ll_gpio_read_pin_output(hal_ll_gpio_pin_t *pin); +#endif + +/** + * @brief Writes pin output state. + * + * Sets single pin logical state. + * + * @param *pin Pin object context. + * Configured during hal_ll_gpio_configure_pin. + * @param value Pin logical state. + * 1/true -- sets pin high state -- over 1.8V + * 0/false -- sets pin low state -- less than 1.8V + * + * @return None + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_write_pin_output(_handle,_value) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base) != NULL) ? \ + ((_value > 0) ? \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->signal.enable = ((hal_ll_gpio_pin_t *)_handle)->mask) : \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->signal.disable = ((hal_ll_gpio_pin_t *)_handle)->mask)) : \ + (0)) +#else +void hal_ll_gpio_write_pin_output(hal_ll_gpio_pin_t *pin, uint8_t value); +#endif + +/** + * @brief Toggles pin logical state. + * + * Checks current state of pin + * and toggles it. + * + * @param *pin Pin object context. + * Configured during hal_ll_gpio_configure_pin. + * + * @return None + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_toggle_pin_output(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base) != NULL) ? \ + ((((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->signal.pin_status & ((hal_ll_gpio_pin_t *)_handle)->mask))) ? \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->signal.disable = ((hal_ll_gpio_pin_t *)_handle)->mask) : \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->signal.enable = ((hal_ll_gpio_pin_t *)_handle)->mask)) : \ + (0)) +#else +void hal_ll_gpio_toggle_pin_output(hal_ll_gpio_pin_t *pin); +#endif + +/** + * @brief Sets pin logical state. + * + * Sets pin logical state to high. + * + * @param *pin Pin object context. + * Configured during hal_ll_gpio_configure_pin. + * + * @return None + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_set_pin_output(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base) != NULL) ? \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->signal.enable = ((hal_ll_gpio_pin_t *)_handle)->mask) : \ + (0)) +#else +void hal_ll_gpio_set_pin_output(hal_ll_gpio_pin_t *pin); +#endif + +/** + * @brief Sets pin logical state. + * + * Sets pin logical state to low. + * + * @param *pin Pin object context. + * Configured during hal_ll_gpio_configure_pin. + * + * @return None + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_clear_pin_output(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base) != NULL) ? \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_pin_t *)_handle)->base)->signal.disable = ((hal_ll_gpio_pin_t *)_handle)->mask) : \ + (0)) +#else +void hal_ll_gpio_clear_pin_output(hal_ll_gpio_pin_t *pin); +#endif + +/** + * @brief Configures port. + * + * Configures port according to specified + * direction. Takes into consideration only + * pins defined by mask. + * + * @param *port Port object context. + * Configured during this functions process. + * @param name Port name. + * @param mask Port pin mask. + * @param direction Port pin direction. + * HAL_LL_GPIO_DIGITAL_INPUT + * HAL_LL_GPIO_DIGITAL_OUTPUT + * + * @return None + */ +void hal_ll_gpio_configure_port(hal_ll_gpio_port_t *port, hal_ll_port_name_t name, hal_ll_gpio_mask_t mask, hal_ll_gpio_direction_t direction); + +/** + * @brief Read port input value. + * + * Checks port data input register value and + * returns it. + * + * @param *port Port object context. + * Configured during hal_ll_gpio_configure_port. + * + * @return hal_ll_port_size_t Port input data register value. + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_read_port_input(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base) != NULL) ? \ + ((hal_ll_port_size_t)((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base)->signal.pin_status & ((hal_ll_gpio_port_t *)_handle)->mask) : \ + (0)) +#else +hal_ll_port_size_t hal_ll_gpio_read_port_input(hal_ll_gpio_port_t *port); +#endif + +/** + * @brief Read port output value. + * + * Checks port data output register value and + * returns it. + * + * @param *port Port object context. + * Configured during hal_ll_gpio_configure_port. + * @return hal_ll_port_size_t Port output data register value. + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_read_port_output(_handle) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base) != NULL) ? \ + ((hal_ll_port_size_t)(((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base)->signal.pin_status) & (((hal_ll_gpio_port_t *)_handle)->mask)) : \ + (0)) +#else +hal_ll_port_size_t hal_ll_gpio_read_port_output(hal_ll_gpio_port_t *port); +#endif + +/** + * @brief Set port state. + * + * Sets port output state. + * Will take into consideration only + * port pins defined by mask in + * port object context. + * + * @param *port Port object context. + * Configured during hal_ll_gpio_configure_port. + * @param value Port output value + * + * @return None + */ +#if defined(FLATTEN_ME) && (FLATTEN_ME_LEVEL >= FLATTEN_ME_LEVEL_LOW) +#define hal_ll_gpio_write_port_output(_handle,_value) ((((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base) != NULL) ? \ + (((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base)->signal.enable = \ + ((hal_ll_port_size_t)_value & ((hal_ll_gpio_port_t *)_handle)->mask), \ + ((hal_ll_gpio_base_handle_t *)((hal_ll_gpio_port_t *)_handle)->base)->signal.disable = \ + (~(hal_ll_port_size_t)_value & ((hal_ll_gpio_port_t *)_handle)->mask)) : \ + (0)) +#else +void hal_ll_gpio_write_port_output(hal_ll_gpio_port_t *port, hal_ll_port_size_t value); +#endif + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/sam/include/gpio/hal_ll_gpio_port.h b/targets/arm/mikroe/sam/include/gpio/hal_ll_gpio_port.h new file mode 100644 index 000000000..cba4e596e --- /dev/null +++ b/targets/arm/mikroe/sam/include/gpio/hal_ll_gpio_port.h @@ -0,0 +1,157 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio.h + * @brief This file contains all the functions prototypes for the GPIO library. + */ + +#ifndef _HAL_LL_GPIO_PORT_H_ +#define _HAL_LL_GPIO_PORT_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_target.h" +#include "hal_ll_gpio_constants.h" +#include "hal_ll_gpio_struct_type.h" + +#define RESET_PINS_OFFSET 32 + +/** + * Helper macros for GPIO HAL + */ +#define GPIO_MODULE_STRUCT_END -1 + +/** + * GPIO module struct defining pins and proprietary functions + */ +typedef struct +{ + uint32_t pins[13]; + uint8_t configs[13]; +} module_struct; + +/** + * Handle and mask types. + */ +typedef handle_t hal_ll_gpio_base_t; + +/** + * Enum used for pin direction selection. + */ +typedef enum +{ + HAL_LL_GPIO_DIGITAL_INPUT = 0, + HAL_LL_GPIO_DIGITAL_OUTPUT = 1 +} hal_ll_gpio_direction_t; + +/** + * Enum used for pin direction selection. + */ +typedef struct hal_ll_gpio_t +{ + hal_ll_gpio_base_t base; + hal_ll_gpio_mask_t mask; +}; + +/** + * Pin and port data types. + */ +typedef struct hal_ll_gpio_t hal_ll_gpio_pin_t; +typedef struct hal_ll_gpio_t hal_ll_gpio_port_t; + +/** + * @brief Get pins port index within a list of available ports + * @param name - desired pin + * @return uint8_t value from 0 to PORT_COUNT-1 + */ +uint8_t hal_ll_gpio_port_index( hal_ll_pin_name_t name ); + +/** + * @brief Get pin mask of provided pin within proprietery port + * @param name - desired pin + * @return uint32_t + */ +uint32_t hal_ll_gpio_pin_mask( hal_ll_pin_name_t name ); + +/** + * @brief Get base address of ports registers + * @param name - desired port + * @return uint32_t address of first regsiter + */ +uint32_t hal_ll_gpio_port_base( hal_ll_port_name_t name ); + +/** + * @brief Set pin as analog input + * @param port - port base address acquired from hal_gpio_ll_port_base + * @param pin_mask - pin mask acquired from hal_gpio_ll_pin_mask + * @return none + */ +void hal_ll_gpio_analog_input( hal_ll_gpio_base_t *port, hal_ll_gpio_mask_t pin_mask ); + +/** + * @brief Set pin as digital input + * @param port - port base address acquired from hal_gpio_ll_port_base + * @param pin_mask - pin mask acquired from hal_gpio_ll_pin_mask + * @return none + */ +void hal_ll_gpio_digital_input( hal_ll_gpio_base_t *port, hal_ll_gpio_mask_t pin_mask ); + +/** + * @brief Set pin as digital output + * @param port - port base address acquired from hal_gpio_ll_port_base + * @param pin_mask - pin mask acquired from hal_gpio_ll_pin_mask + * @return none + */ +void hal_ll_gpio_digital_output( hal_ll_gpio_base_t *port, hal_ll_gpio_mask_t pin_mask ); + +/** + * @brief Initialize structure of pins associated to specific peripheral + * @param module - desired module pins structure + * @return none + */ +void hal_ll_gpio_module_struct_init( module_struct const *module, bool state ); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_PORT_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/sam/include/gpio/implementations/arm_gcc_clang_atsam_e70/hal_ll_gpio_constants.h b/targets/arm/mikroe/sam/include/gpio/implementations/arm_gcc_clang_atsam_e70/hal_ll_gpio_constants.h new file mode 100644 index 000000000..ac120aad7 --- /dev/null +++ b/targets/arm/mikroe/sam/include/gpio/implementations/arm_gcc_clang_atsam_e70/hal_ll_gpio_constants.h @@ -0,0 +1,153 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_constants.h + * @brief GPIO HAL LL macros. + */ + +#ifndef _HAL_LL_GPIO_CONSTANTS_H_ +#define _HAL_LL_GPIO_CONSTANTS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// Define any specific macros here +// REPLACE_MACROS // + +// Predefined macros if missing +#ifndef GPIO_OSPEEDER_OSPEEDR0 +#define GPIO_OSPEEDER_OSPEEDR0 ( uint32_t )0x03 +#endif +#ifndef GPIO_MODER_MODER0 +#define GPIO_MODER_MODER0 ( uint32_t )0x03 +#endif +#ifndef GPIO_OTYPER_OT_0 +#define GPIO_OTYPER_OT_0 ( uint32_t )0x01 +#endif +#ifndef GPIO_PUPDR_PUPDR0 +#define GPIO_PUPDR_PUPDR0 ( uint32_t )0x03 +#endif + +#ifndef GPIO_PIN_MASK_LOW +#define GPIO_PIN_MASK_LOW ( uint32_t )0x00FF +#endif +#ifndef GPIO_PIN_MASK_HIGH +#define GPIO_PIN_MASK_HIGH ( uint32_t )0xFF00 +#endif +#ifndef GPIO_PIN_MASK_ALL +#define GPIO_PIN_MASK_ALL ( uint32_t )0xFFFF +#endif + +#ifndef GPIO_AF_CONFIG_OFFSET +#define GPIO_AF_CONFIG_OFFSET ( uint32_t )20 +#endif +#ifndef GPIO_AF_MASK +#define GPIO_AF_MASK ( 0x0F ) +#endif +#ifndef GPIO_PIN_NAME_MASK +#define GPIO_PIN_NAME_MASK ( ( uint32_t )0xFF ) +#endif +#ifndef GPIO_AF_CONFIG_MASK +#define GPIO_AF_CONFIG_MASK ( ( uint32_t )0x0F << GPIO_AF_CONFIG_OFFSET ) +#endif + +#ifndef GPIO_CFG_MODE_ANALOG +#define GPIO_CFG_MODE_ANALOG ( uint32_t )0x1 +#endif +#ifndef GPIO_CFG_MODE_INPUT +#define GPIO_CFG_MODE_INPUT ( uint32_t )0x2 +#endif +#ifndef GPIO_CFG_MODE_OUTPUT +#define GPIO_CFG_MODE_OUTPUT ( uint32_t )0x4 +#endif +#ifndef GPIO_CFG_MODE_ALT_FUNCTION +#define GPIO_CFG_MODE_ALT_FUNCTION ( uint32_t )0x8 +#endif +#ifndef GPIO_CFG_OTYPE_PP +#define GPIO_CFG_OTYPE_PP ( uint32_t )0x10 +#endif +#ifndef GPIO_CFG_OTYPE_OD +#define GPIO_CFG_OTYPE_OD ( uint32_t )0x20 +#endif +#ifndef GPIO_CFG_PULL_NO +#define GPIO_CFG_PULL_NO ( uint32_t )0x40 +#endif +#ifndef GPIO_CFG_PULL_UP +#define GPIO_CFG_PULL_UP ( uint32_t )0x80 +#endif +#ifndef GPIO_CFG_PULL_DOWN +#define GPIO_CFG_PULL_DOWN ( uint32_t )0x100 +#endif +#ifndef GPIO_CFG_SPEED_LOW +#define GPIO_CFG_SPEED_LOW ( uint32_t )0x0 +#endif +#ifndef GPIO_CFG_SPEED_MEDIUM +#define GPIO_CFG_SPEED_MEDIUM ( uint32_t )0x200 +#endif +#ifndef GPIO_CFG_SPEED_HIGH +#define GPIO_CFG_SPEED_HIGH ( uint32_t )0x400 +#endif +#ifndef GPIO_CFG_SPEED_VERY_HIGH +#define GPIO_CFG_SPEED_VERY_HIGH ( uint32_t )0x800 +#endif +#ifndef GPIO_CFG_SPEED_MAX +#define GPIO_CFG_SPEED_MAX ( uint32_t )0x80000 +#endif + +#ifndef GPIO_AHB_SHIFT +#define GPIO_AHB_SHIFT 17 +#endif + +#ifndef GPIO_CFG_DIGITAL_OUTPUT +#define GPIO_CFG_DIGITAL_OUTPUT ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_SPEED_MAX | GPIO_CFG_OTYPE_PP ) +#endif +#ifndef GPIO_CFG_DIGITAL_INPUT +#define GPIO_CFG_DIGITAL_INPUT ( GPIO_CFG_MODE_INPUT | GPIO_CFG_PULL_NO ) +#endif +#ifndef GPIO_CFG_ANALOG_INPUT +#define GPIO_CFG_ANALOG_INPUT ( GPIO_CFG_MODE_ANALOG | GPIO_CFG_PULL_NO ) +#endif + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_CONSTANTS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/sam/include/gpio/implementations/arm_gcc_clang_atsam_e70/hal_ll_gpio_struct_type.h b/targets/arm/mikroe/sam/include/gpio/implementations/arm_gcc_clang_atsam_e70/hal_ll_gpio_struct_type.h new file mode 100644 index 000000000..785963f29 --- /dev/null +++ b/targets/arm/mikroe/sam/include/gpio/implementations/arm_gcc_clang_atsam_e70/hal_ll_gpio_struct_type.h @@ -0,0 +1,107 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_struct_type.h + * @brief GPIO HAL LL register structure typedef. + */ + +#ifndef _HAL_LL_GPIO_STRUCT_TYPE_H_ +#define _HAL_LL_GPIO_STRUCT_TYPE_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * GPIO module interrupt registers control structure + **/ +typedef struct hal_ll_gpio_interrupt_register_handle +{ + uint32_t enable; + uint32_t disable; + uint32_t mask; + uint32_t status; +} hal_ll_gpio_interrupt_register_handle_t; + +/** + * GPIO module signal register control structure + **/ +typedef struct hal_ll_gpio_signal_register_handle +{ + uint32_t enable; + uint32_t disable; + uint32_t status; + uint32_t pin_status; +} hal_ll_gpio_signal_register_handle_t; + +/** + * GPIO module registers control structure + **/ +typedef struct hal_ll_gpio_register_handle +{ + uint32_t enable; + uint32_t disable; + uint32_t status; + uint32_t unused; +} hal_ll_gpio_register_handle_t; + +/** + * GPIO module registers access structure + */ +typedef struct hal_ll_gpio_base_handle +{ + hal_ll_gpio_register_handle_t pio; /* Parallel input-output controller */ + hal_ll_gpio_register_handle_t output; /* Output configuration controller */ + hal_ll_gpio_register_handle_t filter; /* Input filter controller */ + hal_ll_gpio_signal_register_handle_t signal; /* Output signal controller */ + hal_ll_gpio_interrupt_register_handle_t interrupt; + hal_ll_gpio_register_handle_t multi_driver; + hal_ll_gpio_register_handle_t pullup_disable; + uint32_t abcdsr0; /* Peripheral ABCD Select Register 0 */ + uint32_t abcdsr1; /* Peripheral ABCD Select Register 1 */ +} hal_ll_gpio_base_handle_t; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_STRUCT_TYPE_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/sam/include/gpio/implementations/arm_gcc_clang_atsam_e70/hal_ll_gpio_struct_type.h.bak b/targets/arm/mikroe/sam/include/gpio/implementations/arm_gcc_clang_atsam_e70/hal_ll_gpio_struct_type.h.bak new file mode 100644 index 000000000..36f24c3bf --- /dev/null +++ b/targets/arm/mikroe/sam/include/gpio/implementations/arm_gcc_clang_atsam_e70/hal_ll_gpio_struct_type.h.bak @@ -0,0 +1,107 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_struct_type.h + * @brief GPIO HAL LL register structure typedef. + */ + +#ifndef _HAL_LL_GPIO_STRUCT_TYPE_H_ +#define _HAL_LL_GPIO_STRUCT_TYPE_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * GPIO module interrupt registers control structure + **/ +typedef struct hal_ll_gpio_interrupt_register_handle +{ + uint32_t enable; + uint32_t disable; + uint32_t mask; + uint32_t status; +} hal_ll_gpio_interrupt_register_handle_t; + +/** + * GPIO module signal registers control structure + **/ +typedef struct hal_ll_gpio_signal_register_handle +{ + uint32_t enable; + uint32_t disable; + uint32_t status; + uint32_t pin_status; +} hal_ll_gpio_signal_register_handle_t; + +/** + * GPIO module registers control structure + **/ +typedef struct hal_ll_gpio_register_handle +{ + uint32_t enable; + uint32_t disable; + uint32_t status; + uint32_t unused; +} hal_ll_gpio_register_handle_t; + +/** + * GPIO module registers access structure + */ +typedef struct hal_ll_gpio_base_handle +{ + hal_ll_gpio_register_handle_t pio; /* Parallel input-output controller */ + hal_ll_gpio_register_handle_t output; /* Output configuration controller */ + hal_ll_gpio_register_handle_t filter; /* Input filter controller */ + hal_ll_gpio_signal_register_handle_t signal; /* Output signal controller */ + hal_ll_gpio_interrupt_register_handle_t interrupt; + hal_ll_gpio_register_handle_t multi_driver; + hal_ll_gpio_register_handle_t pullup_disable; + uint32_t abcdsr0; /* Peripheral ABCD Select Register 0 */ + uint32_t abcdsr1; /* Peripheral ABCD Select Register 1 */ +} hal_ll_gpio_base_handle_t; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_STRUCT_TYPE_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/sam/include/hal_ll_pin_names.h b/targets/arm/mikroe/sam/include/hal_ll_pin_names.h new file mode 100644 index 000000000..1f258a2c2 --- /dev/null +++ b/targets/arm/mikroe/sam/include/hal_ll_pin_names.h @@ -0,0 +1,611 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_pin_names.h + * @brief Header file containing symbolic pin name definitions. + */ + +#ifndef _HAL_LL_PIN_NAMES_H_ +#define _HAL_LL_PIN_NAMES_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "mcu_definitions.h" +#include "hal_ll_target_names.h" + +#define GPIO_FEATURE_32BIT_PORT + +#ifdef __PORT_A_CN +#define GPIO_FEATURE_GROUP_1 +#endif +#ifdef __PORT_B_CN +#define GPIO_FEATURE_GROUP_2 +#endif +#ifdef __PORT_C_CN +#define GPIO_FEATURE_GROUP_3 +#endif +#ifdef __PORT_D_CN +#define GPIO_FEATURE_GROUP_4 +#endif +#ifdef __PORT_E_CN +#define GPIO_FEATURE_GROUP_5 +#endif + +#ifdef __PA0_CN +#define PA0 (0x00) +#endif +#ifdef __PA1_CN +#define PA1 (0x01) +#endif +#ifdef __PA2_CN +#define PA2 (0x02) +#endif +#ifdef __PA3_CN +#define PA3 (0x03) +#endif +#ifdef __PA4_CN +#define PA4 (0x04) +#endif +#ifdef __PA5_CN +#define PA5 (0x05) +#endif +#ifdef __PA6_CN +#define PA6 (0x06) +#endif +#ifdef __PA7_CN +#define PA7 (0x07) +#endif +#ifdef __PA8_CN +#define PA8 (0x08) +#endif +#ifdef __PA9_CN +#define PA9 (0x09) +#endif +#ifdef __PA10_CN +#define PA10 (0x0A) +#endif +#ifdef __PA11_CN +#define PA11 (0x0B) +#endif +#ifdef __PA12_CN +#define PA12 (0x0C) +#endif +#ifdef __PA13_CN +#define PA13 (0x0D) +#endif +#ifdef __PA14_CN +#define PA14 (0x0E) +#endif +#ifdef __PA15_CN +#define PA15 (0x0F) +#endif +#ifdef __PA16_CN +#define PA16 (0x10) +#endif +#ifdef __PA17_CN +#define PA17 (0x11) +#endif +#ifdef __PA18_CN +#define PA18 (0x12) +#endif +#ifdef __PA19_CN +#define PA19 (0x13) +#endif +#ifdef __PA20_CN +#define PA20 (0x14) +#endif +#ifdef __PA21_CN +#define PA21 (0x15) +#endif +#ifdef __PA22_CN +#define PA22 (0x16) +#endif +#ifdef __PA23_CN +#define PA23 (0x17) +#endif +#ifdef __PA24_CN +#define PA24 (0x18) +#endif +#ifdef __PA25_CN +#define PA25 (0x19) +#endif +#ifdef __PA26_CN +#define PA26 (0x1A) +#endif +#ifdef __PA27_CN +#define PA27 (0x1B) +#endif +#ifdef __PA28_CN +#define PA28 (0x1C) +#endif +#ifdef __PA29_CN +#define PA29 (0x1D) +#endif +#ifdef __PA30_CN +#define PA30 (0x1E) +#endif +#ifdef __PA31_CN +#define PA31 (0x1F) +#endif + +#ifdef __PB0_CN +#define PB0 (0x20) +#endif +#ifdef __PB1_CN +#define PB1 (0x21) +#endif +#ifdef __PB2_CN +#define PB2 (0x22) +#endif +#ifdef __PB3_CN +#define PB3 (0x23) +#endif +#ifdef __PB4_CN +#define PB4 (0x24) +#endif +#ifdef __PB5_CN +#define PB5 (0x25) +#endif +#ifdef __PB6_CN +#define PB6 (0x26) +#endif +#ifdef __PB7_CN +#define PB7 (0x27) +#endif +#ifdef __PB8_CN +#define PB8 (0x28) +#endif +#ifdef __PB9_CN +#define PB9 (0x29) +#endif +#ifdef __PB10_CN +#define PB10 (0x2A) +#endif +#ifdef __PB11_CN +#define PB11 (0x2B) +#endif +#ifdef __PB12_CN +#define PB12 (0x2C) +#endif +#ifdef __PB13_CN +#define PB13 (0x2D) +#endif +#ifdef __PB14_CN +#define PB14 (0x2E) +#endif +#ifdef __PB15_CN +#define PB15 (0x2F) +#endif +#ifdef __PB16_CN +#define PB16 (0x30) +#endif +#ifdef __PB17_CN +#define PB17 (0x31) +#endif +#ifdef __PB18_CN +#define PB18 (0x32) +#endif +#ifdef __PB19_CN +#define PB19 (0x33) +#endif +#ifdef __PB20_CN +#define PB20 (0x34) +#endif +#ifdef __PB21_CN +#define PB21 (0x35) +#endif +#ifdef __PB22_CN +#define PB22 (0x36) +#endif +#ifdef __PB23_CN +#define PB23 (0x37) +#endif +#ifdef __PB24_CN +#define PB24 (0x38) +#endif +#ifdef __PB25_CN +#define PB25 (0x39) +#endif +#ifdef __PB26_CN +#define PB26 (0x3A) +#endif +#ifdef __PB27_CN +#define PB27 (0x3B) +#endif +#ifdef __PB28_CN +#define PB28 (0x3C) +#endif +#ifdef __PB29_CN +#define PB29 (0x3D) +#endif +#ifdef __PB30_CN +#define PB30 (0x3E) +#endif +#ifdef __PB31_CN +#define PB31 (0x3F) +#endif + +#ifdef __PC0_CN +#define PC0 (0x40) +#endif +#ifdef __PC1_CN +#define PC1 (0x41) +#endif +#ifdef __PC2_CN +#define PC2 (0x42) +#endif +#ifdef __PC3_CN +#define PC3 (0x43) +#endif +#ifdef __PC4_CN +#define PC4 (0x44) +#endif +#ifdef __PC5_CN +#define PC5 (0x45) +#endif +#ifdef __PC6_CN +#define PC6 (0x46) +#endif +#ifdef __PC7_CN +#define PC7 (0x47) +#endif +#ifdef __PC8_CN +#define PC8 (0x48) +#endif +#ifdef __PC9_CN +#define PC9 (0x49) +#endif +#ifdef __PC10_CN +#define PC10 (0x4A) +#endif +#ifdef __PC11_CN +#define PC11 (0x4B) +#endif +#ifdef __PC12_CN +#define PC12 (0x4C) +#endif +#ifdef __PC13_CN +#define PC13 (0x4D) +#endif +#ifdef __PC14_CN +#define PC14 (0x4E) +#endif +#ifdef __PC15_CN +#define PC15 (0x4F) +#endif +#ifdef __PC16_CN +#define PC16 (0x50) +#endif +#ifdef __PC17_CN +#define PC17 (0x51) +#endif +#ifdef __PC18_CN +#define PC18 (0x52) +#endif +#ifdef __PC19_CN +#define PC19 (0x53) +#endif +#ifdef __PC20_CN +#define PC20 (0x54) +#endif +#ifdef __PC21_CN +#define PC21 (0x55) +#endif +#ifdef __PC22_CN +#define PC22 (0x56) +#endif +#ifdef __PC23_CN +#define PC23 (0x57) +#endif +#ifdef __PC24_CN +#define PC24 (0x58) +#endif +#ifdef __PC25_CN +#define PC25 (0x59) +#endif +#ifdef __PC26_CN +#define PC26 (0x5A) +#endif +#ifdef __PC27_CN +#define PC27 (0x5B) +#endif +#ifdef __PC28_CN +#define PC28 (0x5C) +#endif +#ifdef __PC29_CN +#define PC29 (0x5D) +#endif +#ifdef __PC30_CN +#define PC30 (0x5E) +#endif +#ifdef __PC31_CN +#define PC31 (0x5F) +#endif + +#ifdef __PD0_CN +#define PD0 (0x60) +#endif +#ifdef __PD1_CN +#define PD1 (0x61) +#endif +#ifdef __PD2_CN +#define PD2 (0x62) +#endif +#ifdef __PD3_CN +#define PD3 (0x63) +#endif +#ifdef __PD4_CN +#define PD4 (0x64) +#endif +#ifdef __PD5_CN +#define PD5 (0x65) +#endif +#ifdef __PD6_CN +#define PD6 (0x66) +#endif +#ifdef __PD7_CN +#define PD7 (0x67) +#endif +#ifdef __PD8_CN +#define PD8 (0x68) +#endif +#ifdef __PD9_CN +#define PD9 (0x69) +#endif +#ifdef __PD10_CN +#define PD10 (0x6A) +#endif +#ifdef __PD11_CN +#define PD11 (0x6B) +#endif +#ifdef __PD12_CN +#define PD12 (0x6C) +#endif +#ifdef __PD13_CN +#define PD13 (0x6D) +#endif +#ifdef __PD14_CN +#define PD14 (0x6E) +#endif +#ifdef __PD15_CN +#define PD15 (0x6F) +#endif +#ifdef __PD16_CN +#define PD16 (0x70) +#endif +#ifdef __PD17_CN +#define PD17 (0x71) +#endif +#ifdef __PD18_CN +#define PD18 (0x72) +#endif +#ifdef __PD19_CN +#define PD19 (0x73) +#endif +#ifdef __PD20_CN +#define PD20 (0x74) +#endif +#ifdef __PD21_CN +#define PD21 (0x75) +#endif +#ifdef __PD22_CN +#define PD22 (0x76) +#endif +#ifdef __PD23_CN +#define PD23 (0x77) +#endif +#ifdef __PD24_CN +#define PD24 (0x78) +#endif +#ifdef __PD25_CN +#define PD25 (0x79) +#endif +#ifdef __PD26_CN +#define PD26 (0x7A) +#endif +#ifdef __PD27_CN +#define PD27 (0x7B) +#endif +#ifdef __PD28_CN +#define PD28 (0x7C) +#endif +#ifdef __PD29_CN +#define PD29 (0x7D) +#endif +#ifdef __PD30_CN +#define PD30 (0x7E) +#endif +#ifdef __PD31_CN +#define PD31 (0x7F) +#endif + +#ifdef __PE0_CN +#define PE0 (0x80) +#endif +#ifdef __PE1_CN +#define PE1 (0x81) +#endif +#ifdef __PE2_CN +#define PE2 (0x82) +#endif +#ifdef __PE3_CN +#define PE3 (0x83) +#endif +#ifdef __PE4_CN +#define PE4 (0x84) +#endif +#ifdef __PE5_CN +#define PE5 (0x85) +#endif +#ifdef __PE6_CN +#define PE6 (0x86) +#endif +#ifdef __PE7_CN +#define PE7 (0x87) +#endif +#ifdef __PE8_CN +#define PE8 (0x88) +#endif +#ifdef __PE9_CN +#define PE9 (0x89) +#endif +#ifdef __PE10_CN +#define PE10 (0x8A) +#endif +#ifdef __PE11_CN +#define PE11 (0x8B) +#endif +#ifdef __PE12_CN +#define PE12 (0x8C) +#endif +#ifdef __PE13_CN +#define PE13 (0x8D) +#endif +#ifdef __PE14_CN +#define PE14 (0x8E) +#endif +#ifdef __PE15_CN +#define PE15 (0x8F) +#endif +#ifdef __PE16_CN +#define PE16 (0x90) +#endif +#ifdef __PE17_CN +#define PE17 (0x91) +#endif +#ifdef __PE18_CN +#define PE18 (0x92) +#endif +#ifdef __PE19_CN +#define PE19 (0x93) +#endif +#ifdef __PE20_CN +#define PE20 (0x94) +#endif +#ifdef __PE21_CN +#define PE21 (0x95) +#endif +#ifdef __PE22_CN +#define PE22 (0x96) +#endif +#ifdef __PE23_CN +#define PE23 (0x97) +#endif +#ifdef __PE24_CN +#define PE24 (0x98) +#endif +#ifdef __PE25_CN +#define PE25 (0x99) +#endif +#ifdef __PE26_CN +#define PE26 (0x9A) +#endif +#ifdef __PE27_CN +#define PE27 (0x9B) +#endif +#ifdef __PE28_CN +#define PE28 (0x9C) +#endif +#ifdef __PE29_CN +#define PE29 (0x9D) +#endif +#ifdef __PE30_CN +#define PE30 (0x9E) +#endif +#ifdef __PE31_CN +#define PE31 (0x9F) +#endif + +#define PIN_0 (0x00) +#define PIN_1 (0x01) +#define PIN_2 (0x02) +#define PIN_3 (0x03) +#define PIN_4 (0x04) +#define PIN_5 (0x05) +#define PIN_6 (0x06) +#define PIN_7 (0x07) +#define PIN_8 (0x08) +#define PIN_9 (0x09) +#define PIN_10 (0x0A) +#define PIN_11 (0x0B) +#define PIN_12 (0x0C) +#define PIN_13 (0x0D) +#define PIN_14 (0x0E) +#define PIN_15 (0x0F) +#define PIN_16 (0x10) +#define PIN_17 (0x11) +#define PIN_18 (0x12) +#define PIN_19 (0x13) +#define PIN_20 (0x14) +#define PIN_21 (0x15) +#define PIN_22 (0x16) +#define PIN_23 (0x17) +#define PIN_24 (0x18) +#define PIN_25 (0x19) +#define PIN_26 (0x1A) +#define PIN_27 (0x1B) +#define PIN_28 (0x1C) +#define PIN_29 (0x1D) +#define PIN_30 (0x1E) +#define PIN_31 (0x1F) + +#ifdef __PORT_A_CN +#define PORT_A (0x00) +#endif +#ifdef __PORT_B_CN +#define PORT_B (0x01) +#endif +#ifdef __PORT_C_CN +#define PORT_C (0x02) +#endif +#ifdef __PORT_D_CN +#define PORT_D (0x03) +#endif +#ifdef __PORT_E_CN +#define PORT_E (0x04) +#endif + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_PIN_NAMES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/sam/include/hal_ll_target.h b/targets/arm/mikroe/sam/include/hal_ll_target.h new file mode 100644 index 000000000..64cf00f75 --- /dev/null +++ b/targets/arm/mikroe/sam/include/hal_ll_target.h @@ -0,0 +1,68 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_target.h + * @brief Header file containing symbolic pin name definitions. + */ + +#ifndef _HAL_LL_TARGET_H_ +#define _HAL_LL_TARGET_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" +// TODO - find a way how to include it properly +#include "../../common/include/hal_ll_bit_control.h" +#include "assembly.h" +#include "common_macros.h" +#include "common_types.h" + +#define HAL_LL_MODULE_ERROR (hal_ll_base_addr_t)(0xFFFFFFFF) +#define HAL_LL_CHANNEL_ERROR (hal_ll_base_addr_t)(0xFFFFFF) +#define HAL_LL_PIN_NC (hal_ll_pin_name_t)(0xFFFF) +#define HAL_LL_PORT_NC (hal_ll_port_name_t)(0xFF) + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_TARGET_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/sam/include/hal_ll_target_names.h b/targets/arm/mikroe/sam/include/hal_ll_target_names.h new file mode 100644 index 000000000..521ed9ec6 --- /dev/null +++ b/targets/arm/mikroe/sam/include/hal_ll_target_names.h @@ -0,0 +1,72 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_target_names.h + * @brief Header file containing symbolic pin name definitions. + */ + +#ifndef _HAL_LL_TARGET_NAMES_H_ +#define _HAL_LL_TARGET_NAMES_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include +#include +#include +#include +#include + +typedef uintptr_t handle_t; +typedef uint32_t hal_ll_gpio_mask_t; +typedef uint32_t hal_ll_pin_name_t; +typedef uint8_t hal_ll_port_name_t; +typedef uint32_t hal_ll_port_size_t; +typedef uint32_t hal_ll_base_addr_t; +typedef uint8_t hal_ll_channel_t; + +typedef int32_t hal_ll_err_t; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_TARGET_NAMES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_master.h b/targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_master.h new file mode 100644 index 000000000..46376d50a --- /dev/null +++ b/targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_master.h @@ -0,0 +1,241 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_master.h + * @brief API for I2C master HAL LOW LEVEL layer. + */ + +#ifndef _HAL_LL_I2C_MASTER_H_ +#define _HAL_LL_I2C_MASTER_H_ + +#include "hal_ll_target.h" + +#ifdef __cplusplus +extern "C"{ +#endif + +/** + * @brief I2C master low level pins config structure. + * + * The context structure for storing low level pin configuration + * for both SCL and SDA pins. + * + */ +typedef struct +{ + hal_ll_pin_af_t pin_scl; + hal_ll_pin_af_t pin_sda; +} hal_ll_i2c_pins_t; + +/** + * @brief I2C master low level handle. + * + * The context for storing low level object handler. + * User is not to change these values or unexpected behaviour + * may occur. + */ +typedef struct +{ + handle_t *hal_ll_i2c_master_handle; + handle_t *hal_drv_i2c_master_handle; + bool init_ll_state; +} hal_ll_i2c_master_handle_register_t; + +/** + * @brief Registers handler for future use. + * + * Registers low level and hal level handlers + * for use with appropriate functions. + * + * @param[in] scl I2C SCL pin. + * @param[in] sda I2C SDA pin. + * @param[in] *handle_map HAL layer local handle map. + * @param[in] *hal_module_id HAL layer module number. + + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_master_handle_register_t *handle_map, uint8_t *hal_module_id ); + +/** + * @brief Configures specified module. + * + * Performs module configuration on the hardware + * level. Enables module specific clock gate and + * sets adequate alternate function values. + * + * @param[in] *handle HAL context object handle. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_module_configure_i2c( handle_t *handle ); + +/** + * @brief Sets I2C slave address. + * + * Registers I2C slave address for specified + * object. + * + * @param[in] *handle HAL context object handle. + * @param[in] addr I2C slave address. + * + * @return void None. + */ +void hal_ll_i2c_master_set_slave_address( handle_t *handle, uint8_t addr ); + +/** + * @brief Sets I2C module speed. + * + * Sets specified speed for module. + * Take into consideration that the module + * will be re-initialized on the hardware level. + * + * @param[in] *handle HAL context object handle. + * @param[in] speed Desired speed value. + * + * @return hal_ll_err_t Module specific error. + * + * Returns value of speed the module was + * initialized to, or module specific error if + * initialization failed. + * When using from low level directly, + * speed can be set to any desired value, + * but take into consideration that not all values + * will work, as this is chip specific. + * Speed value is declared in kbit/s. + */ +hal_ll_err_t hal_ll_i2c_master_set_speed( handle_t *handle, uint32_t speed ); + +/** + * @brief Sets I2C timeout value. + * + * Registers I2C timeout value in number of retries. + * Module shall retry any given operation + * `timeout` number of times before aborting operation. + * + * @param[in] *handle HAL context object handle. + * @param[in] timeout I2C timeout value. + * + * @return void None. + */ +void hal_ll_i2c_master_set_timeout( handle_t *handle, uint16_t timeout ); + +/** + * @brief Executes low level data read on I2C bus. + * + * Function shall generate a START signal, + * followed by lenReadData number of reads + * on the bus. Ends with a STOP signal. + * + * @param handle I2C handle. + * @param *readDatabuf Data buffer where read data + * shall be placed. + * @param lenReadData Number of bytes to read. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_i2c_master_read( handle_t *handle, uint8_t *read_data_buf, size_t len_read_data ); + +/** + * @brief Executes low level data write on I2C bus. + * + * Function shall generate a START signal, + * followed by lenWriteData number of writes + * on the bus. Ends with a STOP signal. + * + * @param handle I2C handle. + * @param *WriteDatabuf Data buffer where data to + * be written is located. + * @param lenWriteData Number of bytes to send. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_i2c_master_write( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data ); + +/** + * @brief Perform a low level write followed by a low level read on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a write operation followed by a + * read operation on the bus. + * The operation consists of a start signal followed by lenWriteData number + * of write operations, a restart signal followed by lenReadData number + * of read operations finishing with a stop signal. + * + * @param handle I2C handle. + * @param[in] *writeDatabuf - Pointer to write data buffer. + * @param[in] lenWriteData - Number of data to be written. + * @param[in] *readDatabuf - Pointer to read data buffer. + * @param[in] lenReadData - Number of data to be read. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data, uint8_t *read_data_buf, size_t len_read_data ); + +/** + * @brief Closes I2C master HAL and HAL_LOW_LEVEL context object. + * + * De-allocates hardware resources for specific driver object and + * de-initializes the module on a hardware level. + * + * @param[in] *handle HAL context object handle. + * + * @return void None. + */ +void hal_ll_i2c_master_close( handle_t *handle ); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_I2C_MASTER_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_pin_map/implementations/arm_gcc_clang_atsam_e70/hal_ll_i2c_pin_map.h b/targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_pin_map/implementations/arm_gcc_clang_atsam_e70/hal_ll_i2c_pin_map.h new file mode 100644 index 000000000..b0f70d9a9 --- /dev/null +++ b/targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_pin_map/implementations/arm_gcc_clang_atsam_e70/hal_ll_i2c_pin_map.h @@ -0,0 +1,94 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_pin_map.h + * @brief I2C HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_I2C_PIN_MAP_H_ +#define _HAL_LL_I2C_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_i2c_module_num(_module_num) (_module_num) + +/*!< @brief Pin function structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + uint8_t af; +} hal_ll_i2c_pin_map_t; + +#define HAL_LL_I2C0_BASE_ADDRESS (0x40018000UL) +#define HAL_LL_I2C1_BASE_ADDRESS (0x4001C000UL) +#define HAL_LL_I2C2_BASE_ADDRESS (0x40060000UL) + +/*!< @brief I2C SCL pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_scl_map[] = +{ + {PA4, HAL_LL_I2C0_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_0), 0}, + {PB5, HAL_LL_I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 0}, + {PD28, HAL_LL_I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 2}, + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SCL +}; + +/*!< @brief I2C SDA pins */ +static const hal_ll_i2c_pin_map_t hal_ll_i2c_sda_map[] = +{ + {PA3, HAL_LL_I2C0_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_0), 0}, + {PB4, HAL_LL_I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 0}, + {PD27, HAL_LL_I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 2}, + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} + //------------ END SDA +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_I2C_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/sam/include/pmc/implementations/arm_gcc_clang_atsam_e70/hal_ll_pmc.h b/targets/arm/mikroe/sam/include/pmc/implementations/arm_gcc_clang_atsam_e70/hal_ll_pmc.h new file mode 100644 index 000000000..81baf6c4a --- /dev/null +++ b/targets/arm/mikroe/sam/include/pmc/implementations/arm_gcc_clang_atsam_e70/hal_ll_pmc.h @@ -0,0 +1,125 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_pmc.h + * @brief Reset and Clock control defines necessary for HAL. + */ + +#ifndef _HAL_LL_PMC_H_ +#define _HAL_LL_PMC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include + +/** + * Core register addresses used in source + */ +#define _PMC_BASE (0x400E0600UL) /* PMC Base Address */ +#define _PMC_SCER ((uint32_t *)(_PMC_BASE + 0x00)) /* System Clock Enable Register */ +#define _PMC_SCDR ((uint32_t *)(_PMC_BASE + 0x04)) /* System Clock Disable Register */ +#define _PMC_SCSR ((uint32_t *)(_PMC_BASE + 0x08)) /* System Clock Status Register */ +#define _PMC_PCER0 ((uint32_t *)(_PMC_BASE + 0x10)) /* Peripheral Clock Enable Register 0 */ +#define _PMC_PCDR0 ((uint32_t *)(_PMC_BASE + 0x14)) /* Peripheral Clock Disable Register 0 */ +#define _PMC_PCSR0 ((uint32_t *)(_PMC_BASE + 0x18)) /* Peripheral Clock Status Register 0 */ +#define _CKGR_UCKR ((uint32_t *)(_PMC_BASE + 0x1C)) /* UTMI Clock Register */ +#define _CKGR_MOR ((uint32_t *)(_PMC_BASE + 0x20)) /* Main Oscillator Register */ +#define _CKGR_MCFR ((uint32_t *)(_PMC_BASE + 0x24)) /* Main Clock Frequency Register */ +#define _CKGR_PLLAR ((uint32_t *)(_PMC_BASE + 0x28)) /* PLLA Register */ +#define _PMC_MCKR ((uint32_t *)(_PMC_BASE + 0x30)) /* Master Clock Register */ +#define _PMC_USB ((uint32_t *)(_PMC_BASE + 0x38)) /* USB Clock Register */ +#define _PMC_PCK0 ((uint32_t *)(_PMC_BASE + 0x40)) /* Programmable Clock Register 0 */ +#define _PMC_PCK1 ((uint32_t *)(_PMC_BASE + 0x44)) /* Programmable Clock Register 1 */ +#define _PMC_PCK2 ((uint32_t *)(_PMC_BASE + 0x48)) /* Programmable Clock Register 2 */ +#define _PMC_PCK3 ((uint32_t *)(_PMC_BASE + 0x4C)) /* Programmable Clock Register 3 */ +#define _PMC_PCK4 ((uint32_t *)(_PMC_BASE + 0x50)) /* Programmable Clock Register 4 */ +#define _PMC_PCK5 ((uint32_t *)(_PMC_BASE + 0x54)) /* Programmable Clock Register 5 */ +#define _PMC_PCK6 ((uint32_t *)(_PMC_BASE + 0x58)) /* Programmable Clock Register 6 */ +#define _PMC_PCK7 ((uint32_t *)(_PMC_BASE + 0x5C)) /* Programmable Clock Register 7 */ +#define _PMC_IER ((uint32_t *)(_PMC_BASE + 0x60)) /* Interrupt Enable Register */ +#define _PMC_IDR ((uint32_t *)(_PMC_BASE + 0x64)) /* Interrupt Disable Register */ +#define _PMC_SR ((uint32_t *)(_PMC_BASE + 0x68)) /* Status Register */ +#define _PMC_IMR ((uint32_t *)(_PMC_BASE + 0x6C)) /* Interrupt Mask Register */ +#define _PMC_FSMR ((uint32_t *)(_PMC_BASE + 0x70)) /* Fast Startup Mode Register */ +#define _PMC_FSPR ((uint32_t *)(_PMC_BASE + 0x74)) /* Fast Startup Polarity Register */ +#define _PMC_FOCR ((uint32_t *)(_PMC_BASE + 0x78)) /* Fault Output Clear Register */ +#define _PMC_WPMR ((uint32_t *)(_PMC_BASE + 0xE4)) /* Write Protection Mode Register */ +#define _PMC_WPSR ((uint32_t *)(_PMC_BASE + 0xE8)) /* Write Protection Status Register */ +#define _PMC_PCER1 ((uint32_t *)(_PMC_BASE + 0x100)) /* Peripheral Clock Enable Register 1 */ +#define _PMC_PCDR1 ((uint32_t *)(_PMC_BASE + 0x104)) /* Peripheral Clock Disable Register 1 */ +#define _PMC_PCSR1 ((uint32_t *)(_PMC_BASE + 0x108)) /* Peripheral Clock Status Register 1 */ +#define _PMC_PCR ((uint32_t *)(_PMC_BASE + 0x10C)) /* Peripheral Control Register */ +#define _PMC_OCR ((uint32_t *)(_PMC_BASE + 0x110)) /* Oscillator Calibration Register */ +#define _PMC_SLPWK_ER0 ((uint32_t *)(_PMC_BASE + 0x114)) /* SleepWalking Enable Register 0 */ +#define _PMC_SLPWK_DR0 ((uint32_t *)(_PMC_BASE + 0x118)) /* SleepWalking Disable Register 0 */ +#define _PMC_SLPWK_SR0 ((uint32_t *)(_PMC_BASE + 0x11C)) /* SleepWalking Status Register 0 */ +#define _PMC_SLPWK_ASR0 ((uint32_t *)(_PMC_BASE + 0x120)) /* SleepWalking Activity Status Register 0 */ +#define _PMC_PMMR ((uint32_t *)(_PMC_BASE + 0x130)) /* PLL Maximum Multiplier Value Register */ +#define _PMC_SLPWK_ER1 ((uint32_t *)(_PMC_BASE + 0x134)) /* SleepWalking Enable Register 1 */ +#define _PMC_SLPWK_DR1 ((uint32_t *)(_PMC_BASE + 0x138)) /* SleepWalking Disable Register 1 */ +#define _PMC_SLPWK_SR1 ((uint32_t *)(_PMC_BASE + 0x13C)) /* SleepWalking Status Register 1 */ +#define _PMC_SLPWK_ASR1 ((uint32_t *)(_PMC_BASE + 0x140)) /* SleepWalking Activity Status Register 1 */ +#define _PMC_SLPWK_AIPR ((uint32_t *)(_PMC_BASE + 0x144)) /* SleepWalking Activity In Progress Register */ + +/** + * RCC Structs used in source + */ +typedef struct pmc_clocks +{ + uint32_t mck; // Master clock frequency in Hz + uint32_t pck[8]; // Peripheral clock frequency in Hz +} pmc_clocks_t; + +/** + * @brief Gets clock values. + * + * @param pmc_clocks_t[OUT] RCC clocks structure. + * + * @return *pmc_clocks_t Structure containing clock values. + */ +void RCC_GetClocksFrequency(pmc_clocks_t *PMC_Clocks); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_PMC_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master.h b/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master.h new file mode 100644 index 000000000..f2035088b --- /dev/null +++ b/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master.h @@ -0,0 +1,232 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master.h + * @brief API for SPI master HAL LOW LEVEL layer. + */ + +#ifndef _HAL_LL_SPI_MASTER_H_ +#define _HAL_LL_SPI_MASTER_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_target.h" +#include "hal_ll_gpio.h" + +/** + * @brief SPI configuration pins structure. + */ +typedef struct +{ + hal_ll_pin_af_t sck; + hal_ll_pin_af_t miso; + hal_ll_pin_af_t mosi; +} hal_ll_spi_master_pins_t; + +/** + * @brief SPI master HAL low lever configuration structure. + */ +typedef struct +{ + uint8_t default_write_data; + hal_ll_pin_name_t sck; + hal_ll_pin_name_t miso; + hal_ll_pin_name_t mosi; + uint32_t speed; +} hal_ll_spi_master_config_t; + +/** + * @brief Enum containing predefined module mode values. + * + * Enum values: + * + * HAL_LL_SPI_MASTER_MODE_0 -- CPOL = 0, CPHA = 0 + * HAL_LL_SPI_MASTER_MODE_1 -- CPOL = 0, CPHA = 1 + * HAL_LL_SPI_MASTER_MODE_2 -- CPOL = 1, CPHA = 0 + * HAL_LL_SPI_MASTER_MODE_3 -- CPOL = 1, CPHA = 1 + */ +typedef enum +{ + HAL_LL_SPI_MASTER_MODE_0 = 0, + HAL_LL_SPI_MASTER_MODE_1, + HAL_LL_SPI_MASTER_MODE_2, + HAL_LL_SPI_MASTER_MODE_3, + + HAL_LL_SPI_MASTER_MODE_DEFAULT = HAL_LL_SPI_MASTER_MODE_0 +} hal_ll_spi_master_mode_t; + +/** + * @brief SPI master HAL low lever handle register. + */ +typedef struct +{ + handle_t *hal_ll_spi_master_handle; + handle_t *hal_drv_spi_master_handle; + bool init_ll_state; +} hal_ll_spi_master_handle_register_t; + +/** + * @brief Registers handler for future use. + * + * Registers low level and hal level handlers + * for use with appropriate functions. + * + * @param[in] *handle HAL context object handle. + * @param[in] sck SPI sck pin. + * @param[in] miso SPI miso pin. + * @param[in] mosi SPI mosi pin. + * @param[in] *handle_map HAL layer local handle map. + * @param[in] *hal_module_id HAL layer module number. + + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_register_handle( hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, + hal_ll_pin_name_t mosi, hal_ll_spi_master_handle_register_t *handle_map, uint8_t *hal_module_id ); + +/** + * @brief Configures specified module. + * + * Performs module configuration on the hardware + * level. Enables module specific clock gate and + * sets adequate alternate function values. + * + * @param[in] *handle HAL context object handle. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_module_configure_spi( handle_t *handle ); + +/** + * @brief Sets SPI Master configuration dummy data. + * @param config[IN] SPI Master module configuration. + * @param config[IN] user-defined dummy data. + */ +void hal_ll_spi_master_set_default_write_data( handle_t *handle, uint8_t dummy_data ); + +/** + * @brief Sets SPI Master configuration dummy data. + * @param config[IN] SPI Master module configuration. + * @param config[IN] user-defined SPI Master baud rate value. + */ +uint32_t hal_ll_spi_master_set_speed( handle_t *handle, uint32_t speed ); + +/** + * @brief Sets SPI Master configuration dummy data. + * @param[in] *handle HAL context object handle. + * @param[in] mode SPI Master de-facto mode selection. + */ +hal_ll_err_t hal_ll_spi_master_set_mode( handle_t *handle, hal_ll_spi_master_mode_t mode ); + +/** + * @brief Executes low level data write on SPI bus. + * + * Function shall generate a START signal, + * followed by write_data_buffer number of writes + * on the bus. + * + * @param *handle HAL context object handle. + * @param *write_data_buffer Data buffer where data to be written is located. + * @param length_data Number of bytes to send. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_write( handle_t *handle, uint8_t *write_data_buffer, size_t length_data); + +/** + * @brief Executes low level data read on SPI bus. + * + * @param handle I2C handle. + * @param *read_data_buffer Data buffer where read data shall be placed. + * @param length_data Number of bytes to read. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_read( handle_t *handle, uint8_t *read_data_buffer, size_t length_data); + +/** + * @brief Perform a low level write followed by a low level read on the SPI bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation followed by a + * read operation on the bus. + * + * @param[in] *handle - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to write data buffer. + * @param[in] length_write_data - Number of data to be written. + * @param[in] *read_data_buffer - Pointer to read data buffer. + * @param[in] length_read_data - Number of data to be read. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_write_then_read( handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data ); + +/** + * @brief Closes SPI Master HAL and HAL_LOW_LEVEL context object. + * + * De-allocates hardware resources for specific driver object and + * de-initializes the module on a hardware level. + * + * @param[in] *handle HAL context object handle. + * + * @return void None. + */ +void hal_ll_spi_master_close( handle_t *handle ); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_SPI_MASTER_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master_pin_map/implementations/arm_gcc_clang_atsam_e70/hal_ll_spi_master_pin_map.h b/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master_pin_map/implementations/arm_gcc_clang_atsam_e70/hal_ll_spi_master_pin_map.h new file mode 100644 index 000000000..e67d0bc76 --- /dev/null +++ b/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master_pin_map/implementations/arm_gcc_clang_atsam_e70/hal_ll_spi_master_pin_map.h @@ -0,0 +1,101 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master_pin_map.h + * @brief SPI HAL LOW LEVEL MASTER PIN MAP. + */ + +#ifndef _HAL_LL_SPI_MASTER_PIN_MAP_H_ +#define _HAL_LL_SPI_MASTER_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_spi_master_module_num(_module_num) (_module_num) + +/*!< @brief Macro defining `weak` attribute */ +#define __weak __attribute__((weak)) + +/*!< SPI module base addresses. */ +static const hal_ll_base_addr_t HAL_LL_SPI0_MASTER_BASE_ADDR = 0x40008000; +static const hal_ll_base_addr_t HAL_LL_SPI1_MASTER_BASE_ADDR = 0x40058000; + +/*!< @brief Pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint8_t module_index; + uint32_t af; +} hal_ll_spi_master_pin_map_t; + +/*!< @brief SPI SCK pins. */ +static const hal_ll_spi_master_pin_map_t _spi_sck_map[] = +{ + {PD22, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 1}, + {PC24, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 2}, + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MISO pins. */ +static const hal_ll_spi_master_pin_map_t _spi_miso_map[] = +{ + {PD20, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 1}, + {PC26, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 2}, + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +/*!< @brief SPI MOSI pins. */ +static const hal_ll_spi_master_pin_map_t _spi_mosi_map[] = +{ + {PD21, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 1}, + {PC27, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 2}, + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_SPI_MASTER_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/sam/include/tim/hal_ll_tim.h b/targets/arm/mikroe/sam/include/tim/hal_ll_tim.h new file mode 100644 index 000000000..a5b601151 --- /dev/null +++ b/targets/arm/mikroe/sam/include/tim/hal_ll_tim.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim.h + * @brief Brief file description. + */ + +#ifndef _HAL_LL_TIM_H_ +#define _HAL_LL_TIM_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_target.h" + +/** + * TIM modules + */ +typedef enum +{ + HAL_LL_TIM_MODULE_DEFAULT = 0xFF, + #if defined(TIM_MODULE_1) + HAL_LL_TIM_MODULE_1 = 1, + #endif + #if defined(TIM_MODULE_2) + HAL_LL_TIM_MODULE_2 = 2, + #endif + #if defined(TIM_MODULE_3) + HAL_LL_TIM_MODULE_3 = 3, + #endif + #if defined(TIM_MODULE_4) + HAL_LL_TIM_MODULE_4 = 4, + #endif + #if defined(TIM_MODULE_5) + HAL_LL_TIM_MODULE_5 = 5, + #endif + #if defined(TIM_MODULE_6) + HAL_LL_TIM_MODULE_6 = 6, + #endif + #if defined(TIM_MODULE_7) + HAL_LL_TIM_MODULE_7 = 7, + #endif + #if defined(TIM_MODULE_8) + HAL_LL_TIM_MODULE_8 = 8, + #endif + #if defined(TIM_MODULE_9) + HAL_LL_TIM_MODULE_9 = 9, + #endif + #if defined(TIM_MODULE_10) + HAL_LL_TIM_MODULE_10 = 10, + #endif + #if defined(TIM_MODULE_11) + HAL_LL_TIM_MODULE_11 = 11, + #endif + #if defined(TIM_MODULE_12) + HAL_LL_TIM_MODULE_12 = 12, + #endif + #if defined(TIM_MODULE_13) + HAL_LL_TIM_MODULE_13 = 13, + #endif + #if defined(TIM_MODULE_14) + HAL_LL_TIM_MODULE_14 = 14, + #endif + #if defined(TIM_MODULE_15) + HAL_LL_TIM_MODULE_15 = 15, + #endif + #if defined(TIM_MODULE_16) + HAL_LL_TIM_MODULE_16 = 16, + #endif + #if defined(TIM_MODULE_17) + HAL_LL_TIM_MODULE_17 = 17, + #endif + #if defined(TIM_MODULE_18) + HAL_LL_TIM_MODULE_18 = 18, + #endif + #if defined(TIM_MODULE_19) + HAL_LL_TIM_MODULE_19 = 19, + #endif + #if defined(TIM_MODULE_20) + HAL_LL_TIM_MODULE_20 = 20, + #endif + #if defined(TIM_MODULE_21) + HAL_LL_TIM_MODULE_21 = 21, + #endif + #if defined(TIM_MODULE_22) + HAL_LL_TIM_MODULE_22 = 22, + #endif + + HAL_LL_TIM_MODULE_NONE +} hal_ll_tim_module_number_t; + +typedef struct +{ + handle_t *hal_ll_tim_handle; + handle_t *hal_drv_tim_handle; + bool init_ll_state; +} hal_ll_tim_handle_register_t; + +/** + * @brief Registers handler for future use. + * + * Registers low level and hal level handlers + * for use with appropriate functions. + * + * @param pin TIM pin. + * @param handle_map HAL layer local handle map. + * @param hal_module_id HAL layer module number. + + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_tim_register_handle( hal_ll_pin_name_t pin, + hal_ll_tim_handle_register_t *handle_map, uint8_t *hal_module_id ); + +/** + * @brief Configures specified module. + * + * Performs module configuration on the hardware + * level. Enables module specific clock gate and + * sets adequate alternate function values. + * + * @param[in] *handle HAL context object handle. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle ); + +/** + * @brief Enables counter for TIM module. + * + * Initializes TIM module on hardware level, if not already initialized and + * starts TIM module. + * + * @param handle TIM handle. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_tim_start( handle_t *handle ); + +/** + * @brief Stops counter for TIM module. + * + * The TIM Module needs to be initialized so that + * the stop can be done. + * + * @param handle TIM handle. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_tim_stop( handle_t *handle ); + +/** + * @brief Set TIM frequency in Hertz. + * + * This function is used to set the TIM frequency, it + * stops TIM module and sets duty_cycle on 0. + * Take into consideration that the module + * will be re-initialized on the hardware level. + * + * @param handle TIM handle. + * @param freq_hz TIM frequency in hz. + * + * @return This function returns the frequency value in hz, + * to which the PWM module is set. + * + * @note If the frequency value is less than allowed, + * the frequency will be set to the lowest possible value for the specified TIM. + */ +uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz ); + +/** + * @brief Set TIM duty cycle in percentages. + * + * The user should enter the duty_ratio in percentages. + * The dut_ratio value should be between 0 and 1 + * (where 0 represents 0% and 1 represents 100%). + * + * @param handle TIM handle. + * @param duty_ratio TIM duty ratio in percentages. + * + * @return hal_ll_err_t Module specific error. + * + * @note Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ); + +/** + * @brief Closes TIM master HAL and HAL_LOW_LEVEL context object. + * + * De-allocates hardware resources for specific driver object and + * de-initializes the module on a hardware level. + * + * @param handle TIM handle. + * + * @return void None. + */ +void hal_ll_tim_close( handle_t *handle ); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_TIM_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/arm_gcc_clang_atsam_e70/hal_ll_tim_pin_map.h b/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/arm_gcc_clang_atsam_e70/hal_ll_tim_pin_map.h new file mode 100644 index 000000000..1e8fcc04a --- /dev/null +++ b/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/arm_gcc_clang_atsam_e70/hal_ll_tim_pin_map.h @@ -0,0 +1,116 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim_pin_map.h + * @brief TIM HAL LOW LEVEL PIN MAP. + */ + +#ifndef _HAL_LL_TIM_PIN_MAP_H_ +#define _HAL_LL_TIM_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_tim_module_num(_module_num) (_module_num) + +/*!< @brief Alternate pin function structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_channel_t channel; + uint8_t af; + hal_ll_pin_name_t module_index; +} hal_ll_tim_pin_map_t; + +typedef enum +{ + HAL_LL_TIM_CHANNEL_0 = 0, + HAL_LL_TIM_CHANNEL_1, + HAL_LL_TIM_CHANNEL_2 +} hal_ll_tim_channel_t; + +#define HAL_LL_TIM0_BASE_ADDRESS (0x4000C000UL) +#define HAL_LL_TIM1_BASE_ADDRESS (0x40010000UL) +#define HAL_LL_TIM2_BASE_ADDRESS (0x40014000UL) +#define HAL_LL_TIM3_BASE_ADDRESS (0x40054000UL) + +#define HAL_LL_ALTERNATE_FUNCTION_MASK 0x0F +#define HAL_LL_SIGNAL_CHANNEL_AB_MASK 0xF0 + +/*!< @brief TIM pins. */ +static const hal_ll_tim_pin_map_t _tim_map[] = { + {PA0, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x01, hal_ll_tim_module_num(TIM_MODULE_0)}, + {PA1, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x11, hal_ll_tim_module_num(TIM_MODULE_0)}, + {PA15, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x01, hal_ll_tim_module_num(TIM_MODULE_0)}, + {PA16, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x11, hal_ll_tim_module_num(TIM_MODULE_0)}, + {PA26, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x01, hal_ll_tim_module_num(TIM_MODULE_0)}, + {PA27, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x11, hal_ll_tim_module_num(TIM_MODULE_0)}, + {PC23, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x01, hal_ll_tim_module_num(TIM_MODULE_1)}, + {PC24, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x11, hal_ll_tim_module_num(TIM_MODULE_1)}, + {PC26, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x01, hal_ll_tim_module_num(TIM_MODULE_1)}, + {PC27, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x11, hal_ll_tim_module_num(TIM_MODULE_1)}, + {PC29, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x01, hal_ll_tim_module_num(TIM_MODULE_1)}, + {PC30, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x11, hal_ll_tim_module_num(TIM_MODULE_1)}, + {PC5, HAL_LL_TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x01, hal_ll_tim_module_num(TIM_MODULE_2)}, + {PC6, HAL_LL_TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x11, hal_ll_tim_module_num(TIM_MODULE_2)}, + {PC8, HAL_LL_TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x01, hal_ll_tim_module_num(TIM_MODULE_2)}, + {PC9, HAL_LL_TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x11, hal_ll_tim_module_num(TIM_MODULE_2)}, + {PC11, HAL_LL_TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x01, hal_ll_tim_module_num(TIM_MODULE_2)}, + {PC12, HAL_LL_TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x11, hal_ll_tim_module_num(TIM_MODULE_2)}, + {PE0, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x01, hal_ll_tim_module_num(TIM_MODULE_3)}, + {PE1, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x11, hal_ll_tim_module_num(TIM_MODULE_3)}, + {PE3, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x01, hal_ll_tim_module_num(TIM_MODULE_3)}, + {PE4, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x11, hal_ll_tim_module_num(TIM_MODULE_3)}, + {PD21, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x02, hal_ll_tim_module_num(TIM_MODULE_3)}, + {PD22, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x12, hal_ll_tim_module_num(TIM_MODULE_3)}, + + { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_CHANNEL_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC } +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_TIM_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/sam/include/uart/hal_ll_uart.h b/targets/arm/mikroe/sam/include/uart/hal_ll_uart.h new file mode 100644 index 000000000..287edf4ff --- /dev/null +++ b/targets/arm/mikroe/sam/include/uart/hal_ll_uart.h @@ -0,0 +1,299 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart.h + * @brief API for UART HAL LOW LEVEL layer. + */ + +#ifndef _HAL_LL_UART_H_ +#define _HAL_LL_UART_H_ + +#include "hal_ll_target.h" + +#ifdef __cplusplus +extern "C"{ +#endif + +/** + * @brief Interrupt request type enum. + */ +typedef enum +{ + HAL_LL_UART_IRQ_RX, /**< RX INT */ + HAL_LL_UART_IRQ_TX /**< TX INT */ +} hal_ll_uart_irq_t; + +/** + * @brief Pointer to interrupt handler function. + */ +typedef void ( *hal_ll_uart_isr_t )( handle_t handle, hal_ll_uart_irq_t event ); + +/** + * @brief Predefined enum values for parity selection. + */ +typedef enum +{ + HAL_LL_UART_PARITY_NONE = 0, + HAL_LL_UART_PARITY_EVEN, + HAL_LL_UART_PARITY_ODD, + + HAL_LL_UART_PARITY_DEFAULT = HAL_LL_UART_PARITY_NONE +} hal_ll_uart_parity_t; + +/** + * @brief Predefined enum values for stop bit selection. + */ +typedef enum +{ + HAL_LL_UART_STOP_BITS_HALF = 0, + HAL_LL_UART_STOP_BITS_ONE, + HAL_LL_UART_STOP_BITS_ONE_AND_A_HALF, + HAL_LL_UART_STOP_BITS_TWO, + + HAL_LL_UART_STOP_BITS_DEFAULT = HAL_LL_UART_STOP_BITS_ONE +} hal_ll_uart_stop_bits_t; + +/** + * @brief Predefined enum values for data bit selection. + */ +typedef enum +{ + HAL_LL_UART_DATA_BITS_7 = 0, + HAL_LL_UART_DATA_BITS_8, + + HAL_LL_UART_DATA_BITS_DEFAULT = HAL_LL_UART_DATA_BITS_8 +} hal_ll_uart_data_bits_t; + +/** + * @brief I2C master low level pins config structure. + * + * The context structure for storing low level pin configuration + * for both SCL and SDA pins. + * + */ +typedef struct +{ + hal_ll_pin_af_t tx_pin; + hal_ll_pin_af_t rx_pin; +} hal_ll_uart_pins_t; + +/** + * @brief I2C master low level handle. + * + * The context for storing low level object handler. + * User is not to change these values or unexpected behaviour + * may occur. + */ +typedef struct +{ + handle_t *hal_ll_uart_handle; + handle_t *hal_drv_uart_handle; + bool init_ll_state; +} hal_ll_uart_handle_register_t; + +/** + * @brief Registers handler for future use. + * + * Registers low level and hal level handlers + * for use with appropriate functions. + * + * @param[in] tx_pin UART TX pin. + * @param[in] rx_pin UART RX pin. + * @param[in] *handle_map HAL layer local handle map. + * @param[in] *hal_module_id HAL layer module number. + + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_uart_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_handle_register_t *handle_map, uint8_t *hal_module_id ); + +/** + * @brief Configures specified module. + * + * Performs module configuration on the hardware + * level. Enables module specific clock gate and + * sets adequate alternate function values. + * + * @param[in] *handle HAL context object handle. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_module_configure_uart( handle_t *handle ); + +/** + * @brief Registers interrupt handlers for future use. + * + * Registers low level interrupt handlers + * for use with appropriate functions. + * + * @param[in] handle HAL context object handle. + * @param[in] handler Predefined pointer function. + * @param[in] obj HAL context handle address. + + * @return None. + */ +void hal_ll_uart_register_irq_handler( handle_t *handle, hal_ll_uart_isr_t handler, handle_t obj ); + +/** + * @brief Sets desired baud rate. + * + * Initializes module with specified baud rate value. + * Take into consideration that if the difference + * between desired baud rate and actual baud + * rate the hw was initialized to is greater than + * 1%, baud rate shall not be set. + * If this occurs, return value shall be + * the error percentage. + * + * @param[in] handle HAL context object handle. + * @param[in] baud Desired baud rate value in Bits/s. + * + * @return Actual baud rate value the hw module was initialized to, + * or module specific error value if init failed. + */ +hal_ll_err_t hal_ll_uart_set_baud( handle_t *handle, uint32_t baud ); + +/** + * @brief Sets desired parity. + * + * Initializes module with specified parity value. + * + * @param[in] handle HAL context object handle. + * @param[in] parity One of pre-defined values. + * + * @return Re-init module state. If neccessary. + */ +hal_ll_err_t hal_ll_uart_set_parity( handle_t *handle, hal_ll_uart_parity_t parity ); + +/** + * @brief Sets desired stop bits. + * + * Initializes module with specified stop bits value. + * + * @param[in] handle HAL context object handle. + * @param[in] stop_bit One of pre-defined values. + * + * @return Re-init module state. If neccessary. + */ +hal_ll_err_t hal_ll_uart_set_stop_bits( handle_t *handle, hal_ll_uart_stop_bits_t stop_bit ); + +/** + * @brief Sets desired data bits. + * + * Initializes module with specified data bits value. + * + * @param[in] handle HAL context object handle. + * @param[in] data_bit One of pre-defined values. + * + * @return Re-init module state. If neccessary. + */ +hal_ll_err_t hal_ll_uart_set_data_bits( handle_t *handle, hal_ll_uart_data_bits_t data_bit ); + +/** + * @brief Enables module specific interrupt. + * + * Enables module specific interrupt and registers + * interrupt on hardware level and enables it. + * + * @param[in] handle HAL context object handle. + * @param[in] irq Chip interrupt IRQ value. + * + * @return void None. + */ +void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq ); + +/** + * @brief Disables module specific interrupt. + * + * Disables module specific interrupt. + * + * @param[in] handle HAL context object handle. + * @param[in] irq Chip interrupt IRQ value. + * + * @return void None. + */ +void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ); + +/** + * @brief Performs read operation. + * + * Reads one byte on a hardware level. + * + * @param[in] handle HAL context object handle. + * + * @return uint8_t Data read from hw register. + */ +uint8_t hal_ll_uart_read( handle_t *handle ); + +/** + * @brief Performs write operation. + * + * Accesses hardware data registers and + * writes data directly to it. + * + * @param[in] handle HAL context object handle. + * @param[in] wr_data Data to be written. + * + * @return void None. + */ +void hal_ll_uart_write( handle_t *handle, uint8_t wr_data); + +/** + * @brief Closes UART HAL and HAL_LOW_LEVEL context object. + * + * De-allocates hardware resources for specific driver object and + * de-initializes the module on a hardware level. + * + * @param[in] *handle HAL context object handle. + * + * @return void None. + */ +void hal_ll_uart_close( handle_t *handle ); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_UART_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/sam/include/uart/hal_ll_uart_pin_map/implementations/arm_gcc_clang_atsam_e70/hal_ll_uart_pin_map.h b/targets/arm/mikroe/sam/include/uart/hal_ll_uart_pin_map/implementations/arm_gcc_clang_atsam_e70/hal_ll_uart_pin_map.h new file mode 100644 index 000000000..714030cb0 --- /dev/null +++ b/targets/arm/mikroe/sam/include/uart/hal_ll_uart_pin_map/implementations/arm_gcc_clang_atsam_e70/hal_ll_uart_pin_map.h @@ -0,0 +1,110 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart_pin_map.h + * @brief UART HAL LOW LEVEL PIN MAPS. + */ + +#ifndef _HAL_LL_UART_PIN_MAP_H_ +#define _HAL_LL_UART_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_usart_module_num(_module_num) (_module_num) +#define hal_ll_uart_module_num(_module_num) (_module_num + USART_MODULE_COUNT) + +/*!< @brief Pin structure */ +typedef struct +{ + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint8_t af; +} hal_ll_uart_pin_map_t; + +#define HAL_LL_USART0_BASE_ADDRESS 0x40024000UL +#define HAL_LL_USART1_BASE_ADDRESS 0x40028000UL +#define HAL_LL_USART2_BASE_ADDRESS 0x4002C000UL +#define HAL_LL_UART0_BASE_ADDRESS 0x400E0800UL +#define HAL_LL_UART1_BASE_ADDRESS 0x400E0A00UL +#define HAL_LL_UART2_BASE_ADDRESS 0x400E1A00UL +#define HAL_LL_UART3_BASE_ADDRESS 0x400E1C00UL +#define HAL_LL_UART4_BASE_ADDRESS 0x400E1E00UL + +/*!< @brief UART TX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = +{ + {hal_ll_usart_module_num(USART_MODULE_0), PB1, HAL_LL_USART0_BASE_ADDRESS, 2}, + {hal_ll_usart_module_num(USART_MODULE_1), PB4, HAL_LL_USART0_BASE_ADDRESS, 3}, + {hal_ll_usart_module_num(USART_MODULE_2), PD16, HAL_LL_USART0_BASE_ADDRESS, 1}, + {hal_ll_uart_module_num(UART_MODULE_0), PA10, HAL_LL_UART0_BASE_ADDRESS, 0}, + {hal_ll_uart_module_num(UART_MODULE_1), PA4, HAL_LL_UART1_BASE_ADDRESS, 2}, + {hal_ll_uart_module_num(UART_MODULE_1), PA6, HAL_LL_UART1_BASE_ADDRESS, 2}, + {hal_ll_uart_module_num(UART_MODULE_2), PD26, HAL_LL_UART2_BASE_ADDRESS, 2}, + {hal_ll_uart_module_num(UART_MODULE_3), PD30, HAL_LL_UART3_BASE_ADDRESS, 0}, + {hal_ll_uart_module_num(UART_MODULE_3), PD31, HAL_LL_UART3_BASE_ADDRESS, 1}, + {hal_ll_uart_module_num(UART_MODULE_4), PD19, HAL_LL_UART4_BASE_ADDRESS, 2}, + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} +}; + +/*!< @brief UART RX pins */ +static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = +{ + {hal_ll_usart_module_num(USART_MODULE_0), PB0, HAL_LL_USART0_BASE_ADDRESS, 2}, + {hal_ll_usart_module_num(USART_MODULE_1), PA21, HAL_LL_USART1_BASE_ADDRESS, 2}, + {hal_ll_usart_module_num(USART_MODULE_2), PD15, HAL_LL_USART2_BASE_ADDRESS, 1}, + {hal_ll_uart_module_num(UART_MODULE_0), PA9, HAL_LL_UART0_BASE_ADDRESS, 0}, + {hal_ll_uart_module_num(UART_MODULE_1), PA5, HAL_LL_UART1_BASE_ADDRESS, 2}, + {hal_ll_uart_module_num(UART_MODULE_2), PD25, HAL_LL_UART2_BASE_ADDRESS, 2}, + {hal_ll_uart_module_num(UART_MODULE_3), PD28, HAL_LL_UART3_BASE_ADDRESS, 0}, + {hal_ll_uart_module_num(UART_MODULE_4), PD18, HAL_LL_UART4_BASE_ADDRESS, 2}, + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_UART_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt b/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt new file mode 100644 index 000000000..807e64d39 --- /dev/null +++ b/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt @@ -0,0 +1,73 @@ +## ./targets/arm/mikroe/ai_generated/stm32/src/gpio/CMakeLists.txt + +## Check if current module is generated or not +set(MODULE_IS_GENERATED false) +get_files_recurse(${CMAKE_CURRENT_LIST_DIR}/implementations CMAKE_FILES cmake) +check_if_module_is_generated(MODULE_IS_GENERATED "${CMAKE_FILES}") + +## If current MCU has this module, add it +if(MODULE_IS_GENERATED) + set(hal_ll_def_list "") + set(MEMAKE_MCU_NAME_FIRST_7 "") + set(mcu_header_path "") + + find_cortex(hal_ll_def_list) + list(APPEND hal_ll_def_list ${MCU_NAME}) + set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) + + ## BEGIN GPIO + list(APPEND hal_ll_def_list "MACRO_USAGE_GPIO") + foreach(cmakeFile ${CMAKE_FILES}) + include(${cmakeFile}) + endforeach() + ## END GPIO + + mikrosdk_add_library(lib_hal_ll_gpio MikroSDK.HalLowLevel.GPIO + ${pmc_subimplementation}/hal_ll_pmc.h + ../../include/hal_ll_target.h + # BEGIN GPIO + hal_ll_gpio.c + ${gpio_subimplementation} + ../../include/gpio/hal_ll_gpio.h + ../../include/gpio/hal_ll_gpio_port.h + ${gpio_subimplementation_include_dir}/hal_ll_gpio_constants.h + ${gpio_subimplementation_include_dir}/hal_ll_gpio_struct_type.h + # END GPIO + + ) + + target_compile_definitions(lib_hal_ll_gpio PUBLIC + ${hal_ll_def_list} + ) + + target_link_libraries(lib_hal_ll_gpio PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon + ) + + string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) + target_include_directories(lib_hal_ll_gpio + PRIVATE + ../../include + # BEGIN GPIO + ../../include/gpio + ${gpio_subimplementation_include_dir} + # END GPIO + # BEGIN PMC + ${pmc_subimplementation} + # END PMC + INTERFACE + # BUILD + $ + $ + $ + $ + # INSTALL + $ + $ + ) + + mikrosdk_install(MikroSDK.HalLowLevel.GPIO) + install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.GPIO ../../include/gpio/hal_ll_gpio.h ${gpio_subimplementation_include_dir}/hal_ll_gpio_constants.h ${gpio_subimplementation_include_dir}/hal_ll_gpio_struct_type.h ../../include/gpio/hal_ll_gpio_port.h) +endif() diff --git a/targets/arm/mikroe/sam/src/gpio/hal_ll_gpio.c b/targets/arm/mikroe/sam/src/gpio/hal_ll_gpio.c new file mode 100644 index 000000000..bbf3c6166 --- /dev/null +++ b/targets/arm/mikroe/sam/src/gpio/hal_ll_gpio.c @@ -0,0 +1,185 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio.c + * @brief GPIO HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_gpio_port.h" + +/******************************************************************************* + * + */ +void hal_ll_gpio_configure_pin( hal_ll_gpio_pin_t *pin, hal_ll_pin_name_t name, hal_ll_gpio_direction_t direction ) +{ + pin->base = ( hal_ll_gpio_base_t )hal_ll_gpio_port_base( hal_ll_gpio_port_index( name ) ); + pin->mask = hal_ll_gpio_pin_mask( name ); + + if ( direction == HAL_LL_GPIO_DIGITAL_INPUT) + hal_ll_gpio_digital_input( pin->base, pin->mask ); + else + hal_ll_gpio_digital_output( pin->base, pin->mask ); +} + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +uint8_t hal_ll_gpio_read_pin_input( hal_ll_gpio_pin_t *pin ) +{ + hal_ll_gpio_base_handle_t *port_ptr = ( hal_ll_gpio_base_handle_t * ) pin->base; + + return ( port_ptr->signal.pin_status & pin->mask ) ? 0x01 : 0x00; +} +#endif + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +uint8_t hal_ll_gpio_read_pin_output( hal_ll_gpio_pin_t *pin ) +{ + hal_ll_gpio_base_handle_t *port_ptr = ( hal_ll_gpio_base_handle_t * ) pin->base; + + return ( port_ptr->signal.pin_status & pin->mask ) ? 0x01 : 0x00; +} +#endif + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +void hal_ll_gpio_write_pin_output( hal_ll_gpio_pin_t *pin, uint8_t value ) +{ + hal_ll_gpio_base_handle_t *port_ptr = ( hal_ll_gpio_base_handle_t * ) pin->base; + + if ( value ) + port_ptr->signal.enable = pin->mask; + else + port_ptr->signal.disable = pin->mask; +} +#endif + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +void hal_ll_gpio_toggle_pin_output( hal_ll_gpio_pin_t *pin ) +{ + uint8_t value = hal_ll_gpio_read_pin_output( pin ); + hal_ll_gpio_write_pin_output( pin, !value ); +} +#endif + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +void hal_ll_gpio_set_pin_output( hal_ll_gpio_pin_t *pin ) +{ + hal_ll_gpio_base_handle_t *port_ptr = ( hal_ll_gpio_base_handle_t * ) pin->base; + + port_ptr->signal.enable = pin->mask; +} +#endif + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +void hal_ll_gpio_clear_pin_output( hal_ll_gpio_pin_t *pin ) +{ + hal_ll_gpio_base_handle_t *port_ptr = ( hal_ll_gpio_base_handle_t * ) pin->base; + + port_ptr->signal.disable = pin->mask; +} +#endif + +/******************************************************************************* + * + */ +void hal_ll_gpio_configure_port( hal_ll_gpio_port_t *port, hal_ll_port_name_t name, hal_ll_gpio_mask_t mask, hal_ll_gpio_direction_t direction ) +{ + port->base = hal_ll_gpio_port_base( name ); + port->mask = mask; + + if ( direction == HAL_LL_GPIO_DIGITAL_INPUT ) + hal_ll_gpio_digital_input( port->base, port->mask ); + else + hal_ll_gpio_digital_output( port->base, port->mask ); +} + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +hal_ll_port_size_t hal_ll_gpio_read_port_input( hal_ll_gpio_port_t *port ) +{ + hal_ll_gpio_base_handle_t *port_ptr = ( hal_ll_gpio_base_handle_t * )port->base; + + return port_ptr->signal.pin_status; +} +#endif + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +hal_ll_port_size_t hal_ll_gpio_read_port_output(hal_ll_gpio_port_t *port) +{ + hal_ll_gpio_base_handle_t *port_ptr = ( hal_ll_gpio_base_handle_t * )port->base; + + return port_ptr->signal.pin_status; +} +#endif + +/******************************************************************************* + * + */ +#if (FLATTEN_ME_LEVEL < FLATTEN_ME_LEVEL_LOW) +void hal_ll_gpio_write_port_output(hal_ll_gpio_port_t *port, hal_ll_port_size_t value) +{ + hal_ll_gpio_base_handle_t *port_ptr = (hal_ll_gpio_base_handle_t *)port->base; + + port_ptr->signal.enable = value & port->mask; + port_ptr->signal.disable = ~value & port->mask; +} +#endif + +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/sam/src/gpio/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake b/targets/arm/mikroe/sam/src/gpio/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake new file mode 100644 index 000000000..1a3ac0db6 --- /dev/null +++ b/targets/arm/mikroe/sam/src/gpio/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake @@ -0,0 +1,6 @@ +if(${MCU_NAME} MATCHES "^ATSAME70Q21B$") + set(gpio_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_gpio_port.c") + set(pmc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/pmc/implementations/arm_gcc_clang_atsam_e70") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/arm_gcc_clang_atsam_e70") + list(APPEND hal_ll_def_list "ATSAME7x") +endif() diff --git a/targets/arm/mikroe/sam/src/gpio/implementations/arm_gcc_clang_atsam_e70/hal_ll_gpio_port.c b/targets/arm/mikroe/sam/src/gpio/implementations/arm_gcc_clang_atsam_e70/hal_ll_gpio_port.c new file mode 100644 index 000000000..e2645e2d7 --- /dev/null +++ b/targets/arm/mikroe/sam/src/gpio/implementations/arm_gcc_clang_atsam_e70/hal_ll_gpio_port.c @@ -0,0 +1,270 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_port.c + * @brief GPIO HAL LOW LEVEL ported layer implementation. + */ + +#include "hal_ll_gpio_port.h" +#include "hal_ll_pmc.h" + +// ------------------------------------------------------------- PRIVATE MACROS + +/**< @brief Utility macro for geting pin name based on port and bit for that pin on that port. */ +#define HAL_LL_GET_PIN(port_name, pin_index) ( ( hal_ll_pin_name_t ) ( ( port_name << 0x04 ) + pin_index ) ) + +// -------------------------------------------------------------- PRIVATE TYPES + +/** + * Defines used in source + */ + // GPIO Register addresses and offsets +#define HAL_LL_GPIOA_BASE_ADDR 0x400E0E00UL +#define HAL_LL_GPIOB_BASE_ADDR 0x400E1000UL +#define HAL_LL_GPIOC_BASE_ADDR 0x400E1200UL +#define HAL_LL_GPIOD_BASE_ADDR 0x400E1400UL +#define HAL_LL_GPIOE_BASE_ADDR 0x400E1600UL + +#define HAL_LL_PMC_ID_PIOA_BIT 0x0A +#define HAL_LL_PMC_ID_PIOB_BIT 0x0B +#define HAL_LL_PMC_ID_PIOC_BIT 0x0C +#define HAL_LL_PMC_ID_PIOD_BIT 0x10 +#define HAL_LL_PMC_ID_PIOE_BIT 0x11 + +#define HAL_LL_PERIPHERAL_A 0 +#define HAL_LL_PERIPHERAL_B 1 +#define HAL_LL_PERIPHERAL_C 2 +#define HAL_LL_PERIPHERAL_D 3 +// EOF GPIO Register addresses and offsets + + +/*!< @brief GPIO PORT array */ +static const uint32_t _hal_ll_gpio_port_base [ 5 ] = +{ + HAL_LL_GPIOA_BASE_ADDR, + HAL_LL_GPIOB_BASE_ADDR, + HAL_LL_GPIOC_BASE_ADDR, + HAL_LL_GPIOD_BASE_ADDR, + HAL_LL_GPIOE_BASE_ADDR +}; + +// ----------------------------------------------- PRIVATE FUNCTION DECLARATIONS + +/** + * @brief Configure single port pins + * + * @param[in] port - port base address + * @param[in] pin_mask - desired pin + * @param[in] config - pin settings + * @return none + */ +static void hal_ll_gpio_config( hal_ll_gpio_base_t *port, hal_ll_gpio_mask_t pin_mask, uint32_t config ); + +/** + * @brief Configure pin that has analog function. + * + * @param[in] pin - Desired pin. + * @param[in] is_digital - Pin configuration( true = digital, false = analog ). + * @return none + */ +static void hal_ll_gpio_port_configure_analog_pin( hal_ll_pin_name_t pin, bool is_digital ); + +/** + * @brief Configure port pins. + * + * @param[in] port - Port base address. + * @param[in] pin - Desired single pin. + * @param[in] config - Pin settings. + * @return none + */ +static void hal_ll_gpio_port_config( hal_ll_gpio_base_t *port, hal_ll_pin_name_t pin, uint32_t config ); + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void hal_ll_gpio_config_pin_alternate_enable( uint8_t module_pin, uint8_t module_config, bool state ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFFINITIONS + +static uint8_t hal_ll_gpio_pin_index( hal_ll_pin_name_t name ) +{ + return ( hal_ll_port_name_t )name % PORT_SIZE; +} + +uint8_t hal_ll_gpio_port_index( hal_ll_pin_name_t name ) +{ + return ( hal_ll_port_name_t )name / PORT_SIZE; +} + +uint32_t hal_ll_gpio_pin_mask( hal_ll_pin_name_t name ) +{ + return ( ( uint32_t )0x01 << hal_ll_gpio_pin_index( name ) ); +} + +uint32_t hal_ll_gpio_port_base( hal_ll_port_name_t name ) +{ + return _hal_ll_gpio_port_base[ name ]; +} + +void hal_ll_gpio_analog_input( hal_ll_gpio_base_t *port, hal_ll_gpio_mask_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_ANALOG_INPUT ); +} + +void hal_ll_gpio_digital_input( hal_ll_gpio_base_t *port, hal_ll_gpio_mask_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_INPUT ); +} + +void hal_ll_gpio_digital_output( hal_ll_gpio_base_t *port, hal_ll_gpio_mask_t pin_mask ) +{ + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_OUTPUT ); +} + +void hal_ll_gpio_module_struct_init( module_struct const *module, bool state ) +{ + int8_t index = 0; + + while ( module->pins[ index ] != GPIO_MODULE_STRUCT_END ) + { + hal_ll_gpio_config_pin_alternate_enable( module->pins[ index ], module->configs[ index ], state ); + + index++; + } +} + +/** + * @brief Enable gpio port clock + * @param port - port base address + * @return none + */ +static void hal_ll_gpio_clock_enable( hal_ll_gpio_base_t *port ) +{ + uint32_t pos = 0; + + switch ( ( uint32_t )port ) + { + case HAL_LL_GPIOA_BASE_ADDR: pos = HAL_LL_PMC_ID_PIOA_BIT; break; + case HAL_LL_GPIOB_BASE_ADDR: pos = HAL_LL_PMC_ID_PIOB_BIT; break; + case HAL_LL_GPIOC_BASE_ADDR: pos = HAL_LL_PMC_ID_PIOC_BIT; break; + case HAL_LL_GPIOD_BASE_ADDR: pos = HAL_LL_PMC_ID_PIOD_BIT; break; + case HAL_LL_GPIOE_BASE_ADDR: pos = HAL_LL_PMC_ID_PIOE_BIT; break; + } + + set_reg_bit( _PMC_PCER0, pos ); +} + +static void hal_ll_gpio_config( hal_ll_gpio_base_t *port, hal_ll_gpio_mask_t pin_mask, uint32_t config ) +{ + uint8_t pin_num = 0; + uint32_t pin_pos = 0; + uint32_t current_pin = 0; + uint32_t port_base = 0; + + hal_ll_gpio_base_handle_t *port_ptr; + + port_ptr = ( hal_ll_gpio_base_handle_t *)port; + + hal_ll_gpio_clock_enable( port ); + + // Check if it is a digital signal or alternate function + if ( ( config & GPIO_CFG_MODE_ANALOG ) != GPIO_CFG_MODE_ANALOG ) { + if ( config & GPIO_CFG_MODE_INPUT ) { + // Set gpio direction as input with filtering. + port_ptr->pio.enable |= pin_mask; + port_ptr->filter.enable |= pin_mask; + } else { + // Set gpio direction as output. + port_ptr->pio.enable |= pin_mask; + port_ptr->output.enable |= pin_mask; + } + } + else { + // Set to analog input without filtering. + port_ptr->pio.disable = pin_mask; + port_ptr->output.disable = pin_mask; + port_ptr->filter.disable = pin_mask; + } +} + +/** + * @brief Configure port pins alternate + * functions + * @param module_pin - desired pin + * config - pin settings + * @return none + */ +static void hal_ll_gpio_config_pin_alternate_enable( uint8_t module_pin, uint8_t module_config, bool state ) +{ + hal_ll_pin_name_t pin_index; + hal_ll_gpio_base_handle_t *port_ptr; + + // Get the port address. + port_ptr = ( hal_ll_gpio_base_handle_t *)hal_ll_gpio_port_base( hal_ll_gpio_port_index ( module_pin ) ); + + // Get the pin index. + pin_index = hal_ll_gpio_pin_index( module_pin ); + + // Disable PIO control over this pin. + port_ptr->pio.disable |= 1 << pin_index; + + switch ( module_config ) { + case HAL_LL_PERIPHERAL_A: + clear_reg_bit(&port_ptr->abcdsr0, pin_index); + clear_reg_bit(&port_ptr->abcdsr1, pin_index); + break; + case HAL_LL_PERIPHERAL_B: + set_reg_bit(&port_ptr->abcdsr0, pin_index); + clear_reg_bit(&port_ptr->abcdsr1, pin_index); + break; + case HAL_LL_PERIPHERAL_C: + clear_reg_bit(&port_ptr->abcdsr0, pin_index); + set_reg_bit(&port_ptr->abcdsr1, pin_index); + break; + case HAL_LL_PERIPHERAL_D: + set_reg_bit(&port_ptr->abcdsr0, pin_index); + set_reg_bit(&port_ptr->abcdsr1, pin_index); + break; + } +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/sam/src/hal_ll/CMakeLists.txt b/targets/arm/mikroe/sam/src/hal_ll/CMakeLists.txt new file mode 100644 index 000000000..c19f23209 --- /dev/null +++ b/targets/arm/mikroe/sam/src/hal_ll/CMakeLists.txt @@ -0,0 +1,16 @@ +## ./targets/arm/mikroe/ai_generated/sam/src/hal_ll/CMakeLists.txt +add_library(lib_hal_ll INTERFACE) + +add_library(MikroSDK.HalLowLevel ALIAS lib_hal_ll) + +target_link_libraries(lib_hal_ll INTERFACE + MikroSDK.HalLowLevel.GPIO +) + +get_files_recurse(${CMAKE_CURRENT_LIST_DIR}/../gpio CMAKE_FILES cmake) +foreach(cmakeFile ${CMAKE_FILES}) + include(${cmakeFile}) +endforeach() + +mikrosdk_install(MikroSDK.HalLowLevel) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel ${pmc_subimplementation}/hal_ll_pmc.h ../../include/hal_ll_target.h ../../include/hal_ll_pin_names.h ../../include/hal_ll_target_names.h) diff --git a/targets/arm/mikroe/sam/src/i2c/CMakeLists.txt b/targets/arm/mikroe/sam/src/i2c/CMakeLists.txt new file mode 100644 index 000000000..069bc8330 --- /dev/null +++ b/targets/arm/mikroe/sam/src/i2c/CMakeLists.txt @@ -0,0 +1,82 @@ +## ./targets/arm/mikroe/ai_generated/sam/src/i2c/CMakeLists.txt + +## Check if current module is generated or not +set(MODULE_IS_GENERATED false) +get_files_recurse(${CMAKE_CURRENT_LIST_DIR}/implementations CMAKE_FILES cmake) +check_if_module_is_generated(MODULE_IS_GENERATED "${CMAKE_FILES}") + +## If current MCU has this module, add it +if(MODULE_IS_GENERATED) + set(hal_ll_def_list "") + set(mcu_header_path "") + + find_cortex(hal_ll_def_list) + list(APPEND hal_ll_def_list ${MCU_NAME}) + set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) + + ## BEGIN I2C + list(APPEND hal_ll_def_list "MACRO_USAGE_I2C") + foreach(cmakeFile ${CMAKE_FILES}) + include(${cmakeFile}) + endforeach() + ## END I2C + + if (NOT DEFINED _MSDK_TFT_TP_) + list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") + else() + if (${_MSDK_TFT_TP_} MATCHES "__TP_TSC2003__") + list(APPEND hal_ll_def_list "__TFT_RESISTIVE_TSC2003__") + else() + list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") + endif() + endif() + + mikrosdk_add_library(lib_hal_ll_i2c_master MikroSDK.HalLowLevel.I2C.Master + ${pmc_subimplementation}/hal_ll_pmc.h + ../../include/hal_ll_target.h + # BEGIN I2C + ${i2c_subimplementation} + ../../include/i2c/hal_ll_i2c_master.h + ${i2c_pin_map}/hal_ll_i2c_pin_map.h + # END I2C + ) + + target_compile_definitions(lib_hal_ll_i2c_master PUBLIC + ${hal_ll_def_list} + ) + + target_link_libraries(lib_hal_ll_i2c_master PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon + ) + + string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) + target_include_directories(lib_hal_ll_i2c_master + PRIVATE + ../../include + ../../include/gpio + ${gpio_subimplementation_include_dir} + # BEGIN I2C + ../../include/i2c + ${i2c_pin_map} + # END I2C + # BEGIN PMC + ${pmc_subimplementation} + # END PMC + INTERFACE + # BUILD + $ + $ + $ + $ + $ + $ + # INSTALL + $ + $ + ) + + mikrosdk_install(MikroSDK.HalLowLevel.I2C.Master) + install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.I2C.Master ../../include/i2c/hal_ll_i2c_master.h) +endif() diff --git a/targets/arm/mikroe/sam/src/i2c/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake b/targets/arm/mikroe/sam/src/i2c/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake new file mode 100644 index 000000000..3c1a5d6d4 --- /dev/null +++ b/targets/arm/mikroe/sam/src/i2c/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake @@ -0,0 +1,7 @@ +if(${MCU_NAME} MATCHES "^ATSAME70Q21B") + set(i2c_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_i2c_master.c") + set(pmc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/pmc/implementations/arm_gcc_clang_atsam_e70") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/arm_gcc_clang_atsam_e70") + list(APPEND hal_ll_def_list "ATSAME7x") + set(i2c_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/i2c/hal_ll_i2c_pin_map/implementations/arm_gcc_clang_atsam_e70") +endif() diff --git a/targets/arm/mikroe/sam/src/i2c/implementations/arm_gcc_clang_atsam_e70/hal_ll_i2c_master.c b/targets/arm/mikroe/sam/src/i2c/implementations/arm_gcc_clang_atsam_e70/hal_ll_i2c_master.c new file mode 100644 index 000000000..c1a2f541e --- /dev/null +++ b/targets/arm/mikroe/sam/src/i2c/implementations/arm_gcc_clang_atsam_e70/hal_ll_i2c_master.c @@ -0,0 +1,835 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_i2c_master.c + * @brief I2C master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_pmc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_i2c_master.h" +#include "hal_ll_i2c_pin_map.h" +#include "mcu.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Macros used for calculating speed value and configuring the clock register */ +#define hal_ll_get_system_clock (Get_Fosc_kHz() * 1000) +#define hal_ll_i2c_configure_divider_register(_cldiv,_chdiv,_ckdiv) ((0xFF & _cldiv) | (0xFF00 & (_chdiv << 8)) | (0x70000 & (_ckdiv << 16))) +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_i2c_get_module_state_address ((hal_ll_i2c_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_i2c_get_handle (hal_ll_i2c_master_handle_register_t *)hal_ll_i2c_get_module_state_address->hal_ll_i2c_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_i2c_get_base_struct(_handle) ((hal_ll_i2c_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_i2c_get_base_from_hal_handle ((hal_ll_i2c_hw_specifics_map_t *)((hal_ll_i2c_master_handle_register_t *)\ + (((hal_ll_i2c_master_handle_register_t *)(handle))->hal_ll_i2c_master_handle))->hal_ll_i2c_master_handle)->base + +/*!< @brief Default I2C bit-rate if no speed is set */ +#define HAL_LL_I2C_MASTER_SPEED_100K 100000UL +#define HAL_LL_I2C_MASTER_LOW_DIVIDER_SPEED_LIMIT 384000UL +#define HAL_LL_I2C_MASTER_SPEED_400K 400000UL + +/*!< @brief Default pass count value upon reset */ +#define HAL_LL_I2C_DEFAULT_PASS_COUNT 0xFFFFU + +/*!< @brief Macro used for timeout */ +#define HAL_LL_I2C_LOOP_INDEX 10000U + +/*!< @brief Macro used for calculating dividers */ +#define HAL_LL_TWIHS_CLK_DIVIDER 2 +#define HAL_LL_TWIHS_CLK_CALC_ARGU 3 +#define HAL_LL_TWIHS_CLK_DIV_MIN 7 +#define HAL_LL_TWIHS_CLK_DIV_MAX 0xFF + +/*!< @brief Macros defining register bit location */ +#define HAL_LL_TWIHS_SR_TXCOMP_BIT 0 +#define HAL_LL_TWIHS_SR_RXRDY_BIT 1 +#define HAL_LL_TWIHS_SR_TXRDY_BIT 2 +#define HAL_LL_TWIHS_SR_ARBLST_BIT 9 + +#define HAL_LL_TWIHS_CR_START_BIT 0 +#define HAL_LL_TWIHS_CR_STOP_BIT 1 +#define HAL_LL_TWIHS_CR_MSEN_BIT 2 +#define HAL_LL_TWIHS_CR_SVDIS_BIT 5 +#define HAL_LL_TWIHS_CR_SWRST_BIT 7 + +#define HAL_LL_TWIHS_MMR_MREAD_BIT 12 +#define HAL_LL_TWIHS_MMR_DADR_START_BIT 16 + +#define HAL_LL_PID_TWIHS2_BIT 9 +#define HAL_LL_PID_TWIHS0_BIT 19 +#define HAL_LL_PID_TWIHS1_BIT 20 + +/*!< @brief Macros defining register bit masks */ +#define HAL_LL_TWIHS_CWGR_100K_MASK 0x3939 +#define HAL_LL_TWIHS_CWGR_400K_MASK 0x0B0C + +/*!< @brief Macros used for module pin checking */ +#define HAL_LL_I2C_SCL_PIN 0 +#define HAL_LL_I2C_SDA_PIN 1 +#define HAL_LL_I2C_MODULE_PIN_COUNT 2 + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief I2C register structure */ +typedef struct +{ + hal_ll_base_addr_t cr; + hal_ll_base_addr_t mmr; + hal_ll_base_addr_t smr; + hal_ll_base_addr_t iadr; + hal_ll_base_addr_t cwgr; + hal_ll_base_addr_t _unused[3]; + hal_ll_base_addr_t sr; + hal_ll_base_addr_t ier; + hal_ll_base_addr_t idr; + hal_ll_base_addr_t imr; + hal_ll_base_addr_t rhr; + hal_ll_base_addr_t thr; + hal_ll_base_addr_t smbtr; +} hal_ll_i2c_base_handle_t; + +/*!< @brief I2C hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_i2c_pins_t pins; + uint32_t speed; + uint8_t address; + uint16_t timeout; +} hal_ll_i2c_hw_specifics_map_t; + +/*!< @brief I2C hw specific module values */ +typedef struct +{ + uint16_t pin_scl; + uint16_t pin_sda; +} hal_ll_i2c_pin_id; + +/*!< @brief I2C hw specific error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_SUCCESS = 0, + HAL_LL_I2C_MASTER_WRONG_PINS, + HAL_LL_I2C_MASTER_MODULE_ERROR, + + HAL_LL_I2C_MASTER_ERROR = (-1) +} hal_ll_i2c_master_err_t; + +/*!< @brief I2C end mode selection values */ +typedef enum +{ + HAL_LL_I2C_MASTER_END_MODE_RESTART = 0, + HAL_LL_I2C_MASTER_END_MODE_STOP, + HAL_LL_I2C_MASTER_WRITE_THEN_READ +} hal_ll_i2c_master_end_mode_t; + +/*!< @brief I2C timeout error values */ +typedef enum +{ + HAL_LL_I2C_MASTER_TIMEOUT_START = 1300, + HAL_LL_I2C_MASTER_TIMEOUT_STOP, + HAL_LL_I2C_MASTER_TIMEOUT_WRITE, + HAL_LL_I2C_MASTER_TIMEOUT_READ, + HAL_LL_I2C_MASTER_ARBITRATION_LOST, + HAL_LL_I2C_MASTER_TIMEOUT_INIT +} hal_ll_i2c_master_timeout_t; + +/** + * @brief Enum containing predefined module standard speed values. + * + * Enum values: + * HAL_LL_I2C_MASTER_SPEED_STANDARD -- Speed set at 100K + * HAL_LL_I2C_MASTER_SPEED_FULL -- Speed set at 400K + * HAL_LL_I2C_MASTER_SPEED_FAST -- Speed set at 1M + */ +typedef enum +{ + HAL_LL_I2C_MASTER_SPEED_STANDARD = 0, + HAL_LL_I2C_MASTER_SPEED_FULL, + HAL_LL_I2C_MASTER_SPEED_FAST +} hal_ll_i2c_master_speed_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief I2C hardware specific info */ +static hal_ll_i2c_hw_specifics_map_t hal_ll_i2c_hw_specifics_map[] = +{ + {HAL_LL_I2C0_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_0), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + {HAL_LL_I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + {HAL_LL_I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_i2c_master_handle_register_t *low_level_handle; +static volatile hal_ll_i2c_hw_specifics_map_t *hal_ll_i2c_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks scl and sda pins the user has passed with pre-defined + * pins in scl and sda maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] scl - SCL pre-defined pin name. + * @param[in] sda - SDA pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_i2c_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_i2c_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Get adequate I2C bit-rate value. + * + * Returns one of pre-defined bit-rate values, + * or the closest bit-rate based on bit_rate + * value passed to the function. + * + * @param[in] bit_rate - I2C bit rate. + * @return uint32_t Adequate bit-rate value. + * + * Returns adequate value to be latter written into bare metal register address. + * Take into consideration that this returns a predefined value. + * + * HAL_LL_I2C_MASTER_SPEED_100K -- 100Kbit/s + * HAL_LL_I2C_MASTER_SPEED_400K -- 400Kbit/s + * HAL_LL_I2C_MASTER_SPEED_1M -- 1Mbit/s + * HAL_LL_I2C_MASTER_SPEED_3M2 -- 3.2Mbit/s + */ +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Enable clock for I2C module on hardware level. + * + * Initializes I2C module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return None + */ +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Initialize I2C module on hardware level. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific return values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * I2C SCL and SDA pins. + * + * @param[in] module_index I2C HW module index -- 0,1,2... + * @param[in] *index_list Array with SCL and SDA map index values + * and module number + * + * @return None + */ +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ); + +/** + * @brief Sets I2C pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if I2C is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return None + */ +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Full I2C module initialization procedure. + * + * Initializes I2C module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Configure I2C module for data transfer. + * + * @param[in] hal_ll_hw_reg - I2C module base address. + * @param[in] slave_address - client address. + * @param[in] read - defines either it is read operation or write. + * @return void None. + */ +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint8_t slave_address, bool read ); + +/** + * @brief Generates start signal on I2C bus. + * + * Generates a start signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Generates stop signal on I2C bus. + * + * Generates a stop signal on the I2C bus. + * + * @param[in] map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ); + +/** + * @brief Perform a read on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] readDatabuf - Pointer to data buffer. + * @param[in] lenReadData - Number of data to be read. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ); + +/** + * @brief Perform a write on the I2C bus. + * + * Initializes I2C module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] writeDatabuf - Pointer to data buffer. + * @param[in] lenWriteData - Number of data to be written. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_master_handle_register_t *handle_map, uint8_t *hal_module_id ) { + + hal_ll_i2c_pin_id index_list[ I2C_MODULE_COUNT ] = { HAL_LL_PIN_NC, HAL_LL_PIN_NC }; + uint16_t pin_check_result; + + // Check if pins are valid + if ( ( pin_check_result = hal_ll_i2c_master_check_pins( scl, sda, &index_list, handle_map ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_I2C_MASTER_WRONG_PINS; + }; + + if ( ( hal_ll_i2c_hw_specifics_map[ pin_check_result ].pins.pin_scl.pin_name != scl ) || + ( hal_ll_i2c_hw_specifics_map[ pin_check_result ].pins.pin_sda.pin_name != sda ) ) + { + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_i2c_master_map_pins( pin_check_result, &index_list ); + + hal_ll_i2c_master_alternate_functions_set_state( &hal_ll_i2c_hw_specifics_map[ pin_check_result ], true ); + + handle_map[ pin_check_result ].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[ pin_check_result ].hal_ll_i2c_master_handle = ( handle_t *)&hal_ll_i2c_hw_specifics_map[ pin_check_result ].base; + + handle_map[ pin_check_result ].hal_ll_i2c_master_handle = ( handle_t *)&hal_ll_module_state[ pin_check_result ].hal_ll_i2c_master_handle; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_i2c( handle_t *handle ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_i2c_get_module_state_address ); + hal_ll_i2c_master_handle_register_t *hal_handle = ( hal_ll_i2c_master_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_i2c_hw_specifics_map_local->module_index; + + hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ); + + hal_ll_module_state[ pin_check_result ].hal_ll_i2c_master_handle = ( handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[ pin_check_result ].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_i2c_master_set_speed( handle_t *handle, uint32_t speed ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_i2c_get_module_state_address ); + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->speed = speed; + + if ( hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ) != HAL_LL_I2C_MASTER_SUCCESS ) { + return HAL_LL_I2C_MASTER_TIMEOUT_INIT; + } + + low_level_handle->init_ll_state = true; + + return hal_ll_i2c_hw_specifics_map_local->speed; +} + +void hal_ll_i2c_master_set_timeout( handle_t *handle, uint16_t timeout ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_i2c_get_module_state_address ); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->timeout = timeout; + } +} + +void hal_ll_i2c_master_set_slave_address( handle_t *handle, uint8_t addr ) { + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_i2c_get_module_state_address ); + + if( hal_ll_i2c_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_i2c_hw_specifics_map_local->address = addr; + } +} + +hal_ll_err_t hal_ll_i2c_master_read( handle_t *handle, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_i2c_get_module_state_address ); + + return hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_i2c_get_module_state_address ); + + return hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_END_MODE_STOP ); +} + +hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data, uint8_t *read_data_buf, size_t len_read_data ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_i2c_get_module_state_address ); + + if ( hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + + /** + * @note Wait for drivers to set-up + * correctly. + **/ + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_22us(); + #endif + + if( hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != NULL ) { + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +void hal_ll_i2c_master_close( handle_t *handle ) { + low_level_handle = hal_ll_i2c_get_handle; + hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_i2c_get_module_state_address ); + + if( low_level_handle->hal_ll_i2c_master_handle != NULL ) { + low_level_handle->hal_ll_i2c_master_handle = NULL; + low_level_handle->hal_drv_i2c_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_i2c_hw_specifics_map_local->address = 0; + hal_ll_i2c_hw_specifics_map_local->timeout = HAL_LL_I2C_DEFAULT_PASS_COUNT; + hal_ll_i2c_hw_specifics_map_local->speed = HAL_LL_I2C_MASTER_SPEED_100K; + + hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_local, true ); + hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_local, false ); + hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_local, false ); + + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_name = HAL_LL_PIN_NC; + hal_ll_i2c_hw_specifics_map_local->pins.pin_scl.pin_af = 0; + hal_ll_i2c_hw_specifics_map_local->pins.pin_sda.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base ); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + uint8_t dummy_data; + + #ifdef __TFT_RESISTIVE_TSC2003__ + Delay_1ms(); + #endif + + hal_ll_i2c_master_configure_transfer( hal_ll_hw_reg, map->address, true ); + + status = hal_ll_i2c_master_start( map ); + + for ( transfer_counter; transfer_counter < len_read_data - 1; transfer_counter++ ) { + while ( !( check_reg_bit( &hal_ll_hw_reg->sr, HAL_LL_TWIHS_SR_RXRDY_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + } + read_data_buf[ transfer_counter ] = read_reg( &hal_ll_hw_reg->rhr ); + } + + if ( ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) || ( mode == HAL_LL_I2C_MASTER_WRITE_THEN_READ ) ) { + status = hal_ll_i2c_master_stop( map ); + + // For ATSAM MCUs last data byte should be read after stop bit has beed sent to end the receiving. + while ( !( check_reg_bit( &hal_ll_hw_reg->sr, HAL_LL_TWIHS_SR_RXRDY_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_READ; + } + } + read_data_buf[ transfer_counter ] = read_reg( &hal_ll_hw_reg->rhr ); + + while ( !( check_reg_bit( &hal_ll_hw_reg->sr, HAL_LL_TWIHS_SR_TXCOMP_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_STOP; + } + } + } + + /* + * Clear the receive register because ATSAM MCUs with TWIHS + * registers keep strething the clock line till TXCOMP flag + * is not set that causes the garbage readings although + * receiving is finished. + */ + dummy_data = read_reg( &hal_ll_hw_reg->rhr ); + + if( status != HAL_LL_I2C_MASTER_SUCCESS ) { + return status; + } + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base ); + uint16_t time_counter = map->timeout; + size_t transfer_counter = NULL; + uint8_t status = NULL; + + hal_ll_i2c_master_configure_transfer( hal_ll_hw_reg, map->address, false ); + + for ( transfer_counter; transfer_counter < len_write_data; transfer_counter++ ) + { + while ( !( check_reg_bit( &hal_ll_hw_reg->sr, HAL_LL_TWIHS_SR_TXRDY_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + write_reg( &hal_ll_hw_reg->thr, write_data_buf[ transfer_counter ] ); + } + + time_counter = map->timeout; + while ( !( check_reg_bit( &hal_ll_hw_reg->sr, HAL_LL_TWIHS_SR_TXRDY_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } + } + + if ( ( mode == HAL_LL_I2C_MASTER_END_MODE_STOP ) || ( mode == HAL_LL_I2C_MASTER_WRITE_THEN_READ ) ) + { + hal_ll_i2c_master_stop( map ); + + while ( !( check_reg_bit( &hal_ll_hw_reg->sr, HAL_LL_TWIHS_SR_TXCOMP_BIT ) ) ) { + if ( map->timeout ) { + if ( !time_counter-- ) + return HAL_LL_I2C_MASTER_TIMEOUT_STOP; + } + } + } + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static void hal_ll_i2c_master_configure_transfer( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint8_t slave_address, bool read ) { + + write_reg( &hal_ll_hw_reg->mmr, ( slave_address << HAL_LL_TWIHS_MMR_DADR_START_BIT ) ); + + if ( read ) + set_reg_bit( &hal_ll_hw_reg->mmr, HAL_LL_TWIHS_MMR_MREAD_BIT ); +} + +static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base ); + uint16_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &hal_ll_hw_reg->cr, HAL_LL_TWIHS_CR_START_BIT ); + + if ( check_reg_bit( &hal_ll_hw_reg->sr, HAL_LL_TWIHS_SR_ARBLST_BIT ) ) + return HAL_LL_I2C_MASTER_ARBITRATION_LOST; + + while ( loop_index-- ) + assembly( nop ); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base ); + uint16_t time_counter = map->timeout; + uint32_t loop_index = HAL_LL_I2C_LOOP_INDEX; + + set_reg_bit( &hal_ll_hw_reg->cr, HAL_LL_TWIHS_CR_STOP_BIT ); + + while ( loop_index-- ) + assembly(nop); + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pin_id *index_list, hal_ll_i2c_master_handle_register_t *handle_map ) { + static const uint16_t scl_map_size = ( sizeof( hal_ll_i2c_scl_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + static const uint16_t sda_map_size = ( sizeof( hal_ll_i2c_sda_map ) / sizeof( hal_ll_i2c_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t scl_index; + uint16_t sda_index; + + if ( (HAL_LL_PIN_NC == scl) || (HAL_LL_PIN_NC == sda) ) { + return HAL_LL_PIN_NC; + } + + for ( scl_index = 0; scl_index < scl_map_size; scl_index++ ) { + if ( hal_ll_i2c_scl_map[ scl_index ].pin == scl ) { + for ( sda_index = 0; sda_index < sda_map_size; sda_index++ ) { + if ( hal_ll_i2c_sda_map[ sda_index ].pin == sda ) { + if ( hal_ll_i2c_scl_map[ scl_index ].module_index == hal_ll_i2c_sda_map[ sda_index ].module_index ) { + // Get module number. + hal_ll_module_id = hal_ll_i2c_scl_map[ scl_index ].module_index; + // Map pin names. + index_list[hal_ll_module_id].pin_scl = scl_index; + index_list[hal_ll_module_id].pin_sda = sda_index; + + // Check if module is taken. + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_i2c_master_handle ) { + return hal_ll_module_id; + } else if ( I2C_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_i2c_master_handle_register_t ) ); + static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_i2c_master_handle_register_t )); + + while( hal_ll_module_count-- ) { + if (hal_ll_i2c_get_base_from_hal_handle == hal_ll_i2c_hw_specifics_map[ hal_ll_module_count ].base) { + return &hal_ll_i2c_hw_specifics_map[ hal_ll_module_count ]; + } + } + + return &hal_ll_i2c_hw_specifics_map[ hal_ll_module_error ]; +} + +static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + case ( hal_ll_i2c_module_num( I2C_MODULE_0 ) ): + if ( hal_ll_state ) { + set_reg_bit( _PMC_PCER0, HAL_LL_PID_TWIHS0_BIT ); + } else { + set_reg_bit( _PMC_PCDR0, HAL_LL_PID_TWIHS0_BIT ); + } + break; + case ( hal_ll_i2c_module_num( I2C_MODULE_1 ) ): + if ( hal_ll_state ) { + set_reg_bit( _PMC_PCER0, HAL_LL_PID_TWIHS1_BIT ); + } else { + set_reg_bit( _PMC_PCDR0, HAL_LL_PID_TWIHS1_BIT ); + } + break; + case ( hal_ll_i2c_module_num( I2C_MODULE_2 ) ): + if ( hal_ll_state ) { + set_reg_bit( _PMC_PCER1, HAL_LL_PID_TWIHS2_BIT ); + } else { + set_reg_bit( _PMC_PCDR1, HAL_LL_PID_TWIHS2_BIT ); + } + break; + + default: + break; + } +} + +static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pin_id *index_list ) { + // Map new pins + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_name = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].pin; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_name = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].pin; + // SCL and SDA could have different alternate function settings, hence save both AF values. + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl.pin_af = hal_ll_i2c_scl_map[ index_list[module_index].pin_scl ].af; + hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda.pin_af = hal_ll_i2c_sda_map[ index_list[module_index].pin_sda ].af; +} + +static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if( (map->pins.pin_scl.pin_name != HAL_LL_PIN_NC) && (map->pins.pin_sda.pin_name != HAL_LL_PIN_NC) ) { + module.pins[0] = map->pins.pin_scl.pin_name; + module.pins[1] = map->pins.pin_sda.pin_name; + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = map->pins.pin_scl.pin_af; + module.configs[1] = map->pins.pin_sda.pin_af; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base ); + uint32_t ckdiv = 0; + uint32_t cldiv, chdiv, c_lh_div, twihs_cwgr; + + // High-Speed can be only used in slave mode, 400k is the max speed allowed for master. + switch ( map->speed ) { + case HAL_LL_I2C_MASTER_SPEED_STANDARD: + write_reg( &hal_ll_hw_reg->cwgr, HAL_LL_TWIHS_CWGR_100K_MASK ); + break; + case HAL_LL_I2C_MASTER_SPEED_FULL: + write_reg( &hal_ll_hw_reg->cwgr, HAL_LL_TWIHS_CWGR_400K_MASK ); + break; + + default: + return HAL_LL_I2C_MASTER_ERROR; + } + + return HAL_LL_I2C_MASTER_SUCCESS; +} + +static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base ); + uint16_t time_counter = map->timeout; + int8_t status = HAL_LL_I2C_MASTER_SUCCESS; + + // Reset TWIHS control register. + set_reg_bit( &hal_ll_hw_reg->cr, HAL_LL_TWIHS_CR_SWRST_BIT ); + + // Get the actual speed and set the dividers for clock. + status = hal_ll_i2c_get_speed( map ); + + // Make sure I2C is not in Slave Mode. + set_reg_bit( &hal_ll_hw_reg->cr, HAL_LL_TWIHS_CR_SVDIS_BIT ); + + // Enable I2C in Master Mode. + set_reg_bit( &hal_ll_hw_reg->cr, HAL_LL_TWIHS_CR_MSEN_BIT ); + + return status; +} + +static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ) { + hal_ll_i2c_master_set_clock( map, true ); + + return hal_ll_i2c_hw_init( map ); +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/sam/src/spi_master/CMakeLists.txt b/targets/arm/mikroe/sam/src/spi_master/CMakeLists.txt new file mode 100644 index 000000000..ae54e3d22 --- /dev/null +++ b/targets/arm/mikroe/sam/src/spi_master/CMakeLists.txt @@ -0,0 +1,72 @@ +## ./targets/arm/mikroe/ai_generated/sam/src/spi_master/CMakeLists.txt + +## Check if current module is generated or not +set(MODULE_IS_GENERATED false) +get_files_recurse(${CMAKE_CURRENT_LIST_DIR}/implementations CMAKE_FILES cmake) +check_if_module_is_generated(MODULE_IS_GENERATED "${CMAKE_FILES}") + +## If current MCU has this module, add it +if(MODULE_IS_GENERATED) + set(hal_ll_def_list "") + set(mcu_header_path "") + + find_cortex(hal_ll_def_list) + list(APPEND hal_ll_def_list ${MCU_NAME}) + set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) + + # BEGIN SPI + list(APPEND hal_ll_def_list "MACRO_USAGE_SPI") + foreach(cmakeFile ${CMAKE_FILES}) + include(${cmakeFile}) + endforeach() + # END SPI + + mikrosdk_add_library(lib_hal_ll_spi_master MikroSDK.HalLowLevel.SPI.Master + ${pmc_subimplementation}/hal_ll_pmc.h + ../../include/hal_ll_target.h + # BEGIN SPI + ${spi_subimplementation} + ../../include/spi_master/hal_ll_spi_master.h + ${spi_pin_map}/hal_ll_spi_master_pin_map.h + # END SPI + ) + + target_compile_definitions(lib_hal_ll_spi_master PUBLIC + ${hal_ll_def_list} + ) + + target_link_libraries(lib_hal_ll_spi_master PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon + ) + + string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) + target_include_directories(lib_hal_ll_spi_master + PRIVATE + ../../include + ../../include/gpio + ${gpio_subimplementation_include_dir} + # BEGIN SPI + ../../include/spi_master + ${spi_pin_map} + # END SPI + # BEGIN PMC + ${pmc_subimplementation} + # END PMC + INTERFACE + # BUILD + $ + $ + $ + $ + $ + $ + # INSTALL + $ + $ + ) + + mikrosdk_install(MikroSDK.HalLowLevel.SPI.Master) + install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.SPI.Master ../../include/spi_master/hal_ll_spi_master.h) +endif() diff --git a/targets/arm/mikroe/sam/src/spi_master/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake b/targets/arm/mikroe/sam/src/spi_master/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake new file mode 100644 index 000000000..0db085336 --- /dev/null +++ b/targets/arm/mikroe/sam/src/spi_master/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake @@ -0,0 +1,7 @@ +if(${MCU_NAME} MATCHES "^ATSAME70Q21B") + set(spi_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_spi_master.c") + set(pmc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/pmc/implementations/arm_gcc_clang_atsam_e70") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/arm_gcc_clang_atsam_e70") + list(APPEND hal_ll_def_list "ATSAME7x") + set(spi_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/spi_master/hal_ll_spi_master_pin_map/implementations/arm_gcc_clang_atsam_e70") +endif() diff --git a/targets/arm/mikroe/sam/src/spi_master/implementations/arm_gcc_clang_atsam_e70/hal_ll_spi_master.c b/targets/arm/mikroe/sam/src/spi_master/implementations/arm_gcc_clang_atsam_e70/hal_ll_spi_master.c new file mode 100644 index 000000000..b6a970fbe --- /dev/null +++ b/targets/arm/mikroe/sam/src/spi_master/implementations/arm_gcc_clang_atsam_e70/hal_ll_spi_master.c @@ -0,0 +1,668 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_spi_master.c + * @brief SPI Master HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_pmc.h" +#include "hal_ll_spi_master.h" +#include "hal_ll_spi_master_pin_map.h" + +#include "mcu.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_spi_master_handle_register_t hal_ll_module_state[SPI_MODULE_COUNT] = {(handle_t *)NULL, (handle_t *)NULL, false}; + +// ------------------------------------------------------------- PRIVATE MACROS + +/*!< @brief Helper macro for getting system clock */ +#define hal_ll_get_system_clock (Get_Fosc_kHz() * 1000) + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_spi_master_get_module_state_address ((hal_ll_spi_master_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_spi_master_get_handle (hal_ll_spi_master_handle_register_t *)hal_ll_spi_master_get_module_state_address->hal_ll_spi_master_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_spi_master_get_base_struct(_handle) ((hal_ll_spi_master_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_spi_master_get_base_from_hal_handle ((hal_ll_spi_master_hw_specifics_map_t *)((hal_ll_spi_master_handle_register_t *)\ + (((hal_ll_spi_master_handle_register_t *)(handle))->hal_ll_spi_master_handle))->hal_ll_spi_master_handle)->base + +/*!< @brief Macros defining bit location */ +#define HAL_LL_SPI_CSR_CPOL_BIT 0 +#define HAL_LL_SPI_CR_SPIEN_BIT 0 +#define HAL_LL_SPI_MR_MSTR_BIT 0 +#define HAL_LL_SPI_SR_RDRF_BIT 0 +#define HAL_LL_SPI_SR_TDRE_BIT 1 +#define HAL_LL_SPI_CSR_NCPHA_BIT 1 +#define HAL_LL_SPI_CR_SPIDIS_BIT 1 +#define HAL_LL_SPI_MR_PS_BIT 1 +#define HAL_LL_SPI_MR_PCSDEC_BIT 2 +#define HAL_LL_SPI_CR_SWRST_BIT 7 +#define HAL_LL_SPI_CSR_SCBR_START_BIT 8 +#define HAL_LL_PID_SPI1_BIT 10 +#define HAL_LL_PID_SPI0_BIT 21 + +/*!< @#brief Macros defining register masks */ +#define HAL_LL_CSR_BITS_MASK 0xF0 +#define HAL_LL_SPI_MR_PCS_MASK 0xE0000 + +/*!< @brief Macros used for calculating baud rate value */ +#define hal_ll_spi_master_get_divider(_fosc,_speed) (_fosc/_speed) +#define hal_ll_spi_master_get_actual_speed(_fosc,_divider) (_fosc/_divider) + +/*!< @brief Default SPI Master bit-rate if no speed is set */ +#define HAL_LL_SPI_MASTER_SPEED_100K 100000 + +// -------------------------------------------------------------- PRIVATE TYPES + +/*!< @brief SPI register structure. */ +typedef struct { + uint32_t cr; + uint32_t mr; + uint32_t rdr; + uint32_t tdr; + uint32_t sr; + uint32_t ier; + uint32_t idr; + uint32_t imr; + uint32_t _unused[4]; + uint32_t csr[4]; +} hal_ll_spi_master_base_handle_t; + +/*!< @brief SPI Master hardware specific structure */ +typedef struct { + hal_ll_base_addr_t base; + uint8_t module_index; + hal_ll_spi_master_pins_t pins; + uint8_t dummy_data; + uint32_t speed; + uint32_t hw_actual_speed; + hal_ll_spi_master_mode_t mode; +} hal_ll_spi_master_hw_specifics_map_t; + +/*!< @brief SPI hw specific module values */ +typedef struct +{ + uint16_t pin_sck; + uint16_t pin_miso; + uint16_t pin_mosi; +} hal_ll_spi_pin_id; + +/*!< @brief SPI Master hw specific error values */ +typedef enum { + HAL_LL_SPI_MASTER_SUCCESS = 0, + HAL_LL_SPI_MASTER_WRONG_PINS, + HAL_LL_SPI_MASTER_MODULE_ERROR, + + HAL_LL_SPI_MASTER_ERROR = (-1) +} hal_ll_spi_master_err_t; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief SPI Master hardware specific info */ +static hal_ll_spi_master_hw_specifics_map_t hal_ll_spi_master_hw_specifics_map[] = { + { HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num( SPI_MODULE_0 ), { HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0 }, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT }, + { HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num( SPI_MODULE_1 ), { HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0 }, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT }, + + { HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, { HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0 }, 0, 0, 0, 0 } +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_spi_master_handle_register_t *low_level_handle; +static volatile hal_ll_spi_master_hw_specifics_map_t *hal_ll_spi_master_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks SCK, MISO and MOSI pins the user has passed with pre-defined + * pins in SCK, MISO and MOSI maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] sck - SCK pre-defined pin name. + * @param[in] miso - MISO pre-defined pin name. + * @param[in] mosi - MOSI pre-defined pin name. + * @param[in] *index_list - Index list address + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_spi_master_check_pins( hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_spi_master_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_spi_master_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Enable clock for SPI Master module on hardware level. + * + * Initializes SPI Master module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - True(enable clock)/False(disable clock). + * @param[in] *clock_value - SPI Master baud rate value taken from a specific peripheral clock bus. + * @return None + */ +static void hal_ll_spi_master_set_clock( hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value ); + +/** + * @brief Sets SPI Master pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if SPI is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] *map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + */ +static void hal_ll_spi_master_alternate_functions_set_state( hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Full SPI Master module initialization procedure. + * + * Initializes SPI Master module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param[in] *map - Object specific context handler. + * @return hal_ll_err_t Module specific values. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_t *map ); + +/** + * @brief Perform a read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a read operation on the bus. + * + * @param[in] *map - Object specific context handler. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] read_data_length - Number of data to be read. + * @param[in] dummy_data - Data required for read procedure. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_read_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data ); + +/** + * @brief Perform a write on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] map - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] write_data_length - Number of data to be written. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +static void hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length ); + +/** + * @brief Perform a write then read on the SPI Master bus. + * + * Initializes SPI Master module on hardware level, if not initialized beforehand + * and continues to perform a write operation on the bus. + * + * @param[in] *handle - Object specific context handler. + * @param[in] *write_data_buffer - Pointer to data buffer. + * @param[in] length_write_data - Number of data to be written. + * @param[in] *read_data_buffer - Pointer to data buffer. + * @param[in] length_read_data - Number of data to be read. + * @return hal_ll_err_t Module specific error values. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_spi_master_write_then_read( handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * SPI SCK, MISO and MOSI pins. + * + * @param[in] module_index SPI HW module index -- 0,1,2... + * @param[in] *index_list Array with SCK, MISO and MOSI map index values + * and module number + * + * @return None + */ +static void hal_ll_spi_master_map_pins( uint8_t module_index, hal_ll_spi_pin_id *index_list ); + + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS + +hal_ll_err_t hal_ll_spi_master_register_handle( hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi, hal_ll_spi_master_handle_register_t *handle_map, uint8_t *hal_module_id ) { + hal_ll_spi_pin_id index_list[ SPI_MODULE_COUNT ] = { HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC }; + uint16_t pin_check_result; + + // Check user-defined pins. + if ( ( pin_check_result = hal_ll_spi_master_check_pins( sck, miso, mosi, &index_list, handle_map ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_SPI_MASTER_WRONG_PINS; + }; + + // If user has come with the same SPI hardware module, and with the same pair of the pins, the pin mapping procedure + // will not have to take a place; otherwise, clear af-s, map new pins, set af-s, and set init state to false. + if (( hal_ll_spi_master_hw_specifics_map[ pin_check_result ].pins.sck.pin_name != sck ) || + ( hal_ll_spi_master_hw_specifics_map[ pin_check_result ].pins.miso.pin_name != miso ) || + ( hal_ll_spi_master_hw_specifics_map[ pin_check_result ].pins.mosi.pin_name != mosi ) ) { + + hal_ll_spi_master_alternate_functions_set_state( &hal_ll_spi_master_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_spi_master_map_pins( pin_check_result, &index_list ); + + hal_ll_spi_master_alternate_functions_set_state( &hal_ll_spi_master_hw_specifics_map[ pin_check_result ], true ); + + handle_map[ pin_check_result ].init_ll_state = false; + } + + // Return id of the SPI module that is going to be used. + *hal_module_id = pin_check_result; + + // Insert current module into hal_ll_module_state map. + hal_ll_module_state[ pin_check_result ].hal_ll_spi_master_handle = ( handle_t *)&hal_ll_spi_master_hw_specifics_map[ pin_check_result ].base; + + // Return the same info about module one level up ( into the HAL level ). + handle_map[ pin_check_result ].hal_ll_spi_master_handle = ( handle_t *)&hal_ll_module_state[ pin_check_result ].hal_ll_spi_master_handle; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_spi( handle_t *handle ) { + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + hal_ll_spi_master_handle_register_t *hal_handle = ( hal_ll_spi_master_handle_register_t *) *handle; + uint8_t pin_check_result = hal_ll_spi_master_hw_specifics_map_local->module_index; + + hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local); + + hal_ll_module_state[ pin_check_result ].hal_ll_spi_master_handle = ( handle_t *)&hal_ll_spi_master_hw_specifics_map[ pin_check_result ].base; + hal_ll_module_state[ pin_check_result ].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_set_default_write_data( handle_t *handle, uint8_t dummy_data ) { + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + + if ( hal_ll_spi_master_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + hal_ll_spi_master_hw_specifics_map_local->dummy_data = dummy_data; + } +} + +hal_ll_err_t hal_ll_spi_master_write( handle_t *handle, uint8_t *write_data_buffer, size_t length_data ) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + + hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_data ); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_read( handle_t *handle, uint8_t *read_data_buffer, size_t length_data ) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + + hal_ll_spi_master_read_bare_metal( hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data ); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +hal_ll_err_t hal_ll_spi_master_write_then_read( handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data ) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + + hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_hw_specifics_map_local->base, write_data_buffer, length_write_data ); + + hal_ll_spi_master_read_bare_metal( hal_ll_spi_master_hw_specifics_map_local->base, read_data_buffer, length_read_data, hal_ll_spi_master_hw_specifics_map_local->dummy_data ); + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +uint32_t hal_ll_spi_master_set_speed( handle_t *handle, uint32_t speed ) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + + low_level_handle->init_ll_state = false; + + // Insert user-defined baud rate into local map. + hal_ll_spi_master_hw_specifics_map_local->speed = speed; + + // Init once again, but with updated SPI Master baud rate value. + hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + // Return value of the SPI Master baud rate value. + return hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed; +} + +hal_ll_err_t hal_ll_spi_master_set_mode( handle_t *handle, hal_ll_spi_master_mode_t mode ) { + // Get low level HAL handle. + low_level_handle = hal_ll_spi_master_get_handle; + // Get appropriate hw specifics map. + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + + low_level_handle->init_ll_state = false; + + // Insert user-defined mode into local map. + hal_ll_spi_master_hw_specifics_map_local->mode = mode; + + // Init once again, but with updated SPI Master mode value. + hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return HAL_LL_SPI_MASTER_SUCCESS; +} + +void hal_ll_spi_master_close( handle_t* handle ) { + uint32_t dummy; + low_level_handle = hal_ll_spi_master_get_handle; + hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_spi_master_get_module_state_address ); + + if ( low_level_handle->hal_ll_spi_master_handle != NULL ) { + low_level_handle->hal_ll_spi_master_handle = NULL; + low_level_handle->hal_drv_spi_master_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_spi_master_hw_specifics_map_local->mode = HAL_LL_SPI_MASTER_MODE_DEFAULT; + hal_ll_spi_master_hw_specifics_map_local->speed = HAL_LL_SPI_MASTER_SPEED_100K; + hal_ll_spi_master_hw_specifics_map_local->dummy_data = 0; + hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed = 0; + + hal_ll_spi_master_set_clock( hal_ll_spi_master_hw_specifics_map_local, true, &dummy ); + hal_ll_spi_master_alternate_functions_set_state( hal_ll_spi_master_hw_specifics_map_local, false ); + hal_ll_spi_master_set_clock( hal_ll_spi_master_hw_specifics_map_local, false, &dummy ); + + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_name = HAL_LL_PIN_NC; + hal_ll_spi_master_hw_specifics_map_local->pins.sck.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.miso.pin_af = 0; + hal_ll_spi_master_hw_specifics_map_local->pins.mosi.pin_af = 0; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +uint8_t hal_ll_spi_master_transfer_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t data_buffer ) { + // Wait for the Transmit Data Register to be empty. + while ( !( check_reg_bit( &hal_ll_hw_reg->sr, HAL_LL_SPI_SR_TDRE_BIT ) ) ); + + // Write data to the Transmit Data Register. + write_reg( &hal_ll_hw_reg->tdr, data_buffer ); + + // Wait for the transmission to complete. + while ( !( check_reg_bit( &hal_ll_hw_reg->sr, HAL_LL_SPI_SR_RDRF_BIT ) ) ); + + // Return read data. + return *( ( volatile uint8_t *)&hal_ll_hw_reg->rdr ); +} + +static void hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length ) { + size_t transfer_counter = 0; + + // Write the first data to be transmitted into the SPI_DR register. + for( transfer_counter = 0; transfer_counter < write_data_length; transfer_counter++ ) { + // If we are good to go ( if the tx buffer value has been shifted to the shift register ), write the data. + hal_ll_spi_master_transfer_bare_metal( hal_ll_hw_reg, write_data_buffer[ transfer_counter ] ); + } +} + +static void hal_ll_spi_master_read_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data ) { + size_t transfer_counter = 0; + + // Read the first data to be transmitted into the SPI_DR register. + for( transfer_counter = 0; transfer_counter < read_data_length; transfer_counter++ ) { + // If we are good to go ( if the value from shift register has been shifted to the rx register ), read the data. + read_data_buffer[ transfer_counter ] = hal_ll_spi_master_transfer_bare_metal( hal_ll_hw_reg, dummy_data ); + } +} + +static hal_ll_pin_name_t hal_ll_spi_master_check_pins( hal_ll_pin_name_t sck_pin, hal_ll_pin_name_t miso_pin, hal_ll_pin_name_t mosi_pin, hal_ll_spi_pin_id *index_list, hal_ll_spi_master_handle_register_t *handle_map ) { + static const uint16_t sck_map_size = ( sizeof( _spi_sck_map ) ) / ( sizeof( hal_ll_spi_master_pin_map_t ) ); + static const uint16_t miso_map_size = ( sizeof( _spi_miso_map ) ) / ( sizeof( hal_ll_spi_master_pin_map_t ) ); + static const uint16_t mosi_map_size = ( sizeof( _spi_mosi_map ) ) / ( sizeof( hal_ll_spi_master_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t miso_index; + uint16_t mosi_index; + uint16_t sck_index; + + if ( ( HAL_LL_PIN_NC == sck_pin ) || ( HAL_LL_PIN_NC == miso_pin ) || ( HAL_LL_PIN_NC == mosi_pin ) ) { + return HAL_LL_PIN_NC; + } + + // Check pins from the specific pin maps with the user defined pins. + for ( sck_index = 0; sck_index < sck_map_size; sck_index++ ) { + if ( _spi_sck_map[ sck_index ].pin == sck_pin ) { + for ( miso_index = 0; miso_index < miso_map_size; miso_index++ ) { + if ( _spi_miso_map[ miso_index ].pin == miso_pin ) { + if ( _spi_sck_map[ sck_index ].module_index ==_spi_miso_map[ miso_index ].module_index ) { + for ( mosi_index = 0; mosi_index < mosi_map_size; mosi_index++ ) { + if ( _spi_mosi_map[mosi_index ].pin == mosi_pin ) { + if ( _spi_sck_map[sck_index].module_index ==_spi_mosi_map[ mosi_index ].module_index ) { + // Get module number + hal_ll_module_id = _spi_sck_map[ sck_index ].module_index; + + // Map pin names + index_list[ hal_ll_module_id ].pin_sck = sck_index; + index_list[ hal_ll_module_id ].pin_miso = miso_index; + index_list[ hal_ll_module_id ].pin_mosi = mosi_index; + + // Check if module is taken + if ( NULL == handle_map[hal_ll_module_id].hal_drv_spi_master_handle ) { + return hal_ll_module_id; + } else if ( SPI_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static void hal_ll_spi_master_map_pins( uint8_t module_index, hal_ll_spi_pin_id *index_list ) { + // if every single pin is OK, insert them into this new map, and use this map in all low level functions. + hal_ll_spi_master_hw_specifics_map[ module_index ].pins.sck.pin_name = _spi_sck_map[ index_list[ module_index ].pin_sck ].pin; + hal_ll_spi_master_hw_specifics_map[ module_index ].pins.miso.pin_name = _spi_miso_map[ index_list[ module_index ].pin_miso ].pin; + hal_ll_spi_master_hw_specifics_map[ module_index ].pins.mosi.pin_name = _spi_mosi_map[ index_list[ module_index ].pin_mosi ].pin; + + // SCK, MISO and MOSI pins could have different alternate function settings, hence save all the AF-s. + hal_ll_spi_master_hw_specifics_map[ module_index ].pins.sck.pin_af = _spi_sck_map[ index_list[ module_index ].pin_sck ].af; + hal_ll_spi_master_hw_specifics_map[ module_index ].pins.miso.pin_af = _spi_miso_map[ index_list[ module_index ].pin_miso ].af; + hal_ll_spi_master_hw_specifics_map[ module_index ].pins.mosi.pin_af = _spi_mosi_map[ index_list[ module_index ].pin_mosi ].af; +} + +static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_spi_master_handle_register_t ) ); + + static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_spi_master_handle_register_t ) ); + + while ( hal_ll_module_count-- ) { + if ( hal_ll_spi_master_get_base_from_hal_handle == hal_ll_spi_master_hw_specifics_map[ hal_ll_module_count ].base ) { + return &hal_ll_spi_master_hw_specifics_map[ hal_ll_module_count ]; + } + } + + // If NOK, return pointer to the last row of this map ( point to null pointer ). + return &hal_ll_spi_master_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_spi_master_set_clock( hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value ) { + switch ( map->module_index ) { + case ( hal_ll_spi_master_module_num( SPI_MODULE_0 ) ): + ( hal_ll_state == true )?( set_reg_bit( _PMC_PCER0, HAL_LL_PID_SPI0_BIT ) ):( set_reg_bit( _PMC_PCDR0, HAL_LL_PID_SPI0_BIT ) ); + break; + case ( hal_ll_spi_master_module_num( SPI_MODULE_1 ) ): + ( hal_ll_state == true )?( set_reg_bit( _PMC_PCER1, HAL_LL_PID_SPI1_BIT ) ):( set_reg_bit( _PMC_PCDR1, HAL_LL_PID_SPI1_BIT ) ); + break; + + } + + *clock_value = hal_ll_get_system_clock; +} + +static void hal_ll_spi_master_alternate_functions_set_state( hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if((map->pins.sck.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC) && (map->pins.miso.pin_name != HAL_LL_PIN_NC)) { + module.pins[0] = map->pins.sck.pin_name; + module.pins[1] = map->pins.miso.pin_name; + module.pins[2] = map->pins.mosi.pin_name; + module.pins[3] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = map->pins.sck.pin_af; + module.configs[1] = map->pins.miso.pin_af; + module.configs[2] = map->pins.mosi.pin_af; + module.configs[3] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init(&module, hal_ll_state); + } +} + +static uint32_t hal_ll_spi_master_hw_init( hal_ll_spi_master_hw_specifics_map_t *map, uint32_t clock_value ) { + uint8_t divider; + + hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = (hal_ll_spi_master_base_handle_t *)map->base; + + // Reset and disable SPI before configuration. + set_reg_bit( &hal_ll_hw_reg->cr, HAL_LL_SPI_CR_SWRST_BIT ); + set_reg_bit( &hal_ll_hw_reg->cr, HAL_LL_SPI_CR_SPIDIS_BIT ); + + // Populate appropriate register values to get appropriate data transfer baud rate prescalers. + divider = hal_ll_spi_master_get_divider( clock_value, map->speed ); + write_reg( &hal_ll_hw_reg->csr[0], divider << HAL_LL_SPI_CSR_SCBR_START_BIT ); + + // Choose whether idle state for the clock is high level (1) or low level (0). + if ( map->mode <= HAL_LL_SPI_MASTER_MODE_1 ) { + clear_reg_bit( &hal_ll_hw_reg->csr[0], HAL_LL_SPI_CSR_CPOL_BIT ); + } else { + set_reg_bit( &hal_ll_hw_reg->csr[0], HAL_LL_SPI_CSR_CPOL_BIT ); + } + + // Choose whether transmit occurs on the transition from ACTIVE to IDLE (1), or vice versa (0). + if ( map->mode == HAL_LL_SPI_MASTER_MODE_0 || map->mode == HAL_LL_SPI_MASTER_MODE_2 ) { + set_reg_bit( &hal_ll_hw_reg->csr[0], HAL_LL_SPI_CSR_NCPHA_BIT ); + } else { + clear_reg_bit( &hal_ll_hw_reg->csr[0], HAL_LL_SPI_CSR_NCPHA_BIT ); + } + + // Enable variable peripheral select. + set_reg_bit( &hal_ll_hw_reg->mr, HAL_LL_SPI_MR_PS_BIT ); + + // Enable chip select decoding. + set_reg_bit( &hal_ll_hw_reg->mr, HAL_LL_SPI_MR_PCSDEC_BIT ); + + // Enable independant CS lines. + set_reg_bits( &hal_ll_hw_reg->mr, HAL_LL_SPI_MR_PCS_MASK ); + + // Configure SPI in Host mode. + set_reg_bit( &hal_ll_hw_reg->mr, HAL_LL_SPI_MR_MSTR_BIT ); + + // Set FIFO reception threshold to 8-bit. + clear_reg_bits( &hal_ll_hw_reg->csr[0], HAL_LL_CSR_BITS_MASK ); + + // Enable SPI peripheral. + set_reg_bit( &hal_ll_hw_reg->cr, HAL_LL_SPI_CR_SPIEN_BIT ); + + return ( hal_ll_spi_master_get_actual_speed( clock_value, divider ) ); +} + +static void hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_t *map ) { + uint32_t clock_value; + + // Enable specific clock module. + hal_ll_spi_master_set_clock( map, true, &clock_value ); + + // Enable specific alternate functions. + hal_ll_spi_master_alternate_functions_set_state( map, true ); + + // Finally, write user-defined settings into hardware registers. + hal_ll_spi_master_hw_init( map, clock_value ); +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/sam/src/tim/CMakeLists.txt b/targets/arm/mikroe/sam/src/tim/CMakeLists.txt new file mode 100644 index 000000000..3d1af1613 --- /dev/null +++ b/targets/arm/mikroe/sam/src/tim/CMakeLists.txt @@ -0,0 +1,71 @@ +## ./targets/arm/mikroe/ai_generated/sam/src/tim/CMakeLists.txt + +## Check if current module is generated or not +set(MODULE_IS_GENERATED false) +get_files_recurse(${CMAKE_CURRENT_LIST_DIR}/implementations CMAKE_FILES cmake) +check_if_module_is_generated(MODULE_IS_GENERATED "${CMAKE_FILES}") + +## If current MCU has this module, add it +if(MODULE_IS_GENERATED) + set(hal_ll_def_list "") + set(mcu_header_path "") + + find_cortex(hal_ll_def_list) + list(APPEND hal_ll_def_list ${MCU_NAME}) + set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) + + ## BEGIN TIM + list(APPEND hal_ll_def_list "MACRO_USAGE_TIM") + foreach(cmakeFile ${CMAKE_FILES}) + include(${cmakeFile}) + endforeach() + ## END TIM + + mikrosdk_add_library(lib_hal_ll_tim MikroSDK.HalLowLevel.TIM + ${pmc_subimplementation}/hal_ll_pmc.h + ../../include/hal_ll_target.h + # BEGIN TIM + ${tim_subimplementation} + ../../include/tim/hal_ll_tim.h + ${tim_pin_map}/hal_ll_tim_pin_map.h + # END TIM + ) + + target_compile_definitions(lib_hal_ll_tim PUBLIC + ${hal_ll_def_list} + ) + + target_link_libraries(lib_hal_ll_tim PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon + ) + + string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) + target_include_directories(lib_hal_ll_tim + PRIVATE + ../../include + ../../include/gpio + ${gpio_subimplementation_include_dir} + # BEGIN TIM + ../../include/tim + ${tim_pin_map} + # END TIM + # BEGIN PMC + ${pmc_subimplementation} + # END PMC + INTERFACE + # BUILD + $ + $ + $ + $ + $ + # INSTALL + $ + $ + ) + + mikrosdk_install(MikroSDK.HalLowLevel.TIM) + install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.TIM ../../include/tim/hal_ll_tim.h) +endif() diff --git a/targets/arm/mikroe/sam/src/tim/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake b/targets/arm/mikroe/sam/src/tim/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake new file mode 100644 index 000000000..cc64ee0d0 --- /dev/null +++ b/targets/arm/mikroe/sam/src/tim/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake @@ -0,0 +1,7 @@ +if(${MCU_NAME} MATCHES "^ATSAME70Q21B$") + set(tim_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_tim.c") + set(pmc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/pmc/implementations/arm_gcc_clang_atsam_e70") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/arm_gcc_clang_atsam_e70") + list(APPEND hal_ll_def_list "ATSAME7x") + set(tim_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/tim/hal_ll_tim_pin_map/implementations/arm_gcc_clang_atsam_e70") +endif() diff --git a/targets/arm/mikroe/sam/src/tim/implementations/arm_gcc_clang_atsam_e70/hal_ll_tim.c b/targets/arm/mikroe/sam/src/tim/implementations/arm_gcc_clang_atsam_e70/hal_ll_tim.c new file mode 100644 index 000000000..39564369c --- /dev/null +++ b/targets/arm/mikroe/sam/src/tim/implementations/arm_gcc_clang_atsam_e70/hal_ll_tim.c @@ -0,0 +1,743 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_tim.c + * @brief TIM HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_gpio.h" +#include "hal_ll_pmc.h" +#include "hal_ll_tim.h" +#include "hal_ll_tim_pin_map.h" +#include "mcu.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COUNT ]; + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Timer counter channel signal. */ +#define HAL_LL_TIOA_CHANNEL_SIGNAL 0 +#define HAL_LL_TIOB_CHANNEL_SIGNAL 1 + +/*!< @brief Register bits macros. */ +#define HAL_LL_TC_CCR_CLKEN_BIT 0 +#define HAL_LL_TC_CCR_CLKDIS_BIT 1 +#define HAL_LL_TC_CCR_SWTRG_BIT 2 +#define HAL_LL_TC_EMR_NODIVCLK_BIT 8 +#define HAL_LL_TC_CMR_WAVE_BIT 15 +#define HAL_LL_PID_TC6_BIT 15 +#define HAL_LL_PID_TC7_BIT 16 +#define HAL_LL_PID_TC8_BIT 17 +#define HAL_LL_PID_TC9_BIT 18 +#define HAL_LL_PID_TC10_BIT 19 +#define HAL_LL_PID_TC11_BIT 20 +#define HAL_LL_PID_TC0_BIT 23 +#define HAL_LL_PID_TC1_BIT 24 +#define HAL_LL_PID_TC2_BIT 25 +#define HAL_LL_PID_TC3_BIT 26 +#define HAL_LL_PID_TC4_BIT 27 +#define HAL_LL_PID_TC5_BIT 28 + +/*!< @brief Register masks macros. */ +#define HAL_LL_TC_CMR_TIMER_CLOCK2_MASK 0x1 +#define HAL_LL_TC_CMR_TIMER_CLOCK3_MASK 0x2 +#define HAL_LL_TC_CMR_TIMER_CLOCK4_MASK 0x3 +#define HAL_LL_TC_CMR_WAVSEL_UP_RC_MASK 0x4000 +#define HAL_LL_TC_CMR_ACPA_CLEAR_MASK 0x20000 +#define HAL_LL_TC_CMR_ACPC_SET_MASK 0x40000 +#define HAL_LL_TC_CMR_BCPB_CLEAR_MASK 0x2000000 +#define HAL_LL_TC_CMR_BCPC_SET_MASK 0x4000000 + +/*!< @brief Helper macro fpr getting clock speed */ +#define hal_ll_get_system_clock (Get_Fosc_kHz() * 1000) +#define hal_ll_tim_timer_clock_2 (hal_ll_get_system_clock / 8) +#define hal_ll_tim_timer_clock_3 (hal_ll_get_system_clock / 32) +#define hal_ll_tim_timer_clock_4 (hal_ll_get_system_clock / 128) + +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_tim_get_base_struct(_handle) ((hal_ll_tim_base_handle_t *)_handle) + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_tim_get_module_state_address ((hal_ll_tim_handle_register_t *)*handle) + +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_tim_get_handle ( hal_ll_tim_handle_register_t * )hal_ll_tim_get_module_state_address->hal_ll_tim_handle + +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_tim_get_base_from_hal_handle ((hal_ll_tim_hw_specifics_map_t *)((hal_ll_tim_handle_register_t *)\ + (((hal_ll_tim_handle_register_t *)(handle))->hal_ll_tim_handle))->hal_ll_tim_handle)->base + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief TIM channel register ctructure. */ +typedef struct +{ + uint32_t ccr; + uint32_t cmr; + uint32_t smmr; + uint32_t rab; + uint32_t cv; + uint32_t ra; + uint32_t rb; + uint32_t rc; + uint32_t sr; + uint32_t ier; + uint32_t idr; + uint32_t imr; + uint32_t emr; + uint32_t _unused[3]; +} hal_ll_tim_channel_handle_t; + +/*!< @brief TIM register structure. */ +typedef struct +{ + hal_ll_tim_channel_handle_t channel[3]; +} hal_ll_tim_base_handle_t; + +/*!< @brief TIM pin structure */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_channel_t channel; + uint8_t af; +} hal_ll_tim_t; + +/*!< @brief TIM hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_tim_t config; + uint16_t max_period; + uint32_t freq_hz; + hal_ll_pin_name_t module_index; +} hal_ll_tim_hw_specifics_map_t; + +/*!< @brief TIM hw specific error values */ +typedef enum +{ + HAL_LL_TIM_SUCCESS = 0, + HAL_LL_TIM_MODULE_ERROR, + HAL_LL_TIM_WRONG_PIN, + + HAL_LL_TIM_ERROR = (-1) +} hal_ll_tim_err_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief TIM specific info */ +static hal_ll_tim_hw_specifics_map_t hal_ll_tim_hw_specifics_map[] = +{ + {HAL_LL_TIM0_BASE_ADDRESS, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, hal_ll_tim_module_num(TIM_MODULE_0)}, + {HAL_LL_TIM1_BASE_ADDRESS, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, hal_ll_tim_module_num(TIM_MODULE_1)}, + {HAL_LL_TIM2_BASE_ADDRESS, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, hal_ll_tim_module_num(TIM_MODULE_2)}, + {HAL_LL_TIM3_BASE_ADDRESS, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, hal_ll_tim_module_num(TIM_MODULE_3)}, + + {HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, HAL_LL_PIN_NC} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_tim_handle_register_t *low_level_handle; +static volatile hal_ll_tim_hw_specifics_map_t *hal_ll_tim_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Enable TIM module 0 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @param channel - TIM0 channel. + * @return none + */ +static inline void _hal_ll_tim0_set_clock( hal_ll_channel_t channel, bool hal_ll_state ); + +/** + * @brief Enable TIM module 1 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @param channel - TIM1 channel. + * @return none + */ +static inline void _hal_ll_tim1_set_clock( hal_ll_channel_t channel, bool hal_ll_state ); + +/** + * @brief Enable TIM module 2 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @param channel - TIM2 channel. + * @return none + */ +static inline void _hal_ll_tim2_set_clock( hal_ll_channel_t channel, bool hal_ll_state ); + +/** + * @brief Enable TIM module 3 clock. + * @param hal_ll_stat - True(enable clock)/False(disable clock). + * @param channel - TIM3 channel. + * @return none + */ +static inline void _hal_ll_tim3_set_clock( hal_ll_channel_t channel, bool hal_ll_state ); + +/** + * @brief Enable TIM module gate clock. + * @param map - Object specific context handler. + * @return None + */ +static void _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Based on selected TIM, + * return clock speed. + * @param map - Object specific context handler. + * @return uint32_t clock source. + */ +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Initialize TIM module on hardware level. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Full TIM module initialization procedure. + * + * Initializes TIM module on hardware level, based on beforehand + * set configuration and module handler. Sets adequate pin alternate functions. + * Initializes module clock. + * + * @param map - Object specific context handler. + * @return none + * + */ +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_tim_hw_specifics_map array index. + * + * @param handle - Object specific context handler. + * @return hal_ll_tim_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Check if pin is adequate. + * + * Checks tim pin the user has passed with pre-defined + * pin in tim map. + * + * @param pin - TIM pre-defined pin name. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TIM pin. + * + * @param[in] module_index TIM HW module index -- 0,1,2... + * @param[in] *index_list Array with TIM map index values + * + * @return None + */ +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ); + +/** + * @brief Sets TIM pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if TIM is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param map - Object specific context handler. + * + * @param hal_ll_state - Init/De-init + * @return none + * + */ +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_tim_register_handle( hal_ll_pin_name_t pin, hal_ll_tim_handle_register_t *handle_map, + uint8_t *hal_module_id ) { + + uint8_t index; + uint16_t pin_check_result; + + if ( ( pin_check_result = _hal_ll_tim_check_pin( pin, &index, handle_map ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_TIM_WRONG_PIN; + } + + if ( hal_ll_tim_hw_specifics_map[ pin_check_result ].config.pin != pin ){ + // Clear previous module alternate functions + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], false ); + + _hal_ll_tim_map_pin( pin_check_result, index ); + + _hal_ll_tim_alternate_functions_set_state( &hal_ll_tim_hw_specifics_map[ pin_check_result ], true ); + + handle_map[ pin_check_result ].init_ll_state = false; + + hal_ll_module_state[ pin_check_result ].init_ll_state = false; + + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = ( handle_t * )&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + + handle_map[ pin_check_result ].hal_ll_tim_handle = ( handle_t *)&hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle; + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle ) { + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + hal_ll_tim_handle_register_t *hal_handle = ( hal_ll_tim_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_tim_hw_specifics_map_local->module_index; + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = ( handle_t *)&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; + hal_ll_module_state[ pin_check_result ].init_ll_state = true; + hal_handle->init_ll_state = true; + + return HAL_LL_TIM_SUCCESS; +} + +uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz ) { + + uint8_t channel_num; + uint32_t ck_psc; + uint32_t tmp_freq; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if( HAL_LL_MODULE_ERROR == hal_ll_tim_hw_specifics_map_local->base ) { + return HAL_LL_TIM_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + channel_num = hal_ll_tim_hw_specifics_map_local->config.channel; + + // Stop capture/compare. + set_reg_bit( &hal_ll_hw_reg->channel[ channel_num ].ccr, HAL_LL_TC_CCR_CLKDIS_BIT ); + + // Check if the pin uses channel signal A or B (0x00 for signal A and 0x10 for signal B). + if ( !( hal_ll_tim_hw_specifics_map_local->config.af & HAL_LL_SIGNAL_CHANNEL_AB_MASK ) ) + clear_reg( &hal_ll_hw_reg->channel[ channel_num ].ra ); + else + clear_reg( &hal_ll_hw_reg->channel[ channel_num ].rb ); + + hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz; + + _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + + return tmp_freq; +} + +hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ) { + + float tmp_duty; + uint8_t channel_num = hal_ll_tim_hw_specifics_map_local->config.channel; + uint32_t max_duty = 0; + uint16_t max_period; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + if ( low_level_handle->init_ll_state == false ) { + hal_ll_tim_start( handle ); + low_level_handle->init_ll_state = true; + } + + tmp_duty = duty_ratio * 100; + max_period = hal_ll_tim_hw_specifics_map_local->max_period; + + max_duty = ( ( float )max_period / 100 ) * tmp_duty; + + // Check if the pin uses channel signal A or B (0x00 for signal A and 0x10 for signal B). + if ( !( hal_ll_tim_hw_specifics_map_local->config.af & HAL_LL_SIGNAL_CHANNEL_AB_MASK ) ) { + // Set duty for TIOAx pin. + write_reg( &hal_ll_hw_reg->channel[ channel_num ].ra, max_duty ); + } else { + // Set duty for TIOBx pin. + write_reg( &hal_ll_hw_reg->channel[ channel_num ].rb, max_duty ); + } + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_start( handle_t *handle ) { + uint8_t channel_num = hal_ll_tim_hw_specifics_map_local->config.channel; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + // Set UP mode with automatic trigger on RC Compare Position (go from 0 to RC value). + set_reg_bits( &hal_ll_hw_reg->channel[ channel_num ].cmr, HAL_LL_TC_CMR_WAVSEL_UP_RC_MASK ); + + // Check if the pin uses channel signal A or B (0x00 for signal A and 0x10 for signal B). + if ( !( hal_ll_tim_hw_specifics_map_local->config.af & HAL_LL_SIGNAL_CHANNEL_AB_MASK ) ) { + // Clear TIOAx pin on RA compare and set on RC compare. + set_reg_bits( &hal_ll_hw_reg->channel[ channel_num ].cmr, HAL_LL_TC_CMR_ACPA_CLEAR_MASK ); + set_reg_bits( &hal_ll_hw_reg->channel[ channel_num ].cmr, HAL_LL_TC_CMR_ACPC_SET_MASK ); + } else { + // Clear TIOBx pin on RB compare and set on RC compare. + set_reg_bits( &hal_ll_hw_reg->channel[ channel_num ].cmr, HAL_LL_TC_CMR_BCPB_CLEAR_MASK ); + set_reg_bits( &hal_ll_hw_reg->channel[ channel_num ].cmr, HAL_LL_TC_CMR_BCPC_SET_MASK ); + } + + // Enable counter. + set_reg_bit( &hal_ll_hw_reg->channel[ channel_num ].ccr, HAL_LL_TC_CCR_CLKEN_BIT ); + + // Trigger the counter. + set_reg_bit( &hal_ll_hw_reg->channel[ channel_num ].ccr, HAL_LL_TC_CCR_SWTRG_BIT ); + + return HAL_LL_TIM_SUCCESS; +} + +hal_ll_err_t hal_ll_tim_stop( handle_t *handle ) { + uint8_t channel_num = hal_ll_tim_hw_specifics_map_local->config.channel; + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); + + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); + + // Disable counter. + set_reg_bit( &hal_ll_hw_reg->channel[ channel_num ].ccr, HAL_LL_TC_CCR_CLKDIS_BIT ); + + return HAL_LL_TIM_SUCCESS; +} + +void hal_ll_tim_close( handle_t *handle ) { + + low_level_handle = hal_ll_tim_get_handle; + hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_tim_get_module_state_address); + + if( low_level_handle->hal_ll_tim_handle != NULL ) { + low_level_handle->hal_ll_tim_handle = NULL; + low_level_handle->hal_drv_tim_handle = NULL; + + low_level_handle->init_ll_state = false; + + hal_ll_tim_hw_specifics_map_local->max_period = 0; + hal_ll_tim_hw_specifics_map_local->freq_hz = 0; + + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, true ); + _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_local, false ); + _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_local->base, false ); + + hal_ll_tim_hw_specifics_map_local->config.pin = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.channel = HAL_LL_PIN_NC; + hal_ll_tim_hw_specifics_map_local->config.af = NULL; + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static inline void _hal_ll_tim0_set_clock( hal_ll_channel_t channel_num, bool hal_ll_state ) { + uint8_t id_pos; + + // Get the appropriate PID number. + switch ( channel_num ) + { + case HAL_LL_TIM_CHANNEL_0: + id_pos = HAL_LL_PID_TC0_BIT; + break; + case HAL_LL_TIM_CHANNEL_1: + id_pos = HAL_LL_PID_TC1_BIT; + break; + case HAL_LL_TIM_CHANNEL_2: + id_pos = HAL_LL_PID_TC2_BIT; + break; + } + + // Enable/disable clock for appropriate channel and timer. + if( hal_ll_state ) { + set_reg_bit( _PMC_PCER0, id_pos ); + } else { + set_reg_bit( _PMC_PCDR0, id_pos ); + } +} + +static inline void _hal_ll_tim1_set_clock( hal_ll_channel_t channel_num, bool hal_ll_state ) { + uint8_t id_pos; + + // Get the appropriate PID number. + switch ( channel_num ) + { + case HAL_LL_TIM_CHANNEL_0: + id_pos = HAL_LL_PID_TC3_BIT; + break; + case HAL_LL_TIM_CHANNEL_1: + id_pos = HAL_LL_PID_TC4_BIT; + break; + case HAL_LL_TIM_CHANNEL_2: + id_pos = HAL_LL_PID_TC5_BIT; + break; + } + + // Enable/disable clock for appropriate channel and timer. + if( hal_ll_state ) { + set_reg_bit( _PMC_PCER0, id_pos ); + } else { + set_reg_bit( _PMC_PCDR0, id_pos ); + } +} + +static inline void _hal_ll_tim2_set_clock( hal_ll_channel_t channel_num, bool hal_ll_state ) { + uint8_t id_pos; + + // Get the appropriate PID number. + switch ( channel_num ) + { + case HAL_LL_TIM_CHANNEL_0: + id_pos = HAL_LL_PID_TC6_BIT; + break; + case HAL_LL_TIM_CHANNEL_1: + id_pos = HAL_LL_PID_TC7_BIT; + break; + case HAL_LL_TIM_CHANNEL_2: + id_pos = HAL_LL_PID_TC8_BIT; + break; + } + + // Enable/disable clock for appropriate channel and timer. + if( hal_ll_state ) { + set_reg_bit( _PMC_PCER1, id_pos ); + } else { + set_reg_bit( _PMC_PCDR1, id_pos ); + } +} + +static inline void _hal_ll_tim3_set_clock( hal_ll_channel_t channel_num, bool hal_ll_state ) { + uint8_t id_pos; + + // Get the appropriate PID number. + switch ( channel_num ) + { + case HAL_LL_TIM_CHANNEL_0: + id_pos = HAL_LL_PID_TC9_BIT; + break; + case HAL_LL_TIM_CHANNEL_1: + id_pos = HAL_LL_PID_TC10_BIT; + break; + case HAL_LL_TIM_CHANNEL_2: + id_pos = HAL_LL_PID_TC11_BIT; + break; + } + + // Enable/disable clock for appropriate channel and timer. + if( hal_ll_state ) { + set_reg_bit( _PMC_PCER1, id_pos ); + } else { + set_reg_bit( _PMC_PCDR1, id_pos ); + } +} + +static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ) { + + hal_ll_pin_name_t pin_num; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + uint16_t map_size = ( sizeof( _tim_map ) / sizeof( hal_ll_tim_pin_map_t ) ); + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + // Check if the selected pin is valid. + for ( pin_num = 0; pin_num < map_size; pin_num++ ) { + if ( _tim_map[ pin_num ].pin == pin ) { + // Get module number + hal_ll_module_id = _tim_map[ pin_num ].module_index; + if ( NULL == handle_map[hal_ll_module_id].hal_drv_tim_handle ) { + *index = pin_num; + return hal_ll_module_id; + } else if ( TIM_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + // By default return last error msg. + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) ); + + while( hal_ll_module_count-- ) { + if ( hal_ll_tim_get_base_from_hal_handle == hal_ll_tim_hw_specifics_map [ hal_ll_module_count ].base) { + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_count ]; + } + } + + return &hal_ll_tim_hw_specifics_map[ hal_ll_module_error ]; +} + +static void _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) { + + switch ( map->base ) { + case ( HAL_LL_TIM0_BASE_ADDRESS ): + _hal_ll_tim0_set_clock( map->config.channel, hal_ll_state ); + break; + case ( HAL_LL_TIM1_BASE_ADDRESS ): + _hal_ll_tim1_set_clock( map->config.channel, hal_ll_state ); + break; + case ( HAL_LL_TIM2_BASE_ADDRESS ): + _hal_ll_tim2_set_clock( map->config.channel, hal_ll_state ); + break; + case ( HAL_LL_TIM3_BASE_ADDRESS ): + _hal_ll_tim3_set_clock( map->config.channel, hal_ll_state ); + break; + } +} + +static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ) { + + uint8_t tmp_channel; + + // Map new pin. + hal_ll_tim_hw_specifics_map[ module_index ].config.pin = _tim_map[ index ].pin; + tmp_channel = _tim_map[ index ].channel; + hal_ll_tim_hw_specifics_map[ module_index ].config.af = _tim_map[ index ].af; +} + +static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if ( ( map->config.pin != HAL_LL_PIN_NC ) && map->config.pin != HAL_LL_PIN_NC ) { + module.pins[0] = map->config.pin; + module.pins[1] = map->config.pin; + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = map->config.af & HAL_LL_ALTERNATE_FUNCTION_MASK; + module.configs[1] = map->config.af & HAL_LL_ALTERNATE_FUNCTION_MASK; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_tim_hw_specifics_map_t *map ) { + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); + uint8_t channel_num = map->config.channel; + + if ( UINT16_MAX < hal_ll_get_system_clock / map->freq_hz ) { + if ( UINT16_MAX < hal_ll_tim_timer_clock_2 / map->freq_hz ) { + if ( UINT16_MAX < hal_ll_tim_timer_clock_3 / map->freq_hz ) { + if ( UINT16_MAX < hal_ll_tim_timer_clock_4 / map->freq_hz ) { + // Clock divider can't be more than 16-bit field can handle. + return HAL_LL_TIM_MODULE_ERROR; + } else { + // Set TIM clock to be FOSC / 128. + set_reg_bits( &hal_ll_hw_reg->channel[ channel_num ].cmr, HAL_LL_TC_CMR_TIMER_CLOCK4_MASK ); + return hal_ll_tim_timer_clock_4; + } + } else { + // Set TIM clock to be FOSC / 32. + set_reg_bits( &hal_ll_hw_reg->channel[ channel_num ].cmr, HAL_LL_TC_CMR_TIMER_CLOCK3_MASK ); + return hal_ll_tim_timer_clock_3; + } + } else { + // Set TIM clock to be FOSC / 8. + set_reg_bits( &hal_ll_hw_reg->channel[ channel_num ].cmr, HAL_LL_TC_CMR_TIMER_CLOCK2_MASK ); + return hal_ll_tim_timer_clock_2; + } + } else { + // Set TIM clock to be FOSC. + set_reg_bit( &hal_ll_hw_reg->channel[ channel_num ].emr, HAL_LL_TC_EMR_NODIVCLK_BIT ); + return hal_ll_get_system_clock; + } +} + +static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { + hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); + uint8_t channel_num = map->config.channel; + uint32_t ck_psc; + + // Get clock speed prescaler. + ck_psc = _hal_ll_tim_get_clock_speed( map ) / map->freq_hz; + + // Write the prescale value to set the desired frequency. + write_reg( &hal_ll_hw_reg->channel[ channel_num ].rc, ck_psc ); + + // Counter is used in waveform mode. + set_reg_bit( &hal_ll_hw_reg->channel[ channel_num ].cmr, HAL_LL_TC_CMR_WAVE_BIT ); + + // Write max period to global array. + map->max_period = ( uint16_t )ck_psc; +} + +static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ) { + + _hal_ll_tim_set_clock( map, true ); + + _hal_ll_tim_alternate_functions_set_state( map, true ); + + _hal_ll_tim_hw_init( map ); +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/sam/src/uart/CMakeLists.txt b/targets/arm/mikroe/sam/src/uart/CMakeLists.txt new file mode 100644 index 000000000..681982e76 --- /dev/null +++ b/targets/arm/mikroe/sam/src/uart/CMakeLists.txt @@ -0,0 +1,72 @@ +## ./targets/arm/mikroe/ai_generated/sam/src/uart/CMakeLists.txt + +## Check if current module is generated or not +set(MODULE_IS_GENERATED false) +get_files_recurse(${CMAKE_CURRENT_LIST_DIR}/implementations CMAKE_FILES cmake) +check_if_module_is_generated(MODULE_IS_GENERATED "${CMAKE_FILES}") + +## If current MCU has this module, add it +if(MODULE_IS_GENERATED) + set(hal_ll_def_list "") + set(mcu_header_path "") + + find_cortex(hal_ll_def_list) + list(APPEND hal_ll_def_list ${MCU_NAME}) + set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) + + ## BEGIN UART + list(APPEND hal_ll_def_list "MACRO_USAGE_UART") + foreach(cmakeFile ${CMAKE_FILES}) + include(${cmakeFile}) + endforeach() + ## END UART + + mikrosdk_add_library(lib_hal_ll_uart MikroSDK.HalLowLevel.UART + ${pmc_subimplementation}/hal_ll_pmc.h + ../../include/hal_ll_target.h + # BEGIN UART + ${uart_subimplementation} + ../../include/uart/hal_ll_uart.h + ${uart_pin_map}/hal_ll_uart_pin_map.h + # END UART + ) + + target_compile_definitions(lib_hal_ll_uart PUBLIC + ${hal_ll_def_list} + ) + + target_link_libraries(lib_hal_ll_uart PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon + ) + + string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) + target_include_directories(lib_hal_ll_uart + PRIVATE + ../../include + ../../include/gpio + ${gpio_subimplementation_include_dir} + # BEGIN UART + ../../include/uart + ${uart_pin_map} + # END UART + # BEGIN PMC + ${pmc_subimplementation} + # END PMC + INTERFACE + # BUILD + $ + $ + $ + $ + $ + $ + # INSTALL + $ + $ + ) + + mikrosdk_install(MikroSDK.HalLowLevel.UART) + install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.UART ../../include/uart/hal_ll_uart.h) +endif() diff --git a/targets/arm/mikroe/sam/src/uart/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake b/targets/arm/mikroe/sam/src/uart/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake new file mode 100644 index 000000000..b32bc4423 --- /dev/null +++ b/targets/arm/mikroe/sam/src/uart/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake @@ -0,0 +1,7 @@ +if(${MCU_NAME} MATCHES "^ATSAME70Q21B$") + set(uart_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_uart.c") + set(pmc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/pmc/implementations/arm_gcc_clang_atsam_e70") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/arm_gcc_clang_atsam_e70") + list(APPEND hal_ll_def_list "ATSAME7x") + set(uart_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/uart/hal_ll_uart_pin_map/implementations/arm_gcc_clang_atsam_e70") +endif() diff --git a/targets/arm/mikroe/sam/src/uart/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake.bak b/targets/arm/mikroe/sam/src/uart/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake.bak new file mode 100644 index 000000000..96a370e6c --- /dev/null +++ b/targets/arm/mikroe/sam/src/uart/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake.bak @@ -0,0 +1,7 @@ +if(${MCU_NAME} MATCHES "^ATSAME70Q21B$") + set(uart_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_uart.c") + set(pmc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/pmc/implementations/arm_gcc_clang_atsam_e70") + set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/arm_gcc_clang_atsam_e70") + list(APPEND hal_ll_def_list "SATSAME7x") + set(uart_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/uart/hal_ll_uart_pin_map/implementations/arm_gcc_clang_atsam_e70") +endif() diff --git a/targets/arm/mikroe/sam/src/uart/implementations/arm_gcc_clang_atsam_e70/hal_ll_uart.c b/targets/arm/mikroe/sam/src/uart/implementations/arm_gcc_clang_atsam_e70/hal_ll_uart.c new file mode 100644 index 000000000..f62c0b437 --- /dev/null +++ b/targets/arm/mikroe/sam/src/uart/implementations/arm_gcc_clang_atsam_e70/hal_ll_uart.c @@ -0,0 +1,1103 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_uart.c + * @brief UART HAL LOW LEVEL layer implementation. + */ + +#include "hal_ll_pmc.h" +#include "hal_ll_uart.h" +#include "hal_ll_gpio.h" +#include "hal_ll_core.h" +#include "hal_ll_core_defines.h" +#include "hal_ll_uart_pin_map.h" +#include "mcu.h" + +/*!< @brief Local handle list */ +static volatile hal_ll_uart_handle_register_t hal_ll_module_state[UART_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; + +// ------------------------------------------------------------- PRIVATE MACROS + +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_uart_get_base_from_hal_handle ((hal_ll_uart_hw_specifics_map_t *)((hal_ll_uart_handle_register_t *)\ + (((hal_ll_uart_handle_register_t *)(handle))->hal_ll_uart_handle))->hal_ll_uart_handle)->base + +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_uart_get_handle (hal_ll_uart_handle_register_t *)hal_ll_uart_get_module_state_address->hal_ll_uart_handle + +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_uart_get_base_struct(_handle) ((hal_ll_uart_base_handle_t *)_handle) + +/*!< @brief Macros used for calculating actual baud rate value and error value */ +#define HAL_LL_UART_ACCEPTABLE_ERROR (float)1.0 +#define hal_ll_get_system_clock (Get_Fosc_kHz() * 1000) +#define hal_ll_uart_real_baud_rate(_div) (hal_ll_get_system_clock / (16 * _div)) +#define hal_ll_baud_rate_register_divider(_baud) (hal_ll_get_system_clock / (16 * _baud)) +#define hal_ll_uart_get_baud_error(_baud_real,_baud) (((float)(abs(_baud_real - _baud)) / _baud) * 100) + +/*!< @brief Macros defining bit location */ +#define HAL_LL_PID_UART0_BIT 7 +#define HAL_LL_PID_UART1_BIT 8 +#define HAL_LL_PID_UART2_BIT 12 +#define HAL_LL_PID_UART3_BIT 13 +#define HAL_LL_PID_UART4_BIT 14 + +#define HAL_LL_PID_USART0_BIT 13 +#define HAL_LL_PID_USART1_BIT 14 +#define HAL_LL_PID_USART2_BIT 15 + +#define HAL_LL_CR_RXEN_BIT 4 +#define HAL_LL_CR_RXDIS_BIT 5 +#define HAL_LL_CR_TXEN_BIT 6 +#define HAL_LL_CR_TXDIS_BIT 7 + +#define HAL_LL_UART_IER_RXRDY_BIT 0 +#define HAL_LL_UART_IER_TXRDY_BIT 1 + +#define HAL_LL_UART_IMR_RXRDY_FLAG 0x1 +#define HAL_LL_UART_IMR_TXRDY_FLAG 0x2 + +#define HAL_LL_UART_SR_RXRDY_FLAG 0x1 +#define HAL_LL_UART_SR_TXRDY_FLAG 0x2 + +/*!< @#brief Macros defining register masks */ +#define HAL_LL_UART_MR_DATA_LENGTH_7_BIT_MASK 0x0080 +#define HAL_LL_UART_MR_DATA_LENGTH_8_BIT_MASK 0x00C0 +#define HAL_LL_UART_MR_PARITY_EVEN_MASK 0x0000 +#define HAL_LL_UART_MR_PARITY_ODD_MASK 0x0200 +#define HAL_LL_UART_MR_PARITY_NONE_MASK 0x0800 +#define HAL_LL_UART_MR_STOP_BITS_ONE_MASK 0x0000 +#define HAL_LL_UART_MR_STOP_BITS_ONE_AND_HALF_MASK 0x1000 +#define HAL_LL_UART_MR_STOP_BITS_TWO_MASK 0x2000 + +#define HAL_LL_UART_CR_DISABLE_MASK 0x00AC + +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_uart_get_module_state_address ((hal_ll_uart_handle_register_t *)*handle) + +/*!< @brief Macro used for interrupt status register flag check + * Used in interrupt handlers. + */ +#define hal_ll_uart_get_status_flags(_handle,_flag) (((hal_ll_uart_base_handle_t *)_handle)->imr & _flag) + +/*!< @brief Macro used for module interrupt source check. + * Used in interrupt handlers. + */ + #define hal_ll_uart_get_interrupt_source(_handle,_bit) (((hal_ll_uart_base_handle_t *)_handle)->sr & _bit) + +/*!< @brief UART HW register structure */ +typedef struct +{ + hal_ll_base_addr_t cr; + hal_ll_base_addr_t mr; + hal_ll_base_addr_t ier; + hal_ll_base_addr_t idr; + hal_ll_base_addr_t imr; + hal_ll_base_addr_t sr; + hal_ll_base_addr_t rhr; + hal_ll_base_addr_t thr; + hal_ll_base_addr_t brgr; + hal_ll_base_addr_t cmpr; +} hal_ll_uart_base_handle_t; + +/*!< @brief UART baud rate structure */ +typedef struct +{ + uint32_t baud; + uint32_t real_baud; +} hal_ll_uart_baud_t; + +/*!< @brief UART hw specific structure */ +typedef struct +{ + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_uart_pins_t pins; + hal_ll_uart_baud_t baud_rate; + hal_ll_uart_parity_t parity; + hal_ll_uart_stop_bits_t stop_bit; + hal_ll_uart_data_bits_t data_bit; +} hal_ll_uart_hw_specifics_map_t; + +/*!< @brief UART hw specific module values */ +typedef struct +{ + uint16_t pin_tx; + uint16_t pin_rx; +} hal_ll_uart_pin_id; + +/*!< @brief UART hw specific error values */ +typedef enum +{ + HAL_LL_UART_SUCCESS = 0, + HAL_LL_UART_WRONG_PINS, + HAL_LL_UART_MODULE_ERROR, + + HAL_LL_UART_ERROR = (-1) +} hal_ll_uart_err_t; + +/*!< @brief UART module state selection */ +typedef enum +{ + HAL_LL_UART_DISABLE = 0, + HAL_LL_UART_ENABLE +} hal_ll_uart_state_t; + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief UART hardware specific info */ +static hal_ll_uart_hw_specifics_map_t hal_ll_uart_hw_specifics_map[] = +{ + {HAL_LL_USART0_BASE_ADDRESS, hal_ll_usart_module_num(USART_MODULE_0), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + {HAL_LL_USART1_BASE_ADDRESS, hal_ll_usart_module_num(USART_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + {HAL_LL_USART2_BASE_ADDRESS, hal_ll_usart_module_num(USART_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + {HAL_LL_UART0_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_0), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + {HAL_LL_UART1_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + {HAL_LL_UART2_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + {HAL_LL_UART3_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + {HAL_LL_UART4_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_4), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {0, 0}, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR} +}; + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_uart_handle_register_t *low_level_handle; +static volatile hal_ll_uart_hw_specifics_map_t *hal_ll_uart_hw_specifics_map_local; + +/*!< @brief Global interrupt handlers used in functions */ +static hal_ll_uart_isr_t irq_handler; +static handle_t objects[UART_MODULE_COUNT]; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Check if pins are adequate. + * + * Checks tx and rx pins the user has passed with pre-defined + * pins in tx and rx maps. Take into consideration that module + * index numbers have to be the same for both pins. + * + * @param[in] tx_pin - TX pre-defined pin name. + * @param[in] rx_pin - RX pre-defined pin name. + * @param[in] *index_list - Array containing map index numbers. + * @return hal_ll_pin_name_t Module index based on pins. + * + * Returns pre-defined module index from pin maps, if pins + * are adequate. + */ +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin names and alternate function values for + * TX and RX pins. + * + * @param[in] module_index UART HW module index -- 0,1,2... + * @param[in] *index_list Array with TX and RX map index values + * and module number + * + * @return None + */ +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ); + +/** + * @brief Sets UART pin alternate function state. + * + * Sets adequate value for alternate function settings. + * This function must be called if UART is to work. + * Based on value of hal_ll_state, alternate functions can be + * set or cleared. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_state - Init/De-init + * + * @return void None. + */ +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_uart_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_uart_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Enable clock for UART module on hardware level. + * + * Initializes UART module clock on hardware level, based on beforehand + * set configuration and module handler. + * + * @param[in] map - Object specific context handler. + * @param[in] hal_ll_stat - True(enable clock)/False(disable clock). + * + * @return void None. + */ +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); + +/** + * @brief Finds UART module index. + * + * Finds UART index(module number) based on + * handle value. + * + * @param[in] handle - Object specific context handler. + * + * @return uint8_t Module number. + * Returns values from 0 to 9. + */ +static uint8_t hal_ll_uart_find_index( handle_t *handle ); + +/** + * @brief Clears UART registers. + * + * Clears UART module configuration + * registers, effectively disabling the module itself. + * Take into consideration that any IRQ bits + * are not cleared. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * + * @return void None. + */ +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ); + +/** + * @brief Sets desired baud rate on hardware level. + * + * Initializes module with specified baud rate value. + * Take into consideration that if the difference + * between desired baud rate and actual baud + * rate the hw was initialized to is greater than + * 1%, baud rate shall not be set. + * If this occurs, return value shall be + * the error percentage. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired stop bits. + * + * Initializes module on hardware level + * with specified stop bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired data bits. + * + * Initializes module on hardware level + * with specified data bit bit value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets desired parity. + * + * Initializes module on hardware level + * with specified parity value. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Sets module clock value. + * + * Enables/disables specific UART module + * clock gate. + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable clock) / false(disable clock) + * + * @return void None. + */ +static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module TX line state. + * + * Enables/disables specific UART module + * TX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable transmitter pin) / false(disable transmitter pin) + * + * @return void None. + */ +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Sets module RX line state. + * + * Enables/disables specific UART module + * RX pin state + * + * @param[in] hal_ll_hw_reg - UART HW register structure. + * @param[in] pin_state - true(enable receive pin) / false(disable receive pin) + * + * @return void None. + */ +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); + +/** + * @brief Initialize UART module. + * + * Enables UART module clogk gate first. + * Sets pin alternate function state. + * Initializes specific UART module. + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ); + +/** + * @brief Initialize UART module on the hardware level. + * + * Performs UART module initialization on + * the hardware level. + * + * Procedure: + * 1. Clears control registers + * 2. Sets data bit value + * 3. Sets parity value + * 4. Sets stop bit value + * 5. Sets baud rate value + * 6. Enables transmit pin + * 7. Enables receive pin + * 8. Enables clock gate for specific module + * + * @param[in] map - Object specific context handler. + * + * @return void None. + */ +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_uart_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_handle_register_t *handle_map, uint8_t *hal_module_id ) { + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + // Check if pins are valid + if ( (pin_check_result = hal_ll_uart_check_pins( tx_pin, rx_pin, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + if ( (hal_ll_uart_hw_specifics_map[pin_check_result].pins.tx_pin.pin_name != tx_pin) || + (hal_ll_uart_hw_specifics_map[pin_check_result].pins.rx_pin.pin_name != rx_pin) ) + { + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], false ); + + hal_ll_uart_map_pins( pin_check_result, &index_list ); + + hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], true ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_uart_handle; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_uart( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + uint16_t pin_check_result; + + if ( (pin_check_result = hal_ll_uart_check_pins( hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name, + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name, &index_list, (void *)0 ) ) == HAL_LL_PIN_NC ) { + return HAL_LL_UART_WRONG_PINS; + }; + + hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_baud( handle_t *handle, uint32_t baud ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = baud; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud; +} + +hal_ll_err_t hal_ll_uart_set_parity( handle_t *handle, hal_ll_uart_parity_t parity ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->parity = parity; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_stop_bits( handle_t *handle, hal_ll_uart_stop_bits_t stop_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->stop_bit = stop_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +hal_ll_err_t hal_ll_uart_set_data_bits( handle_t *handle, hal_ll_uart_data_bits_t data_bit ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + // Chips using implementation 1 do not support 7 bit data + if( data_bit == HAL_LL_UART_DATA_BITS_7 ) { + return HAL_LL_UART_MODULE_ERROR; + } + + low_level_handle->init_ll_state = false; + + hal_ll_uart_hw_specifics_map_local->data_bit = data_bit; + + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); + + low_level_handle->init_ll_state = true; + + return HAL_LL_UART_SUCCESS; +} + +void hal_ll_uart_close( handle_t *handle ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( low_level_handle->hal_ll_uart_handle != NULL ) { + hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_local, false ); + + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_RX); + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_TX); + + hal_ll_uart_clear_regs(hal_ll_uart_hw_specifics_map_local->base); + hal_ll_uart_set_clock(hal_ll_uart_hw_specifics_map_local, false); + + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_af = 0; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name = HAL_LL_PIN_NC; + hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_af = 0; + + hal_ll_uart_hw_specifics_map_local->baud_rate.baud = 115200UL; + hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud = 0; + + irq_handler = NULL; + objects[ hal_ll_uart_find_index( handle ) ] = NULL; + + low_level_handle->hal_ll_uart_handle = NULL; + low_level_handle->hal_drv_uart_handle = NULL; + + low_level_handle->init_ll_state = false; + } +} + +void hal_ll_uart_register_irq_handler( handle_t *handle, hal_ll_uart_isr_t handler, handle_t obj ) { + irq_handler = handler; + objects[ hal_ll_uart_find_index( handle ) ] = obj; +} + +void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + set_reg_bit( &hal_ll_hw_reg->ier, HAL_LL_UART_IER_RXRDY_BIT ); + break; + + case HAL_LL_UART_IRQ_TX: + set_reg_bit( &hal_ll_hw_reg->ier, HAL_LL_UART_IER_TXRDY_BIT ); + break; + + default: + break; + } + + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + case hal_ll_usart_module_num( USART_MODULE_0 ): + hal_ll_core_enable_irq( USART0_NVIC ); + break; + + case hal_ll_usart_module_num( USART_MODULE_1 ): + hal_ll_core_enable_irq( USART1_NVIC ); + break; + + case hal_ll_usart_module_num( USART_MODULE_2 ): + hal_ll_core_enable_irq( USART2_NVIC ); + break; + + case hal_ll_uart_module_num( UART_MODULE_0 ): + hal_ll_core_enable_irq( UART0_NVIC ); + break; + + case hal_ll_uart_module_num( UART_MODULE_1 ): + hal_ll_core_enable_irq( UART1_NVIC ); + break; + + case hal_ll_uart_module_num( UART_MODULE_2 ): + hal_ll_core_enable_irq( UART2_NVIC ); + break; + + case hal_ll_uart_module_num( UART_MODULE_3 ): + hal_ll_core_enable_irq( UART3_NVIC ); + break; + + case hal_ll_uart_module_num( UART_MODULE_4 ): + hal_ll_core_enable_irq( UART4_NVIC ); + break; + + + default: + break; + } +} + +void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ) { + low_level_handle = hal_ll_uart_get_handle; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + switch ( irq ) { + case HAL_LL_UART_IRQ_RX: + set_reg_bit( &hal_ll_hw_reg->idr, HAL_LL_UART_IER_RXRDY_BIT ); + break; + + case HAL_LL_UART_IRQ_TX: + set_reg_bit( &hal_ll_hw_reg->idr, HAL_LL_UART_IER_TXRDY_BIT ); + break; + + default: + break; + } + // Check if module interrupt flags are set or not + if ( ( !hal_ll_uart_get_status_flags( hal_ll_uart_hw_specifics_map_local->base , HAL_LL_UART_IMR_RXRDY_FLAG ) ) && + ( !hal_ll_uart_get_status_flags( hal_ll_uart_hw_specifics_map_local->base , HAL_LL_UART_IMR_TXRDY_FLAG ) ) ) + { + switch ( hal_ll_uart_hw_specifics_map_local->module_index ) + { + case hal_ll_usart_module_num( USART_MODULE_0 ): + hal_ll_core_disable_irq( USART0_NVIC ); + break; + + case hal_ll_usart_module_num( USART_MODULE_1 ): + hal_ll_core_disable_irq( USART1_NVIC ); + break; + + case hal_ll_usart_module_num( USART_MODULE_2 ): + hal_ll_core_disable_irq( USART2_NVIC ); + break; + + case hal_ll_uart_module_num( UART_MODULE_0 ): + hal_ll_core_disable_irq( UART0_NVIC ); + break; + + case hal_ll_uart_module_num( UART_MODULE_1 ): + hal_ll_core_disable_irq( UART1_NVIC ); + break; + + case hal_ll_uart_module_num( UART_MODULE_2 ): + hal_ll_core_disable_irq( UART2_NVIC ); + break; + + case hal_ll_uart_module_num( UART_MODULE_3 ): + hal_ll_core_disable_irq( UART3_NVIC ); + break; + + case hal_ll_uart_module_num( UART_MODULE_4 ): + hal_ll_core_disable_irq( UART4_NVIC ); + break; + + + default: + break; + } + } +} + +void hal_ll_uart_write( handle_t *handle, uint8_t wr_data) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + write_reg( &hal_ll_hw_reg->thr, wr_data ); +} + +uint8_t hal_ll_uart_read( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + + return ( read_reg( &hal_ll_hw_reg->rhr ) ); +} + +// ------------------------------------------------------------- DEFAULT EXCEPTION HANDLERS + +void USART0_Handler(void) { + if( hal_ll_uart_get_status_flags( HAL_LL_USART0_BASE_ADDRESS , HAL_LL_UART_IMR_RXRDY_FLAG ) ) { + if( ( hal_ll_uart_get_interrupt_source( HAL_LL_USART0_BASE_ADDRESS, HAL_LL_UART_SR_RXRDY_FLAG ) ) ) { + irq_handler( objects[ hal_ll_usart_module_num( USART_MODULE_0 ) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART0_BASE_ADDRESS , HAL_LL_UART_IMR_TXRDY_FLAG ) ) { + if( ( hal_ll_uart_get_interrupt_source( HAL_LL_USART0_BASE_ADDRESS, HAL_LL_UART_SR_TXRDY_FLAG ) ) ) { + irq_handler( objects[ hal_ll_usart_module_num( USART_MODULE_0 ) ], HAL_LL_UART_IRQ_TX ); + } + } +} + +void USART1_Handler(void) { + if( hal_ll_uart_get_status_flags( HAL_LL_USART1_BASE_ADDRESS , HAL_LL_UART_IMR_RXRDY_FLAG ) ) { + if( ( hal_ll_uart_get_interrupt_source( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_SR_RXRDY_FLAG ) ) ) { + irq_handler( objects[ hal_ll_usart_module_num( USART_MODULE_1 ) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART1_BASE_ADDRESS , HAL_LL_UART_IMR_TXRDY_FLAG ) ) { + if( ( hal_ll_uart_get_interrupt_source( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_SR_TXRDY_FLAG ) ) ) { + irq_handler( objects[ hal_ll_usart_module_num( USART_MODULE_1 ) ], HAL_LL_UART_IRQ_TX ); + } + } +} + +void USART2_Handler(void) { + if( hal_ll_uart_get_status_flags( HAL_LL_USART2_BASE_ADDRESS , HAL_LL_UART_IMR_RXRDY_FLAG ) ) { + if( ( hal_ll_uart_get_interrupt_source( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_SR_RXRDY_FLAG ) ) ) { + irq_handler( objects[ hal_ll_usart_module_num( USART_MODULE_2 ) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_USART2_BASE_ADDRESS , HAL_LL_UART_IMR_TXRDY_FLAG ) ) { + if( ( hal_ll_uart_get_interrupt_source( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_SR_TXRDY_FLAG ) ) ) { + irq_handler( objects[ hal_ll_usart_module_num( USART_MODULE_2 ) ], HAL_LL_UART_IRQ_TX ); + } + } +} + +void UART0_Handler(void) { + if( hal_ll_uart_get_status_flags( HAL_LL_UART0_BASE_ADDRESS , HAL_LL_UART_IMR_RXRDY_FLAG ) ) { + if( ( hal_ll_uart_get_interrupt_source( HAL_LL_UART0_BASE_ADDRESS, HAL_LL_UART_SR_RXRDY_FLAG ) ) ) { + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_0 ) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_UART0_BASE_ADDRESS , HAL_LL_UART_IMR_TXRDY_FLAG ) ) { + if( ( hal_ll_uart_get_interrupt_source( HAL_LL_UART0_BASE_ADDRESS, HAL_LL_UART_SR_TXRDY_FLAG ) ) ) { + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_0 ) ], HAL_LL_UART_IRQ_TX ); + } + } +} + +void UART1_Handler(void) { + if( hal_ll_uart_get_status_flags( HAL_LL_UART1_BASE_ADDRESS , HAL_LL_UART_IMR_RXRDY_FLAG ) ) { + if( ( hal_ll_uart_get_interrupt_source( HAL_LL_UART1_BASE_ADDRESS, HAL_LL_UART_SR_RXRDY_FLAG ) ) ) { + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_1 ) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_UART1_BASE_ADDRESS , HAL_LL_UART_IMR_TXRDY_FLAG ) ) { + if( ( hal_ll_uart_get_interrupt_source( HAL_LL_UART1_BASE_ADDRESS, HAL_LL_UART_SR_TXRDY_FLAG ) ) ) { + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_1 ) ], HAL_LL_UART_IRQ_TX ); + } + } +} + +void UART2_Handler(void) { + if( hal_ll_uart_get_status_flags( HAL_LL_UART2_BASE_ADDRESS , HAL_LL_UART_IMR_RXRDY_FLAG ) ) { + if( ( hal_ll_uart_get_interrupt_source( HAL_LL_UART2_BASE_ADDRESS, HAL_LL_UART_SR_RXRDY_FLAG ) ) ) { + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_2 ) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_UART2_BASE_ADDRESS , HAL_LL_UART_IMR_TXRDY_FLAG ) ) { + if( ( hal_ll_uart_get_interrupt_source( HAL_LL_UART2_BASE_ADDRESS, HAL_LL_UART_SR_TXRDY_FLAG ) ) ) { + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_2 ) ], HAL_LL_UART_IRQ_TX ); + } + } +} + +void UART3_Handler(void) { + if( hal_ll_uart_get_status_flags( HAL_LL_UART3_BASE_ADDRESS , HAL_LL_UART_IMR_RXRDY_FLAG ) ) { + if( ( hal_ll_uart_get_interrupt_source( HAL_LL_UART3_BASE_ADDRESS, HAL_LL_UART_SR_RXRDY_FLAG ) ) ) { + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_3 ) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_UART3_BASE_ADDRESS , HAL_LL_UART_IMR_TXRDY_FLAG ) ) { + if( ( hal_ll_uart_get_interrupt_source( HAL_LL_UART3_BASE_ADDRESS, HAL_LL_UART_SR_TXRDY_FLAG ) ) ) { + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_3 ) ], HAL_LL_UART_IRQ_TX ); + } + } +} + +void UART4_Handler(void) { + if( hal_ll_uart_get_status_flags( HAL_LL_UART4_BASE_ADDRESS , HAL_LL_UART_IMR_RXRDY_FLAG ) ) { + if( ( hal_ll_uart_get_interrupt_source( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_SR_RXRDY_FLAG ) ) ) { + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_4 ) ], HAL_LL_UART_IRQ_RX ); + } + } + if( hal_ll_uart_get_status_flags( HAL_LL_UART4_BASE_ADDRESS , HAL_LL_UART_IMR_TXRDY_FLAG ) ) { + if( ( hal_ll_uart_get_interrupt_source( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_SR_TXRDY_FLAG ) ) ) { + irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_4 ) ], HAL_LL_UART_IRQ_TX ); + } + } +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static uint8_t hal_ll_uart_find_index( handle_t *handle ) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + if( hal_ll_uart_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + return hal_ll_uart_hw_specifics_map_local->module_index; + } else { + return NULL; + } +} + +static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ) { + static const uint16_t tx_map_size = ( sizeof( hal_ll_uart_tx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + static const uint16_t rx_map_size = ( sizeof( hal_ll_uart_rx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); + uint8_t hal_ll_module_id = 0; + uint8_t index_counter = 0; + uint16_t tx_index; + uint16_t rx_index; + + if ( ( HAL_LL_PIN_NC == tx_pin ) || ( HAL_LL_PIN_NC == rx_pin ) ) { + return HAL_LL_PIN_NC; + } + + for ( tx_index = 0; tx_index < tx_map_size; tx_index++ ) + { + if ( hal_ll_uart_tx_map[ tx_index ].pin == tx_pin ) + { + for ( rx_index = 0; rx_index < rx_map_size; rx_index++ ) + { + if ( hal_ll_uart_rx_map[ rx_index ].pin == rx_pin ) + { + if ( hal_ll_uart_tx_map[ tx_index ].base == hal_ll_uart_rx_map[ rx_index ].base ) { + // Get module number + hal_ll_module_id = hal_ll_uart_tx_map[ tx_index ].module_index; + + // Map pin names + index_list[hal_ll_module_id].pin_tx = tx_index; + index_list[hal_ll_module_id].pin_rx = rx_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_uart_handle ) { + return hal_ll_module_id; + } else if ( UART_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { + return HAL_LL_PIN_NC; + } +} + +static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + + while( hal_ll_module_count-- ) { + if (hal_ll_uart_get_base_from_hal_handle == hal_ll_uart_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_uart_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_uart_hw_specifics_map[hal_ll_module_error]; +} + +static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + switch ( map->module_index ) + { + case ( hal_ll_usart_module_num(USART_MODULE_0) ): + (hal_ll_state == true)?(set_reg_bit( _PMC_PCER0, HAL_LL_PID_USART0_BIT )):(clear_reg_bit( _PMC_PCER0, HAL_LL_PID_USART0_BIT )); + break; + + case ( hal_ll_usart_module_num(USART_MODULE_1) ): + (hal_ll_state == true)?(set_reg_bit( _PMC_PCER0, HAL_LL_PID_USART1_BIT )):(clear_reg_bit( _PMC_PCER0, HAL_LL_PID_USART1_BIT )); + break; + + case ( hal_ll_usart_module_num(USART_MODULE_2) ): + (hal_ll_state == true)?(set_reg_bit( _PMC_PCER0, HAL_LL_PID_USART2_BIT )):(clear_reg_bit( _PMC_PCER0, HAL_LL_PID_USART2_BIT )); + break; + + case ( hal_ll_uart_module_num(UART_MODULE_0) ): + (hal_ll_state == true)?(set_reg_bit( _PMC_PCER0, HAL_LL_PID_UART0_BIT )):(clear_reg_bit( _PMC_PCER0, HAL_LL_PID_UART0_BIT )); + break; + + case ( hal_ll_uart_module_num(UART_MODULE_1) ): + (hal_ll_state == true)?(set_reg_bit( _PMC_PCER0, HAL_LL_PID_UART1_BIT )):(clear_reg_bit( _PMC_PCER0, HAL_LL_PID_UART1_BIT )); + break; + + case ( hal_ll_uart_module_num(UART_MODULE_2) ): + (hal_ll_state == true)?(set_reg_bit( _PMC_PCER1, HAL_LL_PID_UART2_BIT )):(clear_reg_bit( _PMC_PCER1, HAL_LL_PID_UART2_BIT )); + break; + + case ( hal_ll_uart_module_num(UART_MODULE_3) ): + (hal_ll_state == true)?(set_reg_bit( _PMC_PCER1, HAL_LL_PID_UART3_BIT )):(clear_reg_bit( _PMC_PCER1, HAL_LL_PID_UART3_BIT )); + break; + + case ( hal_ll_uart_module_num(UART_MODULE_4) ): + (hal_ll_state == true)?(set_reg_bit( _PMC_PCER1, HAL_LL_PID_UART4_BIT )):(clear_reg_bit( _PMC_PCER1, HAL_LL_PID_UART4_BIT )); + break; + + + default: + break; + } +} + +static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ) { + // Map new pins + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_name = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].pin; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_name = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].pin; + // TX and RX could have different alternate function settings, hence save both AF values + hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_af = hal_ll_uart_tx_map[ index_list[module_index].pin_tx ].af; + hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_af = hal_ll_uart_rx_map[ index_list[module_index].pin_rx ].af; +} + +static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { + module_struct module; + + if ( ( map->pins.tx_pin.pin_name != HAL_LL_PIN_NC ) && map->pins.rx_pin.pin_name != HAL_LL_PIN_NC ) { + module.pins[0] = map->pins.tx_pin.pin_name; + module.pins[1] = map->pins.rx_pin.pin_name; + module.pins[2] = GPIO_MODULE_STRUCT_END; + + module.configs[0] = map->pins.tx_pin.pin_af; + module.configs[1] = map->pins.rx_pin.pin_af; + module.configs[2] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + } +} + +static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + uint16_t baud_rate_register_divider = hal_ll_baud_rate_register_divider( map->baud_rate.baud ); + uint32_t real_baud_rate = hal_ll_uart_real_baud_rate( baud_rate_register_divider ); + + SCB->CPACR |= ((3UL << 20) | (3UL << 22)); + + // float check = (float)(real_baud_rate - map->baud_rate.baud) / (float)map->baud_rate.baud; + + // If error greater than specified, cancel setting baud rate. + if ( HAL_LL_UART_ACCEPTABLE_ERROR < hal_ll_uart_get_baud_error( real_baud_rate, map->baud_rate.baud )) { + map->baud_rate.real_baud = hal_ll_uart_get_baud_error( real_baud_rate, map->baud_rate.baud ); + } else { + map->baud_rate.real_baud = real_baud_rate; + + write_reg( &hal_ll_hw_reg->brgr, baud_rate_register_divider ); + } +} + +static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->stop_bit ) + { + case HAL_LL_UART_STOP_BITS_ONE: + set_reg_bits( &hal_ll_hw_reg->mr, HAL_LL_UART_MR_STOP_BITS_ONE_MASK ); + break; + case HAL_LL_UART_STOP_BITS_ONE_AND_A_HALF: + set_reg_bits( &hal_ll_hw_reg->mr, HAL_LL_UART_MR_STOP_BITS_ONE_AND_HALF_MASK ); + break; + case HAL_LL_UART_STOP_BITS_TWO: + set_reg_bits( &hal_ll_hw_reg->mr, HAL_LL_UART_MR_STOP_BITS_TWO_MASK ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->data_bit ) + { + case HAL_LL_UART_DATA_BITS_7: + set_reg_bits( &hal_ll_hw_reg->mr, HAL_LL_UART_MR_DATA_LENGTH_7_BIT_MASK ); + break; + + case HAL_LL_UART_DATA_BITS_8: + set_reg_bits( &hal_ll_hw_reg->mr, HAL_LL_UART_MR_DATA_LENGTH_8_BIT_MASK ); + break; + + + default: + break; + } +} + +static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + + switch ( map->parity ) + { + case HAL_LL_UART_PARITY_NONE: + set_reg_bits( &hal_ll_hw_reg->mr, HAL_LL_UART_MR_PARITY_NONE_MASK ); + break; + case HAL_LL_UART_PARITY_EVEN: + set_reg_bits( &hal_ll_hw_reg->mr, HAL_LL_UART_MR_PARITY_EVEN_MASK ); + break; + case HAL_LL_UART_PARITY_ODD: + set_reg_bits( &hal_ll_hw_reg->mr, HAL_LL_UART_MR_PARITY_ODD_MASK ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + set_reg_bit( &hal_ll_hw_reg->cr, HAL_LL_CR_TXDIS_BIT ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &hal_ll_hw_reg->cr, HAL_LL_CR_TXEN_BIT ); + break; + + default: + break; + } +} + +static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { + switch ( pin_state ) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit( &hal_ll_hw_reg->cr, HAL_LL_CR_RXDIS_BIT ); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit( &hal_ll_hw_reg->cr, HAL_LL_CR_RXEN_BIT ); + break; + + default: + break; + } +} + +static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ) { + clear_reg( &hal_ll_hw_reg->cr ); + clear_reg( &hal_ll_hw_reg->mr ); + clear_reg( &hal_ll_hw_reg->ier ); + hal_ll_hw_reg->cr = HAL_LL_UART_CR_DISABLE_MASK; +} + +static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_clear_regs( map->base ); + + hal_ll_uart_set_data_bits_bare_metal( map ); + + hal_ll_uart_set_parity_bare_metal( map ); + + hal_ll_uart_set_stop_bits_bare_metal( map ); + + hal_ll_uart_set_baud_bare_metal( map ); + + hal_ll_uart_set_transmitter( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_receiver( map->base, HAL_LL_UART_ENABLE ); +} + +static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ) { + hal_ll_uart_set_clock( map, true ); + + hal_ll_uart_alternate_functions_set_state( map, true ); + + hal_ll_uart_hw_init( map ); +} +// ------------------------------------------------------------------------- END From f65705b9307b40d5f23f2e2660f9b3a8ae35adc4 Mon Sep 17 00:00:00 2001 From: "ivan.ruzavin" Date: Mon, 18 Nov 2024 15:05:59 +0100 Subject: [PATCH 03/56] Cmake build WIP --- .../arm/mikroe/sam/src/gpio/CMakeLists.txt | 124 ++++++++--------- .../arm_gcc_clang_atsam_e70/CMakeLists.cmake | 6 - .../hal_ll_gpio_port.c | 0 targets/arm/mikroe/sam/src/i2c/CMakeLists.txt | 126 ++++++++--------- .../CMakeLists.cmake | 0 .../hal_ll_i2c_master.c | 0 .../mikroe/sam/src/spi_master/CMakeLists.txt | 116 ++++++++-------- .../CMakeLists.cmake | 0 .../hal_ll_spi_master.c | 0 targets/arm/mikroe/sam/src/tim/CMakeLists.txt | 130 ++++++++---------- .../CMakeLists.cmake | 0 .../hal_ll_tim.c | 0 .../arm/mikroe/sam/src/uart/CMakeLists.txt | 120 ++++++++-------- .../CMakeLists.cmake.bak | 7 - .../CMakeLists.cmake | 0 .../hal_ll_uart.c | 0 16 files changed, 281 insertions(+), 348 deletions(-) delete mode 100644 targets/arm/mikroe/sam/src/gpio/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake rename targets/arm/mikroe/sam/src/gpio/implementations/{arm_gcc_clang_atsam_e70 => implementation_1}/hal_ll_gpio_port.c (100%) rename targets/arm/mikroe/sam/src/i2c/implementations/{arm_gcc_clang_atsam_e70 => implementation_1}/CMakeLists.cmake (100%) rename targets/arm/mikroe/sam/src/i2c/implementations/{arm_gcc_clang_atsam_e70 => implementation_1}/hal_ll_i2c_master.c (100%) rename targets/arm/mikroe/sam/src/spi_master/implementations/{arm_gcc_clang_atsam_e70 => implementation_1}/CMakeLists.cmake (100%) rename targets/arm/mikroe/sam/src/spi_master/implementations/{arm_gcc_clang_atsam_e70 => implementation_1}/hal_ll_spi_master.c (100%) rename targets/arm/mikroe/sam/src/tim/implementations/{arm_gcc_clang_atsam_e70 => implementation_1}/CMakeLists.cmake (100%) rename targets/arm/mikroe/sam/src/tim/implementations/{arm_gcc_clang_atsam_e70 => implementation_1}/hal_ll_tim.c (100%) delete mode 100644 targets/arm/mikroe/sam/src/uart/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake.bak rename targets/arm/mikroe/sam/src/uart/implementations/{arm_gcc_clang_atsam_e70 => implementation_1}/CMakeLists.cmake (100%) rename targets/arm/mikroe/sam/src/uart/implementations/{arm_gcc_clang_atsam_e70 => implementation_1}/hal_ll_uart.c (100%) diff --git a/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt b/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt index 807e64d39..ce4072091 100644 --- a/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt @@ -1,73 +1,59 @@ -## ./targets/arm/mikroe/ai_generated/stm32/src/gpio/CMakeLists.txt +## ./targets/arm/mikroe/stm32/src/gpio/CMakeLists.txt +set(hal_ll_def_list "") +set(MEMAKE_MCU_NAME_FIRST_7 "") +set(mcu_header_path "") -## Check if current module is generated or not -set(MODULE_IS_GENERATED false) -get_files_recurse(${CMAKE_CURRENT_LIST_DIR}/implementations CMAKE_FILES cmake) -check_if_module_is_generated(MODULE_IS_GENERATED "${CMAKE_FILES}") +find_cortex(hal_ll_def_list) -## If current MCU has this module, add it -if(MODULE_IS_GENERATED) - set(hal_ll_def_list "") - set(MEMAKE_MCU_NAME_FIRST_7 "") - set(mcu_header_path "") +list(APPEND hal_ll_def_list ${MCU_NAME}) +list(APPEND hal_ll_def_list "MACRO_USAGE_GPIO") +set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) - find_cortex(hal_ll_def_list) - list(APPEND hal_ll_def_list ${MCU_NAME}) - set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) - - ## BEGIN GPIO - list(APPEND hal_ll_def_list "MACRO_USAGE_GPIO") - foreach(cmakeFile ${CMAKE_FILES}) - include(${cmakeFile}) - endforeach() - ## END GPIO - - mikrosdk_add_library(lib_hal_ll_gpio MikroSDK.HalLowLevel.GPIO - ${pmc_subimplementation}/hal_ll_pmc.h - ../../include/hal_ll_target.h - # BEGIN GPIO - hal_ll_gpio.c - ${gpio_subimplementation} - ../../include/gpio/hal_ll_gpio.h - ../../include/gpio/hal_ll_gpio_port.h - ${gpio_subimplementation_include_dir}/hal_ll_gpio_constants.h - ${gpio_subimplementation_include_dir}/hal_ll_gpio_struct_type.h - # END GPIO - - ) - - target_compile_definitions(lib_hal_ll_gpio PUBLIC - ${hal_ll_def_list} - ) - - target_link_libraries(lib_hal_ll_gpio PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon - ) - - string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) - target_include_directories(lib_hal_ll_gpio - PRIVATE - ../../include - # BEGIN GPIO - ../../include/gpio - ${gpio_subimplementation_include_dir} - # END GPIO - # BEGIN PMC - ${pmc_subimplementation} - # END PMC - INTERFACE - # BUILD - $ - $ - $ - $ - # INSTALL - $ - $ - ) - - mikrosdk_install(MikroSDK.HalLowLevel.GPIO) - install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.GPIO ../../include/gpio/hal_ll_gpio.h ${gpio_subimplementation_include_dir}/hal_ll_gpio_constants.h ${gpio_subimplementation_include_dir}/hal_ll_gpio_struct_type.h ../../include/gpio/hal_ll_gpio_port.h) +## BEGIN GPIO +if(${MCU_NAME} MATCHES "ATSAME7.+") + set(gpio_subimplementation "implementations/implementation_1") endif() +## END GPIO + +mikrosdk_add_library(lib_hal_ll_gpio MikroSDK.HalLowLevel.GPIO + # BEGIN GPIO + hal_ll_gpio.c + ${gpio_subimplementation}/hal_ll_gpio_port.c + # END GPIO + ../../include/hal_ll_pmc.h + ../../include/hal_ll_target.h + # BEGIN GPIO + ../../include/gpio/hal_ll_gpio.h + ../../include/gpio/hal_ll_gpio_port.h + ../../include/gpio/${gpio_subimplementation}/hal_ll_gpio_constants.h + ../../include/gpio/${gpio_subimplementation}/hal_ll_gpio_struct_type.h + # END GPIO + +) + +target_compile_definitions(lib_hal_ll_gpio PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_gpio PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_gpio + PRIVATE + ../../include + # BEGIN GPIO + ../../include/gpio + # END GPIO + + INTERFACE + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.GPIO) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.GPIO ../../include/gpio/hal_ll_gpio.h ../../include/gpio/hal_ll_gpio_constants.h ../../include/gpio/hal_ll_gpio_port.h) diff --git a/targets/arm/mikroe/sam/src/gpio/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake b/targets/arm/mikroe/sam/src/gpio/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake deleted file mode 100644 index 1a3ac0db6..000000000 --- a/targets/arm/mikroe/sam/src/gpio/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake +++ /dev/null @@ -1,6 +0,0 @@ -if(${MCU_NAME} MATCHES "^ATSAME70Q21B$") - set(gpio_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_gpio_port.c") - set(pmc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/pmc/implementations/arm_gcc_clang_atsam_e70") - set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/arm_gcc_clang_atsam_e70") - list(APPEND hal_ll_def_list "ATSAME7x") -endif() diff --git a/targets/arm/mikroe/sam/src/gpio/implementations/arm_gcc_clang_atsam_e70/hal_ll_gpio_port.c b/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c similarity index 100% rename from targets/arm/mikroe/sam/src/gpio/implementations/arm_gcc_clang_atsam_e70/hal_ll_gpio_port.c rename to targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c diff --git a/targets/arm/mikroe/sam/src/i2c/CMakeLists.txt b/targets/arm/mikroe/sam/src/i2c/CMakeLists.txt index 069bc8330..5349766df 100644 --- a/targets/arm/mikroe/sam/src/i2c/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/i2c/CMakeLists.txt @@ -1,82 +1,66 @@ -## ./targets/arm/mikroe/ai_generated/sam/src/i2c/CMakeLists.txt +## ./targets/arm/mikroe/stm32/src/i2c/CMakeLists.txt +set(hal_ll_def_list "") +set(MEMAKE_MCU_NAME_FIRST_7 "") +set(mcu_header_path "") -## Check if current module is generated or not -set(MODULE_IS_GENERATED false) -get_files_recurse(${CMAKE_CURRENT_LIST_DIR}/implementations CMAKE_FILES cmake) -check_if_module_is_generated(MODULE_IS_GENERATED "${CMAKE_FILES}") +find_cortex(hal_ll_def_list) -## If current MCU has this module, add it -if(MODULE_IS_GENERATED) - set(hal_ll_def_list "") - set(mcu_header_path "") +find_mcu_header_path(hal_ll_def_list mcu_header_path MEMAKE_MCU_NAME_FIRST_7) +## BEGIN I2C +list(APPEND hal_ll_def_list "MACRO_USAGE_I2C") - find_cortex(hal_ll_def_list) - list(APPEND hal_ll_def_list ${MCU_NAME}) - set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) - - ## BEGIN I2C - list(APPEND hal_ll_def_list "MACRO_USAGE_I2C") - foreach(cmakeFile ${CMAKE_FILES}) - include(${cmakeFile}) - endforeach() - ## END I2C +if(${MCU_NAME} MATCHES "^ATSAME7.+") + set(i2c_subimplementation "implementations/implementation_1") +endif() - if (NOT DEFINED _MSDK_TFT_TP_) - list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") +if (NOT DEFINED _MSDK_TFT_TP_) + list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") +else() + if (${_MSDK_TFT_TP_} MATCHES "__TP_TSC2003__") + list(APPEND hal_ll_def_list "__TFT_RESISTIVE_TSC2003__") else() - if (${_MSDK_TFT_TP_} MATCHES "__TP_TSC2003__") - list(APPEND hal_ll_def_list "__TFT_RESISTIVE_TSC2003__") - else() - list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") - endif() + list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__") endif() +endif() - mikrosdk_add_library(lib_hal_ll_i2c_master MikroSDK.HalLowLevel.I2C.Master - ${pmc_subimplementation}/hal_ll_pmc.h - ../../include/hal_ll_target.h - # BEGIN I2C - ${i2c_subimplementation} - ../../include/i2c/hal_ll_i2c_master.h - ${i2c_pin_map}/hal_ll_i2c_pin_map.h - # END I2C - ) +mikrosdk_add_library(lib_hal_ll_i2c_master MikroSDK.HalLowLevel.I2C.Master + ${i2c_subimplementation}/hal_ll_i2c_master.c - target_compile_definitions(lib_hal_ll_i2c_master PUBLIC - ${hal_ll_def_list} - ) + ../../include/hal_ll_pmc.h + ../../include/hal_ll_target.h +# BEGIN I2C + ../../include/i2c/hal_ll_i2c_master.h + ../../include/i2c/hal_ll_i2c_pin_map/${i2c_subimplementation}/hal_ll_i2c_pin_map.h +# END I2C +) - target_link_libraries(lib_hal_ll_i2c_master PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon - ) +target_compile_definitions(lib_hal_ll_i2c_master PUBLIC + ${hal_ll_def_list} +) - string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) - target_include_directories(lib_hal_ll_i2c_master - PRIVATE - ../../include - ../../include/gpio - ${gpio_subimplementation_include_dir} - # BEGIN I2C - ../../include/i2c - ${i2c_pin_map} - # END I2C - # BEGIN PMC - ${pmc_subimplementation} - # END PMC - INTERFACE - # BUILD - $ - $ - $ - $ - $ - $ - # INSTALL - $ - $ - ) +target_link_libraries(lib_hal_ll_i2c_master PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_i2c_master + PRIVATE + ../../include + ../../include/gpio +# BEGIN I2C + ../../include/i2c + ../../include/i2c/${i2c_subimplementation} +# END I2C - mikrosdk_install(MikroSDK.HalLowLevel.I2C.Master) - install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.I2C.Master ../../include/i2c/hal_ll_i2c_master.h) -endif() + INTERFACE + $ + $ + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.I2C.Master) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.I2C.Master ../../include/i2c/hal_ll_i2c_master.h) diff --git a/targets/arm/mikroe/sam/src/i2c/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake b/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/CMakeLists.cmake similarity index 100% rename from targets/arm/mikroe/sam/src/i2c/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake rename to targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/CMakeLists.cmake diff --git a/targets/arm/mikroe/sam/src/i2c/implementations/arm_gcc_clang_atsam_e70/hal_ll_i2c_master.c b/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c similarity index 100% rename from targets/arm/mikroe/sam/src/i2c/implementations/arm_gcc_clang_atsam_e70/hal_ll_i2c_master.c rename to targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c diff --git a/targets/arm/mikroe/sam/src/spi_master/CMakeLists.txt b/targets/arm/mikroe/sam/src/spi_master/CMakeLists.txt index ae54e3d22..377721ad9 100644 --- a/targets/arm/mikroe/sam/src/spi_master/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/spi_master/CMakeLists.txt @@ -1,72 +1,64 @@ -## ./targets/arm/mikroe/ai_generated/sam/src/spi_master/CMakeLists.txt +## ./targets/arm/mikroe/sam/src/spi_master/CMakeLists.txt -## Check if current module is generated or not -set(MODULE_IS_GENERATED false) -get_files_recurse(${CMAKE_CURRENT_LIST_DIR}/implementations CMAKE_FILES cmake) -check_if_module_is_generated(MODULE_IS_GENERATED "${CMAKE_FILES}") +set(hal_ll_def_list "") +set(mcu_header_path "") -## If current MCU has this module, add it -if(MODULE_IS_GENERATED) - set(hal_ll_def_list "") - set(mcu_header_path "") +find_cortex(hal_ll_def_list) +list(APPEND hal_ll_def_list ${MCU_NAME}) +set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) - find_cortex(hal_ll_def_list) - list(APPEND hal_ll_def_list ${MCU_NAME}) - set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) +# BEGIN SPI +list(APPEND hal_ll_def_list "MACRO_USAGE_SPI") +foreach(cmakeFile ${CMAKE_FILES}) + include(${cmakeFile}) +endforeach() +# END SPI +mikrosdk_add_library(lib_hal_ll_spi_master MikroSDK.HalLowLevel.SPI.Master + ${pmc_subimplementation}/hal_ll_pmc.h + ../../include/hal_ll_target.h # BEGIN SPI - list(APPEND hal_ll_def_list "MACRO_USAGE_SPI") - foreach(cmakeFile ${CMAKE_FILES}) - include(${cmakeFile}) - endforeach() + ${spi_subimplementation} + ../../include/spi_master/hal_ll_spi_master.h + ${spi_pin_map}/hal_ll_spi_master_pin_map.h # END SPI +) - mikrosdk_add_library(lib_hal_ll_spi_master MikroSDK.HalLowLevel.SPI.Master - ${pmc_subimplementation}/hal_ll_pmc.h - ../../include/hal_ll_target.h - # BEGIN SPI - ${spi_subimplementation} - ../../include/spi_master/hal_ll_spi_master.h - ${spi_pin_map}/hal_ll_spi_master_pin_map.h - # END SPI - ) - - target_compile_definitions(lib_hal_ll_spi_master PUBLIC - ${hal_ll_def_list} - ) +target_compile_definitions(lib_hal_ll_spi_master PUBLIC + ${hal_ll_def_list} +) - target_link_libraries(lib_hal_ll_spi_master PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon - ) +target_link_libraries(lib_hal_ll_spi_master PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) - string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) - target_include_directories(lib_hal_ll_spi_master - PRIVATE - ../../include - ../../include/gpio - ${gpio_subimplementation_include_dir} - # BEGIN SPI - ../../include/spi_master - ${spi_pin_map} - # END SPI - # BEGIN PMC - ${pmc_subimplementation} - # END PMC - INTERFACE - # BUILD - $ - $ - $ - $ - $ - $ - # INSTALL - $ - $ - ) +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_spi_master + PRIVATE + ../../include + ../../include/gpio + ${gpio_subimplementation_include_dir} + # BEGIN SPI + ../../include/spi_master + ${spi_pin_map} + # END SPI + # BEGIN PMC + ${pmc_subimplementation} + # END PMC + INTERFACE + # BUILD + $ + $ + $ + $ + $ + $ + # INSTALL + $ + $ +) - mikrosdk_install(MikroSDK.HalLowLevel.SPI.Master) - install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.SPI.Master ../../include/spi_master/hal_ll_spi_master.h) -endif() +mikrosdk_install(MikroSDK.HalLowLevel.SPI.Master) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.SPI.Master ../../include/spi_master/hal_ll_spi_master.h) diff --git a/targets/arm/mikroe/sam/src/spi_master/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake b/targets/arm/mikroe/sam/src/spi_master/implementations/implementation_1/CMakeLists.cmake similarity index 100% rename from targets/arm/mikroe/sam/src/spi_master/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake rename to targets/arm/mikroe/sam/src/spi_master/implementations/implementation_1/CMakeLists.cmake diff --git a/targets/arm/mikroe/sam/src/spi_master/implementations/arm_gcc_clang_atsam_e70/hal_ll_spi_master.c b/targets/arm/mikroe/sam/src/spi_master/implementations/implementation_1/hal_ll_spi_master.c similarity index 100% rename from targets/arm/mikroe/sam/src/spi_master/implementations/arm_gcc_clang_atsam_e70/hal_ll_spi_master.c rename to targets/arm/mikroe/sam/src/spi_master/implementations/implementation_1/hal_ll_spi_master.c diff --git a/targets/arm/mikroe/sam/src/tim/CMakeLists.txt b/targets/arm/mikroe/sam/src/tim/CMakeLists.txt index 3d1af1613..10758a4c0 100644 --- a/targets/arm/mikroe/sam/src/tim/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/tim/CMakeLists.txt @@ -1,71 +1,63 @@ -## ./targets/arm/mikroe/ai_generated/sam/src/tim/CMakeLists.txt - -## Check if current module is generated or not -set(MODULE_IS_GENERATED false) -get_files_recurse(${CMAKE_CURRENT_LIST_DIR}/implementations CMAKE_FILES cmake) -check_if_module_is_generated(MODULE_IS_GENERATED "${CMAKE_FILES}") - -## If current MCU has this module, add it -if(MODULE_IS_GENERATED) - set(hal_ll_def_list "") - set(mcu_header_path "") - - find_cortex(hal_ll_def_list) - list(APPEND hal_ll_def_list ${MCU_NAME}) - set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) - - ## BEGIN TIM - list(APPEND hal_ll_def_list "MACRO_USAGE_TIM") - foreach(cmakeFile ${CMAKE_FILES}) - include(${cmakeFile}) - endforeach() - ## END TIM - - mikrosdk_add_library(lib_hal_ll_tim MikroSDK.HalLowLevel.TIM - ${pmc_subimplementation}/hal_ll_pmc.h - ../../include/hal_ll_target.h +## ./targets/arm/mikroe/sam/src/tim/CMakeLists.txt + +set(hal_ll_def_list "") +set(mcu_header_path "") + +find_cortex(hal_ll_def_list) +list(APPEND hal_ll_def_list ${MCU_NAME}) +set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) + +## BEGIN TIM +list(APPEND hal_ll_def_list "MACRO_USAGE_TIM") +foreach(cmakeFile ${CMAKE_FILES}) + include(${cmakeFile}) +endforeach() +## END TIM + +mikrosdk_add_library(lib_hal_ll_tim MikroSDK.HalLowLevel.TIM + ${pmc_subimplementation}/hal_ll_pmc.h + ../../include/hal_ll_target.h + # BEGIN TIM + ${tim_subimplementation} + ../../include/tim/hal_ll_tim.h + ${tim_pin_map}/hal_ll_tim_pin_map.h + # END TIM +) + +target_compile_definitions(lib_hal_ll_tim PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_tim PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) + +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_tim + PRIVATE + ../../include + ../../include/gpio + ${gpio_subimplementation_include_dir} # BEGIN TIM - ${tim_subimplementation} - ../../include/tim/hal_ll_tim.h - ${tim_pin_map}/hal_ll_tim_pin_map.h + ../../include/tim + ${tim_pin_map} # END TIM - ) - - target_compile_definitions(lib_hal_ll_tim PUBLIC - ${hal_ll_def_list} - ) - - target_link_libraries(lib_hal_ll_tim PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon - ) - - string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) - target_include_directories(lib_hal_ll_tim - PRIVATE - ../../include - ../../include/gpio - ${gpio_subimplementation_include_dir} - # BEGIN TIM - ../../include/tim - ${tim_pin_map} - # END TIM - # BEGIN PMC - ${pmc_subimplementation} - # END PMC - INTERFACE - # BUILD - $ - $ - $ - $ - $ - # INSTALL - $ - $ - ) - - mikrosdk_install(MikroSDK.HalLowLevel.TIM) - install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.TIM ../../include/tim/hal_ll_tim.h) -endif() + # BEGIN PMC + ${pmc_subimplementation} + # END PMC + INTERFACE + # BUILD + $ + $ + $ + $ + $ + # INSTALL + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.TIM) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.TIM ../../include/tim/hal_ll_tim.h) diff --git a/targets/arm/mikroe/sam/src/tim/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake b/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/CMakeLists.cmake similarity index 100% rename from targets/arm/mikroe/sam/src/tim/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake rename to targets/arm/mikroe/sam/src/tim/implementations/implementation_1/CMakeLists.cmake diff --git a/targets/arm/mikroe/sam/src/tim/implementations/arm_gcc_clang_atsam_e70/hal_ll_tim.c b/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c similarity index 100% rename from targets/arm/mikroe/sam/src/tim/implementations/arm_gcc_clang_atsam_e70/hal_ll_tim.c rename to targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c diff --git a/targets/arm/mikroe/sam/src/uart/CMakeLists.txt b/targets/arm/mikroe/sam/src/uart/CMakeLists.txt index 681982e76..6b489a04a 100644 --- a/targets/arm/mikroe/sam/src/uart/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/uart/CMakeLists.txt @@ -1,72 +1,64 @@ -## ./targets/arm/mikroe/ai_generated/sam/src/uart/CMakeLists.txt +## ./targets/arm/mikroe/sam/src/uart/CMakeLists.txt -## Check if current module is generated or not -set(MODULE_IS_GENERATED false) -get_files_recurse(${CMAKE_CURRENT_LIST_DIR}/implementations CMAKE_FILES cmake) -check_if_module_is_generated(MODULE_IS_GENERATED "${CMAKE_FILES}") +set(hal_ll_def_list "") +set(mcu_header_path "") -## If current MCU has this module, add it -if(MODULE_IS_GENERATED) - set(hal_ll_def_list "") - set(mcu_header_path "") +find_cortex(hal_ll_def_list) +list(APPEND hal_ll_def_list ${MCU_NAME}) +set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) - find_cortex(hal_ll_def_list) - list(APPEND hal_ll_def_list ${MCU_NAME}) - set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) +## BEGIN UART +list(APPEND hal_ll_def_list "MACRO_USAGE_UART") +foreach(cmakeFile ${CMAKE_FILES}) + include(${cmakeFile}) +endforeach() +## END UART - ## BEGIN UART - list(APPEND hal_ll_def_list "MACRO_USAGE_UART") - foreach(cmakeFile ${CMAKE_FILES}) - include(${cmakeFile}) - endforeach() - ## END UART +mikrosdk_add_library(lib_hal_ll_uart MikroSDK.HalLowLevel.UART + ${pmc_subimplementation}/hal_ll_pmc.h + ../../include/hal_ll_target.h + # BEGIN UART + ${uart_subimplementation} + ../../include/uart/hal_ll_uart.h + ${uart_pin_map}/hal_ll_uart_pin_map.h + # END UART +) - mikrosdk_add_library(lib_hal_ll_uart MikroSDK.HalLowLevel.UART - ${pmc_subimplementation}/hal_ll_pmc.h - ../../include/hal_ll_target.h - # BEGIN UART - ${uart_subimplementation} - ../../include/uart/hal_ll_uart.h - ${uart_pin_map}/hal_ll_uart_pin_map.h - # END UART - ) - - target_compile_definitions(lib_hal_ll_uart PUBLIC - ${hal_ll_def_list} - ) +target_compile_definitions(lib_hal_ll_uart PUBLIC + ${hal_ll_def_list} +) - target_link_libraries(lib_hal_ll_uart PUBLIC - MikroC.Core - MikroSDK.HalLowLevelCore - MikroSDK.HalLowLevelCommon - ) +target_link_libraries(lib_hal_ll_uart PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) - string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) - target_include_directories(lib_hal_ll_uart - PRIVATE - ../../include - ../../include/gpio - ${gpio_subimplementation_include_dir} - # BEGIN UART - ../../include/uart - ${uart_pin_map} - # END UART - # BEGIN PMC - ${pmc_subimplementation} - # END PMC - INTERFACE - # BUILD - $ - $ - $ - $ - $ - $ - # INSTALL - $ - $ - ) +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_uart + PRIVATE + ../../include + ../../include/gpio + ${gpio_subimplementation_include_dir} + # BEGIN UART + ../../include/uart + ${uart_pin_map} + # END UART + # BEGIN PMC + ${pmc_subimplementation} + # END PMC + INTERFACE + # BUILD + $ + $ + $ + $ + $ + $ + # INSTALL + $ + $ +) - mikrosdk_install(MikroSDK.HalLowLevel.UART) - install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.UART ../../include/uart/hal_ll_uart.h) -endif() +mikrosdk_install(MikroSDK.HalLowLevel.UART) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.UART ../../include/uart/hal_ll_uart.h) diff --git a/targets/arm/mikroe/sam/src/uart/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake.bak b/targets/arm/mikroe/sam/src/uart/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake.bak deleted file mode 100644 index 96a370e6c..000000000 --- a/targets/arm/mikroe/sam/src/uart/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake.bak +++ /dev/null @@ -1,7 +0,0 @@ -if(${MCU_NAME} MATCHES "^ATSAME70Q21B$") - set(uart_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_uart.c") - set(pmc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/pmc/implementations/arm_gcc_clang_atsam_e70") - set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/arm_gcc_clang_atsam_e70") - list(APPEND hal_ll_def_list "SATSAME7x") - set(uart_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/uart/hal_ll_uart_pin_map/implementations/arm_gcc_clang_atsam_e70") -endif() diff --git a/targets/arm/mikroe/sam/src/uart/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake b/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/CMakeLists.cmake similarity index 100% rename from targets/arm/mikroe/sam/src/uart/implementations/arm_gcc_clang_atsam_e70/CMakeLists.cmake rename to targets/arm/mikroe/sam/src/uart/implementations/implementation_1/CMakeLists.cmake diff --git a/targets/arm/mikroe/sam/src/uart/implementations/arm_gcc_clang_atsam_e70/hal_ll_uart.c b/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c similarity index 100% rename from targets/arm/mikroe/sam/src/uart/implementations/arm_gcc_clang_atsam_e70/hal_ll_uart.c rename to targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c From 330e4961b44475b70f6da7cc99804b619b330ddd Mon Sep 17 00:00:00 2001 From: Ivan Ruzavin Date: Mon, 18 Nov 2024 15:54:22 +0100 Subject: [PATCH 04/56] Updated target Cmake files --- targets/arm/mikroe/sam/CMakeLists.txt | 2 +- .../arm/mikroe/sam/src/gpio/CMakeLists.txt | 3 +- .../arm/mikroe/sam/src/hal_ll/CMakeLists.txt | 17 ++++--- targets/arm/mikroe/sam/src/i2c/CMakeLists.txt | 8 ++-- .../mikroe/sam/src/spi_master/CMakeLists.txt | 46 ++++++++---------- targets/arm/mikroe/sam/src/tim/CMakeLists.txt | 47 +++++++++---------- .../arm/mikroe/sam/src/uart/CMakeLists.txt | 47 +++++++++---------- 7 files changed, 76 insertions(+), 94 deletions(-) diff --git a/targets/arm/mikroe/sam/CMakeLists.txt b/targets/arm/mikroe/sam/CMakeLists.txt index d0d3a2cba..8b2369fc9 100644 --- a/targets/arm/mikroe/sam/CMakeLists.txt +++ b/targets/arm/mikroe/sam/CMakeLists.txt @@ -1,4 +1,4 @@ -## ./targets/arm/mikroe/ai_generated/stm32/CMakeLists.txt +## ./targets/arm/mikroe/sam/CMakeLists.txt # ALL MODULES add_subdirectory(src/hal_ll) diff --git a/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt b/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt index ce4072091..cf13ae82f 100644 --- a/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt @@ -1,6 +1,5 @@ -## ./targets/arm/mikroe/stm32/src/gpio/CMakeLists.txt +## ./targets/arm/mikroe/sam/src/gpio/CMakeLists.txt set(hal_ll_def_list "") -set(MEMAKE_MCU_NAME_FIRST_7 "") set(mcu_header_path "") find_cortex(hal_ll_def_list) diff --git a/targets/arm/mikroe/sam/src/hal_ll/CMakeLists.txt b/targets/arm/mikroe/sam/src/hal_ll/CMakeLists.txt index c19f23209..08e71add6 100644 --- a/targets/arm/mikroe/sam/src/hal_ll/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/hal_ll/CMakeLists.txt @@ -1,16 +1,15 @@ -## ./targets/arm/mikroe/ai_generated/sam/src/hal_ll/CMakeLists.txt +## ./targets/arm/mikroe/sam/src/hal_ll/CMakeLists.txt add_library(lib_hal_ll INTERFACE) -add_library(MikroSDK.HalLowLevel ALIAS lib_hal_ll) +add_library(MikroSDK.HalLowLevel ALIAS lib_hal_ll) + +set(module_list "") +set(module_list_supported "") +set_module_support(module_list module_list_supported ${MCU_NAME} "hal_ll_layer") target_link_libraries(lib_hal_ll INTERFACE - MikroSDK.HalLowLevel.GPIO + ${module_list} ) -get_files_recurse(${CMAKE_CURRENT_LIST_DIR}/../gpio CMAKE_FILES cmake) -foreach(cmakeFile ${CMAKE_FILES}) - include(${cmakeFile}) -endforeach() - mikrosdk_install(MikroSDK.HalLowLevel) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel ${pmc_subimplementation}/hal_ll_pmc.h ../../include/hal_ll_target.h ../../include/hal_ll_pin_names.h ../../include/hal_ll_target_names.h) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel ../../include/hal_ll_pmc.h ../../include/hal_ll_target.h ../../include/hal_ll_pin_names.h ../../include/hal_ll_target_names.h) diff --git a/targets/arm/mikroe/sam/src/i2c/CMakeLists.txt b/targets/arm/mikroe/sam/src/i2c/CMakeLists.txt index 5349766df..61f28f7f2 100644 --- a/targets/arm/mikroe/sam/src/i2c/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/i2c/CMakeLists.txt @@ -1,11 +1,13 @@ -## ./targets/arm/mikroe/stm32/src/i2c/CMakeLists.txt +## ./targets/arm/mikroe/sam/src/i2c/CMakeLists.txt set(hal_ll_def_list "") -set(MEMAKE_MCU_NAME_FIRST_7 "") set(mcu_header_path "") find_cortex(hal_ll_def_list) -find_mcu_header_path(hal_ll_def_list mcu_header_path MEMAKE_MCU_NAME_FIRST_7) +list(APPEND hal_ll_def_list ${MCU_NAME}) +list(APPEND hal_ll_def_list "MACRO_USAGE_GPIO") +set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) + ## BEGIN I2C list(APPEND hal_ll_def_list "MACRO_USAGE_I2C") diff --git a/targets/arm/mikroe/sam/src/spi_master/CMakeLists.txt b/targets/arm/mikroe/sam/src/spi_master/CMakeLists.txt index 377721ad9..72d00eb27 100644 --- a/targets/arm/mikroe/sam/src/spi_master/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/spi_master/CMakeLists.txt @@ -1,27 +1,27 @@ ## ./targets/arm/mikroe/sam/src/spi_master/CMakeLists.txt - set(hal_ll_def_list "") set(mcu_header_path "") find_cortex(hal_ll_def_list) + list(APPEND hal_ll_def_list ${MCU_NAME}) +list(APPEND hal_ll_def_list "MACRO_USAGE_GPIO") set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) -# BEGIN SPI +if (${MCU_NAME} MATCHES "^ATSAME7.+") + set(spi_subimplementation "implementations/implementation_1") +endif() list(APPEND hal_ll_def_list "MACRO_USAGE_SPI") -foreach(cmakeFile ${CMAKE_FILES}) - include(${cmakeFile}) -endforeach() -# END SPI mikrosdk_add_library(lib_hal_ll_spi_master MikroSDK.HalLowLevel.SPI.Master - ${pmc_subimplementation}/hal_ll_pmc.h + ${spi_subimplementation}/hal_ll_spi_master.c + + ../../include/hal_ll_pmc.h ../../include/hal_ll_target.h - # BEGIN SPI - ${spi_subimplementation} +# BEGIN SPI ../../include/spi_master/hal_ll_spi_master.h - ${spi_pin_map}/hal_ll_spi_master_pin_map.h - # END SPI + ../../include/spi_master/${spi_subimplementation}/hal_ll_spi_master_pin_map.h +# END SPI ) target_compile_definitions(lib_hal_ll_spi_master PUBLIC @@ -33,29 +33,21 @@ target_link_libraries(lib_hal_ll_spi_master PUBLIC MikroSDK.HalLowLevelCore MikroSDK.HalLowLevelCommon ) - string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) target_include_directories(lib_hal_ll_spi_master PRIVATE - ../../include - ../../include/gpio - ${gpio_subimplementation_include_dir} - # BEGIN SPI - ../../include/spi_master - ${spi_pin_map} - # END SPI - # BEGIN PMC - ${pmc_subimplementation} - # END PMC + ../../include + ../../include/gpio +# BEGIN SPI + ../../include/spi_master + ../../include/spi_master/${spi_subimplementation} +# END SPI + INTERFACE - # BUILD $ $ $ - $ - $ - $ - # INSTALL + $ $ $ ) diff --git a/targets/arm/mikroe/sam/src/tim/CMakeLists.txt b/targets/arm/mikroe/sam/src/tim/CMakeLists.txt index 10758a4c0..9d7d69ef0 100644 --- a/targets/arm/mikroe/sam/src/tim/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/tim/CMakeLists.txt @@ -1,27 +1,30 @@ ## ./targets/arm/mikroe/sam/src/tim/CMakeLists.txt - set(hal_ll_def_list "") set(mcu_header_path "") find_cortex(hal_ll_def_list) + list(APPEND hal_ll_def_list ${MCU_NAME}) +list(APPEND hal_ll_def_list "MACRO_USAGE_GPIO") set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) ## BEGIN TIM -list(APPEND hal_ll_def_list "MACRO_USAGE_TIM") -foreach(cmakeFile ${CMAKE_FILES}) - include(${cmakeFile}) -endforeach() +if (${MCU_NAME} MATCHES "^ATSAME7.+") + set(tim_subimplementation "implementations/implementation_1") +endif() ## END TIM +list(APPEND hal_ll_def_list "MACRO_USAGE_TIM") + mikrosdk_add_library(lib_hal_ll_tim MikroSDK.HalLowLevel.TIM - ${pmc_subimplementation}/hal_ll_pmc.h + ${tim_subimplementation}/hal_ll_tim.c + + ../../include/hal_ll_omc.h ../../include/hal_ll_target.h - # BEGIN TIM - ${tim_subimplementation} +# BEGIN TIM ../../include/tim/hal_ll_tim.h - ${tim_pin_map}/hal_ll_tim_pin_map.h - # END TIM + ../../include/tim/${tim_subimplementation}/hal_ll_tim_pin_map.h +# END TIM ) target_compile_definitions(lib_hal_ll_tim PUBLIC @@ -33,28 +36,20 @@ target_link_libraries(lib_hal_ll_tim PUBLIC MikroSDK.HalLowLevelCore MikroSDK.HalLowLevelCommon ) - string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) target_include_directories(lib_hal_ll_tim PRIVATE - ../../include - ../../include/gpio - ${gpio_subimplementation_include_dir} - # BEGIN TIM - ../../include/tim - ${tim_pin_map} - # END TIM - # BEGIN PMC - ${pmc_subimplementation} - # END PMC + ../../include + ../../include/gpio +:: BEGIN TIM + ../../include/tim + ../../include/tim/${tim_subimplementation} +:: END TIM + INTERFACE - # BUILD $ $ - $ - $ - $ - # INSTALL + $ $ $ ) diff --git a/targets/arm/mikroe/sam/src/uart/CMakeLists.txt b/targets/arm/mikroe/sam/src/uart/CMakeLists.txt index 6b489a04a..5553131e9 100644 --- a/targets/arm/mikroe/sam/src/uart/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/uart/CMakeLists.txt @@ -1,27 +1,30 @@ ## ./targets/arm/mikroe/sam/src/uart/CMakeLists.txt - set(hal_ll_def_list "") set(mcu_header_path "") find_cortex(hal_ll_def_list) + list(APPEND hal_ll_def_list ${MCU_NAME}) +list(APPEND hal_ll_def_list "MACRO_USAGE_GPIO") set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) ## BEGIN UART -list(APPEND hal_ll_def_list "MACRO_USAGE_UART") -foreach(cmakeFile ${CMAKE_FILES}) - include(${cmakeFile}) -endforeach() +if (${MCU_NAME} MATCHES "^ATSAME7.+") + set(uart_subimplementation "implementations/implementation_1") +endif() ## END UART +list(APPEND hal_ll_def_list "MACRO_USAGE_UART") + mikrosdk_add_library(lib_hal_ll_uart MikroSDK.HalLowLevel.UART - ${pmc_subimplementation}/hal_ll_pmc.h + ${uart_subimplementation}/hal_ll_uart.c + + ../../include/hal_ll_pmc.h ../../include/hal_ll_target.h - # BEGIN UART - ${uart_subimplementation} +# BEGIN UART ../../include/uart/hal_ll_uart.h - ${uart_pin_map}/hal_ll_uart_pin_map.h - # END UART + ../../include/uart/${uart_subimplementation}/hal_ll_uart_pin_map.h +# END UART ) target_compile_definitions(lib_hal_ll_uart PUBLIC @@ -33,29 +36,21 @@ target_link_libraries(lib_hal_ll_uart PUBLIC MikroSDK.HalLowLevelCore MikroSDK.HalLowLevelCommon ) - string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) target_include_directories(lib_hal_ll_uart PRIVATE - ../../include - ../../include/gpio - ${gpio_subimplementation_include_dir} - # BEGIN UART - ../../include/uart - ${uart_pin_map} - # END UART - # BEGIN PMC - ${pmc_subimplementation} - # END PMC + ../../include + ../../include/gpio + # BEGIN UART + ../../include/uart + ../../include/uart/${uart_subimplementation} + # END UART + INTERFACE - # BUILD $ $ $ - $ - $ - $ - # INSTALL + $ $ $ ) From 87479f965257f23190dda2db156d885d7aa48a8b Mon Sep 17 00:00:00 2001 From: Ivan Ruzavin Date: Mon, 18 Nov 2024 16:00:48 +0100 Subject: [PATCH 05/56] changed implementation names --- .../hal_ll_gpio_constants.h | 0 .../hal_ll_gpio_struct_type.h | 0 .../hal_ll_gpio_struct_type.h.bak | 0 .../hal_ll_i2c_pin_map.h | 0 .../{arm_gcc_clang_atsam_e70 => implementation_1}/hal_ll_pmc.h | 0 .../hal_ll_spi_master_pin_map.h | 0 .../hal_ll_tim_pin_map.h | 0 .../hal_ll_uart_pin_map.h | 0 8 files changed, 0 insertions(+), 0 deletions(-) rename targets/arm/mikroe/sam/include/gpio/implementations/{arm_gcc_clang_atsam_e70 => implementation_1}/hal_ll_gpio_constants.h (100%) rename targets/arm/mikroe/sam/include/gpio/implementations/{arm_gcc_clang_atsam_e70 => implementation_1}/hal_ll_gpio_struct_type.h (100%) rename targets/arm/mikroe/sam/include/gpio/implementations/{arm_gcc_clang_atsam_e70 => implementation_1}/hal_ll_gpio_struct_type.h.bak (100%) rename targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_pin_map/implementations/{arm_gcc_clang_atsam_e70 => implementation_1}/hal_ll_i2c_pin_map.h (100%) rename targets/arm/mikroe/sam/include/pmc/implementations/{arm_gcc_clang_atsam_e70 => implementation_1}/hal_ll_pmc.h (100%) rename targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master_pin_map/implementations/{arm_gcc_clang_atsam_e70 => implementation_1}/hal_ll_spi_master_pin_map.h (100%) rename targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/{arm_gcc_clang_atsam_e70 => implementation_1}/hal_ll_tim_pin_map.h (100%) rename targets/arm/mikroe/sam/include/uart/hal_ll_uart_pin_map/implementations/{arm_gcc_clang_atsam_e70 => implementation_1}/hal_ll_uart_pin_map.h (100%) diff --git a/targets/arm/mikroe/sam/include/gpio/implementations/arm_gcc_clang_atsam_e70/hal_ll_gpio_constants.h b/targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_constants.h similarity index 100% rename from targets/arm/mikroe/sam/include/gpio/implementations/arm_gcc_clang_atsam_e70/hal_ll_gpio_constants.h rename to targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_constants.h diff --git a/targets/arm/mikroe/sam/include/gpio/implementations/arm_gcc_clang_atsam_e70/hal_ll_gpio_struct_type.h b/targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_struct_type.h similarity index 100% rename from targets/arm/mikroe/sam/include/gpio/implementations/arm_gcc_clang_atsam_e70/hal_ll_gpio_struct_type.h rename to targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_struct_type.h diff --git a/targets/arm/mikroe/sam/include/gpio/implementations/arm_gcc_clang_atsam_e70/hal_ll_gpio_struct_type.h.bak b/targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_struct_type.h.bak similarity index 100% rename from targets/arm/mikroe/sam/include/gpio/implementations/arm_gcc_clang_atsam_e70/hal_ll_gpio_struct_type.h.bak rename to targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_struct_type.h.bak diff --git a/targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_pin_map/implementations/arm_gcc_clang_atsam_e70/hal_ll_i2c_pin_map.h b/targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_pin_map/implementations/implementation_1/hal_ll_i2c_pin_map.h similarity index 100% rename from targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_pin_map/implementations/arm_gcc_clang_atsam_e70/hal_ll_i2c_pin_map.h rename to targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_pin_map/implementations/implementation_1/hal_ll_i2c_pin_map.h diff --git a/targets/arm/mikroe/sam/include/pmc/implementations/arm_gcc_clang_atsam_e70/hal_ll_pmc.h b/targets/arm/mikroe/sam/include/pmc/implementations/implementation_1/hal_ll_pmc.h similarity index 100% rename from targets/arm/mikroe/sam/include/pmc/implementations/arm_gcc_clang_atsam_e70/hal_ll_pmc.h rename to targets/arm/mikroe/sam/include/pmc/implementations/implementation_1/hal_ll_pmc.h diff --git a/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master_pin_map/implementations/arm_gcc_clang_atsam_e70/hal_ll_spi_master_pin_map.h b/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master_pin_map/implementations/implementation_1/hal_ll_spi_master_pin_map.h similarity index 100% rename from targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master_pin_map/implementations/arm_gcc_clang_atsam_e70/hal_ll_spi_master_pin_map.h rename to targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master_pin_map/implementations/implementation_1/hal_ll_spi_master_pin_map.h diff --git a/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/arm_gcc_clang_atsam_e70/hal_ll_tim_pin_map.h b/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/implementation_1/hal_ll_tim_pin_map.h similarity index 100% rename from targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/arm_gcc_clang_atsam_e70/hal_ll_tim_pin_map.h rename to targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/implementation_1/hal_ll_tim_pin_map.h diff --git a/targets/arm/mikroe/sam/include/uart/hal_ll_uart_pin_map/implementations/arm_gcc_clang_atsam_e70/hal_ll_uart_pin_map.h b/targets/arm/mikroe/sam/include/uart/hal_ll_uart_pin_map/implementations/implementation_1/hal_ll_uart_pin_map.h similarity index 100% rename from targets/arm/mikroe/sam/include/uart/hal_ll_uart_pin_map/implementations/arm_gcc_clang_atsam_e70/hal_ll_uart_pin_map.h rename to targets/arm/mikroe/sam/include/uart/hal_ll_uart_pin_map/implementations/implementation_1/hal_ll_uart_pin_map.h From 9abfa0cf4c853e63fa48c2582b26d3d5a4426791 Mon Sep 17 00:00:00 2001 From: Ivan Ruzavin Date: Mon, 18 Nov 2024 16:05:49 +0100 Subject: [PATCH 06/56] Replaced pmc header --- .../{pmc/implementations/implementation_1 => }/hal_ll_pmc.h | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename targets/arm/mikroe/sam/include/{pmc/implementations/implementation_1 => }/hal_ll_pmc.h (100%) diff --git a/targets/arm/mikroe/sam/include/pmc/implementations/implementation_1/hal_ll_pmc.h b/targets/arm/mikroe/sam/include/hal_ll_pmc.h similarity index 100% rename from targets/arm/mikroe/sam/include/pmc/implementations/implementation_1/hal_ll_pmc.h rename to targets/arm/mikroe/sam/include/hal_ll_pmc.h From 60fe32b2328f2a2d0c9d5bbc92672f2971f50b2f Mon Sep 17 00:00:00 2001 From: Ivan Ruzavin Date: Mon, 18 Nov 2024 16:07:16 +0100 Subject: [PATCH 07/56] fixed pmc naming --- targets/arm/mikroe/sam/src/tim/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/arm/mikroe/sam/src/tim/CMakeLists.txt b/targets/arm/mikroe/sam/src/tim/CMakeLists.txt index 9d7d69ef0..57adf7a1d 100644 --- a/targets/arm/mikroe/sam/src/tim/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/tim/CMakeLists.txt @@ -19,7 +19,7 @@ list(APPEND hal_ll_def_list "MACRO_USAGE_TIM") mikrosdk_add_library(lib_hal_ll_tim MikroSDK.HalLowLevel.TIM ${tim_subimplementation}/hal_ll_tim.c - ../../include/hal_ll_omc.h + ../../include/hal_ll_pmc.h ../../include/hal_ll_target.h # BEGIN TIM ../../include/tim/hal_ll_tim.h From db5d0283424b6497c1f0679011e1ba8793c83cea Mon Sep 17 00:00:00 2001 From: Ivan Ruzavin Date: Mon, 18 Nov 2024 17:26:36 +0100 Subject: [PATCH 08/56] Build attempt --- .../hal_ll_gpio_struct_type.h.bak | 107 ------------------ .../arm/mikroe/sam/src/gpio/CMakeLists.txt | 6 +- targets/arm/mikroe/sam/src/i2c/CMakeLists.txt | 10 +- .../mikroe/sam/src/spi_master/CMakeLists.txt | 12 +- targets/arm/mikroe/sam/src/tim/CMakeLists.txt | 12 +- .../arm/mikroe/sam/src/uart/CMakeLists.txt | 8 +- 6 files changed, 25 insertions(+), 130 deletions(-) delete mode 100644 targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_struct_type.h.bak diff --git a/targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_struct_type.h.bak b/targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_struct_type.h.bak deleted file mode 100644 index 36f24c3bf..000000000 --- a/targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_struct_type.h.bak +++ /dev/null @@ -1,107 +0,0 @@ -/**************************************************************************** -** -** Copyright (C) 2024 MikroElektronika d.o.o. -** Contact: https://www.mikroe.com/contact -** -** This file is part of the mikroSDK package -** -** Commercial License Usage -** -** Licensees holding valid commercial NECTO compilers AI licenses may use this -** file in accordance with the commercial license agreement provided with the -** Software or, alternatively, in accordance with the terms contained in -** a written agreement between you and The MikroElektronika Company. -** For licensing terms and conditions see -** https://www.mikroe.com/legal/software-license-agreement. -** For further information use the contact form at -** https://www.mikroe.com/contact. -** -** -** GNU Lesser General Public License Usage -** -** Alternatively, this file may be used for -** non-commercial projects under the terms of the GNU Lesser -** General Public License version 3 as published by the Free Software -** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. -** -** The above copyright notice and this permission notice shall be -** included in all copies or substantial portions of the Software. -** -** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT -** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE -** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -** -****************************************************************************/ -/*! - * @file hal_ll_gpio_struct_type.h - * @brief GPIO HAL LL register structure typedef. - */ - -#ifndef _HAL_LL_GPIO_STRUCT_TYPE_H_ -#define _HAL_LL_GPIO_STRUCT_TYPE_H_ - -#ifdef __cplusplus -extern "C"{ -#endif - -#include - -/** - * GPIO module interrupt registers control structure - **/ -typedef struct hal_ll_gpio_interrupt_register_handle -{ - uint32_t enable; - uint32_t disable; - uint32_t mask; - uint32_t status; -} hal_ll_gpio_interrupt_register_handle_t; - -/** - * GPIO module signal registers control structure - **/ -typedef struct hal_ll_gpio_signal_register_handle -{ - uint32_t enable; - uint32_t disable; - uint32_t status; - uint32_t pin_status; -} hal_ll_gpio_signal_register_handle_t; - -/** - * GPIO module registers control structure - **/ -typedef struct hal_ll_gpio_register_handle -{ - uint32_t enable; - uint32_t disable; - uint32_t status; - uint32_t unused; -} hal_ll_gpio_register_handle_t; - -/** - * GPIO module registers access structure - */ -typedef struct hal_ll_gpio_base_handle -{ - hal_ll_gpio_register_handle_t pio; /* Parallel input-output controller */ - hal_ll_gpio_register_handle_t output; /* Output configuration controller */ - hal_ll_gpio_register_handle_t filter; /* Input filter controller */ - hal_ll_gpio_signal_register_handle_t signal; /* Output signal controller */ - hal_ll_gpio_interrupt_register_handle_t interrupt; - hal_ll_gpio_register_handle_t multi_driver; - hal_ll_gpio_register_handle_t pullup_disable; - uint32_t abcdsr0; /* Peripheral ABCD Select Register 0 */ - uint32_t abcdsr1; /* Peripheral ABCD Select Register 1 */ -} hal_ll_gpio_base_handle_t; - -#ifdef __cplusplus -} -#endif - -#endif // _HAL_LL_GPIO_STRUCT_TYPE_H_ -// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt b/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt index cf13ae82f..982cb213e 100644 --- a/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt @@ -9,7 +9,7 @@ list(APPEND hal_ll_def_list "MACRO_USAGE_GPIO") set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) ## BEGIN GPIO -if(${MCU_NAME} MATCHES "ATSAME7.+") +if(${MCU_NAME} MATCHES "^ATSAME7.+") set(gpio_subimplementation "implementations/implementation_1") endif() ## END GPIO @@ -45,14 +45,16 @@ target_include_directories(lib_hal_ll_gpio ../../include # BEGIN GPIO ../../include/gpio + ../../include/gpio/${gpio_subimplementation} # END GPIO INTERFACE $ $ + $ $ $ ) mikrosdk_install(MikroSDK.HalLowLevel.GPIO) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.GPIO ../../include/gpio/hal_ll_gpio.h ../../include/gpio/hal_ll_gpio_constants.h ../../include/gpio/hal_ll_gpio_port.h) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.GPIO ../../include/gpio/hal_ll_gpio.h ../../include/gpio/${gpio_subimplementation}/hal_ll_gpio_constants.h ../../include/gpio/${gpio_subimplementation}/hal_ll_gpio_struct_type.h ../../include/gpio/hal_ll_gpio_port.h) diff --git a/targets/arm/mikroe/sam/src/i2c/CMakeLists.txt b/targets/arm/mikroe/sam/src/i2c/CMakeLists.txt index 61f28f7f2..4a2036319 100644 --- a/targets/arm/mikroe/sam/src/i2c/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/i2c/CMakeLists.txt @@ -30,10 +30,10 @@ mikrosdk_add_library(lib_hal_ll_i2c_master MikroSDK.HalLowLevel.I2C.Master ../../include/hal_ll_pmc.h ../../include/hal_ll_target.h -# BEGIN I2C + # BEGIN I2C ../../include/i2c/hal_ll_i2c_master.h ../../include/i2c/hal_ll_i2c_pin_map/${i2c_subimplementation}/hal_ll_i2c_pin_map.h -# END I2C + # END I2C ) target_compile_definitions(lib_hal_ll_i2c_master PUBLIC @@ -50,10 +50,10 @@ target_include_directories(lib_hal_ll_i2c_master PRIVATE ../../include ../../include/gpio -# BEGIN I2C + # BEGIN I2C ../../include/i2c - ../../include/i2c/${i2c_subimplementation} -# END I2C + ../../include/i2c/hal_ll_i2c_pin_map/${i2c_subimplementation} + # END I2C INTERFACE $ diff --git a/targets/arm/mikroe/sam/src/spi_master/CMakeLists.txt b/targets/arm/mikroe/sam/src/spi_master/CMakeLists.txt index 72d00eb27..424dd9c9c 100644 --- a/targets/arm/mikroe/sam/src/spi_master/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/spi_master/CMakeLists.txt @@ -18,10 +18,10 @@ mikrosdk_add_library(lib_hal_ll_spi_master MikroSDK.HalLowLevel.SPI.Master ../../include/hal_ll_pmc.h ../../include/hal_ll_target.h -# BEGIN SPI + # BEGIN SPI ../../include/spi_master/hal_ll_spi_master.h - ../../include/spi_master/${spi_subimplementation}/hal_ll_spi_master_pin_map.h -# END SPI + ../../include/spi_master/hal_ll_spi_master_pin_map/${spi_subimplementation}/hal_ll_spi_master_pin_map.h + # END SPI ) target_compile_definitions(lib_hal_ll_spi_master PUBLIC @@ -38,10 +38,10 @@ target_include_directories(lib_hal_ll_spi_master PRIVATE ../../include ../../include/gpio -# BEGIN SPI + # BEGIN SPI ../../include/spi_master - ../../include/spi_master/${spi_subimplementation} -# END SPI + ../../include/spi_master/hal_ll_spi_master_pin_map/${spi_subimplementation} + # END SPI INTERFACE $ diff --git a/targets/arm/mikroe/sam/src/tim/CMakeLists.txt b/targets/arm/mikroe/sam/src/tim/CMakeLists.txt index 57adf7a1d..7fbe27141 100644 --- a/targets/arm/mikroe/sam/src/tim/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/tim/CMakeLists.txt @@ -21,10 +21,10 @@ mikrosdk_add_library(lib_hal_ll_tim MikroSDK.HalLowLevel.TIM ../../include/hal_ll_pmc.h ../../include/hal_ll_target.h -# BEGIN TIM + # BEGIN TIM ../../include/tim/hal_ll_tim.h - ../../include/tim/${tim_subimplementation}/hal_ll_tim_pin_map.h -# END TIM + ../../include/tim/hal_ll_tim_pin_map/${tim_subimplementation}/hal_ll_tim_pin_map.h + # END TIM ) target_compile_definitions(lib_hal_ll_tim PUBLIC @@ -41,10 +41,10 @@ target_include_directories(lib_hal_ll_tim PRIVATE ../../include ../../include/gpio -:: BEGIN TIM + # BEGIN TIM ../../include/tim - ../../include/tim/${tim_subimplementation} -:: END TIM + ../../include/tim/hal_ll_tim_pin_map/${tim_subimplementation} + # END TIM INTERFACE $ diff --git a/targets/arm/mikroe/sam/src/uart/CMakeLists.txt b/targets/arm/mikroe/sam/src/uart/CMakeLists.txt index 5553131e9..a1f724137 100644 --- a/targets/arm/mikroe/sam/src/uart/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/uart/CMakeLists.txt @@ -21,10 +21,10 @@ mikrosdk_add_library(lib_hal_ll_uart MikroSDK.HalLowLevel.UART ../../include/hal_ll_pmc.h ../../include/hal_ll_target.h -# BEGIN UART + # BEGIN UART ../../include/uart/hal_ll_uart.h - ../../include/uart/${uart_subimplementation}/hal_ll_uart_pin_map.h -# END UART + ../../include/uart/hal_ll_uart_pin_map/${uart_subimplementation}/hal_ll_uart_pin_map.h + # END UART ) target_compile_definitions(lib_hal_ll_uart PUBLIC @@ -43,7 +43,7 @@ target_include_directories(lib_hal_ll_uart ../../include/gpio # BEGIN UART ../../include/uart - ../../include/uart/${uart_subimplementation} + ../../include/uart/hal_ll_uart_pin_map/${uart_subimplementation} # END UART INTERFACE From aed7615175c45d79d89e51ab2a3787f923483c3a Mon Sep 17 00:00:00 2001 From: Ivan Ruzavin Date: Mon, 18 Nov 2024 20:28:09 +0100 Subject: [PATCH 09/56] Build success --- hal/interface/CMakeLists.txt | 8 +- .../ATSAME70Q21B/LQFP144/mcu_definitions.h | 8 + targets/arm/mikroe/sam/CMakeLists.txt | 4 +- .../arm/mikroe/sam/include/adc/hal_ll_adc.h | 227 +++++++++++ .../implementation_1/hal_ll_adc_pin_map.h | 128 ++++++ .../implementation_1/hal_ll_one_wire.h | 232 +++++++++++ targets/arm/mikroe/sam/src/adc/CMakeLists.txt | 60 +++ .../implementation_1/hal_ll_adc.c | 367 ++++++++++++++++++ .../arm/mikroe/sam/src/gpio/CMakeLists.txt | 1 + targets/arm/mikroe/sam/src/i2c/CMakeLists.txt | 8 +- .../mikroe/sam/src/one_wire/CMakeLists.txt | 42 ++ .../implementation_1/hal_ll_one_wire.c | 208 ++++++++++ .../mikroe/sam/src/spi_master/CMakeLists.txt | 6 +- targets/arm/mikroe/sam/src/tim/CMakeLists.txt | 7 +- .../arm/mikroe/sam/src/uart/CMakeLists.txt | 7 +- 15 files changed, 1298 insertions(+), 15 deletions(-) create mode 100644 targets/arm/mikroe/sam/include/adc/hal_ll_adc.h create mode 100644 targets/arm/mikroe/sam/include/adc/hal_ll_adc_pin_map/implementations/implementation_1/hal_ll_adc_pin_map.h create mode 100644 targets/arm/mikroe/sam/include/one_wire/implementations/implementation_1/hal_ll_one_wire.h create mode 100644 targets/arm/mikroe/sam/src/adc/CMakeLists.txt create mode 100644 targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c create mode 100644 targets/arm/mikroe/sam/src/one_wire/CMakeLists.txt create mode 100644 targets/arm/mikroe/sam/src/one_wire/implementations/implementation_1/hal_ll_one_wire.c diff --git a/hal/interface/CMakeLists.txt b/hal/interface/CMakeLists.txt index 0f59e0b2d..6829f0b0c 100644 --- a/hal/interface/CMakeLists.txt +++ b/hal/interface/CMakeLists.txt @@ -14,7 +14,12 @@ else() set(chip_architecture "__implementation_error__") endif() +set(mcu_defs_path ${MCU_NAME}) + if(${MCU_NAME} MATCHES "(^STM32(.+)$)") + if(AI_GENERATED_SDK) + set(mcu_defs_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) + endif() set(vendor_id "stm32") elseif(${MCU_NAME} MATCHES "(^MK(.+)$)") set(vendor_id "nxp") @@ -27,6 +32,7 @@ elseif(${MCU_NAME} MATCHES "(^PIC18(.+)$)") elseif(${MCU_NAME} MATCHES "(^GD32VF(.+)$)") set(vendor_id "gigadevice") elseif(${MCU_NAME} MATCHES "^(AT)?SAM(.+)$") + set(mcu_defs_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) set(vendor_id "sam") elseif(${MCU_NAME} MATCHES "AT") set(vendor_id "avr") @@ -40,7 +46,7 @@ string(TOUPPER ${vendor_id} vendor_id_upper) target_include_directories(lib_hal_interface INTERFACE $ - $ + $ $ $ ) diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21B/LQFP144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21B/LQFP144/mcu_definitions.h index 6603608ec..95202c405 100644 --- a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21B/LQFP144/mcu_definitions.h +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21B/LQFP144/mcu_definitions.h @@ -48,6 +48,14 @@ extern "C"{ #endif +//ADC +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) +#define ADC_MODULE_2 (2) + +#define ADC_MODULE_COUNT (3) +//EOF ADC + //I2C #define I2C0_SDA_PA3_AFA #define I2C0_SCL_PA4_AFA diff --git a/targets/arm/mikroe/sam/CMakeLists.txt b/targets/arm/mikroe/sam/CMakeLists.txt index 8b2369fc9..e813459d0 100644 --- a/targets/arm/mikroe/sam/CMakeLists.txt +++ b/targets/arm/mikroe/sam/CMakeLists.txt @@ -8,7 +8,7 @@ set(module_list_supported "") set_module_support(module_list module_list_supported ${MCU_NAME} "hal_ll_layer") if (msdk_adc IN_LIST module_list_supported) - # add_subdirectory(src/adc) + add_subdirectory(src/adc) endif() if (msdk_gpio_in IN_LIST module_list_supported) add_subdirectory(src/gpio) @@ -26,7 +26,7 @@ if (msdk_uart IN_LIST module_list_supported) add_subdirectory(src/uart) endif() if (msdk_onewire IN_LIST module_list_supported) - # add_subdirectory(src/one_wire) + add_subdirectory(src/one_wire) endif() if (msdk_can IN_LIST module_list_supported) # add_subdirectory(src/can) diff --git a/targets/arm/mikroe/sam/include/adc/hal_ll_adc.h b/targets/arm/mikroe/sam/include/adc/hal_ll_adc.h new file mode 100644 index 000000000..28f63e282 --- /dev/null +++ b/targets/arm/mikroe/sam/include/adc/hal_ll_adc.h @@ -0,0 +1,227 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc.h + * @brief This file contains all the functions prototypes for the ADC library. + */ + +#ifndef _HAL_LL_ADC_H_ +#define _HAL_LL_ADC_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_target.h" +#include "hal_ll_pmc.h" + +#define HAL_ADC_6BIT_RES_VAL 0x003FU +#define HAL_ADC_8BIT_RES_VAL 0x00FFU +#define HAL_ADC_10BIT_RES_VAL 0x03FFU +#define HAL_ADC_12BIT_RES_VAL 0x0FFFU +#define HAL_ADC_14BIT_RES_VAL 0x3FFFU +#define HAL_ADC_16BIT_RES_VAL 0xFFFFU + +/** + * @brief ADC low level handle. + * + * The context for storing low level object handler. + * User is not to change these values or unexpected behaviour + * may occur. + */ +typedef struct +{ + handle_t *hal_ll_adc_handle; + handle_t *hal_drv_adc_handle; + bool init_ll_state; +} hal_ll_adc_handle_register_t; + +/** + * ADC VREF. + */ +typedef enum +{ + HAL_LL_ADC_VREF_EXTERNAL = 0, + HAL_LL_ADC_VREF_DEFAULT = HAL_LL_ADC_VREF_EXTERNAL +} hal_ll_adc_voltage_reference_t; + +/** + * ADC resolution. + */ +typedef enum +{ + HAL_LL_ADC_RESOLUTION_NOT_SET = 0, + HAL_LL_ADC_RESOLUTION_6_BIT, /**< 6 bit resolution */ + HAL_LL_ADC_RESOLUTION_8_BIT, /**< 8 bit resolution */ + HAL_LL_ADC_RESOLUTION_10_BIT, /**< 10 bit resolution */ + HAL_LL_ADC_RESOLUTION_12_BIT, /**< 12 bit resolution */ + HAL_LL_ADC_RESOLUTION_14_BIT, /**< 14 bit resolution */ + HAL_LL_ADC_RESOLUTION_16_BIT, /**< 16 bit resolution */ + + /*!< Default resolution. */ + HAL_LL_ADC_RESOLUTION_DEFAULT = HAL_LL_ADC_RESOLUTION_CMAKE +} hal_ll_adc_resolution_t; + +/** + * @brief ADC low level specific structure. + * + * User is not to change these values or unexpected behaviour + * may occur. + */ +typedef struct +{ + hal_ll_base_addr_t base; + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_adc_voltage_reference_t vref_input; + float vref_value; + uint32_t resolution; + uint8_t channel; +} hal_ll_adc_hw_specifics_map_t; + +/** + * @brief Configures specified module. + * + * Performs module configuration on the hardware + * level. + * + * @param[in] *handle HAL context object handle. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_module_configure_adc( handle_t *handle ); + +/** + * @brief Registers handler for future use. + * + * Registers low level and hal level handlers + * for use with appropriate functions. + * + * @param[in] *handle HAL context object handle. + * @param[in] pin Analog input pin. + * @param[in] vref_input Voltage reference source. + * @param[in] resolution Analog data resolution. + * @param[in] *handle_map HAL layer local handle map. + * @param[in] *hal_module_id HAL layer module number. + + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_adc_register_handle(hal_ll_pin_name_t pin, hal_ll_adc_voltage_reference_t vref_input, hal_ll_adc_resolution_t resolution, hal_ll_adc_handle_register_t *handle_map, uint8_t *hal_module_id); + +/** + * @brief Sets ADC resolution. + * + * Sets specified ADC resolution for module. + * Take into consideration that the module + * will be re-initialized on the hardware level. + * + * @param[in] *handle HAL context object handle. + * @param[in] resolution ADC resolution. + * + * @return hal_ll_err_t Module specific error or success. + */ +hal_ll_err_t hal_ll_adc_set_resolution(handle_t *handle, hal_ll_adc_resolution_t resolution); + +/** + * @brief Sets ADC reference voltage source. + * + * Sets ADC reference voltage source for specified + * object. Take into consideration that the module + * will be re-initialized on the hardware level. + * + * @param[in] *handle HAL context object handle. + * @param[in] vref_input ADC reference voltage source. + * + * @return hal_ll_err_t Module specific error or success. + */ +hal_ll_err_t hal_ll_adc_set_vref_input(handle_t *handle, hal_ll_adc_voltage_reference_t vref_input); + +/** + * @brief Sets ADC reference voltage value. + * + * Sets ADC reference voltage value for specified + * object. + * + * @param[in] *handle HAL context object handle. + * @param[in] vref_input ADC reference voltage value. + * + * @return void None. + */ +void hal_ll_adc_set_vref_value(handle_t *handle, float vref_value); + +/** + * @brief Executes data read via ADC module. + * + * Function shall read raw unsigned analog value. + * + * @param handle ADC handle. + * @param *readDatabuf Data buffer where read data + * shall be placed. + * + * @return hal_ll_err_t Module specific error. + * + * Returns one of pre-defined error values. + * Take into consideration that this is hardware specific. + */ +hal_ll_err_t hal_ll_adc_read(handle_t *handle, uint16_t *readDatabuf ); + +/** + * @brief Closes ADC HAL and HAL_LOW_LEVEL context object. + * + * De-allocates hardware resources for specific driver object and + * de-initializes the module on a hardware level. + * + * @param[in] *handle HAL context object handle. + * + * @return void None. + */ +void hal_ll_adc_close( handle_t *handle ); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_ADC_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/sam/include/adc/hal_ll_adc_pin_map/implementations/implementation_1/hal_ll_adc_pin_map.h b/targets/arm/mikroe/sam/include/adc/hal_ll_adc_pin_map/implementations/implementation_1/hal_ll_adc_pin_map.h new file mode 100644 index 000000000..cefec80bc --- /dev/null +++ b/targets/arm/mikroe/sam/include/adc/hal_ll_adc_pin_map/implementations/implementation_1/hal_ll_adc_pin_map.h @@ -0,0 +1,128 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc_pin_map.h + * @brief Header file containing symbolic pin name definitions. + */ + +#ifndef _HAL_LL_ADC_PIN_MAP_H_ +#define _HAL_LL_ADC_PIN_MAP_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_pin_names.h" + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +/** + * ADC channels. + */ +typedef enum +{ + HAL_LL_ADC_CHANNEL_0 = 0, + HAL_LL_ADC_CHANNEL_1, + HAL_LL_ADC_CHANNEL_2, + HAL_LL_ADC_CHANNEL_3, + HAL_LL_ADC_CHANNEL_4, + HAL_LL_ADC_CHANNEL_5, + HAL_LL_ADC_CHANNEL_6, + HAL_LL_ADC_CHANNEL_7, + HAL_LL_ADC_CHANNEL_8, + HAL_LL_ADC_CHANNEL_9, + HAL_LL_ADC_CHANNEL_10, + HAL_LL_ADC_CHANNEL_11, + HAL_LL_ADC_CHANNEL_12, + HAL_LL_ADC_CHANNEL_13, + HAL_LL_ADC_CHANNEL_14, + HAL_LL_ADC_CHANNEL_15, + HAL_LL_ADC_CHANNEL_16, + HAL_LL_ADC_CHANNEL_17, + HAL_LL_ADC_CHANNEL_18, + HAL_LL_ADC_CHANNEL_19, + HAL_LL_ADC_CHANNEL_20, + HAL_LL_ADC_CHANNEL_21, + HAL_LL_ADC_CHANNEL_22, + HAL_LL_ADC_CHANNEL_23, + HAL_LL_ADC_CHANNEL_24, + HAL_LL_ADC_CHANNEL_25, + HAL_LL_ADC_CHANNEL_26, + HAL_LL_ADC_CHANNEL_27, + HAL_LL_ADC_CHANNEL_28, + HAL_LL_ADC_CHANNEL_29, + HAL_LL_ADC_CHANNEL_30, + HAL_LL_ADC_CHANNEL_31, + + HAL_LL_ADC_CHANNEL_NC = 0xFFFF +} hal_ll_adc_channel_t; + +/*!< @brief ADC pin structure. */ +typedef struct +{ + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + hal_ll_pin_name_t module_index; + hal_ll_adc_channel_t channel; +} hal_ll_adc_pin_map_t; + +/*!< ADC module base addresses. */ +#ifdef ADC_MODULE_1 +static const hal_ll_base_addr_t ADC1_BASE_ADDR = 0x40012000; +#endif +#ifdef ADC_MODULE_2 +static const hal_ll_base_addr_t ADC2_BASE_ADDR = 0x40012100; +#endif +#ifdef ADC_MODULE_3 +static const hal_ll_base_addr_t ADC3_BASE_ADDR = 0x40012200; +#endif + +/*!< ADC input pins. */ +static const hal_ll_adc_pin_map_t _adc_map[] = +{ + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_CHANNEL_ERROR} +}; + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_ADC_PIN_MAP_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/sam/include/one_wire/implementations/implementation_1/hal_ll_one_wire.h b/targets/arm/mikroe/sam/include/one_wire/implementations/implementation_1/hal_ll_one_wire.h new file mode 100644 index 000000000..dd63b77e7 --- /dev/null +++ b/targets/arm/mikroe/sam/include/one_wire/implementations/implementation_1/hal_ll_one_wire.h @@ -0,0 +1,232 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_one_wire.h + * @brief API for One Wire HAL LOW LEVEL layer. + */ + +#ifndef _HAL_LL_ONE_WIRE_H_ +#define _HAL_LL_ONE_WIRE_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +#include "hal_ll_gpio.h" + +/** + * @brief Structure for storing One Wire device address. + * @details Unique One Wire address used for device addressing. + */ +typedef struct { + uint8_t address[8]; /*!< One Wire address buffer. */ +} hal_ll_one_wire_rom_address_t; + +/** + * @brief One Wire HAL Low Level context structure. + * @details The context structure for storing driver internal state. The contents of the + * context structure are used by the module and must not be altered. Reading or + * writing data directly from a control structure by user should be avoided. + */ +typedef struct { + hal_ll_pin_name_t data_pin; // One Wire data pin. + volatile uint32_t moder; // Register for altering GPIO pin direction. + volatile uint32_t moder_set; // Variable for configuring pin as General purpose output. + volatile uint32_t moder_clear; // Variable for configuring pin as General purpose input (reset state). + volatile uint32_t bsrr; // Register for GPIO port bit set/reset. + volatile uint32_t idr; // Register for reading current GPIO pin state. +} hal_ll_one_wire_local_t; + +/** + * @brief One Wire HAL Low Level initialization configuration structure. + * + * @details + * - data_pin value - to be configured as desired. + * - state value - NOTE must not be altered (it is supposed to be set automatically in Low Level Layer). + */ +typedef struct { + hal_ll_pin_name_t data_pin; /*!< One Wire pin - user is to configure it as desired. */ + bool state; /*!< State of a pin. NOTE must not be altered. */ +} hal_ll_one_wire_t; + +/** + * @details Enum containing predefined module return values. + */ +typedef enum { + HAL_LL_ONE_WIRE_SUCCESS = 0, /*!< Success. */ + HAL_LL_ONE_WIRE_ERROR = (-1) /*!< Error. */ +} hal_ll_one_wire_err_t; + +/** + * @brief Opens One Wire HAL Low Level object. + * @details Opens One Wire HAL Low Level object on selected pin. + * Enables appropriate PORT clock, configures pin to have digital output functionality, + * makes sure that HIGH voltage state is applied on pin before any One Wire actions. + * @param[in,out] *obj One Wire HAL Low Level object. + * See #hal_ll_one_wire_t structure definition for detailed explanation. + * @return None. + * @pre Make sure that \p LowLevel structure has been adequately + * populated beforehand. + * @note It is recommended to check return value for error. + */ +void hal_ll_one_wire_open( hal_ll_one_wire_t *obj ); + +/** + * @brief Reset One Wire bus. + * @details Host shall send reset sequence and devices shall go into reset state. + * @param[in,out] *handle One Wire HAL Low Level object. + * See #hal_one_wire_t structure definition for detailed explanation. + * @return The function can return one of the values defined by + * #hal_ll_one_wire_err_t, which is size dependant on the architecture. + * @pre Before calling this function, + * the user is expected to call #hal_ll_one_wire_open function. + */ +hal_ll_err_t hal_ll_one_wire_reset( hal_ll_one_wire_t *obj ); + +/** + * @brief Reads device's ROM information. + * @details Allows the host to read eight-bit family code, + * 48-bit serial number, and eight-bit CRC. + * + * @important THIS FUNCTION IS TO BE ISSUED ONLY IF WE ARE DEALING WITH + * ONE DEVICE ONLY. THIS FUNCTION AUTOMATICALLY RESETS ONE WIRE BUS. + * @param[in] *obj One Wire HAL Low Level object. + * See #hal_one_wire_t structure definition for detailed explanation. + * @param[out] *device_rom_address Buffer for One Wire device ROM information. + * @return The function can return one of the values defined by + * #hal_ll_one_wire_err_t, which is size dependant on the architecture. + */ +hal_ll_err_t hal_ll_one_wire_read_rom( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *device_rom_address ); + +/** + * @brief Access device's level functions without transmitting ROM information. + * @details Allows the host to access device functions without + * providing the 64-bit ROM identification number. + * + * @important THIS FUNCTION IS TO BE ISSUED ONLY IF WE ARE DEALING WITH + * ONE DEVICE ONLY. THIS FUNCTION AUTOMATICALLY RESETS ONE WIRE BUS. + * @param[in] *obj One Wire HAL Low Level object. + * See #hal_one_wire_t structure definition for detailed explanation. + * @return The function can return one of the values defined by + * #hal_ll_one_wire_err_t, which is size dependant on the architecture. + */ +hal_ll_err_t hal_ll_one_wire_skip_rom( hal_ll_one_wire_t *obj ); + +/** + * @brief Selects a specific One Wire capable device on bus. + * @details Select a One Wire device with specific ID. + * + * @param[in] *obj One Wire HAL Low Level object. + * See #hal_ll_one_wire_t structure definition for detailed explanation. + * @param[in] device_rom_address Buffer for One Wire device ROM information. + * @return The function can return one of the values defined by + * #hal_ll_one_wire_err_t, which is size dependant on the architecture. + * @pre Before calling this function, + * the user is expected to call #hal_one_wire_open function. + */ +hal_ll_err_t hal_ll_one_wire_match_rom( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *device_rom_address ); + +/** + * @brief Search One Wire capable device on bus. + * @details Search and list 1st device that is One Wire capable. + * + * @param[in] *obj One Wire HAL Low Level object. + * See #hal_ll_one_wire_t structure definition for detailed explanation. + * @param[out] *one_wire_device_list Buffer for One Wire device ROM information. + * @return The function can return one of the values defined by + * #hal_ll_one_wire_err_t, which is size dependant on the architecture. + * @pre Before calling this function, + * the user is expected to call #hal_ll_one_wire_open function. + */ +hal_ll_err_t hal_ll_one_wire_search_first_device( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ); + +/** + * @brief Search One Wire capable devices on bus. + * @details Search devices that is One Wire capable. + * + * @param[in] *obj One Wire HAL Low Level object. + * See #hal_ll_one_wire_t structure definition for detailed explanation. + * @param[out] *one_wire_device_list Buffer for One Wire device ROM information. + * @return The function can return one of the values defined by + * #hal_ll_one_wire_err_t, which is size dependant on the architecture. + * @pre Before calling this function, + * the user is expected to call #hal_ll_one_wire_open function. + */ +hal_ll_err_t hal_ll_one_wire_search_next_device( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ); + +/** + * @brief Writes byte to One Wire bus. + * @details Writes byte to One Wire bus. + * @param[in] *write_data_buffer Data transmit buffer. + * @param[in] write_data_length Number of bytes to write from data transmit buffer. + * @return None. + * @pre Before calling this function, + * the user is expected to call #hal_ll_one_wire_open function. + */ +void hal_ll_one_wire_write_byte( uint8_t *write_data_buffer, size_t write_data_length ); + +/** + * @brief Reads byte from One Wire bus. + * @details Reads byte from One Wire bus. + * @param[out] *read_data_buffer Data receive buffer. + * @param[in] read_data_length Number of bytes to be read. + * @return None. + * @pre Before calling this function, + * the user is expected to call #hal_ll_one_wire_open function. + */ +void hal_ll_one_wire_read_byte( uint8_t *read_data_buffer, size_t read_data_length ); + +/** + * @brief Reconfigures One Wire pin settings. + * @details Enables appropriate PORT clock, configures pin to have digital output functionality, + * makes sure that HIGH voltage state is applied on pin before any One Wire actions. + * @param[in] *obj One Wire HAL Low Level object. + * See #hal_ll_one_wire_t structure definition for detailed explanation. + * @return None. + * @pre Before calling this function, + * the user is expected to call #hal_one_wire_open function. + */ +void hal_ll_one_wire_reconfigure( hal_ll_one_wire_t *obj ); + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_ONE_WIRE_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/sam/src/adc/CMakeLists.txt b/targets/arm/mikroe/sam/src/adc/CMakeLists.txt new file mode 100644 index 000000000..a8e1aaf8d --- /dev/null +++ b/targets/arm/mikroe/sam/src/adc/CMakeLists.txt @@ -0,0 +1,60 @@ +## ./targets/arm/mikroe/sam/src/adc/CMakeLists.txt +set(hal_ll_def_list "") +set(mcu_header_path "") + +find_cortex(hal_ll_def_list) + +list(APPEND hal_ll_def_list ${MCU_NAME}) +list(APPEND hal_ll_def_list "MACRO_USAGE_ADC") +set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) + +##BEGIN ADC +list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_12_BIT") + +if (${MCU_NAME} MATCHES "^ATSAME7.+") + set(adc_subimplementation "implementations/implementation_1") +endif() +##END ADC + +mikrosdk_add_library(lib_hal_ll_adc MikroSDK.HalLowLevel.ADC + ${adc_subimplementation}/hal_ll_adc.c + ../../include/hal_ll_pmc.h + ../../include/hal_ll_target.h + #BEGIN ADC + ../../include/adc/hal_ll_adc.h + ../../include/adc/hal_ll_adc_pin_map/${adc_subimplementation}/hal_ll_adc_pin_map.h + #END ADC +) + +target_compile_definitions(lib_hal_ll_adc PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_adc PUBLIC + MikroC.Core + MikroSDK.HalLowLevelCore + MikroSDK.HalLowLevelCommon +) +string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) +target_include_directories(lib_hal_ll_adc + PRIVATE + ../../include + ../../include/gpio + ../../include/gpio/${adc_subimplementation} + #BEGIN ADC + ../../include/adc + ../../include/adc/hal_ll_adc_pin_map/${adc_subimplementation} + #END ADC + INTERFACE + $ + $ + $ + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.ADC) + +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.ADC ../../include/adc/hal_ll_adc.h) diff --git a/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c b/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c new file mode 100644 index 000000000..f87e75796 --- /dev/null +++ b/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c @@ -0,0 +1,367 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_adc.c + * @brief Low level HAL ADC source file. + */ + +#include "hal_ll_adc.h" +#include "hal_ll_gpio.h" +#include "hal_ll_adc_pin_map.h" +#include "delays.h" + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro for getting hal_ll_module_state address */ +#define hal_ll_adc_get_module_state_address ((hal_ll_adc_handle_register_t *)*handle) +/*!< @brief Helper macro for getting module specific control register structure base address // first register address */ +#define hal_ll_adc_get_handle (hal_ll_adc_handle_register_t *)hal_ll_adc_get_module_state_address->hal_ll_adc_handle +/*!< @brief Helper macro for getting module specific control register structure */ +#define hal_ll_adc_get_base_struct(_handle) ((hal_ll_adc_base_handle_t *)_handle) +/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ +#define hal_ll_adc_get_base_from_hal_handle ((hal_ll_adc_hw_specifics_map_t *)((hal_ll_adc_handle_register_t *)\ + (((hal_ll_adc_handle_register_t *)(handle))->hal_ll_adc_handle))->hal_ll_adc_handle)->base + +/*!< @brief Helper macro for getting adequate module index number */ +#define hal_ll_adc_module_num(_module_num) (_module_num - 1) + +#define HAL_LL_ADC_CCR_OFFSET 0x304 + +#define HAL_LL_ADC_ADON_BIT 0 +#define HAL_LL_ADC_SR_EOC_BIT 1 +#define HAL_LL_ADC_CONT_BIT 1 +#define HAL_LL_ADC_SCAN_BIT 8 +#define HAL_LL_ADC_ALIGN_BIT 11 +#define HAL_LL_ADC_RESOLUTION_BIT0 24 +#define HAL_LL_ADC_RESOLUTION_BIT1 25 +#define HAL_LL_ADC_SWSTART_BIT 30 + +#define HAL_LL_ADC1_ENABLE_CLOCK 8 +#define HAL_LL_ADC2_ENABLE_CLOCK 9 +#define HAL_LL_ADC3_ENABLE_CLOCK 10 + +#define HAL_LL_ADC_CONT 0x2ul +#define HAL_LL_ADC_SCAN 0x100ul +#define HAL_LL_ADC_ALIGN 0x800ul +#define HAL_LL_ADC_JEXTSEL 0xE0000ul + +#define HAL_LL_ADC_16MHZ 16000000ul +#define HAL_LL_ADC_60MHZ 60000000ul +#define HAL_LL_ADC_72MHZ 72000000ul +#define HAL_LL_ADC_120MHZ 120000000ul +#define HAL_LL_ADC_144MHZ 144000000ul +#define HAL_LL_ADC_180MHZ 180000000ul + +#define HAL_LL_ADC_PRESCALER_2 0x00000000ul +#define HAL_LL_ADC_PRESCALER_4 0x00010000ul +#define HAL_LL_ADC_PRESCALER_6 0x00020000ul +#define HAL_LL_ADC_PRESCALER_8 0x00030000ul + +#define HAL_LL_ADC_PRESCALER_MASK 0x00F00000ul +#define HAL_LL_ADC_SEQUENCE_LENGTH_MASK 0x00F00000ul +#define HAL_LL_ADC_CONVERSION_ONE 0x0000001Ful + +#define HAL_LL_ADC_12BIT_RES 0x00000000ul +#define HAL_LL_ADC_10BIT_RES 0x01000000ul +#define HAL_LL_ADC_8BIT_RES 0x02000000ul +#define HAL_LL_ADC_6BIT_RES 0x03000000ul + +#define HAL_LL_RESOLUTION_MASK 0xFCFFFFFFul + +#define HAL_LL_MODULE_INDEX_ERROR 0xFFFFFFFFul + +// -------------------------------------------------------------- PRIVATE TYPES +/*!< @brief Local handle list */ +static hal_ll_adc_handle_register_t hal_ll_module_state[ADC_MODULE_COUNT] = { (handle_t *) NULL, (handle_t *) NULL, false }; + +/** + * ADC modules + */ +typedef enum +{ + HAL_LL_MODULE_ADC_DEFAULT = 0xFF, + #if defined(ADC_MODULE) + HAL_LL_MODULE_ADC_1 = 1, + #elif defined(ADC_MODULE_1) + HAL_LL_MODULE_ADC_1 = 1, + #endif + #if defined(ADC_MODULE_2) + HAL_LL_MODULE_ADC_2 = 2, + #endif + #if defined(ADC_MODULE_3) + HAL_LL_MODULE_ADC_3 = 3, + #endif + #if defined(ADC_MODULE_4) + HAL_LL_MODULE_ADC_4 = 4, + #endif + HAL_LL_MODULE_ADC_NONE +} hal_ll_adc_module_number_t; + +/** + * Return values + */ +typedef enum +{ + HAL_LL_ADC_SUCCESS = 0, + HAL_LL_ADC_WRONG_PIN, + + HAL_LL_ADC_UNSUPPORTED_RESOLUTION = 1100, + HAL_LL_ADC_UNSUPPORTED_VREF, + HAL_LL_ADC_WRONG_CHANNEL, + HAL_LL_ADC_ERROR = (-1) +} hal_ll_adc_err_t; + +/*!< @brief ADC register structure. */ +typedef struct +{ + uint32_t sr; /* Address offset 0x00 */ + uint32_t cr1; /* Address offset 0x04 */ + uint32_t cr2; /* Address offset 0x08 */ + uint32_t smpr1; /* Address offset 0x0C */ + uint32_t smpr2; /* Address offset 0x10 */ + uint32_t jofr1; /* Address offset 0x14 */ + uint32_t jofr2; /* Address offset 0x18 */ + uint32_t jofr3; /* Address offset 0x1C */ + uint32_t jofr4; /* Address offset 0x20 */ + uint32_t htr; /* Address offset 0x24 */ + uint32_t ltr; /* Address offset 0x28 */ + uint32_t sqr1; /* Address offset 0x2C */ + uint32_t sqr2; /* Address offset 0x30 */ + uint32_t sqr3; /* Address offset 0x34 */ + uint32_t jsqr; /* Address offset 0x38 */ + uint32_t jdr1; /* Address offset 0x3C */ + uint32_t jdr2; /* Address offset 0x40 */ + uint32_t jdr3; /* Address offset 0x44 */ + uint32_t jdr4; /* Address offset 0x48 */ + uint32_t dr; /* Address offset 0x4C */ +} hal_ll_adc_base_handle_t; + +/*!< @brief ADC hw specific module values */ +typedef struct +{ + uint16_t pin_an[ADC_MODULE_COUNT]; +} hal_ll_adc_pin_id; + +static hal_ll_adc_hw_specifics_map_t hal_ll_adc_hw_specifics_map[] = +{ + #ifdef ADC_MODULE_1 + {ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + #ifdef ADC_MODULE_2 + {ADC2_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + #ifdef ADC_MODULE_3 + {ADC3_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + + {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF} +}; + +// ------------------------------------------------------------------ VARIABLES + +/*!< @brief Global handle variables used in functions */ +static volatile hal_ll_adc_handle_register_t *low_level_handle; +static volatile hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local; + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Enable ADC module 1 clock. + * @param none + * @return none + */ +static inline void adc1_enable_clock(); + +/** + * @brief Enable ADC module 2 clock. + * @param none + * @return none + */ +static inline void adc2_enable_clock(); + +/** + * @brief Enable ADC module 3 clock. + * @param none + * @return none + */ +static inline void adc3_enable_clock(); + +/** + * @brief Initialize ADC module. + * @param *map - ADC module local map. + * @return None + */ +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ); + +/** + * @brief Check if pins are adequate. + * + * Checks analog pin the user has passed with pre-defined + * pins in ADC pin map. + * + * @param[in] pin - ADC pre-defined pin name. + * @param[in] *index - ADC map index value. + * @return hal_ll_pin_name_t Module index based on pin. + * + * Returns pre-defined module index from pin maps, if pin + * is adequate. + */ +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ); + +/** + * @brief Maps new-found module specific values. + * + * Maps pin name and channel. + * + * @param[in] module_index ADC HW module index -- 0,1,2... + * @param[in] *index Pointer with ADC pin map index value + * + * @return None + */ +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ); + +/** + * @brief Get local hardware specific map. + * + * Checks handle value and returns address of adequate + * hal_ll_adc_hw_specifics_map array index. + * + * @param[in] handle - Object specific context handler. + * @return hal_ll_adc_hw_specifics_map_t Map address. + * + * Returns pre-defined map index address based on handle value, + * if handle is adequate. + */ +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); + +/** + * @brief Enable ADC module gate clock. + * @param *base - ADC module base address. + * @return None + */ +static void _hal_ll_adc_enable_clock( uint8_t base ); + +/** + * @brief Initialize ADC module. + * @param *base - ADC module base address. + * @param resolution - ADC module resolution. + * @return None + */ +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +hal_ll_err_t hal_ll_adc_register_handle(hal_ll_pin_name_t pin, hal_ll_adc_voltage_reference_t vref_input, hal_ll_adc_resolution_t resolution, hal_ll_adc_handle_register_t *handle_map, uint8_t *hal_module_id) +{ + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_module_configure_adc( handle_t *handle ) +{ + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_resolution(handle_t *handle, hal_ll_adc_resolution_t resolution) +{ + return HAL_LL_ADC_SUCCESS; +} + +hal_ll_err_t hal_ll_adc_set_vref_input(handle_t *handle, hal_ll_adc_voltage_reference_t vref_input) +{ + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_set_vref_value(handle_t *handle, float vref_value) +{ + +} + +hal_ll_err_t hal_ll_adc_read( handle_t *handle, uint16_t *readDatabuf ) +{ + return HAL_LL_ADC_SUCCESS; +} + +void hal_ll_adc_close( handle_t *handle ) +{ + +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS +static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ) +{ + return HAL_LL_PIN_NC; +} + +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ) +{ + +} + +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) +{ + +} + +static inline void adc1_enable_clock() +{ + +} + +static inline void adc2_enable_clock() +{ + +} + +static inline void adc3_enable_clock() +{ + +} + +static void _hal_ll_adc_enable_clock( uint8_t base ) +{ + +} + +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ) +{ + +} + +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ) +{ + +} +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt b/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt index 982cb213e..723c95109 100644 --- a/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt @@ -39,6 +39,7 @@ target_link_libraries(lib_hal_ll_gpio PUBLIC MikroSDK.HalLowLevelCore MikroSDK.HalLowLevelCommon ) + string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) target_include_directories(lib_hal_ll_gpio PRIVATE diff --git a/targets/arm/mikroe/sam/src/i2c/CMakeLists.txt b/targets/arm/mikroe/sam/src/i2c/CMakeLists.txt index 4a2036319..5226a7c36 100644 --- a/targets/arm/mikroe/sam/src/i2c/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/i2c/CMakeLists.txt @@ -5,11 +5,8 @@ set(mcu_header_path "") find_cortex(hal_ll_def_list) list(APPEND hal_ll_def_list ${MCU_NAME}) -list(APPEND hal_ll_def_list "MACRO_USAGE_GPIO") -set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) - -## BEGIN I2C list(APPEND hal_ll_def_list "MACRO_USAGE_I2C") +set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) if(${MCU_NAME} MATCHES "^ATSAME7.+") set(i2c_subimplementation "implementations/implementation_1") @@ -45,11 +42,13 @@ target_link_libraries(lib_hal_ll_i2c_master PUBLIC MikroSDK.HalLowLevelCore MikroSDK.HalLowLevelCommon ) + string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) target_include_directories(lib_hal_ll_i2c_master PRIVATE ../../include ../../include/gpio + ../../include/gpio/${i2c_subimplementation} # BEGIN I2C ../../include/i2c ../../include/i2c/hal_ll_i2c_pin_map/${i2c_subimplementation} @@ -58,6 +57,7 @@ target_include_directories(lib_hal_ll_i2c_master INTERFACE $ $ + $ $ $ $ diff --git a/targets/arm/mikroe/sam/src/one_wire/CMakeLists.txt b/targets/arm/mikroe/sam/src/one_wire/CMakeLists.txt new file mode 100644 index 000000000..dc0e4fded --- /dev/null +++ b/targets/arm/mikroe/sam/src/one_wire/CMakeLists.txt @@ -0,0 +1,42 @@ +## ./targets/arm/mikroe/sam/src/one_wire/CMakeLists.txt +set(hal_ll_def_list) +set(mcu_header_path "") + +list(APPEND hal_ll_def_list ${MCU_NAME}) +list(APPEND hal_ll_def_list "MACRO_USAGE_ONE_WIRE") +set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) + +if(${MCU_NAME} MATCHES "^ATSAME7.+") + set(ow_subimplementation "implementations/implementation_1") +endif() + +mikrosdk_add_library(lib_hal_ll_one_wire MikroSDK.HalLowLevel.OneWire + ${ow_subimplementation}/hal_ll_one_wire.c + + ../../include/one_wire/${ow_subimplementation}/hal_ll_one_wire.h +) + +target_compile_definitions(lib_hal_ll_one_wire PUBLIC + ${hal_ll_def_list} +) + +target_link_libraries(lib_hal_ll_one_wire PUBLIC + MikroC.Core + MikroSDK.HalLowLevel.GPIO + MikroSDK.HalLowLevelCommon +) +target_include_directories(lib_hal_ll_one_wire + PRIVATE + ../../include/gpio + ../../include/gpio/${ow_subimplementation} + ../../include/one_wire/${ow_subimplementation} + INTERFACE + $ + $ + $ + $ + $ +) + +mikrosdk_install(MikroSDK.HalLowLevel.OneWire) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.OneWire ../../include/one_wire/${ow_subimplementation}/hal_ll_one_wire.h) diff --git a/targets/arm/mikroe/sam/src/one_wire/implementations/implementation_1/hal_ll_one_wire.c b/targets/arm/mikroe/sam/src/one_wire/implementations/implementation_1/hal_ll_one_wire.c new file mode 100644 index 000000000..1710a5f8f --- /dev/null +++ b/targets/arm/mikroe/sam/src/one_wire/implementations/implementation_1/hal_ll_one_wire.c @@ -0,0 +1,208 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_one_wire.c + * @brief One Wire HAL LOW LEVEL layer implementation. + */ +#include "hal_ll_one_wire.h" +#include "delays.h" + +// ------------------------------------------------------------- PRIVATE MACROS +/*!< @brief Helper macro getting minimum bits per transfer. */ +#define HAL_LL_ONE_WIRE_MINIMUM_BITS_PER_TRANSFER (8) + +/*!< @brief Helper macro for reset pins offset. */ +#define RESET_PINS_OFFSET (16) + +// ------------------------------------------------------------------ VARIABLES +/*!< @brief Helper macro for starting to enumerate device ID(s). */ +static uint8_t hal_ll_one_wire_search_rom_command = ONE_WIRE_CMD_ROM_SEARCH; + +/*!< @brief Helper macro for reading a device ID. */ +static uint8_t hal_ll_one_wire_read_rom_command_legacy = ONE_WIRE_CMD_ROM_READ_LEGACY; +static uint8_t hal_ll_one_wire_read_rom_command = ONE_WIRE_CMD_ROM_READ; + +/*!< @brief Helper macro for ignoring a device ID. */ +static uint8_t hal_ll_one_wire_skip_rom_command = ONE_WIRE_CMD_ROM_SKIP; + +/*!< @brief Helper macro for selecting a device with specific ID. */ +static uint8_t hal_ll_one_wire_match_rom_command = ONE_WIRE_CMD_ROM_MATCH; + +/*!< @brief Helper flag if One Wire device is the last one left on the bus. */ +static uint8_t last_device_flag = 0; + +/*!< @brief Helper flag for last discrepancy. */ +static uint8_t last_discrepancy = 0; + +/*!< @brief Helper flag for last family discrepancy. */ +static uint8_t last_family_discrepancy = 0; + +/*!< @brief Helper instance consisting of hardware specifics. */ +static hal_ll_one_wire_local_t one_wire_handle; + +__weak void one_wire_timing_value_a( void ) { + Delay_5us(); +} + +__weak void one_wire_timing_value_b( void ) { + Delay_64us(); +} + +__weak void one_wire_timing_value_c( void ) { + Delay_60us(); +} + +__weak void one_wire_timing_value_d( void ) { + Delay_6us(); +} + +__weak void one_wire_timing_value_e( void ) { + Delay_6us(); +} + +__weak void one_wire_timing_value_f( void ) { + Delay_50us(); +} + +__weak void one_wire_timing_value_h( void ) { + Delay_480us(); +} + +__weak void one_wire_timing_value_i( void ) { + Delay_70us(); +} + +__weak void one_wire_timing_value_j( void ) { + Delay_410us(); +} + +// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS +/** + * @brief Writes bit to One Wire bus. + * @details Writes bit to One Wire bus. + * @param[in] write_data_buffer Data transmit buffer. + */ +static void hal_ll_one_wire_write_bit( uint8_t write_data_buffer ); + +/** + * @brief Reads bit from One Wire bus. + * @details Reads bit from One Wire bus. + * @param[in] write_data_buffer Data receive buffer. + */ +static void hal_ll_one_wire_read_bit( uint8_t *read_data_buffer ); + +/** + * @brief Search One Wire capable device on bus. + * @details Search One Wire capable device on bus. + * + * @param[in] *obj One Wire HAL Low Level object. + * See #hal_ll_one_wire_t structure definition for detailed explanation. + * @param[out] *one_wire_device_list Buffer for One Wire device ROM information. + */ +static hal_ll_err_t hal_ll_one_wire_search( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ); + +// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS +void hal_ll_one_wire_open( hal_ll_one_wire_t *obj ) +{ + +} + +hal_ll_err_t hal_ll_one_wire_reset( hal_ll_one_wire_t *obj ) +{ + +} + +hal_ll_err_t hal_ll_one_wire_read_rom( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *device_rom_address ) +{ + return HAL_LL_ONE_WIRE_SUCCESS; +} + +hal_ll_err_t hal_ll_one_wire_skip_rom( hal_ll_one_wire_t *obj ) +{ + return HAL_LL_ONE_WIRE_SUCCESS; +} + +hal_ll_err_t hal_ll_one_wire_match_rom( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *device_rom_address ) +{ + return HAL_LL_ONE_WIRE_SUCCESS; +} + +hal_ll_err_t hal_ll_one_wire_search_first_device( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ) +{ + return HAL_LL_ONE_WIRE_SUCCESS; +} + +hal_ll_err_t hal_ll_one_wire_search_next_device( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ) +{ + return HAL_LL_ONE_WIRE_SUCCESS; +} + +static hal_ll_err_t hal_ll_one_wire_search( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ) +{ + +} + +void hal_ll_one_wire_write_byte( uint8_t *write_data_buffer, size_t write_data_length ) +{ + +} + +void hal_ll_one_wire_read_byte( uint8_t *read_data_buffer, size_t read_data_length ) +{ + +} + +void hal_ll_one_wire_reconfigure( hal_ll_one_wire_t *obj ) +{ + +} + +// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS + +static void hal_ll_one_wire_write_bit( uint8_t write_data_buffer ) +{ + +} + +static void hal_ll_one_wire_read_bit( uint8_t *read_data_buffer ) +{ + +} + +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/sam/src/spi_master/CMakeLists.txt b/targets/arm/mikroe/sam/src/spi_master/CMakeLists.txt index 424dd9c9c..68960db35 100644 --- a/targets/arm/mikroe/sam/src/spi_master/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/spi_master/CMakeLists.txt @@ -5,13 +5,12 @@ set(mcu_header_path "") find_cortex(hal_ll_def_list) list(APPEND hal_ll_def_list ${MCU_NAME}) -list(APPEND hal_ll_def_list "MACRO_USAGE_GPIO") +list(APPEND hal_ll_def_list "MACRO_USAGE_SPI") set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) if (${MCU_NAME} MATCHES "^ATSAME7.+") set(spi_subimplementation "implementations/implementation_1") endif() -list(APPEND hal_ll_def_list "MACRO_USAGE_SPI") mikrosdk_add_library(lib_hal_ll_spi_master MikroSDK.HalLowLevel.SPI.Master ${spi_subimplementation}/hal_ll_spi_master.c @@ -33,11 +32,13 @@ target_link_libraries(lib_hal_ll_spi_master PUBLIC MikroSDK.HalLowLevelCore MikroSDK.HalLowLevelCommon ) + string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) target_include_directories(lib_hal_ll_spi_master PRIVATE ../../include ../../include/gpio + ../../include/gpio/${spi_subimplementation} # BEGIN SPI ../../include/spi_master ../../include/spi_master/hal_ll_spi_master_pin_map/${spi_subimplementation} @@ -46,6 +47,7 @@ target_include_directories(lib_hal_ll_spi_master INTERFACE $ $ + $ $ $ $ diff --git a/targets/arm/mikroe/sam/src/tim/CMakeLists.txt b/targets/arm/mikroe/sam/src/tim/CMakeLists.txt index 7fbe27141..88d04ec99 100644 --- a/targets/arm/mikroe/sam/src/tim/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/tim/CMakeLists.txt @@ -5,7 +5,7 @@ set(mcu_header_path "") find_cortex(hal_ll_def_list) list(APPEND hal_ll_def_list ${MCU_NAME}) -list(APPEND hal_ll_def_list "MACRO_USAGE_GPIO") +list(APPEND hal_ll_def_list "MACRO_USAGE_TIM") set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) ## BEGIN TIM @@ -14,8 +14,6 @@ if (${MCU_NAME} MATCHES "^ATSAME7.+") endif() ## END TIM -list(APPEND hal_ll_def_list "MACRO_USAGE_TIM") - mikrosdk_add_library(lib_hal_ll_tim MikroSDK.HalLowLevel.TIM ${tim_subimplementation}/hal_ll_tim.c @@ -36,11 +34,13 @@ target_link_libraries(lib_hal_ll_tim PUBLIC MikroSDK.HalLowLevelCore MikroSDK.HalLowLevelCommon ) + string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) target_include_directories(lib_hal_ll_tim PRIVATE ../../include ../../include/gpio + ../../include/gpio/${tim_subimplementation} # BEGIN TIM ../../include/tim ../../include/tim/hal_ll_tim_pin_map/${tim_subimplementation} @@ -48,6 +48,7 @@ target_include_directories(lib_hal_ll_tim INTERFACE $ + $ $ $ $ diff --git a/targets/arm/mikroe/sam/src/uart/CMakeLists.txt b/targets/arm/mikroe/sam/src/uart/CMakeLists.txt index a1f724137..a49745c77 100644 --- a/targets/arm/mikroe/sam/src/uart/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/uart/CMakeLists.txt @@ -5,7 +5,7 @@ set(mcu_header_path "") find_cortex(hal_ll_def_list) list(APPEND hal_ll_def_list ${MCU_NAME}) -list(APPEND hal_ll_def_list "MACRO_USAGE_GPIO") +list(APPEND hal_ll_def_list "MACRO_USAGE_UART") set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) ## BEGIN UART @@ -14,8 +14,6 @@ if (${MCU_NAME} MATCHES "^ATSAME7.+") endif() ## END UART -list(APPEND hal_ll_def_list "MACRO_USAGE_UART") - mikrosdk_add_library(lib_hal_ll_uart MikroSDK.HalLowLevel.UART ${uart_subimplementation}/hal_ll_uart.c @@ -36,11 +34,13 @@ target_link_libraries(lib_hal_ll_uart PUBLIC MikroSDK.HalLowLevelCore MikroSDK.HalLowLevelCommon ) + string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) target_include_directories(lib_hal_ll_uart PRIVATE ../../include ../../include/gpio + ../../include/gpio/${uart_subimplementation} # BEGIN UART ../../include/uart ../../include/uart/hal_ll_uart_pin_map/${uart_subimplementation} @@ -49,6 +49,7 @@ target_include_directories(lib_hal_ll_uart INTERFACE $ $ + $ $ $ $ From 81bcbcacc289e3899a53eca62f9910fbadaac85a Mon Sep 17 00:00:00 2001 From: Ivan Ruzavin Date: Mon, 18 Nov 2024 20:37:00 +0100 Subject: [PATCH 10/56] Updated CopyRight year --- targets/arm/mikroe/core/CMakeLists.txt | 2 +- targets/arm/mikroe/core/src/sam/m7/hal_ll_core_port.c | 2 +- targets/arm/mikroe/sam/include/gpio/hal_ll_gpio.h | 2 +- targets/arm/mikroe/sam/include/gpio/hal_ll_gpio_port.h | 2 +- .../implementation_1/hal_ll_gpio_constants.h | 2 +- .../implementation_1/hal_ll_gpio_struct_type.h | 2 +- targets/arm/mikroe/sam/include/hal_ll_pin_names.h | 2 +- targets/arm/mikroe/sam/include/hal_ll_pmc.h | 2 +- targets/arm/mikroe/sam/include/hal_ll_target.h | 2 +- targets/arm/mikroe/sam/include/hal_ll_target_names.h | 2 +- targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_master.h | 2 +- .../implementations/implementation_1/hal_ll_i2c_pin_map.h | 2 +- .../arm/mikroe/sam/include/spi_master/hal_ll_spi_master.h | 2 +- .../implementation_1/hal_ll_spi_master_pin_map.h | 2 +- targets/arm/mikroe/sam/include/tim/hal_ll_tim.h | 2 +- .../implementations/implementation_1/hal_ll_tim_pin_map.h | 2 +- targets/arm/mikroe/sam/include/uart/hal_ll_uart.h | 2 +- .../implementations/implementation_1/hal_ll_uart_pin_map.h | 2 +- targets/arm/mikroe/sam/src/gpio/hal_ll_gpio.c | 2 +- .../implementations/implementation_1/hal_ll_gpio_port.c | 2 +- .../i2c/implementations/implementation_1/CMakeLists.cmake | 7 ------- .../implementations/implementation_1/hal_ll_i2c_master.c | 2 +- .../implementations/implementation_1/CMakeLists.cmake | 7 ------- .../implementations/implementation_1/hal_ll_spi_master.c | 2 +- .../tim/implementations/implementation_1/CMakeLists.cmake | 7 ------- .../src/tim/implementations/implementation_1/hal_ll_tim.c | 2 +- .../uart/implementations/implementation_1/CMakeLists.cmake | 7 ------- .../uart/implementations/implementation_1/hal_ll_uart.c | 2 +- 28 files changed, 24 insertions(+), 52 deletions(-) delete mode 100644 targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/CMakeLists.cmake delete mode 100644 targets/arm/mikroe/sam/src/spi_master/implementations/implementation_1/CMakeLists.cmake delete mode 100644 targets/arm/mikroe/sam/src/tim/implementations/implementation_1/CMakeLists.cmake delete mode 100644 targets/arm/mikroe/sam/src/uart/implementations/implementation_1/CMakeLists.cmake diff --git a/targets/arm/mikroe/core/CMakeLists.txt b/targets/arm/mikroe/core/CMakeLists.txt index b763c88f7..d4e2c5fb3 100644 --- a/targets/arm/mikroe/core/CMakeLists.txt +++ b/targets/arm/mikroe/core/CMakeLists.txt @@ -37,7 +37,7 @@ elseif(${MCU_NAME} MATCHES "^TM4C.*") set(chip_vendor "tiva") list(APPEND hal_ll_core_def_list ${chip_vendor}) set(hal_ll_core_source "m4") -elseif(${MCU_NAME} MATCHES "^ATSAM.*") +elseif(${MCU_NAME} MATCHES "^(AT)?SAM.*") set(chip_vendor "sam") list(APPEND hal_ll_core_def_list ${chip_vendor}) set(hal_ll_core_source "m7") diff --git a/targets/arm/mikroe/core/src/sam/m7/hal_ll_core_port.c b/targets/arm/mikroe/core/src/sam/m7/hal_ll_core_port.c index f008614ab..2fb90ba2d 100644 --- a/targets/arm/mikroe/core/src/sam/m7/hal_ll_core_port.c +++ b/targets/arm/mikroe/core/src/sam/m7/hal_ll_core_port.c @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) 2024 MikroElektronika d.o.o. +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** This file is part of the mikroSDK package diff --git a/targets/arm/mikroe/sam/include/gpio/hal_ll_gpio.h b/targets/arm/mikroe/sam/include/gpio/hal_ll_gpio.h index d67b30360..f80371db5 100644 --- a/targets/arm/mikroe/sam/include/gpio/hal_ll_gpio.h +++ b/targets/arm/mikroe/sam/include/gpio/hal_ll_gpio.h @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) 2024 MikroElektronika d.o.o. +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** This file is part of the mikroSDK package diff --git a/targets/arm/mikroe/sam/include/gpio/hal_ll_gpio_port.h b/targets/arm/mikroe/sam/include/gpio/hal_ll_gpio_port.h index cba4e596e..846706ae4 100644 --- a/targets/arm/mikroe/sam/include/gpio/hal_ll_gpio_port.h +++ b/targets/arm/mikroe/sam/include/gpio/hal_ll_gpio_port.h @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) 2024 MikroElektronika d.o.o. +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** This file is part of the mikroSDK package diff --git a/targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_constants.h b/targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_constants.h index ac120aad7..2804108f0 100644 --- a/targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_constants.h +++ b/targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_constants.h @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) 2024 MikroElektronika d.o.o. +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** This file is part of the mikroSDK package diff --git a/targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_struct_type.h b/targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_struct_type.h index 785963f29..8609d25c9 100644 --- a/targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_struct_type.h +++ b/targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_struct_type.h @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) 2024 MikroElektronika d.o.o. +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** This file is part of the mikroSDK package diff --git a/targets/arm/mikroe/sam/include/hal_ll_pin_names.h b/targets/arm/mikroe/sam/include/hal_ll_pin_names.h index 1f258a2c2..bcc332280 100644 --- a/targets/arm/mikroe/sam/include/hal_ll_pin_names.h +++ b/targets/arm/mikroe/sam/include/hal_ll_pin_names.h @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) 2024 MikroElektronika d.o.o. +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** This file is part of the mikroSDK package diff --git a/targets/arm/mikroe/sam/include/hal_ll_pmc.h b/targets/arm/mikroe/sam/include/hal_ll_pmc.h index 81baf6c4a..94d7dc56e 100644 --- a/targets/arm/mikroe/sam/include/hal_ll_pmc.h +++ b/targets/arm/mikroe/sam/include/hal_ll_pmc.h @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) 2024 MikroElektronika d.o.o. +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** This file is part of the mikroSDK package diff --git a/targets/arm/mikroe/sam/include/hal_ll_target.h b/targets/arm/mikroe/sam/include/hal_ll_target.h index 64cf00f75..145b53fb9 100644 --- a/targets/arm/mikroe/sam/include/hal_ll_target.h +++ b/targets/arm/mikroe/sam/include/hal_ll_target.h @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) 2024 MikroElektronika d.o.o. +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** This file is part of the mikroSDK package diff --git a/targets/arm/mikroe/sam/include/hal_ll_target_names.h b/targets/arm/mikroe/sam/include/hal_ll_target_names.h index 521ed9ec6..a6d3cd6bf 100644 --- a/targets/arm/mikroe/sam/include/hal_ll_target_names.h +++ b/targets/arm/mikroe/sam/include/hal_ll_target_names.h @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) 2024 MikroElektronika d.o.o. +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** This file is part of the mikroSDK package diff --git a/targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_master.h b/targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_master.h index 46376d50a..86cae29fa 100644 --- a/targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_master.h +++ b/targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_master.h @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) 2024 MikroElektronika d.o.o. +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** This file is part of the mikroSDK package diff --git a/targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_pin_map/implementations/implementation_1/hal_ll_i2c_pin_map.h b/targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_pin_map/implementations/implementation_1/hal_ll_i2c_pin_map.h index b0f70d9a9..7c326ec40 100644 --- a/targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_pin_map/implementations/implementation_1/hal_ll_i2c_pin_map.h +++ b/targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_pin_map/implementations/implementation_1/hal_ll_i2c_pin_map.h @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) 2024 MikroElektronika d.o.o. +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** This file is part of the mikroSDK package diff --git a/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master.h b/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master.h index f2035088b..f7dedec8c 100644 --- a/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master.h +++ b/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master.h @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) 2024 MikroElektronika d.o.o. +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** This file is part of the mikroSDK package diff --git a/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master_pin_map/implementations/implementation_1/hal_ll_spi_master_pin_map.h b/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master_pin_map/implementations/implementation_1/hal_ll_spi_master_pin_map.h index e67d0bc76..4077f5dd7 100644 --- a/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master_pin_map/implementations/implementation_1/hal_ll_spi_master_pin_map.h +++ b/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master_pin_map/implementations/implementation_1/hal_ll_spi_master_pin_map.h @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) 2024 MikroElektronika d.o.o. +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** This file is part of the mikroSDK package diff --git a/targets/arm/mikroe/sam/include/tim/hal_ll_tim.h b/targets/arm/mikroe/sam/include/tim/hal_ll_tim.h index a5b601151..41669a1b2 100644 --- a/targets/arm/mikroe/sam/include/tim/hal_ll_tim.h +++ b/targets/arm/mikroe/sam/include/tim/hal_ll_tim.h @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) 2024 MikroElektronika d.o.o. +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** This file is part of the mikroSDK package diff --git a/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/implementation_1/hal_ll_tim_pin_map.h b/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/implementation_1/hal_ll_tim_pin_map.h index 1e8fcc04a..d341a28c3 100644 --- a/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/implementation_1/hal_ll_tim_pin_map.h +++ b/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/implementation_1/hal_ll_tim_pin_map.h @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) 2024 MikroElektronika d.o.o. +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** This file is part of the mikroSDK package diff --git a/targets/arm/mikroe/sam/include/uart/hal_ll_uart.h b/targets/arm/mikroe/sam/include/uart/hal_ll_uart.h index 287edf4ff..da7be67a7 100644 --- a/targets/arm/mikroe/sam/include/uart/hal_ll_uart.h +++ b/targets/arm/mikroe/sam/include/uart/hal_ll_uart.h @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) 2024 MikroElektronika d.o.o. +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** This file is part of the mikroSDK package diff --git a/targets/arm/mikroe/sam/include/uart/hal_ll_uart_pin_map/implementations/implementation_1/hal_ll_uart_pin_map.h b/targets/arm/mikroe/sam/include/uart/hal_ll_uart_pin_map/implementations/implementation_1/hal_ll_uart_pin_map.h index 714030cb0..ab01323cc 100644 --- a/targets/arm/mikroe/sam/include/uart/hal_ll_uart_pin_map/implementations/implementation_1/hal_ll_uart_pin_map.h +++ b/targets/arm/mikroe/sam/include/uart/hal_ll_uart_pin_map/implementations/implementation_1/hal_ll_uart_pin_map.h @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) 2024 MikroElektronika d.o.o. +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** This file is part of the mikroSDK package diff --git a/targets/arm/mikroe/sam/src/gpio/hal_ll_gpio.c b/targets/arm/mikroe/sam/src/gpio/hal_ll_gpio.c index bbf3c6166..a3073f599 100644 --- a/targets/arm/mikroe/sam/src/gpio/hal_ll_gpio.c +++ b/targets/arm/mikroe/sam/src/gpio/hal_ll_gpio.c @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) 2024 MikroElektronika d.o.o. +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** This file is part of the mikroSDK package diff --git a/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c b/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c index e2645e2d7..9201bcbd3 100644 --- a/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c +++ b/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) 2024 MikroElektronika d.o.o. +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** This file is part of the mikroSDK package diff --git a/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/CMakeLists.cmake b/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/CMakeLists.cmake deleted file mode 100644 index 3c1a5d6d4..000000000 --- a/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/CMakeLists.cmake +++ /dev/null @@ -1,7 +0,0 @@ -if(${MCU_NAME} MATCHES "^ATSAME70Q21B") - set(i2c_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_i2c_master.c") - set(pmc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/pmc/implementations/arm_gcc_clang_atsam_e70") - set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/arm_gcc_clang_atsam_e70") - list(APPEND hal_ll_def_list "ATSAME7x") - set(i2c_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/i2c/hal_ll_i2c_pin_map/implementations/arm_gcc_clang_atsam_e70") -endif() diff --git a/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c b/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c index c1a2f541e..24a9078e2 100644 --- a/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c +++ b/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) 2024 MikroElektronika d.o.o. +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** This file is part of the mikroSDK package diff --git a/targets/arm/mikroe/sam/src/spi_master/implementations/implementation_1/CMakeLists.cmake b/targets/arm/mikroe/sam/src/spi_master/implementations/implementation_1/CMakeLists.cmake deleted file mode 100644 index 0db085336..000000000 --- a/targets/arm/mikroe/sam/src/spi_master/implementations/implementation_1/CMakeLists.cmake +++ /dev/null @@ -1,7 +0,0 @@ -if(${MCU_NAME} MATCHES "^ATSAME70Q21B") - set(spi_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_spi_master.c") - set(pmc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/pmc/implementations/arm_gcc_clang_atsam_e70") - set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/arm_gcc_clang_atsam_e70") - list(APPEND hal_ll_def_list "ATSAME7x") - set(spi_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/spi_master/hal_ll_spi_master_pin_map/implementations/arm_gcc_clang_atsam_e70") -endif() diff --git a/targets/arm/mikroe/sam/src/spi_master/implementations/implementation_1/hal_ll_spi_master.c b/targets/arm/mikroe/sam/src/spi_master/implementations/implementation_1/hal_ll_spi_master.c index b6a970fbe..410815157 100644 --- a/targets/arm/mikroe/sam/src/spi_master/implementations/implementation_1/hal_ll_spi_master.c +++ b/targets/arm/mikroe/sam/src/spi_master/implementations/implementation_1/hal_ll_spi_master.c @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) 2024 MikroElektronika d.o.o. +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** This file is part of the mikroSDK package diff --git a/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/CMakeLists.cmake b/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/CMakeLists.cmake deleted file mode 100644 index cc64ee0d0..000000000 --- a/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/CMakeLists.cmake +++ /dev/null @@ -1,7 +0,0 @@ -if(${MCU_NAME} MATCHES "^ATSAME70Q21B$") - set(tim_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_tim.c") - set(pmc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/pmc/implementations/arm_gcc_clang_atsam_e70") - set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/arm_gcc_clang_atsam_e70") - list(APPEND hal_ll_def_list "ATSAME7x") - set(tim_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/tim/hal_ll_tim_pin_map/implementations/arm_gcc_clang_atsam_e70") -endif() diff --git a/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c b/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c index 39564369c..81275c205 100644 --- a/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c +++ b/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) 2024 MikroElektronika d.o.o. +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** This file is part of the mikroSDK package diff --git a/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/CMakeLists.cmake b/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/CMakeLists.cmake deleted file mode 100644 index b32bc4423..000000000 --- a/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/CMakeLists.cmake +++ /dev/null @@ -1,7 +0,0 @@ -if(${MCU_NAME} MATCHES "^ATSAME70Q21B$") - set(uart_subimplementation "${CMAKE_CURRENT_LIST_DIR}/hal_ll_uart.c") - set(pmc_subimplementation "${CMAKE_CURRENT_SOURCE_DIR}/../../include/pmc/implementations/arm_gcc_clang_atsam_e70") - set(gpio_subimplementation_include_dir "${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio/implementations/arm_gcc_clang_atsam_e70") - list(APPEND hal_ll_def_list "ATSAME7x") - set(uart_pin_map "${CMAKE_CURRENT_SOURCE_DIR}/../../include/uart/hal_ll_uart_pin_map/implementations/arm_gcc_clang_atsam_e70") -endif() diff --git a/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c b/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c index f62c0b437..170902760 100644 --- a/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c +++ b/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c @@ -1,6 +1,6 @@ /**************************************************************************** ** -** Copyright (C) 2024 MikroElektronika d.o.o. +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. ** Contact: https://www.mikroe.com/contact ** ** This file is part of the mikroSDK package From 85fc3d43ae9b13c37fce0fc48fa541f1f0678ecc Mon Sep 17 00:00:00 2001 From: "ivan.ruzavin" Date: Wed, 20 Nov 2024 08:05:01 +0100 Subject: [PATCH 11/56] PWM works for all pins --- .../implementations/implementation_1/hal_ll_tim.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c b/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c index 81275c205..f4d8df300 100644 --- a/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c +++ b/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c @@ -78,6 +78,7 @@ static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COU #define HAL_LL_TC_CMR_TIMER_CLOCK2_MASK 0x1 #define HAL_LL_TC_CMR_TIMER_CLOCK3_MASK 0x2 #define HAL_LL_TC_CMR_TIMER_CLOCK4_MASK 0x3 +#define HAL_LL_TC_CMR_EEVT_XC0_MASK 0x0400 #define HAL_LL_TC_CMR_WAVSEL_UP_RC_MASK 0x4000 #define HAL_LL_TC_CMR_ACPA_CLEAR_MASK 0x20000 #define HAL_LL_TC_CMR_ACPC_SET_MASK 0x40000 @@ -439,9 +440,10 @@ hal_ll_err_t hal_ll_tim_start( handle_t *handle ) { set_reg_bits( &hal_ll_hw_reg->channel[ channel_num ].cmr, HAL_LL_TC_CMR_ACPA_CLEAR_MASK ); set_reg_bits( &hal_ll_hw_reg->channel[ channel_num ].cmr, HAL_LL_TC_CMR_ACPC_SET_MASK ); } else { - // Clear TIOBx pin on RB compare and set on RC compare. + // Clear TIOBx pin on RB compare and set on RC compare. Also set TIOBx as output. set_reg_bits( &hal_ll_hw_reg->channel[ channel_num ].cmr, HAL_LL_TC_CMR_BCPB_CLEAR_MASK ); set_reg_bits( &hal_ll_hw_reg->channel[ channel_num ].cmr, HAL_LL_TC_CMR_BCPC_SET_MASK ); + set_reg_bits( &hal_ll_hw_reg->channel[ channel_num ].cmr, HAL_LL_TC_CMR_EEVT_XC0_MASK ); } // Enable counter. @@ -658,11 +660,9 @@ static void _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_t *map, bool hal_ static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ) { - uint8_t tmp_channel; - // Map new pin. hal_ll_tim_hw_specifics_map[ module_index ].config.pin = _tim_map[ index ].pin; - tmp_channel = _tim_map[ index ].channel; + hal_ll_tim_hw_specifics_map[ module_index ].config.channel = _tim_map[ index ].channel; hal_ll_tim_hw_specifics_map[ module_index ].config.af = _tim_map[ index ].af; } @@ -671,12 +671,10 @@ static void _hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_m if ( ( map->config.pin != HAL_LL_PIN_NC ) && map->config.pin != HAL_LL_PIN_NC ) { module.pins[0] = map->config.pin; - module.pins[1] = map->config.pin; - module.pins[2] = GPIO_MODULE_STRUCT_END; + module.pins[1] = GPIO_MODULE_STRUCT_END; module.configs[0] = map->config.af & HAL_LL_ALTERNATE_FUNCTION_MASK; - module.configs[1] = map->config.af & HAL_LL_ALTERNATE_FUNCTION_MASK; - module.configs[2] = GPIO_MODULE_STRUCT_END; + module.configs[1] = GPIO_MODULE_STRUCT_END; hal_ll_gpio_module_struct_init( &module, hal_ll_state ); } From 6204204cb1d36777493ef8108b8558299624be36 Mon Sep 17 00:00:00 2001 From: "ivan.ruzavin" Date: Wed, 20 Nov 2024 11:33:50 +0100 Subject: [PATCH 12/56] Implemented One Wire --- .../common/include/hal_ll_bit_control.h | 58 +++ .../hal_ll_gpio_struct_type.h | 2 +- .../implementation_1/hal_ll_one_wire.h | 9 +- .../implementation_1/hal_ll_gpio_port.c | 3 +- .../implementation_1/hal_ll_one_wire.c | 397 ++++++++++++++++-- 5 files changed, 432 insertions(+), 37 deletions(-) diff --git a/targets/arm/mikroe/common/include/hal_ll_bit_control.h b/targets/arm/mikroe/common/include/hal_ll_bit_control.h index dba7328d4..fbd4645db 100644 --- a/targets/arm/mikroe/common/include/hal_ll_bit_control.h +++ b/targets/arm/mikroe/common/include/hal_ll_bit_control.h @@ -51,6 +51,9 @@ extern "C"{ #include #include +/*!< @brief Mask used for register clearing */ +#define HAL_LL_CLEAR 0x00UL + #define selected_reg(__reg) (*__reg) /*!< @brief Low nibble macros */ @@ -63,6 +66,36 @@ extern "C"{ #define HAL_LL_NIBBLE_HIGH_16BIT (0xFF00U) #define HAL_LL_NIBBLE_HIGH_32BIT (0xFFFF0000UL) +/** + * @brief Writes specified value to + * specified register. + * + * @param[in] reg - register address. + * @param[in] _val - Value to be written. + */ +#define write_reg(reg,_val) (selected_reg(reg) = (_val)) + +/** + * @brief Returns value stored + * in a register. + * + * @param[in] reg - register address. + * + * @return Register(reg) value. + */ +#define read_reg(reg) (selected_reg(reg)) + +/** + * @brief Returns value of specified bit + * mask from a register. + * + * @param[in] reg - register address + * @param[in] bit_mask - bit mask. + * + * @return Register(reg) bits value. + */ +#define read_reg_bits(reg,bit_mask) (selected_reg(reg) & (bit_mask)) + /** * @brief Clears one bit in a register * @param reg - register address @@ -70,6 +103,15 @@ extern "C"{ */ #define clear_reg_bit(reg,_bit) (selected_reg(reg)&=~((1UL)<<(_bit))) +/** + * @brief Clears bits specified by bit_mask + * in the specified register. + * + * @param[in] reg - register address + * @param[in] bit_mask - bit mask. + */ +#define clear_reg_bits(reg,bit_mask) (selected_reg(reg) &= ~(bit_mask)) + /** * @brief Sets one bit in a register * @param reg - register address @@ -77,6 +119,15 @@ extern "C"{ */ #define set_reg_bit(reg,_bit) (selected_reg(reg)|=((1UL)<<(_bit))) +/** + * @brief Sets bits specified by bit_mask + * in the specified register. + * + * @param[in] reg - register address + * @param[in] bit_mask - bit mask. + */ +#define set_reg_bits(reg,bit_mask) (selected_reg(reg) |= (bit_mask)) + /** * @brief Returns value of one bit * in a register @@ -86,6 +137,13 @@ extern "C"{ */ #define check_reg_bit(reg,_bit) (selected_reg(reg)&((1UL)<<(_bit))) +/** + * @brief Clears all bits in a register. + * + * @param[in] reg - register address + */ +#define clear_reg(reg) write_reg(reg, HAL_LL_CLEAR) + #ifdef __cplusplus } #endif diff --git a/targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_struct_type.h b/targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_struct_type.h index 8609d25c9..1ae430f74 100644 --- a/targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_struct_type.h +++ b/targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_struct_type.h @@ -94,7 +94,7 @@ typedef struct hal_ll_gpio_base_handle hal_ll_gpio_signal_register_handle_t signal; /* Output signal controller */ hal_ll_gpio_interrupt_register_handle_t interrupt; hal_ll_gpio_register_handle_t multi_driver; - hal_ll_gpio_register_handle_t pullup_disable; + hal_ll_gpio_register_handle_t pullup_off; uint32_t abcdsr0; /* Peripheral ABCD Select Register 0 */ uint32_t abcdsr1; /* Peripheral ABCD Select Register 1 */ } hal_ll_gpio_base_handle_t; diff --git a/targets/arm/mikroe/sam/include/one_wire/implementations/implementation_1/hal_ll_one_wire.h b/targets/arm/mikroe/sam/include/one_wire/implementations/implementation_1/hal_ll_one_wire.h index dd63b77e7..9290d3467 100644 --- a/targets/arm/mikroe/sam/include/one_wire/implementations/implementation_1/hal_ll_one_wire.h +++ b/targets/arm/mikroe/sam/include/one_wire/implementations/implementation_1/hal_ll_one_wire.h @@ -66,11 +66,10 @@ typedef struct { */ typedef struct { hal_ll_pin_name_t data_pin; // One Wire data pin. - volatile uint32_t moder; // Register for altering GPIO pin direction. - volatile uint32_t moder_set; // Variable for configuring pin as General purpose output. - volatile uint32_t moder_clear; // Variable for configuring pin as General purpose input (reset state). - volatile uint32_t bsrr; // Register for GPIO port bit set/reset. - volatile uint32_t idr; // Register for reading current GPIO pin state. + volatile uint32_t pio_oer; // Register for setting GPIO as Output. + volatile uint32_t pio_odr; // Register for setting GPIO as Input. + volatile uint32_t disable; // Register for setting GPIO signal. + volatile uint32_t status; // Register for reading current GPIO pin state. } hal_ll_one_wire_local_t; /** diff --git a/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c b/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c index 9201bcbd3..418210e0f 100644 --- a/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c +++ b/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c @@ -214,9 +214,10 @@ static void hal_ll_gpio_config( hal_ll_gpio_base_t *port, hal_ll_gpio_mask_t pin port_ptr->pio.enable |= pin_mask; port_ptr->filter.enable |= pin_mask; } else { - // Set gpio direction as output. + // Set gpio direction as output and enable Pull Up resistor. port_ptr->pio.enable |= pin_mask; port_ptr->output.enable |= pin_mask; + port_ptr->pullup_off.disable |= pin_mask; } } else { diff --git a/targets/arm/mikroe/sam/src/one_wire/implementations/implementation_1/hal_ll_one_wire.c b/targets/arm/mikroe/sam/src/one_wire/implementations/implementation_1/hal_ll_one_wire.c index 1710a5f8f..72efd09cb 100644 --- a/targets/arm/mikroe/sam/src/one_wire/implementations/implementation_1/hal_ll_one_wire.c +++ b/targets/arm/mikroe/sam/src/one_wire/implementations/implementation_1/hal_ll_one_wire.c @@ -47,9 +47,6 @@ /*!< @brief Helper macro getting minimum bits per transfer. */ #define HAL_LL_ONE_WIRE_MINIMUM_BITS_PER_TRANSFER (8) -/*!< @brief Helper macro for reset pins offset. */ -#define RESET_PINS_OFFSET (16) - // ------------------------------------------------------------------ VARIABLES /*!< @brief Helper macro for starting to enumerate device ID(s). */ static uint8_t hal_ll_one_wire_search_rom_command = ONE_WIRE_CMD_ROM_SEARCH; @@ -138,71 +135,411 @@ static void hal_ll_one_wire_read_bit( uint8_t *read_data_buffer ); static hal_ll_err_t hal_ll_one_wire_search( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ); // ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS -void hal_ll_one_wire_open( hal_ll_one_wire_t *obj ) -{ +void hal_ll_one_wire_open( hal_ll_one_wire_t *obj ) { + // Local instance of One Wire pin. + hal_ll_gpio_pin_t one_wire_pin; + + // Enable appropriate PORT clock, set pin to be digital input. + hal_ll_gpio_configure_pin( &one_wire_pin, obj->data_pin, HAL_LL_GPIO_DIGITAL_OUTPUT ); + /* Register One Wire handle (memorize appropriate GPIO registers and bit positions). */ + hal_ll_one_wire_reconfigure( obj ); } -hal_ll_err_t hal_ll_one_wire_reset( hal_ll_one_wire_t *obj ) -{ +hal_ll_err_t hal_ll_one_wire_reset( hal_ll_one_wire_t *obj ) { + /* Variable for checking whether there are device(s) on + * One Wire data pin (0) or there aren't any devices at all (1). */ + uint8_t device_response = 1; + + // Make sure that pin has output capability. + *(uint32_t *)one_wire_handle.pio_oer = one_wire_handle.data_pin; + // Set pin to LOW voltage level. + *(uint32_t *)one_wire_handle.disable = one_wire_handle.data_pin; + + // Timing value for reset of One Wire bus - LOW voltage level. + one_wire_timing_value_h(); + + // Release One Wire data line ( pull-up resistor will pull the data line up ). + *(uint32_t *)one_wire_handle.pio_odr = one_wire_handle.data_pin; + + // Timing value for reset of One Wire bus - Master sample pulse. + one_wire_timing_value_i(); + + // Check whether there are devices on One Wire data pin. + device_response = *(uint32_t *)one_wire_handle.status & one_wire_handle.data_pin; + // Provide enough time for power injection into internal power logic of devices that are present. + one_wire_timing_value_j(); + + // Return final result of device response. + return device_response; } -hal_ll_err_t hal_ll_one_wire_read_rom( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *device_rom_address ) -{ +hal_ll_err_t hal_ll_one_wire_read_rom( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *device_rom_address ) { + // Initiate Reset sequence. + if ( hal_ll_one_wire_reset( obj ) ) { + return HAL_LL_ONE_WIRE_ERROR; + } + + // Initiate "Read ROM" command. + hal_ll_one_wire_write_byte( &hal_ll_one_wire_read_rom_command, 1 ); + + // Read ROM address. + hal_ll_one_wire_read_byte( &device_rom_address->address[0], 8 ); + return HAL_LL_ONE_WIRE_SUCCESS; } -hal_ll_err_t hal_ll_one_wire_skip_rom( hal_ll_one_wire_t *obj ) -{ +hal_ll_err_t hal_ll_one_wire_skip_rom( hal_ll_one_wire_t *obj ) { + // Initiate Reset sequence. + if ( hal_ll_one_wire_reset( obj ) ) { + return HAL_LL_ONE_WIRE_ERROR; + } + + // Initiate "Skip ROM" command. + hal_ll_one_wire_write_byte( &hal_ll_one_wire_skip_rom_command, 1 ); + return HAL_LL_ONE_WIRE_SUCCESS; } -hal_ll_err_t hal_ll_one_wire_match_rom( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *device_rom_address ) -{ +hal_ll_err_t hal_ll_one_wire_match_rom( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *device_rom_address ) { + // Initiate Reset sequence. + if ( hal_ll_one_wire_reset( obj ) ) { + return HAL_LL_ONE_WIRE_ERROR; + } + + // Initiate "Match" command. + hal_ll_one_wire_write_byte( &hal_ll_one_wire_match_rom_command, 1 ); + + // Send ROM address. + hal_ll_one_wire_write_byte( (uint32_t)device_rom_address, 8 ); + return HAL_LL_ONE_WIRE_SUCCESS; } -hal_ll_err_t hal_ll_one_wire_search_first_device( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ) -{ +hal_ll_err_t hal_ll_one_wire_search_first_device( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ) { + // Reset the search state. + last_discrepancy = 0; + last_device_flag = 0; + last_family_discrepancy = 0; + + // Initiate search algorithm, in order to get first device on One Wire grid. + hal_ll_one_wire_search( obj, one_wire_device_list ); + return HAL_LL_ONE_WIRE_SUCCESS; } -hal_ll_err_t hal_ll_one_wire_search_next_device( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ) -{ +hal_ll_err_t hal_ll_one_wire_search_next_device( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ) { + // Initiate search algorithm, in order to get first device on One Wire grid. + hal_ll_one_wire_search( obj, one_wire_device_list ); + return HAL_LL_ONE_WIRE_SUCCESS; } -static hal_ll_err_t hal_ll_one_wire_search( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ) -{ - +static hal_ll_err_t hal_ll_one_wire_search( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list ) { + // Final search result variable. + uint8_t search_result = 0; + + // Initialize variables for search method. + uint8_t rom_byte_number = 0; + uint8_t rom_byte_mask = 1; + uint8_t id_bit_number = 1; + uint8_t last_zero = 0; + + // The first bit read in a bit search sequence. + // ( logical AND of all of the id_bit_number bits of the devices that are still participating in the search ). + uint8_t id_bit = 0; + + // The complement of id_bit. + // ( logical AND of the complement of all id_bit_number bits of the devices that are still participating in the search ). + uint8_t cmp_id_bit = 0; + + // Search direction ( bit-per-bit search ). + uint8_t search_direction = 0; + + // If the last call was not the last one... + if ( !last_device_flag ) { + + // If there were no any device while executing One Wire reset sequence... + if ( hal_ll_one_wire_reset( obj ) ) { + + // Reset all the important variables. + last_device_flag = 0; + last_discrepancy = 0; + last_family_discrepancy = 0; + + // Stop searching because there are no any One Wire capable devices. + return HAL_LL_ONE_WIRE_ERROR; + } + + // If device(s) has(have) been found, initiate "Search" command. + hal_ll_one_wire_write_byte( &hal_ll_one_wire_search_rom_command, 1 ); + + // Iterate until all 64 bits (8 bytes) of unique ROM 'registration' numbers have not been found. + do { + // Read a bit. + hal_ll_one_wire_read_bit( &id_bit ); + + // Then, read its complement. + hal_ll_one_wire_read_bit( &cmp_id_bit ); + + // Check whether no devices participating in current search. + if ( ( id_bit == 1 ) && ( cmp_id_bit == 1 ) ) { + break; + // Proceed, because we have found some device(s). + } else { + // We are going to check once again whether read bit and + // its complement of all the devices on the One Wire grid are not the same. + // If they are not the same, we are going to start our search with non-complement bit. + if ( id_bit != cmp_id_bit ) { + search_direction = id_bit; // Bit write value for search. + + // Otherwise, there are both binary zeros and ones in the current + // bit position of the participating ROM numbers. This is a discrepancy. + } else { + if ( id_bit_number < last_discrepancy ) { + search_direction = ( ( one_wire_device_list->address[ rom_byte_number ] & rom_byte_mask ) > 0 ); + } else { + search_direction = ( id_bit_number == last_discrepancy ); + } + + // If 0 is picked, save its position. + if ( search_direction == 0) { + last_zero = id_bit_number; + + // Check for last discrepancy in family. + if ( last_zero < 9 ) { + last_family_discrepancy = last_zero; + } + } + } + + // Set or clear bit in the ROM byte rom_byte_number with mask rom_byte_mask. + if ( search_direction == 1 ) { + one_wire_device_list->address[ rom_byte_number ] |= rom_byte_mask; + } else { + one_wire_device_list->address[ rom_byte_number ] &= ~rom_byte_mask; + } + + // Search number search direction write bit. + hal_ll_one_wire_write_bit( search_direction ); + + // Increment the byte counter "id_bit_number", and shift the mask "rom_byte_mask". + id_bit_number++; + rom_byte_mask <<= 1; + + // If the mask is zero, then go to new "serial_num" byte, "rom_byte_number" and "reset_mask". + if ( rom_byte_mask == 0 ) { + rom_byte_number++; + rom_byte_mask = 1; + } + } + } while ( rom_byte_number < HAL_LL_ONE_WIRE_MINIMUM_BITS_PER_TRANSFER ); + + // If the search was successful then... + if ( !( id_bit_number < 65 ) ) { + + last_discrepancy = last_zero; + + // Check for last device. + if ( last_discrepancy == 0 ) { + last_device_flag = 1; + } + search_result = 1; + } + } + // If no device found then reset counters so next "search" will be like a first. + if ( !search_result || !one_wire_device_list->address[0] ) { + last_discrepancy = 0; + last_family_discrepancy = 0; + last_device_flag = 0; + search_result = 0; + } + + // Return info whether we have found some device ID or not. + return search_result; } -void hal_ll_one_wire_write_byte( uint8_t *write_data_buffer, size_t write_data_length ) -{ +void hal_ll_one_wire_write_byte( uint8_t *write_data_buffer, size_t write_data_length ) { + size_t local_byte_checker = 0; + uint8_t local_bit_checker = 0; + uint8_t local_byte = 0; + uint8_t bit_state = 0; + + // For every byte to be sent... + while ( local_byte_checker != write_data_length ) { + + // ...restart bit checker... + local_bit_checker = 0; + + // ...get current byte... + local_byte = write_data_buffer[local_byte_checker++]; + + // For every bit in byte to be sent... + while ( local_bit_checker != HAL_LL_ONE_WIRE_MINIMUM_BITS_PER_TRANSFER ) { + bit_state = ( local_byte >> local_bit_checker++ ) & 1; + + if( bit_state ) { + // Set pin to be digital output. + *(uint32_t *)one_wire_handle.pio_oer = one_wire_handle.data_pin; + + // Set pin to LOW voltage level. + *(uint32_t *)one_wire_handle.disable = one_wire_handle.data_pin; + + // Timing value "a" for writing logical '1' - LOW voltage level. + one_wire_timing_value_a(); + // Release One Wire data line ( pull-up resistor will pull the data line up ). + *(uint32_t *)one_wire_handle.pio_odr = one_wire_handle.data_pin; + // Timing value "b" for writing logical '1' - LOW voltage level. + one_wire_timing_value_b(); + } else { + // Set pin to be digital output. + *(uint32_t *)one_wire_handle.pio_oer = one_wire_handle.data_pin; + + // Set pin to LOW voltage level. + *(uint32_t *)one_wire_handle.disable = one_wire_handle.data_pin; + + // Timing value "c" for writing logical '0' - LOW voltage level. + one_wire_timing_value_c(); + + // Release One Wire data line ( pull-up resistor will pull the data line up ). + *(uint32_t *)one_wire_handle.pio_odr = one_wire_handle.data_pin; + // Timing value "d" for writing logical '0' - HIGH voltage level. + one_wire_timing_value_d(); + } + } + } } -void hal_ll_one_wire_read_byte( uint8_t *read_data_buffer, size_t read_data_length ) -{ +void hal_ll_one_wire_read_byte( uint8_t *read_data_buffer, size_t read_data_length ) { + size_t local_byte_checker = 0; + uint8_t local_bit_checker = 0; + uint8_t local_buffer = 0; + + // For every byte to be read... + while ( local_byte_checker != read_data_length ) { + + // ...restart bit checker and buffer... + local_bit_checker = 0; + local_buffer = 0; + + // For every bit in byte to be read... + while ( local_bit_checker != HAL_LL_ONE_WIRE_MINIMUM_BITS_PER_TRANSFER ) { + // Set pin to be digital output. + *(uint32_t *)one_wire_handle.pio_oer = one_wire_handle.data_pin; + // Set pin to LOW voltage level. + *(uint32_t *)one_wire_handle.disable = one_wire_handle.data_pin; + + // Timing value "a" for bit reading - LOW voltage level. + one_wire_timing_value_a(); + // Release One Wire data line ( pull-up resistor will pull the data line up ). + *( uint32_t* )one_wire_handle.pio_odr = one_wire_handle.data_pin; + // Hold the data line for 6us more. + one_wire_timing_value_e(); + + // Read bit. + local_buffer += ( *(uint32_t *)one_wire_handle.status & one_wire_handle.data_pin ) << local_bit_checker++; + + // Timing value "f" for the rest of the read operation. + one_wire_timing_value_f(); + } + + // Send back one logical level up a byte of data that has been just read. + read_data_buffer[local_byte_checker++] = local_buffer; + } } -void hal_ll_one_wire_reconfigure( hal_ll_one_wire_t *obj ) -{ +void hal_ll_one_wire_reconfigure( hal_ll_one_wire_t *obj ) { + // Local instance of One Wire pin. + hal_ll_gpio_pin_t one_wire_pin; + + // Get pin base address and mask. + one_wire_pin.base = (hal_ll_gpio_base_t)hal_ll_gpio_port_base(hal_ll_gpio_port_index(obj->data_pin)); + one_wire_pin.mask = hal_ll_gpio_pin_mask(obj->data_pin); + + // Memorize info about pin number (for future use). + one_wire_handle.data_pin = one_wire_pin.mask; + + // Get all the GPIO register addresses for appropriate One Wire pin. + hal_ll_gpio_base_handle_t *gpio_ptr = (hal_ll_gpio_base_handle_t *)one_wire_pin.base; + + // Memorize appropriate pin Direction Register (PIO_OER for output and PIO_ODR for input). + one_wire_handle.pio_oer = (uint32_t)&gpio_ptr->output.enable; + one_wire_handle.pio_odr = (uint32_t)&gpio_ptr->output.disable; + // Memorize appropriate pin Status Register (PIO_PDSR register). + one_wire_handle.status = (uint32_t)&gpio_ptr->signal.pin_status; + + // Memorize appropriate Bit Clear Output Direction Register (PIO_CODR register). + one_wire_handle.disable = (uint32_t)&gpio_ptr->signal.disable; + + // Set object state to true. + obj->state = true; } // ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS -static void hal_ll_one_wire_write_bit( uint8_t write_data_buffer ) -{ +static void hal_ll_one_wire_write_bit( uint8_t write_data_buffer ) { + uint8_t bit_state = 0; + size_t local_byte_checker = 0; + uint8_t local_bit_checker = 7; + bit_state = write_data_buffer & 0x1; + + if ( bit_state ) { + // Set pin to be digital output. + *(uint32_t *)one_wire_handle.pio_oer = one_wire_handle.data_pin; + // Set pin to LOW voltage level. + *(uint32_t *)one_wire_handle.disable = one_wire_handle.data_pin; + + // Timing value "a" for writing logical '1' - LOW voltage level. + one_wire_timing_value_a(); + + // Release One Wire data line ( pull-up resistor will pull the data line up ). + *(uint32_t *)one_wire_handle.pio_odr = one_wire_handle.data_pin; + + // Timing value "b" for writing logical '1' - LOW voltage level. + one_wire_timing_value_b(); + } else { + // Set pin to be digital output. + *(uint32_t *)one_wire_handle.pio_oer = one_wire_handle.data_pin; + + // Set pin to LOW voltage level. + *(uint32_t *)one_wire_handle.disable = one_wire_handle.data_pin; + // Timing value "c" for writing logical '0' - LOW voltage level. + one_wire_timing_value_c(); + + // Release One Wire data line ( pull-up resistor will pull the data line up ). + *(uint32_t *)one_wire_handle.pio_odr = one_wire_handle.data_pin; + + // Timing value "d" for writing logical '0' - HIGH voltage level. + one_wire_timing_value_d(); + } } -static void hal_ll_one_wire_read_bit( uint8_t *read_data_buffer ) -{ +static void hal_ll_one_wire_read_bit( uint8_t *read_data_buffer ) { + uint8_t local_bit_checker = 0; + + // Set pin to be digital output. + *(uint32_t *)one_wire_handle.pio_oer = one_wire_handle.data_pin; + // Set pin to LOW voltage level. + *(uint32_t *)one_wire_handle.disable = one_wire_handle.data_pin; + + // Timing value "a" for bit reading - LOW voltage level. + one_wire_timing_value_a(); + + // Release One Wire data line ( pull-up resistor will pull the data line up ). + *(uint32_t *)one_wire_handle.pio_odr = one_wire_handle.data_pin; + // Timing value "e" for sampling read information. + one_wire_timing_value_e(); + + // Read bit. + *read_data_buffer = ( *(uint32_t *)one_wire_handle.status & one_wire_handle.data_pin ); + // Timing value "f" for the rest of the read operation. + one_wire_timing_value_f(); } // ------------------------------------------------------------------------- END From 76f989f77c8801a37f61c1fd23993eefb138cd7a Mon Sep 17 00:00:00 2001 From: "ivan.ruzavin" Date: Wed, 20 Nov 2024 15:01:21 +0100 Subject: [PATCH 13/56] AFEC WIP --- .../ATSAME70Q21B/LQFP144/mcu_definitions.h | 27 +- .../implementation_1/hal_ll_adc_pin_map.h | 55 +-- .../implementation_1/hal_ll_adc.c | 380 +++++++++++++----- 3 files changed, 322 insertions(+), 140 deletions(-) diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21B/LQFP144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21B/LQFP144/mcu_definitions.h index 95202c405..8b5ad12a2 100644 --- a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21B/LQFP144/mcu_definitions.h +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21B/LQFP144/mcu_definitions.h @@ -49,11 +49,34 @@ extern "C"{ #endif //ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + #define ADC_MODULE_0 (0) #define ADC_MODULE_1 (1) -#define ADC_MODULE_2 (2) -#define ADC_MODULE_COUNT (3) +#define ADC_MODULE_COUNT (2) //EOF ADC //I2C diff --git a/targets/arm/mikroe/sam/include/adc/hal_ll_adc_pin_map/implementations/implementation_1/hal_ll_adc_pin_map.h b/targets/arm/mikroe/sam/include/adc/hal_ll_adc_pin_map/implementations/implementation_1/hal_ll_adc_pin_map.h index cefec80bc..180bc0f1d 100644 --- a/targets/arm/mikroe/sam/include/adc/hal_ll_adc_pin_map/implementations/implementation_1/hal_ll_adc_pin_map.h +++ b/targets/arm/mikroe/sam/include/adc/hal_ll_adc_pin_map/implementations/implementation_1/hal_ll_adc_pin_map.h @@ -70,26 +70,6 @@ typedef enum HAL_LL_ADC_CHANNEL_9, HAL_LL_ADC_CHANNEL_10, HAL_LL_ADC_CHANNEL_11, - HAL_LL_ADC_CHANNEL_12, - HAL_LL_ADC_CHANNEL_13, - HAL_LL_ADC_CHANNEL_14, - HAL_LL_ADC_CHANNEL_15, - HAL_LL_ADC_CHANNEL_16, - HAL_LL_ADC_CHANNEL_17, - HAL_LL_ADC_CHANNEL_18, - HAL_LL_ADC_CHANNEL_19, - HAL_LL_ADC_CHANNEL_20, - HAL_LL_ADC_CHANNEL_21, - HAL_LL_ADC_CHANNEL_22, - HAL_LL_ADC_CHANNEL_23, - HAL_LL_ADC_CHANNEL_24, - HAL_LL_ADC_CHANNEL_25, - HAL_LL_ADC_CHANNEL_26, - HAL_LL_ADC_CHANNEL_27, - HAL_LL_ADC_CHANNEL_28, - HAL_LL_ADC_CHANNEL_29, - HAL_LL_ADC_CHANNEL_30, - HAL_LL_ADC_CHANNEL_31, HAL_LL_ADC_CHANNEL_NC = 0xFFFF } hal_ll_adc_channel_t; @@ -104,19 +84,40 @@ typedef struct } hal_ll_adc_pin_map_t; /*!< ADC module base addresses. */ -#ifdef ADC_MODULE_1 -static const hal_ll_base_addr_t ADC1_BASE_ADDR = 0x40012000; -#endif -#ifdef ADC_MODULE_2 -static const hal_ll_base_addr_t ADC2_BASE_ADDR = 0x40012100; +#ifdef ADC_MODULE_0 +static const hal_ll_base_addr_t ADC0_BASE_ADDR = 0x4003C000; #endif -#ifdef ADC_MODULE_3 -static const hal_ll_base_addr_t ADC3_BASE_ADDR = 0x40012200; +#ifdef ADC_MODULE_1 +static const hal_ll_base_addr_t ADC1_BASE_ADDR = 0x40064000; #endif /*!< ADC input pins. */ static const hal_ll_adc_pin_map_t _adc_map[] = { + {PD30, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_0}, + {PA21, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_1}, + {PB3, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_2}, + {PE5, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_3}, + {PE4, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_4}, + {PB2, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_5}, + {PA17, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_6}, + {PA18, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_7}, + {PA19, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_8}, + {PA20, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_9}, + {PB0, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_10}, + {PB1, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_0}, + {PC13, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_1}, + {PC15, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_2}, + {PC12, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_3}, + {PC29, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_4}, + {PC30, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_5}, + {PC31, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_6}, + {PC26, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_7}, + {PC27, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_8}, + {PC0, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_9}, + {PE3, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_10}, + {PE0, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_11}, + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_CHANNEL_ERROR} }; diff --git a/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c b/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c index f87e75796..1d8ed1696 100644 --- a/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c +++ b/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c @@ -45,6 +45,7 @@ #include "hal_ll_gpio.h" #include "hal_ll_adc_pin_map.h" #include "delays.h" +#include "mcu.h" // ------------------------------------------------------------- PRIVATE MACROS /*!< @brief Helper macro for getting hal_ll_module_state address */ @@ -60,48 +61,22 @@ /*!< @brief Helper macro for getting adequate module index number */ #define hal_ll_adc_module_num(_module_num) (_module_num - 1) -#define HAL_LL_ADC_CCR_OFFSET 0x304 - -#define HAL_LL_ADC_ADON_BIT 0 -#define HAL_LL_ADC_SR_EOC_BIT 1 -#define HAL_LL_ADC_CONT_BIT 1 -#define HAL_LL_ADC_SCAN_BIT 8 -#define HAL_LL_ADC_ALIGN_BIT 11 -#define HAL_LL_ADC_RESOLUTION_BIT0 24 -#define HAL_LL_ADC_RESOLUTION_BIT1 25 -#define HAL_LL_ADC_SWSTART_BIT 30 - -#define HAL_LL_ADC1_ENABLE_CLOCK 8 -#define HAL_LL_ADC2_ENABLE_CLOCK 9 -#define HAL_LL_ADC3_ENABLE_CLOCK 10 - -#define HAL_LL_ADC_CONT 0x2ul -#define HAL_LL_ADC_SCAN 0x100ul -#define HAL_LL_ADC_ALIGN 0x800ul -#define HAL_LL_ADC_JEXTSEL 0xE0000ul - -#define HAL_LL_ADC_16MHZ 16000000ul -#define HAL_LL_ADC_60MHZ 60000000ul -#define HAL_LL_ADC_72MHZ 72000000ul -#define HAL_LL_ADC_120MHZ 120000000ul -#define HAL_LL_ADC_144MHZ 144000000ul -#define HAL_LL_ADC_180MHZ 180000000ul - -#define HAL_LL_ADC_PRESCALER_2 0x00000000ul -#define HAL_LL_ADC_PRESCALER_4 0x00010000ul -#define HAL_LL_ADC_PRESCALER_6 0x00020000ul -#define HAL_LL_ADC_PRESCALER_8 0x00030000ul - -#define HAL_LL_ADC_PRESCALER_MASK 0x00F00000ul -#define HAL_LL_ADC_SEQUENCE_LENGTH_MASK 0x00F00000ul -#define HAL_LL_ADC_CONVERSION_ONE 0x0000001Ful - -#define HAL_LL_ADC_12BIT_RES 0x00000000ul -#define HAL_LL_ADC_10BIT_RES 0x01000000ul -#define HAL_LL_ADC_8BIT_RES 0x02000000ul -#define HAL_LL_ADC_6BIT_RES 0x03000000ul - -#define HAL_LL_RESOLUTION_MASK 0xFCFFFFFFul +#define HAL_LL_PID_AFEC1_BIT 8 +#define HAL_LL_PID_AFEC0_BIT 29 + +#define HAL_LL_AFEC_CR_SWRST_BIT 0 +#define HAL_LL_AFEC_CR_START_BIT 1 +#define HAL_LL_AFEC_MR_ONE_BIT 23 + +#define HAL_LL_AFEC_EMR_CMPSEL_BIT 3 +#define HAL_LL_AFEC_EMR_STM_BIT 25 + +#define HAL_LL_AFEC_ACR_PGAEN12_MASK 0x0000000Cul +#define HAL_LL_AFEC_EMR_CMPMODE_OUT_MASK 0x00000003ul +#define HAL_LL_AFEC_EMR_NO_AVERAGE_MASK 0x00000000ul +#define HAL_LL_AFEC_EMR_LOW_RES_MASK 0x00010000ul +#define HAL_LL_AFEC_EMR_OSR16 0x00030000ul +#define HAL_LL_AFEC_EMR_OSR256 0x00050000ul #define HAL_LL_MODULE_INDEX_ERROR 0xFFFFFFFFul @@ -115,20 +90,9 @@ static hal_ll_adc_handle_register_t hal_ll_module_state[ADC_MODULE_COUNT] = { (h typedef enum { HAL_LL_MODULE_ADC_DEFAULT = 0xFF, - #if defined(ADC_MODULE) - HAL_LL_MODULE_ADC_1 = 1, - #elif defined(ADC_MODULE_1) + HAL_LL_MODULE_ADC_0 = 1, HAL_LL_MODULE_ADC_1 = 1, - #endif - #if defined(ADC_MODULE_2) - HAL_LL_MODULE_ADC_2 = 2, - #endif - #if defined(ADC_MODULE_3) - HAL_LL_MODULE_ADC_3 = 3, - #endif - #if defined(ADC_MODULE_4) - HAL_LL_MODULE_ADC_4 = 4, - #endif + HAL_LL_MODULE_ADC_NONE } hal_ll_adc_module_number_t; @@ -146,29 +110,35 @@ typedef enum HAL_LL_ADC_ERROR = (-1) } hal_ll_adc_err_t; -/*!< @brief ADC register structure. */ +/*!< @brief AFEC register structure. */ typedef struct { - uint32_t sr; /* Address offset 0x00 */ - uint32_t cr1; /* Address offset 0x04 */ - uint32_t cr2; /* Address offset 0x08 */ - uint32_t smpr1; /* Address offset 0x0C */ - uint32_t smpr2; /* Address offset 0x10 */ - uint32_t jofr1; /* Address offset 0x14 */ - uint32_t jofr2; /* Address offset 0x18 */ - uint32_t jofr3; /* Address offset 0x1C */ - uint32_t jofr4; /* Address offset 0x20 */ - uint32_t htr; /* Address offset 0x24 */ - uint32_t ltr; /* Address offset 0x28 */ - uint32_t sqr1; /* Address offset 0x2C */ - uint32_t sqr2; /* Address offset 0x30 */ - uint32_t sqr3; /* Address offset 0x34 */ - uint32_t jsqr; /* Address offset 0x38 */ - uint32_t jdr1; /* Address offset 0x3C */ - uint32_t jdr2; /* Address offset 0x40 */ - uint32_t jdr3; /* Address offset 0x44 */ - uint32_t jdr4; /* Address offset 0x48 */ - uint32_t dr; /* Address offset 0x4C */ + uint32_t cr; /**< (AFEC Offset: 0x00) AFEC Control Register */ + uint32_t mr; /**< (AFEC Offset: 0x04) AFEC Mode Register */ + uint32_t emr; /**< (AFEC Offset: 0x08) AFEC Extended Mode Register */ + uint32_t seq1r; /**< (AFEC Offset: 0x0C) AFEC Channel Sequence 1 Register */ + uint32_t seq2r; /**< (AFEC Offset: 0x10) AFEC Channel Sequence 2 Register */ + uint32_t cher; /**< (AFEC Offset: 0x14) AFEC Channel Enable Register */ + uint32_t chdr; /**< (AFEC Offset: 0x18) AFEC Channel Disable Register */ + uint32_t chsr; /**< (AFEC Offset: 0x1C) AFEC Channel Status Register */ + uint32_t lcdr; /**< (AFEC Offset: 0x20) AFEC Last Converted Data Register */ + uint32_t ier; /**< (AFEC Offset: 0x24) AFEC Interrupt Enable Register */ + uint32_t idr; /**< (AFEC Offset: 0x28) AFEC Interrupt Disable Register */ + uint32_t imr; /**< (AFEC Offset: 0x2C) AFEC Interrupt Mask Register */ + uint32_t isr; /**< (AFEC Offset: 0x30) AFEC Interrupt Status Register */ + uint32_t _unused1[6]; /** Reserved 0x34 - 0x4B **/ + uint32_t over; /**< (AFEC Offset: 0x4C) AFEC Overrun Status Register */ + uint32_t cwr; /**< (AFEC Offset: 0x50) AFEC Compare Window Register */ + uint32_t cgr; /**< (AFEC Offset: 0x54) AFEC Channel Gain Register */ + uint32_t _unused2[2]; /** Reserved 0x58 - 0x5F **/ + uint32_t diffr; /**< (AFEC Offset: 0x60) AFEC Channel Differential Register */ + uint32_t cselr; /**< (AFEC Offset: 0x64) AFEC Channel Selection Register */ + uint32_t cdr; /**< (AFEC Offset: 0x68) AFEC Channel Data Register */ + uint32_t cocr; /**< (AFEC Offset: 0x6C) AFEC Channel Offset Compensation Register */ + uint32_t tempmr; /**< (AFEC Offset: 0x70) AFEC Temperature Sensor Mode Register */ + uint32_t tempcwr; /**< (AFEC Offset: 0x74) AFEC Temperature Compare Window Register */ + uint32_t _unused3[7]; /** Reserved 0x78 - 0x93 **/ + uint32_t acr; /**< (AFEC Offset: 0x94) AFEC Analog Control Register */ } hal_ll_adc_base_handle_t; /*!< @brief ADC hw specific module values */ @@ -179,15 +149,8 @@ typedef struct static hal_ll_adc_hw_specifics_map_t hal_ll_adc_hw_specifics_map[] = { - #ifdef ADC_MODULE_1 + {ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, {ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, - #endif - #ifdef ADC_MODULE_2 - {ADC2_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_2), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, - #endif - #ifdef ADC_MODULE_3 - {ADC3_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_3), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, - #endif {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF} }; @@ -200,25 +163,18 @@ static volatile hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local // ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS /** - * @brief Enable ADC module 1 clock. + * @brief Enable ADC module 0 clock. * @param none * @return none */ -static inline void adc1_enable_clock(); +static inline void adc0_enable_clock(); /** - * @brief Enable ADC module 2 clock. - * @param none - * @return none - */ -static inline void adc2_enable_clock(); - -/** - * @brief Enable ADC module 3 clock. + * @brief Enable ADC module 1 clock. * @param none * @return none */ -static inline void adc3_enable_clock(); +static inline void adc1_enable_clock(); /** * @brief Initialize ADC module. @@ -286,82 +242,284 @@ static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolu // ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS hal_ll_err_t hal_ll_adc_register_handle(hal_ll_pin_name_t pin, hal_ll_adc_voltage_reference_t vref_input, hal_ll_adc_resolution_t resolution, hal_ll_adc_handle_register_t *handle_map, uint8_t *hal_module_id) { + uint16_t pin_check_result; + hal_ll_adc_pin_id index = {HAL_LL_PIN_NC}; + + if ( (pin_check_result = hal_ll_adc_check_pins( pin, &index, handle_map )) == HAL_LL_PIN_NC ) { + return HAL_LL_ADC_WRONG_PIN; + }; + + switch ( resolution ) + { + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_AFEC_EMR_LOW_RES_MASK; + break; + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_AFEC_EMR_NO_AVERAGE_MASK; + break; + case HAL_LL_ADC_RESOLUTION_14_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_AFEC_EMR_OSR16; + break; + case HAL_LL_ADC_RESOLUTION_16_BIT: + hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_AFEC_EMR_OSR256; + break; + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + switch ( vref_input ) + { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_VREF; + } + + if ( hal_ll_adc_hw_specifics_map[pin_check_result].pin != pin ) + { + hal_ll_adc_map_pin( pin_check_result, &index ); + + handle_map[pin_check_result].init_ll_state = false; + } + + *hal_module_id = pin_check_result; + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + + handle_map[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_adc_handle; + return HAL_LL_ADC_SUCCESS; } hal_ll_err_t hal_ll_module_configure_adc( handle_t *handle ) { + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + hal_ll_adc_handle_register_t *hal_handle = (hal_ll_adc_handle_register_t *)*handle; + uint8_t pin_check_result = hal_ll_adc_hw_specifics_map_local->module_index; + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].init_ll_state = true; + hal_handle->init_ll_state = true; + return HAL_LL_ADC_SUCCESS; } hal_ll_err_t hal_ll_adc_set_resolution(handle_t *handle, hal_ll_adc_resolution_t resolution) { + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch ( resolution ) + { + case HAL_LL_ADC_RESOLUTION_10_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_AFEC_EMR_LOW_RES_MASK; + break; + case HAL_LL_ADC_RESOLUTION_12_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_AFEC_EMR_NO_AVERAGE_MASK; + break; + case HAL_LL_ADC_RESOLUTION_14_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_AFEC_EMR_OSR16; + break; + case HAL_LL_ADC_RESOLUTION_16_BIT: + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_AFEC_EMR_OSR256; + break; + default: + return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + return HAL_LL_ADC_SUCCESS; } hal_ll_err_t hal_ll_adc_set_vref_input(handle_t *handle, hal_ll_adc_voltage_reference_t vref_input) { + hal_ll_adc_handle_register_t *low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + + low_level_handle->init_ll_state = false; + + switch( vref_input ) { + case HAL_LL_ADC_VREF_EXTERNAL: + break; + + default: + return HAL_LL_ADC_UNSUPPORTED_VREF; + } + + hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); + + low_level_handle->init_ll_state = true; + return HAL_LL_ADC_SUCCESS; } void hal_ll_adc_set_vref_value(handle_t *handle, float vref_value) { + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + hal_ll_adc_hw_specifics_map_local->vref_value = vref_value; } hal_ll_err_t hal_ll_adc_read( handle_t *handle, uint16_t *readDatabuf ) { + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + hal_ll_adc_base_handle_t *afec_regs = ( hal_ll_adc_base_handle_t * )hal_ll_adc_hw_specifics_map_local->base ; + + set_reg_bit(&afec_regs->ier, hal_ll_adc_hw_specifics_map_local->channel); + set_reg_bits(&afec_regs->emr, 6 << HAL_LL_AFEC_EMR_CMPSEL_BIT); + set_reg_bit(&afec_regs->diffr, hal_ll_adc_hw_specifics_map_local->channel); + write_reg(&afec_regs->cselr, hal_ll_adc_hw_specifics_map_local->channel); + set_reg_bit(&afec_regs->cher, hal_ll_adc_hw_specifics_map_local->channel); + + // Enable ADC. + set_reg_bit( &afec_regs->cr, HAL_LL_AFEC_CR_START_BIT ); + + // The application should allow a delay of tSTAB between power up and start of conversion. + Delay_1us(); + + while ( !( check_reg_bit( &afec_regs->isr, hal_ll_adc_hw_specifics_map_local->channel ) ) ); + // Conversion result from AFEC_CRD. + // *readDatabuf = read_reg(&afec_regs->lcdr); + *readDatabuf = read_reg(&afec_regs->cdr); + return HAL_LL_ADC_SUCCESS; } void hal_ll_adc_close( handle_t *handle ) { + hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + low_level_handle = hal_ll_adc_get_handle; + + if( hal_ll_adc_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + + hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_DEFAULT; + hal_ll_adc_hw_specifics_map_local->vref_value = 0; + hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_AFEC_EMR_NO_AVERAGE_MASK; + + low_level_handle->hal_ll_adc_handle = NULL; + low_level_handle->hal_drv_adc_handle = NULL; + low_level_handle->init_ll_state = false; + + hal_ll_adc_hw_specifics_map_local->pin = HAL_LL_PIN_NC; + } } // ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS static hal_ll_pin_name_t hal_ll_adc_check_pins( hal_ll_pin_name_t pin, hal_ll_adc_pin_id *index, hal_ll_adc_handle_register_t *handle_map ) { + static const uint16_t adc_map_size = ( sizeof( _adc_map ) / sizeof( hal_ll_adc_pin_map_t ) ); + uint16_t pin_index = 0; + uint8_t index_counter = 0; + uint8_t hal_ll_module_id = 0; + + if ( HAL_LL_PIN_NC == pin ) { + return HAL_LL_PIN_NC; + } + + for ( pin_index = 0; pin_index < adc_map_size; pin_index++ ) + { + if ( pin == _adc_map[pin_index].pin ) + { + // Get module number + hal_ll_module_id = _adc_map[pin_index].module_index; + // Map pin name + index->pin_an[hal_ll_module_id] = pin_index; + + // Check if module is taken + if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_adc_handle ) { + return hal_ll_module_id; + } else if ( ADC_MODULE_COUNT == ++index_counter ) { + return --index_counter; + } + } + } + + if ( index_counter ) { + return hal_ll_module_id; + } else { return HAL_LL_PIN_NC; + } } -static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ) -{ +static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ) { + // Map new pins + hal_ll_adc_hw_specifics_map[module_index].pin = _adc_map[ index->pin_an[module_index] ].pin; + hal_ll_adc_hw_specifics_map[module_index].channel = _adc_map[ index->pin_an[module_index] ].channel; +} + +static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + while( hal_ll_module_count-- ) { + if (hal_ll_adc_get_base_from_hal_handle == hal_ll_adc_hw_specifics_map[hal_ll_module_count].base) { + return &hal_ll_adc_hw_specifics_map[hal_ll_module_count]; + } + } + + return &hal_ll_adc_hw_specifics_map[hal_ll_module_error]; } -static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) +static inline void adc0_enable_clock() { - + set_reg_bit( _PMC_PCER0, HAL_LL_PID_AFEC0_BIT ); } static inline void adc1_enable_clock() { - + set_reg_bit( _PMC_PCER1, HAL_LL_PID_AFEC1_BIT ); } -static inline void adc2_enable_clock() +static void _hal_ll_adc_enable_clock( uint8_t module_index ) { - + switch ( module_index ) + { + case ( hal_ll_adc_module_num( ADC_MODULE_0 ) ): + adc0_enable_clock(); + break; + case ( hal_ll_adc_module_num( ADC_MODULE_1 ) ): + adc1_enable_clock(); + break; + } } -static inline void adc3_enable_clock() +static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *afec_regs, uint32_t resolution ) { + set_reg_bit( &afec_regs->cr, HAL_LL_AFEC_CR_SWRST_BIT ); -} + write_reg( &afec_regs->emr, resolution ); -static void _hal_ll_adc_enable_clock( uint8_t base ) -{ + set_reg_bit( &afec_regs->mr, HAL_LL_AFEC_MR_ONE_BIT ); -} + set_reg_bit( &afec_regs->emr, HAL_LL_AFEC_EMR_STM_BIT ); -static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ) -{ + set_reg_bits( &afec_regs->emr, HAL_LL_AFEC_EMR_CMPMODE_OUT_MASK); + + set_reg_bits( &afec_regs->acr, HAL_LL_AFEC_ACR_PGAEN12_MASK); + // TODO SET PRESCALER!!! + set_reg_bit( &afec_regs->mr, 16 ); } -static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ) -{ +static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ) { + + hal_ll_gpio_analog_input( hal_ll_gpio_port_base( hal_ll_gpio_port_index( map->pin ) ), + hal_ll_gpio_pin_mask( map->pin ) ); + + _hal_ll_adc_enable_clock( map->module_index ); + + _hal_ll_adc_hw_init((hal_ll_adc_base_handle_t *)map->base, map->resolution); } // ------------------------------------------------------------------------- END From c9fef8b4b2da4b573ce4ed19d9ba0436dd2d3183 Mon Sep 17 00:00:00 2001 From: "ivan.ruzavin" Date: Thu, 21 Nov 2024 14:17:19 +0100 Subject: [PATCH 14/56] AFEC works and tested --- .../implementation_1/hal_ll_adc_pin_map.h | 6 +- .../implementation_1/hal_ll_adc.c | 93 ++++++++++--------- .../implementation_1/hal_ll_gpio_port.c | 4 +- 3 files changed, 51 insertions(+), 52 deletions(-) diff --git a/targets/arm/mikroe/sam/include/adc/hal_ll_adc_pin_map/implementations/implementation_1/hal_ll_adc_pin_map.h b/targets/arm/mikroe/sam/include/adc/hal_ll_adc_pin_map/implementations/implementation_1/hal_ll_adc_pin_map.h index 180bc0f1d..88a25668c 100644 --- a/targets/arm/mikroe/sam/include/adc/hal_ll_adc_pin_map/implementations/implementation_1/hal_ll_adc_pin_map.h +++ b/targets/arm/mikroe/sam/include/adc/hal_ll_adc_pin_map/implementations/implementation_1/hal_ll_adc_pin_map.h @@ -51,7 +51,7 @@ extern "C"{ #include "hal_ll_pin_names.h" /*!< @brief Helper macro for getting adequate module index number */ -#define hal_ll_adc_module_num(_module_num) (_module_num - 1) +#define hal_ll_adc_module_num(_module_num) (_module_num) /** * ADC channels. @@ -84,12 +84,8 @@ typedef struct } hal_ll_adc_pin_map_t; /*!< ADC module base addresses. */ -#ifdef ADC_MODULE_0 static const hal_ll_base_addr_t ADC0_BASE_ADDR = 0x4003C000; -#endif -#ifdef ADC_MODULE_1 static const hal_ll_base_addr_t ADC1_BASE_ADDR = 0x40064000; -#endif /*!< ADC input pins. */ static const hal_ll_adc_pin_map_t _adc_map[] = diff --git a/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c b/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c index 1d8ed1696..f3762572f 100644 --- a/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c +++ b/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c @@ -59,21 +59,22 @@ (((hal_ll_adc_handle_register_t *)(handle))->hal_ll_adc_handle))->hal_ll_adc_handle)->base /*!< @brief Helper macro for getting adequate module index number */ -#define hal_ll_adc_module_num(_module_num) (_module_num - 1) +#define hal_ll_adc_module_num(_module_num) (_module_num) #define HAL_LL_PID_AFEC1_BIT 8 #define HAL_LL_PID_AFEC0_BIT 29 #define HAL_LL_AFEC_CR_SWRST_BIT 0 #define HAL_LL_AFEC_CR_START_BIT 1 -#define HAL_LL_AFEC_MR_ONE_BIT 23 -#define HAL_LL_AFEC_EMR_CMPSEL_BIT 3 +#define HAL_LL_AFEC_EMR_CMPSEL_BIT 3 +#define HAL_LL_AFEC_MR_ONE_BIT 23 #define HAL_LL_AFEC_EMR_STM_BIT 25 -#define HAL_LL_AFEC_ACR_PGAEN12_MASK 0x0000000Cul -#define HAL_LL_AFEC_EMR_CMPMODE_OUT_MASK 0x00000003ul #define HAL_LL_AFEC_EMR_NO_AVERAGE_MASK 0x00000000ul +#define HAL_LL_AFEC_ACR_PGAEN12_MASK 0x0000000Cul +#define HAL_LL_AFEC_MR_PRESCAL_1_MASK 0x00000100ul +#define HAL_LL_AFEC_COCR_OFFSET_MASK 0x00000200ul #define HAL_LL_AFEC_EMR_LOW_RES_MASK 0x00010000ul #define HAL_LL_AFEC_EMR_OSR16 0x00030000ul #define HAL_LL_AFEC_EMR_OSR256 0x00050000ul @@ -90,7 +91,7 @@ static hal_ll_adc_handle_register_t hal_ll_module_state[ADC_MODULE_COUNT] = { (h typedef enum { HAL_LL_MODULE_ADC_DEFAULT = 0xFF, - HAL_LL_MODULE_ADC_0 = 1, + HAL_LL_MODULE_ADC_0 = 0, HAL_LL_MODULE_ADC_1 = 1, HAL_LL_MODULE_ADC_NONE @@ -240,12 +241,12 @@ static void _hal_ll_adc_enable_clock( uint8_t base ); static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolution ); // ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS -hal_ll_err_t hal_ll_adc_register_handle(hal_ll_pin_name_t pin, hal_ll_adc_voltage_reference_t vref_input, hal_ll_adc_resolution_t resolution, hal_ll_adc_handle_register_t *handle_map, uint8_t *hal_module_id) +hal_ll_err_t hal_ll_adc_register_handle( hal_ll_pin_name_t pin, hal_ll_adc_voltage_reference_t vref_input, hal_ll_adc_resolution_t resolution, hal_ll_adc_handle_register_t *handle_map, uint8_t *hal_module_id ) { uint16_t pin_check_result; hal_ll_adc_pin_id index = {HAL_LL_PIN_NC}; - if ( (pin_check_result = hal_ll_adc_check_pins( pin, &index, handle_map )) == HAL_LL_PIN_NC ) { + if ( ( pin_check_result = hal_ll_adc_check_pins( pin, &index, handle_map ) ) == HAL_LL_PIN_NC ) { return HAL_LL_ADC_WRONG_PIN; }; @@ -294,23 +295,23 @@ hal_ll_err_t hal_ll_adc_register_handle(hal_ll_pin_name_t pin, hal_ll_adc_voltag hal_ll_err_t hal_ll_module_configure_adc( handle_t *handle ) { - hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); - hal_ll_adc_handle_register_t *hal_handle = (hal_ll_adc_handle_register_t *)*handle; + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_adc_get_module_state_address ); + hal_ll_adc_handle_register_t *hal_handle = ( hal_ll_adc_handle_register_t *)*handle; uint8_t pin_check_result = hal_ll_adc_hw_specifics_map_local->module_index; hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local ); - hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].hal_ll_adc_handle = ( handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base; hal_ll_module_state[pin_check_result].init_ll_state = true; hal_handle->init_ll_state = true; return HAL_LL_ADC_SUCCESS; } -hal_ll_err_t hal_ll_adc_set_resolution(handle_t *handle, hal_ll_adc_resolution_t resolution) +hal_ll_err_t hal_ll_adc_set_resolution( handle_t *handle, hal_ll_adc_resolution_t resolution ) { low_level_handle = hal_ll_adc_get_handle; - hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_adc_get_module_state_address ); low_level_handle->init_ll_state = false; @@ -339,10 +340,10 @@ hal_ll_err_t hal_ll_adc_set_resolution(handle_t *handle, hal_ll_adc_resolution_t return HAL_LL_ADC_SUCCESS; } -hal_ll_err_t hal_ll_adc_set_vref_input(handle_t *handle, hal_ll_adc_voltage_reference_t vref_input) +hal_ll_err_t hal_ll_adc_set_vref_input( handle_t *handle, hal_ll_adc_voltage_reference_t vref_input ) { hal_ll_adc_handle_register_t *low_level_handle = hal_ll_adc_get_handle; - hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_adc_get_module_state_address ); low_level_handle->init_ll_state = false; @@ -361,36 +362,34 @@ hal_ll_err_t hal_ll_adc_set_vref_input(handle_t *handle, hal_ll_adc_voltage_refe return HAL_LL_ADC_SUCCESS; } -void hal_ll_adc_set_vref_value(handle_t *handle, float vref_value) +void hal_ll_adc_set_vref_value( handle_t *handle, float vref_value ) { low_level_handle = hal_ll_adc_get_handle; - hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_adc_get_module_state_address ); hal_ll_adc_hw_specifics_map_local->vref_value = vref_value; } hal_ll_err_t hal_ll_adc_read( handle_t *handle, uint16_t *readDatabuf ) { - hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); + hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_adc_get_module_state_address ); low_level_handle = hal_ll_adc_get_handle; hal_ll_adc_base_handle_t *afec_regs = ( hal_ll_adc_base_handle_t * )hal_ll_adc_hw_specifics_map_local->base ; - set_reg_bit(&afec_regs->ier, hal_ll_adc_hw_specifics_map_local->channel); - set_reg_bits(&afec_regs->emr, 6 << HAL_LL_AFEC_EMR_CMPSEL_BIT); - set_reg_bit(&afec_regs->diffr, hal_ll_adc_hw_specifics_map_local->channel); - write_reg(&afec_regs->cselr, hal_ll_adc_hw_specifics_map_local->channel); - set_reg_bit(&afec_regs->cher, hal_ll_adc_hw_specifics_map_local->channel); - - // Enable ADC. + // Start conversion. set_reg_bit( &afec_regs->cr, HAL_LL_AFEC_CR_START_BIT ); - // The application should allow a delay of tSTAB between power up and start of conversion. - Delay_1us(); - + // Wait till data is converted. while ( !( check_reg_bit( &afec_regs->isr, hal_ll_adc_hw_specifics_map_local->channel ) ) ); - // Conversion result from AFEC_CRD. - // *readDatabuf = read_reg(&afec_regs->lcdr); - *readDatabuf = read_reg(&afec_regs->cdr); + + // Select the desired channel. + write_reg( &afec_regs->cselr, hal_ll_adc_hw_specifics_map_local->channel ); + + // Select default offset for the converted data. + write_reg( &afec_regs->cocr, HAL_LL_AFEC_COCR_OFFSET_MASK ); + + // Read the conversion result from converted data register. + *readDatabuf = read_reg( &afec_regs->cdr ); return HAL_LL_ADC_SUCCESS; } @@ -400,7 +399,7 @@ void hal_ll_adc_close( handle_t *handle ) hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address); low_level_handle = hal_ll_adc_get_handle; - if( hal_ll_adc_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + if ( hal_ll_adc_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_DEFAULT; hal_ll_adc_hw_specifics_map_local->vref_value = 0; @@ -459,11 +458,11 @@ static void hal_ll_adc_map_pin( uint8_t module_index, hal_ll_adc_pin_id *index ) } static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { - uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); - static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t)); + uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_adc_handle_register_t ) ); + static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_adc_handle_register_t ) ); while( hal_ll_module_count-- ) { - if (hal_ll_adc_get_base_from_hal_handle == hal_ll_adc_hw_specifics_map[hal_ll_module_count].base) { + if ( hal_ll_adc_get_base_from_hal_handle == hal_ll_adc_hw_specifics_map[hal_ll_module_count].base ) { return &hal_ll_adc_hw_specifics_map[hal_ll_module_count]; } } @@ -473,12 +472,12 @@ static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { static inline void adc0_enable_clock() { - set_reg_bit( _PMC_PCER0, HAL_LL_PID_AFEC0_BIT ); + set_reg_bit( _PMC_PCER0, HAL_LL_PID_AFEC0_BIT ); } static inline void adc1_enable_clock() { - set_reg_bit( _PMC_PCER1, HAL_LL_PID_AFEC1_BIT ); + set_reg_bit( _PMC_PCER1, HAL_LL_PID_AFEC1_BIT ); } static void _hal_ll_adc_enable_clock( uint8_t module_index ) @@ -496,20 +495,26 @@ static void _hal_ll_adc_enable_clock( uint8_t module_index ) static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *afec_regs, uint32_t resolution ) { + // Reset the AFEC module. set_reg_bit( &afec_regs->cr, HAL_LL_AFEC_CR_SWRST_BIT ); - write_reg( &afec_regs->emr, resolution ); - + // This bit must be always written. set_reg_bit( &afec_regs->mr, HAL_LL_AFEC_MR_ONE_BIT ); + // Set requested resolution. + write_reg( &afec_regs->emr, resolution ); + + // Set the single trigger mode. set_reg_bit( &afec_regs->emr, HAL_LL_AFEC_EMR_STM_BIT ); - set_reg_bits( &afec_regs->emr, HAL_LL_AFEC_EMR_CMPMODE_OUT_MASK); + // Enable gain amplifier. + set_reg_bits( &afec_regs->acr, HAL_LL_AFEC_ACR_PGAEN12_MASK ); - set_reg_bits( &afec_regs->acr, HAL_LL_AFEC_ACR_PGAEN12_MASK); + // Enable comparison for the desired channel. + set_reg_bits( &afec_regs->emr, hal_ll_adc_hw_specifics_map_local->channel << HAL_LL_AFEC_EMR_CMPSEL_BIT ); - // TODO SET PRESCALER!!! - set_reg_bit( &afec_regs->mr, 16 ); + // Enable the desired channel. + set_reg_bit( &afec_regs->cher, hal_ll_adc_hw_specifics_map_local->channel ); } static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ) { @@ -519,7 +524,7 @@ static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ) { _hal_ll_adc_enable_clock( map->module_index ); - _hal_ll_adc_hw_init((hal_ll_adc_base_handle_t *)map->base, map->resolution); + _hal_ll_adc_hw_init( ( hal_ll_adc_base_handle_t *)map->base, map->resolution ); } // ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c b/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c index 418210e0f..6d6515531 100644 --- a/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c +++ b/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c @@ -221,10 +221,8 @@ static void hal_ll_gpio_config( hal_ll_gpio_base_t *port, hal_ll_gpio_mask_t pin } } else { - // Set to analog input without filtering. + // Set pin to analog. port_ptr->pio.disable = pin_mask; - port_ptr->output.disable = pin_mask; - port_ptr->filter.disable = pin_mask; } } From 6e1bec9426b3e7dd48d3cb6d8a1dae993a21c691 Mon Sep 17 00:00:00 2001 From: "ivan.ruzavin" Date: Thu, 21 Nov 2024 14:27:50 +0100 Subject: [PATCH 15/56] Removed mcu.h --- .../sam/src/adc/implementations/implementation_1/hal_ll_adc.c | 1 - 1 file changed, 1 deletion(-) diff --git a/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c b/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c index f3762572f..53a371b17 100644 --- a/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c +++ b/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c @@ -45,7 +45,6 @@ #include "hal_ll_gpio.h" #include "hal_ll_adc_pin_map.h" #include "delays.h" -#include "mcu.h" // ------------------------------------------------------------- PRIVATE MACROS /*!< @brief Helper macro for getting hal_ll_module_state address */ From eefe6db54f53bdeca910eade849d4b37d9020fbd Mon Sep 17 00:00:00 2001 From: "ivan.ruzavin" Date: Fri, 22 Nov 2024 08:30:37 +0100 Subject: [PATCH 16/56] Updated according to new defs --- .../SAM/ATSAME70Q21B/LQFP144/mcu_definitions.h | 2 +- .../implementations/implementation_1/hal_ll_uart.c | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21B/LQFP144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21B/LQFP144/mcu_definitions.h index 8b5ad12a2..8383ecee6 100644 --- a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21B/LQFP144/mcu_definitions.h +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21B/LQFP144/mcu_definitions.h @@ -164,7 +164,7 @@ extern "C"{ #define UART_MODULE_3 (3) #define UART_MODULE_4 (4) -#define UART_MODULE_COUNT (8) +#define UART_MODULE_COUNT (5) //EOF UART //SPI diff --git a/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c b/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c index 170902760..fdc10e291 100644 --- a/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c +++ b/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c @@ -50,7 +50,7 @@ #include "mcu.h" /*!< @brief Local handle list */ -static volatile hal_ll_uart_handle_register_t hal_ll_module_state[UART_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; +static volatile hal_ll_uart_handle_register_t hal_ll_module_state[UART_MODULE_COUNT + USART_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; // ------------------------------------------------------------- PRIVATE MACROS @@ -84,7 +84,7 @@ static volatile hal_ll_uart_handle_register_t hal_ll_module_state[UART_MODULE_CO #define HAL_LL_CR_RXEN_BIT 4 #define HAL_LL_CR_RXDIS_BIT 5 -#define HAL_LL_CR_TXEN_BIT 6 +#define HAL_LL_CR_TXEN_BIT 6 #define HAL_LL_CR_TXDIS_BIT 7 #define HAL_LL_UART_IER_RXRDY_BIT 0 @@ -201,7 +201,7 @@ static volatile hal_ll_uart_hw_specifics_map_t *hal_ll_uart_hw_specifics_map_loc /*!< @brief Global interrupt handlers used in functions */ static hal_ll_uart_isr_t irq_handler; -static handle_t objects[UART_MODULE_COUNT]; +static handle_t objects[UART_MODULE_COUNT + USART_MODULE_COUNT]; // ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS /** @@ -433,7 +433,7 @@ static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ); // ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS hal_ll_err_t hal_ll_uart_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_handle_register_t *handle_map, uint8_t *hal_module_id ) { - hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT + USART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; uint16_t pin_check_result; // Check if pins are valid @@ -464,7 +464,7 @@ hal_ll_err_t hal_ll_uart_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_n hal_ll_err_t hal_ll_module_configure_uart( handle_t *handle ) { hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); - hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT + USART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; uint16_t pin_check_result; if ( (pin_check_result = hal_ll_uart_check_pins( hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name, @@ -865,7 +865,7 @@ static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_l // Check if module is taken if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_uart_handle ) { return hal_ll_module_id; - } else if ( UART_MODULE_COUNT == ++index_counter ) { + } else if ( ( UART_MODULE_COUNT + USART_MODULE_COUNT ) == ++index_counter ) { return --index_counter; } } From e99022330d3f97b89375b9ac012a53e9bd2387c7 Mon Sep 17 00:00:00 2001 From: "ivan.ruzavin" Date: Fri, 22 Nov 2024 09:27:42 +0100 Subject: [PATCH 17/56] Prepared defs for comparison --- .../ATSAME70Q21B/LQFP144/mcu_definitions.h | 60 +++++++++---------- 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21B/LQFP144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21B/LQFP144/mcu_definitions.h index 8383ecee6..c9be10acd 100644 --- a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21B/LQFP144/mcu_definitions.h +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21B/LQFP144/mcu_definitions.h @@ -48,7 +48,7 @@ extern "C"{ #endif -//ADC +// ADC #define ADC0_PD30_CH0 #define ADC0_PA21_CH1 #define ADC0_PB3_CH2 @@ -77,47 +77,47 @@ extern "C"{ #define ADC_MODULE_1 (1) #define ADC_MODULE_COUNT (2) -//EOF ADC +// EOF ADC -//I2C -#define I2C0_SDA_PA3_AFA +// I2C #define I2C0_SCL_PA4_AFA -#define I2C1_SDA_PB4_AFA +#define I2C0_SDA_PA3_AFA #define I2C1_SCL_PB5_AFA -#define I2C2_SDA_PD27_AFC +#define I2C1_SDA_PB4_AFA #define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC #define I2C_MODULE_0 (0) #define I2C_MODULE_1 (1) #define I2C_MODULE_2 (2) #define I2C_MODULE_COUNT (3) -//EOF I2C +// EOF I2C -//TIM +// TIM #define TIM0_CH0_A_PA0_AFB -#define TIM0_CH0_B_PA1_AFB #define TIM0_CH1_A_PA15_AFB -#define TIM0_CH1_B_PA16_AFB #define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB #define TIM0_CH2_B_PA27_AFB #define TIM1_CH0_A_PC23_AFB -#define TIM1_CH0_B_PC24_AFB #define TIM1_CH1_A_PC26_AFB -#define TIM1_CH1_B_PC27_AFB #define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB #define TIM1_CH2_B_PC30_AFB #define TIM2_CH0_A_PC5_AFB -#define TIM2_CH0_B_PC6_AFB #define TIM2_CH1_A_PC8_AFB -#define TIM2_CH1_B_PC9_AFB #define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB #define TIM2_CH2_B_PC12_AFB #define TIM3_CH0_A_PE0_AFB -#define TIM3_CH0_B_PE1_AFB #define TIM3_CH1_A_PE3_AFB -#define TIM3_CH1_B_PE4_AFB #define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB #define TIM3_CH2_B_PD22_AFC #define TIM_MODULE_0 (0) @@ -127,9 +127,9 @@ extern "C"{ #define TIM_CHANNEL_NUMBER (3) #define TIM_MODULE_COUNT (4) -//EOF TIM +// EOF TIM -//USART +// USART #define USART0_RX_PB0_AFC #define USART0_TX_PB1_AFC #define USART1_RX_PA21_AFC @@ -142,9 +142,9 @@ extern "C"{ #define USART_MODULE_2 (2) #define USART_MODULE_COUNT (3) -//EOF USART +// EOF USART -//UART +// UART #define UART0_RX_PA9_AFA #define UART0_TX_PA10_AFA #define UART1_RX_PA5_AFC @@ -165,9 +165,9 @@ extern "C"{ #define UART_MODULE_4 (4) #define UART_MODULE_COUNT (5) -//EOF UART +// EOF UART -//SPI +// SPI #define SPI0_MISO_PD20_AFB #define SPI0_MOSI_PD21_AFB #define SPI0_SCK_PD22_AFB @@ -179,9 +179,9 @@ extern "C"{ #define SPI_MODULE_1 (1) #define SPI_MODULE_COUNT (2) -//EOF SPI +// EOF SPI -//GPIO +// GPIO #define __PA0_CN #define __PA1_CN #define __PA2_CN @@ -304,19 +304,19 @@ extern "C"{ #define __PORT_E_CN #define PORT_COUNT (5) -#define PORT_SIZE (32) -//EOF GPIO +#define PORT_SIZE (32) +// EOF GPIO -//IVT Table +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) #define USART0_NVIC (13) #define USART1_NVIC (14) #define USART2_NVIC (15) -#define UART0_NVIC (7) -#define UART1_NVIC (8) #define UART2_NVIC (44) #define UART3_NVIC (45) #define UART4_NVIC (46) -//EOF IVT Table +// EOF IVT Table #ifdef __cplusplus } From ee0073050d77abf853d0ee1885defb9d5f344584 Mon Sep 17 00:00:00 2001 From: "ivan.ruzavin" Date: Fri, 22 Nov 2024 11:43:53 +0100 Subject: [PATCH 18/56] Added ifdefs for modules --- .../implementation_1/hal_ll_adc_pin_map.h | 54 ++++---- .../implementation_1/hal_ll_i2c_pin_map.h | 6 + .../hal_ll_spi_master_pin_map.h | 14 +- .../implementation_1/hal_ll_tim_pin_map.h | 8 ++ .../implementation_1/hal_ll_uart_pin_map.h | 16 +++ targets/arm/mikroe/sam/src/adc/CMakeLists.txt | 2 +- .../implementation_1/hal_ll_adc.c | 12 +- .../arm/mikroe/sam/src/gpio/CMakeLists.txt | 2 +- .../implementation_1/hal_ll_gpio_port.c | 40 +++++- targets/arm/mikroe/sam/src/i2c/CMakeLists.txt | 2 +- .../implementation_1/hal_ll_i2c_master.c | 12 ++ .../mikroe/sam/src/one_wire/CMakeLists.txt | 2 +- .../mikroe/sam/src/spi_master/CMakeLists.txt | 6 +- .../implementation_1/hal_ll_spi_master.c | 29 +++- targets/arm/mikroe/sam/src/tim/CMakeLists.txt | 2 +- .../implementation_1/hal_ll_tim.c | 16 +++ .../arm/mikroe/sam/src/uart/CMakeLists.txt | 2 +- .../implementation_1/hal_ll_uart.c | 128 ++++++++++++++---- 18 files changed, 280 insertions(+), 73 deletions(-) diff --git a/targets/arm/mikroe/sam/include/adc/hal_ll_adc_pin_map/implementations/implementation_1/hal_ll_adc_pin_map.h b/targets/arm/mikroe/sam/include/adc/hal_ll_adc_pin_map/implementations/implementation_1/hal_ll_adc_pin_map.h index 88a25668c..c48db748e 100644 --- a/targets/arm/mikroe/sam/include/adc/hal_ll_adc_pin_map/implementations/implementation_1/hal_ll_adc_pin_map.h +++ b/targets/arm/mikroe/sam/include/adc/hal_ll_adc_pin_map/implementations/implementation_1/hal_ll_adc_pin_map.h @@ -84,35 +84,39 @@ typedef struct } hal_ll_adc_pin_map_t; /*!< ADC module base addresses. */ -static const hal_ll_base_addr_t ADC0_BASE_ADDR = 0x4003C000; -static const hal_ll_base_addr_t ADC1_BASE_ADDR = 0x40064000; +#ifdef ADC_MODULE_0 +static const hal_ll_base_addr_t HAL_LL_ADC0_BASE_ADDR = 0x4003C000; +#endif +#ifdef ADC_MODULE_1 +static const hal_ll_base_addr_t HAL_LL_ADC1_BASE_ADDR = 0x40064000; +#endif /*!< ADC input pins. */ static const hal_ll_adc_pin_map_t _adc_map[] = { - {PD30, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_0}, - {PA21, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_1}, - {PB3, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_2}, - {PE5, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_3}, - {PE4, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_4}, - {PB2, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_5}, - {PA17, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_6}, - {PA18, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_7}, - {PA19, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_8}, - {PA20, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_9}, - {PB0, ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_10}, - {PB1, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_0}, - {PC13, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_1}, - {PC15, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_2}, - {PC12, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_3}, - {PC29, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_4}, - {PC30, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_5}, - {PC31, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_6}, - {PC26, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_7}, - {PC27, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_8}, - {PC0, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_9}, - {PE3, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_10}, - {PE0, ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_11}, + {PD30, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_0}, + {PA21, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_1}, + {PB3, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_2}, + {PE5, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_3}, + {PE4, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_4}, + {PB2, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_5}, + {PA17, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_6}, + {PA18, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_7}, + {PA19, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_8}, + {PA20, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_9}, + {PB0, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_10}, + {PB1, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_0}, + {PC13, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_1}, + {PC15, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_2}, + {PC12, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_3}, + {PC29, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_4}, + {PC30, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_5}, + {PC31, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_6}, + {PC26, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_7}, + {PC27, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_8}, + {PC0, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_9}, + {PE3, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_10}, + {PE0, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_11}, {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_CHANNEL_ERROR} }; diff --git a/targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_pin_map/implementations/implementation_1/hal_ll_i2c_pin_map.h b/targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_pin_map/implementations/implementation_1/hal_ll_i2c_pin_map.h index 7c326ec40..b511763fd 100644 --- a/targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_pin_map/implementations/implementation_1/hal_ll_i2c_pin_map.h +++ b/targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_pin_map/implementations/implementation_1/hal_ll_i2c_pin_map.h @@ -62,9 +62,15 @@ typedef struct uint8_t af; } hal_ll_i2c_pin_map_t; +#ifdef I2C_MODULE_0 #define HAL_LL_I2C0_BASE_ADDRESS (0x40018000UL) +#endif +#ifdef I2C_MODULE_1 #define HAL_LL_I2C1_BASE_ADDRESS (0x4001C000UL) +#endif +#ifdef I2C_MODULE_2 #define HAL_LL_I2C2_BASE_ADDRESS (0x40060000UL) +#endif /*!< @brief I2C SCL pins */ static const hal_ll_i2c_pin_map_t hal_ll_i2c_scl_map[] = diff --git a/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master_pin_map/implementations/implementation_1/hal_ll_spi_master_pin_map.h b/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master_pin_map/implementations/implementation_1/hal_ll_spi_master_pin_map.h index 4077f5dd7..4d73df4c7 100644 --- a/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master_pin_map/implementations/implementation_1/hal_ll_spi_master_pin_map.h +++ b/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master_pin_map/implementations/implementation_1/hal_ll_spi_master_pin_map.h @@ -57,8 +57,16 @@ extern "C"{ #define __weak __attribute__((weak)) /*!< SPI module base addresses. */ +#ifdef QSPI_SPI +static const hal_ll_base_addr_t HAL_LL_SPI0_MASTER_BASE_ADDR = 0x4007C000; +#else +#ifdef SPI_MODULE_0 static const hal_ll_base_addr_t HAL_LL_SPI0_MASTER_BASE_ADDR = 0x40008000; +#endif +#ifdef SPI_MODULE_1 static const hal_ll_base_addr_t HAL_LL_SPI1_MASTER_BASE_ADDR = 0x40058000; +#endif +#endif /*!< @brief Pin function structure. */ typedef struct @@ -72,7 +80,7 @@ typedef struct /*!< @brief SPI SCK pins. */ static const hal_ll_spi_master_pin_map_t _spi_sck_map[] = { - {PD22, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 1}, + {PA14, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 0}, {PC24, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 2}, {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} }; @@ -80,7 +88,7 @@ static const hal_ll_spi_master_pin_map_t _spi_sck_map[] = /*!< @brief SPI MISO pins. */ static const hal_ll_spi_master_pin_map_t _spi_miso_map[] = { - {PD20, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 1}, + {PA12, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 0}, {PC26, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 2}, {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} }; @@ -88,7 +96,7 @@ static const hal_ll_spi_master_pin_map_t _spi_miso_map[] = /*!< @brief SPI MOSI pins. */ static const hal_ll_spi_master_pin_map_t _spi_mosi_map[] = { - {PD21, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 1}, + {PA13, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 0}, {PC27, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 2}, {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} }; diff --git a/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/implementation_1/hal_ll_tim_pin_map.h b/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/implementation_1/hal_ll_tim_pin_map.h index d341a28c3..9e29d4f1f 100644 --- a/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/implementation_1/hal_ll_tim_pin_map.h +++ b/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/implementation_1/hal_ll_tim_pin_map.h @@ -70,10 +70,18 @@ typedef enum HAL_LL_TIM_CHANNEL_2 } hal_ll_tim_channel_t; +#ifdef TIM_MODULE_0 #define HAL_LL_TIM0_BASE_ADDRESS (0x4000C000UL) +#endif +#ifdef TIM_MODULE_1 #define HAL_LL_TIM1_BASE_ADDRESS (0x40010000UL) +#endif +#ifdef TIM_MODULE_2 #define HAL_LL_TIM2_BASE_ADDRESS (0x40014000UL) +#endif +#ifdef TIM_MODULE_3 #define HAL_LL_TIM3_BASE_ADDRESS (0x40054000UL) +#endif #define HAL_LL_ALTERNATE_FUNCTION_MASK 0x0F #define HAL_LL_SIGNAL_CHANNEL_AB_MASK 0xF0 diff --git a/targets/arm/mikroe/sam/include/uart/hal_ll_uart_pin_map/implementations/implementation_1/hal_ll_uart_pin_map.h b/targets/arm/mikroe/sam/include/uart/hal_ll_uart_pin_map/implementations/implementation_1/hal_ll_uart_pin_map.h index ab01323cc..f54b741a8 100644 --- a/targets/arm/mikroe/sam/include/uart/hal_ll_uart_pin_map/implementations/implementation_1/hal_ll_uart_pin_map.h +++ b/targets/arm/mikroe/sam/include/uart/hal_ll_uart_pin_map/implementations/implementation_1/hal_ll_uart_pin_map.h @@ -63,14 +63,30 @@ typedef struct uint8_t af; } hal_ll_uart_pin_map_t; +#ifdef USART_MODULE_0 #define HAL_LL_USART0_BASE_ADDRESS 0x40024000UL +#endif +#ifdef USART_MODULE_1 #define HAL_LL_USART1_BASE_ADDRESS 0x40028000UL +#endif +#ifdef USART_MODULE_2 #define HAL_LL_USART2_BASE_ADDRESS 0x4002C000UL +#endif +#ifdef UART_MODULE_0 #define HAL_LL_UART0_BASE_ADDRESS 0x400E0800UL +#endif +#ifdef UART_MODULE_1 #define HAL_LL_UART1_BASE_ADDRESS 0x400E0A00UL +#endif +#ifdef UART_MODULE_2 #define HAL_LL_UART2_BASE_ADDRESS 0x400E1A00UL +#endif +#ifdef UART_MODULE_3 #define HAL_LL_UART3_BASE_ADDRESS 0x400E1C00UL +#endif +#ifdef UART_MODULE_4 #define HAL_LL_UART4_BASE_ADDRESS 0x400E1E00UL +#endif /*!< @brief UART TX pins */ static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = diff --git a/targets/arm/mikroe/sam/src/adc/CMakeLists.txt b/targets/arm/mikroe/sam/src/adc/CMakeLists.txt index a8e1aaf8d..fa26a3159 100644 --- a/targets/arm/mikroe/sam/src/adc/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/adc/CMakeLists.txt @@ -11,7 +11,7 @@ set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_ ##BEGIN ADC list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_12_BIT") -if (${MCU_NAME} MATCHES "^ATSAME7.+") +if (${MCU_NAME} MATCHES "^ATSAM[ESV]7.+") set(adc_subimplementation "implementations/implementation_1") endif() ##END ADC diff --git a/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c b/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c index 53a371b17..19244f223 100644 --- a/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c +++ b/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c @@ -149,8 +149,12 @@ typedef struct static hal_ll_adc_hw_specifics_map_t hal_ll_adc_hw_specifics_map[] = { - {ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, - {ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #ifdef ADC_MODULE_0 + {HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif + #ifdef ADC_MODULE_1 + {HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF}, + #endif {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF} }; @@ -483,12 +487,16 @@ static void _hal_ll_adc_enable_clock( uint8_t module_index ) { switch ( module_index ) { + #ifdef ADC_MODULE_0 case ( hal_ll_adc_module_num( ADC_MODULE_0 ) ): adc0_enable_clock(); break; + #endif + #ifdef ADC_MODULE_1 case ( hal_ll_adc_module_num( ADC_MODULE_1 ) ): adc1_enable_clock(); break; + #endif } } diff --git a/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt b/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt index 723c95109..4fafdb8c0 100644 --- a/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt @@ -9,7 +9,7 @@ list(APPEND hal_ll_def_list "MACRO_USAGE_GPIO") set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) ## BEGIN GPIO -if(${MCU_NAME} MATCHES "^ATSAME7.+") +if(${MCU_NAME} MATCHES "^ATSAM[ESV]7.+") set(gpio_subimplementation "implementations/implementation_1") endif() ## END GPIO diff --git a/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c b/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c index 6d6515531..a59f7416b 100644 --- a/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c +++ b/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c @@ -55,17 +55,27 @@ * Defines used in source */ // GPIO Register addresses and offsets +#ifdef __PORT_A_CN #define HAL_LL_GPIOA_BASE_ADDR 0x400E0E00UL -#define HAL_LL_GPIOB_BASE_ADDR 0x400E1000UL -#define HAL_LL_GPIOC_BASE_ADDR 0x400E1200UL -#define HAL_LL_GPIOD_BASE_ADDR 0x400E1400UL -#define HAL_LL_GPIOE_BASE_ADDR 0x400E1600UL - #define HAL_LL_PMC_ID_PIOA_BIT 0x0A +#endif +#ifdef __PORT_B_CN +#define HAL_LL_GPIOB_BASE_ADDR 0x400E1000UL #define HAL_LL_PMC_ID_PIOB_BIT 0x0B +#endif +#ifdef __PORT_C_CN +#define HAL_LL_GPIOC_BASE_ADDR 0x400E1200UL #define HAL_LL_PMC_ID_PIOC_BIT 0x0C +#endif +#ifdef __PORT_D_CN +#define HAL_LL_GPIOD_BASE_ADDR 0x400E1400UL #define HAL_LL_PMC_ID_PIOD_BIT 0x10 +#endif +#ifdef __PORT_E_CN +#define HAL_LL_GPIOE_BASE_ADDR 0x400E1600UL #define HAL_LL_PMC_ID_PIOE_BIT 0x11 +#endif + #define HAL_LL_PERIPHERAL_A 0 #define HAL_LL_PERIPHERAL_B 1 @@ -77,11 +87,21 @@ /*!< @brief GPIO PORT array */ static const uint32_t _hal_ll_gpio_port_base [ 5 ] = { + #ifdef __PORT_A_CN HAL_LL_GPIOA_BASE_ADDR, + #endif + #ifdef __PORT_B_CN HAL_LL_GPIOB_BASE_ADDR, + #endif + #ifdef __PORT_C_CN HAL_LL_GPIOC_BASE_ADDR, + #endif + #ifdef __PORT_D_CN HAL_LL_GPIOD_BASE_ADDR, + #endif + #ifdef __PORT_E_CN HAL_LL_GPIOE_BASE_ADDR + #endif }; // ----------------------------------------------- PRIVATE FUNCTION DECLARATIONS @@ -184,11 +204,21 @@ static void hal_ll_gpio_clock_enable( hal_ll_gpio_base_t *port ) switch ( ( uint32_t )port ) { + #ifdef __PORT_A_CN case HAL_LL_GPIOA_BASE_ADDR: pos = HAL_LL_PMC_ID_PIOA_BIT; break; + #endif + #ifdef __PORT_B_CN case HAL_LL_GPIOB_BASE_ADDR: pos = HAL_LL_PMC_ID_PIOB_BIT; break; + #endif + #ifdef __PORT_C_CN case HAL_LL_GPIOC_BASE_ADDR: pos = HAL_LL_PMC_ID_PIOC_BIT; break; + #endif + #ifdef __PORT_D_CN case HAL_LL_GPIOD_BASE_ADDR: pos = HAL_LL_PMC_ID_PIOD_BIT; break; + #endif + #ifdef __PORT_E_CN case HAL_LL_GPIOE_BASE_ADDR: pos = HAL_LL_PMC_ID_PIOE_BIT; break; + #endif } set_reg_bit( _PMC_PCER0, pos ); diff --git a/targets/arm/mikroe/sam/src/i2c/CMakeLists.txt b/targets/arm/mikroe/sam/src/i2c/CMakeLists.txt index 5226a7c36..16db385fb 100644 --- a/targets/arm/mikroe/sam/src/i2c/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/i2c/CMakeLists.txt @@ -8,7 +8,7 @@ list(APPEND hal_ll_def_list ${MCU_NAME}) list(APPEND hal_ll_def_list "MACRO_USAGE_I2C") set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) -if(${MCU_NAME} MATCHES "^ATSAME7.+") +if(${MCU_NAME} MATCHES "^ATSAM[ESV]7.+") set(i2c_subimplementation "implementations/implementation_1") endif() diff --git a/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c b/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c index 24a9078e2..d576ddd57 100644 --- a/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c +++ b/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c @@ -194,9 +194,15 @@ typedef enum /*!< @brief I2C hardware specific info */ static hal_ll_i2c_hw_specifics_map_t hal_ll_i2c_hw_specifics_map[] = { + #ifdef I2C_MODULE_0 {HAL_LL_I2C0_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_0), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + #ifdef I2C_MODULE_1 {HAL_LL_I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif + #ifdef I2C_MODULE_2 {HAL_LL_I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, HAL_LL_I2C_MASTER_SPEED_100K , 0, HAL_LL_I2C_DEFAULT_PASS_COUNT}, + #endif {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, 0, 0, 0} }; @@ -734,6 +740,7 @@ static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, bool hal_ll_state ) { switch ( map->module_index ) { + #ifdef I2C_MODULE_0 case ( hal_ll_i2c_module_num( I2C_MODULE_0 ) ): if ( hal_ll_state ) { set_reg_bit( _PMC_PCER0, HAL_LL_PID_TWIHS0_BIT ); @@ -741,6 +748,8 @@ static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, boo set_reg_bit( _PMC_PCDR0, HAL_LL_PID_TWIHS0_BIT ); } break; + #endif + #ifdef I2C_MODULE_1 case ( hal_ll_i2c_module_num( I2C_MODULE_1 ) ): if ( hal_ll_state ) { set_reg_bit( _PMC_PCER0, HAL_LL_PID_TWIHS1_BIT ); @@ -748,6 +757,8 @@ static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, boo set_reg_bit( _PMC_PCDR0, HAL_LL_PID_TWIHS1_BIT ); } break; + #endif + #ifdef I2C_MODULE_2 case ( hal_ll_i2c_module_num( I2C_MODULE_2 ) ): if ( hal_ll_state ) { set_reg_bit( _PMC_PCER1, HAL_LL_PID_TWIHS2_BIT ); @@ -755,6 +766,7 @@ static void hal_ll_i2c_master_set_clock( hal_ll_i2c_hw_specifics_map_t *map, boo set_reg_bit( _PMC_PCDR1, HAL_LL_PID_TWIHS2_BIT ); } break; + #endif default: break; diff --git a/targets/arm/mikroe/sam/src/one_wire/CMakeLists.txt b/targets/arm/mikroe/sam/src/one_wire/CMakeLists.txt index dc0e4fded..ac96bc0fd 100644 --- a/targets/arm/mikroe/sam/src/one_wire/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/one_wire/CMakeLists.txt @@ -6,7 +6,7 @@ list(APPEND hal_ll_def_list ${MCU_NAME}) list(APPEND hal_ll_def_list "MACRO_USAGE_ONE_WIRE") set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) -if(${MCU_NAME} MATCHES "^ATSAME7.+") +if(${MCU_NAME} MATCHES "^ATSAM[ESV]7.+") set(ow_subimplementation "implementations/implementation_1") endif() diff --git a/targets/arm/mikroe/sam/src/spi_master/CMakeLists.txt b/targets/arm/mikroe/sam/src/spi_master/CMakeLists.txt index 68960db35..77a2d3e83 100644 --- a/targets/arm/mikroe/sam/src/spi_master/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/spi_master/CMakeLists.txt @@ -8,7 +8,11 @@ list(APPEND hal_ll_def_list ${MCU_NAME}) list(APPEND hal_ll_def_list "MACRO_USAGE_SPI") set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) -if (${MCU_NAME} MATCHES "^ATSAME7.+") +if (${MCU_NAME} MATCHES "^ATSAM[ESV]7.+") + string(SUBSTRING ${MCU_NAME} 8 10 CMAKE_MCU_NAME_LAST_3) + if (${CMAKE_MCU_NAME_LAST_3} MATCHES "J[19|2[01]") + list(APPEND hal_ll_def_list "QSPI_SPI") + endif() set(spi_subimplementation "implementations/implementation_1") endif() diff --git a/targets/arm/mikroe/sam/src/spi_master/implementations/implementation_1/hal_ll_spi_master.c b/targets/arm/mikroe/sam/src/spi_master/implementations/implementation_1/hal_ll_spi_master.c index 410815157..abfd2b676 100644 --- a/targets/arm/mikroe/sam/src/spi_master/implementations/implementation_1/hal_ll_spi_master.c +++ b/targets/arm/mikroe/sam/src/spi_master/implementations/implementation_1/hal_ll_spi_master.c @@ -103,8 +103,10 @@ typedef struct { uint32_t ier; uint32_t idr; uint32_t imr; + #ifndef QSPI_SPI uint32_t _unused[4]; - uint32_t csr[4]; + #endif + uint32_t csr; } hal_ll_spi_master_base_handle_t; /*!< @brief SPI Master hardware specific structure */ @@ -139,8 +141,12 @@ typedef enum { /*!< @brief SPI Master hardware specific info */ static hal_ll_spi_master_hw_specifics_map_t hal_ll_spi_master_hw_specifics_map[] = { + #ifdef SPI_MODULE_0 { HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num( SPI_MODULE_0 ), { HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0 }, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT }, + #endif + #ifdef SPI_MODULE_1 { HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num( SPI_MODULE_1 ), { HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0 }, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT }, + #endif { HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, { HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0 }, 0, 0, 0, 0 } }; @@ -575,12 +581,16 @@ static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics( handle_t hand static void hal_ll_spi_master_set_clock( hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state, uint32_t *clock_value ) { switch ( map->module_index ) { + #ifdef SPI_MODULE_0 case ( hal_ll_spi_master_module_num( SPI_MODULE_0 ) ): ( hal_ll_state == true )?( set_reg_bit( _PMC_PCER0, HAL_LL_PID_SPI0_BIT ) ):( set_reg_bit( _PMC_PCDR0, HAL_LL_PID_SPI0_BIT ) ); break; + #endif + #ifdef SPI_MODULE_1 case ( hal_ll_spi_master_module_num( SPI_MODULE_1 ) ): ( hal_ll_state == true )?( set_reg_bit( _PMC_PCER1, HAL_LL_PID_SPI1_BIT ) ):( set_reg_bit( _PMC_PCDR1, HAL_LL_PID_SPI1_BIT ) ); break; + #endif } @@ -616,20 +626,20 @@ static uint32_t hal_ll_spi_master_hw_init( hal_ll_spi_master_hw_specifics_map_t // Populate appropriate register values to get appropriate data transfer baud rate prescalers. divider = hal_ll_spi_master_get_divider( clock_value, map->speed ); - write_reg( &hal_ll_hw_reg->csr[0], divider << HAL_LL_SPI_CSR_SCBR_START_BIT ); + write_reg( &hal_ll_hw_reg->csr, divider << HAL_LL_SPI_CSR_SCBR_START_BIT ); // Choose whether idle state for the clock is high level (1) or low level (0). if ( map->mode <= HAL_LL_SPI_MASTER_MODE_1 ) { - clear_reg_bit( &hal_ll_hw_reg->csr[0], HAL_LL_SPI_CSR_CPOL_BIT ); + clear_reg_bit( &hal_ll_hw_reg->csr, HAL_LL_SPI_CSR_CPOL_BIT ); } else { - set_reg_bit( &hal_ll_hw_reg->csr[0], HAL_LL_SPI_CSR_CPOL_BIT ); + set_reg_bit( &hal_ll_hw_reg->csr, HAL_LL_SPI_CSR_CPOL_BIT ); } // Choose whether transmit occurs on the transition from ACTIVE to IDLE (1), or vice versa (0). if ( map->mode == HAL_LL_SPI_MASTER_MODE_0 || map->mode == HAL_LL_SPI_MASTER_MODE_2 ) { - set_reg_bit( &hal_ll_hw_reg->csr[0], HAL_LL_SPI_CSR_NCPHA_BIT ); + set_reg_bit( &hal_ll_hw_reg->csr, HAL_LL_SPI_CSR_NCPHA_BIT ); } else { - clear_reg_bit( &hal_ll_hw_reg->csr[0], HAL_LL_SPI_CSR_NCPHA_BIT ); + clear_reg_bit( &hal_ll_hw_reg->csr, HAL_LL_SPI_CSR_NCPHA_BIT ); } // Enable variable peripheral select. @@ -641,11 +651,16 @@ static uint32_t hal_ll_spi_master_hw_init( hal_ll_spi_master_hw_specifics_map_t // Enable independant CS lines. set_reg_bits( &hal_ll_hw_reg->mr, HAL_LL_SPI_MR_PCS_MASK ); + #ifdef QSPI_SPI + // Configure QSPI in SPI mode + clear_reg_bit( &hal_ll_hw_reg->mr, HAL_LL_SPI_MR_MSTR_BIT ); + #else // Configure SPI in Host mode. set_reg_bit( &hal_ll_hw_reg->mr, HAL_LL_SPI_MR_MSTR_BIT ); + #endif // Set FIFO reception threshold to 8-bit. - clear_reg_bits( &hal_ll_hw_reg->csr[0], HAL_LL_CSR_BITS_MASK ); + clear_reg_bits( &hal_ll_hw_reg->csr, HAL_LL_CSR_BITS_MASK ); // Enable SPI peripheral. set_reg_bit( &hal_ll_hw_reg->cr, HAL_LL_SPI_CR_SPIEN_BIT ); diff --git a/targets/arm/mikroe/sam/src/tim/CMakeLists.txt b/targets/arm/mikroe/sam/src/tim/CMakeLists.txt index 88d04ec99..853de6e6d 100644 --- a/targets/arm/mikroe/sam/src/tim/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/tim/CMakeLists.txt @@ -9,7 +9,7 @@ list(APPEND hal_ll_def_list "MACRO_USAGE_TIM") set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) ## BEGIN TIM -if (${MCU_NAME} MATCHES "^ATSAME7.+") +if (${MCU_NAME} MATCHES "^ATSAM[ESV]7.+") set(tim_subimplementation "implementations/implementation_1") endif() ## END TIM diff --git a/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c b/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c index f4d8df300..3850deae6 100644 --- a/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c +++ b/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c @@ -162,10 +162,18 @@ typedef enum /*!< @brief TIM specific info */ static hal_ll_tim_hw_specifics_map_t hal_ll_tim_hw_specifics_map[] = { + #ifdef TIM_MODULE_0 {HAL_LL_TIM0_BASE_ADDRESS, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, hal_ll_tim_module_num(TIM_MODULE_0)}, + #endif + #ifdef TIM_MODULE_1 {HAL_LL_TIM1_BASE_ADDRESS, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM_MODULE_2 {HAL_LL_TIM2_BASE_ADDRESS, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM_MODULE_3 {HAL_LL_TIM3_BASE_ADDRESS, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif {HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, NULL, HAL_LL_PIN_NC}, 0, 0, HAL_LL_PIN_NC} }; @@ -643,18 +651,26 @@ static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { static void _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) { switch ( map->base ) { + #ifdef TIM_MODULE_0 case ( HAL_LL_TIM0_BASE_ADDRESS ): _hal_ll_tim0_set_clock( map->config.channel, hal_ll_state ); break; + #endif + #ifdef TIM_MODULE_1 case ( HAL_LL_TIM1_BASE_ADDRESS ): _hal_ll_tim1_set_clock( map->config.channel, hal_ll_state ); break; + #endif + #ifdef TIM_MODULE_2 case ( HAL_LL_TIM2_BASE_ADDRESS ): _hal_ll_tim2_set_clock( map->config.channel, hal_ll_state ); break; + #endif + #ifdef TIM_MODULE_3 case ( HAL_LL_TIM3_BASE_ADDRESS ): _hal_ll_tim3_set_clock( map->config.channel, hal_ll_state ); break; + #endif } } diff --git a/targets/arm/mikroe/sam/src/uart/CMakeLists.txt b/targets/arm/mikroe/sam/src/uart/CMakeLists.txt index a49745c77..767bc2d46 100644 --- a/targets/arm/mikroe/sam/src/uart/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/uart/CMakeLists.txt @@ -9,7 +9,7 @@ list(APPEND hal_ll_def_list "MACRO_USAGE_UART") set(mcu_header_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) ## BEGIN UART -if (${MCU_NAME} MATCHES "^ATSAME7.+") +if (${MCU_NAME} MATCHES "^ATSAM[ESV]7.+") set(uart_subimplementation "implementations/implementation_1") endif() ## END UART diff --git a/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c b/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c index fdc10e291..c83aa3ece 100644 --- a/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c +++ b/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c @@ -183,14 +183,30 @@ typedef enum /*!< @brief UART hardware specific info */ static hal_ll_uart_hw_specifics_map_t hal_ll_uart_hw_specifics_map[] = { + #ifdef USART_MODULE_0 {HAL_LL_USART0_BASE_ADDRESS, hal_ll_usart_module_num(USART_MODULE_0), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef USART_MODULE_1 {HAL_LL_USART1_BASE_ADDRESS, hal_ll_usart_module_num(USART_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef USART_MODULE_2 {HAL_LL_USART2_BASE_ADDRESS, hal_ll_usart_module_num(USART_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_0 {HAL_LL_UART0_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_0), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_1 {HAL_LL_UART1_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_2 {HAL_LL_UART2_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_3 {HAL_LL_UART3_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif + #ifdef UART_MODULE_4 {HAL_LL_UART4_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_4), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + #endif {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {0, 0}, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR} }; @@ -602,37 +618,53 @@ void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq ) { switch ( hal_ll_uart_hw_specifics_map_local->module_index ) { - case hal_ll_usart_module_num( USART_MODULE_0 ): - hal_ll_core_enable_irq( USART0_NVIC ); - break; + #ifdef USART_MODULE_0 + case hal_ll_usart_module_num( USART_MODULE_0 ): + hal_ll_core_enable_irq( USART0_NVIC ); + break; + #endif - case hal_ll_usart_module_num( USART_MODULE_1 ): - hal_ll_core_enable_irq( USART1_NVIC ); - break; + #ifdef USART_MODULE_1 + case hal_ll_usart_module_num( USART_MODULE_1 ): + hal_ll_core_enable_irq( USART1_NVIC ); + break; + #endif - case hal_ll_usart_module_num( USART_MODULE_2 ): - hal_ll_core_enable_irq( USART2_NVIC ); - break; + #ifdef USART_MODULE_2 + case hal_ll_usart_module_num( USART_MODULE_2 ): + hal_ll_core_enable_irq( USART2_NVIC ); + break; + #endif - case hal_ll_uart_module_num( UART_MODULE_0 ): - hal_ll_core_enable_irq( UART0_NVIC ); - break; + #ifdef UART_MODULE_0 + case hal_ll_uart_module_num( UART_MODULE_0 ): + hal_ll_core_enable_irq( UART0_NVIC ); + break; + #endif - case hal_ll_uart_module_num( UART_MODULE_1 ): - hal_ll_core_enable_irq( UART1_NVIC ); - break; + #ifdef UART_MODULE_1 + case hal_ll_uart_module_num( UART_MODULE_1 ): + hal_ll_core_enable_irq( UART1_NVIC ); + break; + #endif - case hal_ll_uart_module_num( UART_MODULE_2 ): - hal_ll_core_enable_irq( UART2_NVIC ); - break; + #ifdef UART_MODULE_2 + case hal_ll_uart_module_num( UART_MODULE_2 ): + hal_ll_core_enable_irq( UART2_NVIC ); + break; + #endif - case hal_ll_uart_module_num( UART_MODULE_3 ): - hal_ll_core_enable_irq( UART3_NVIC ); - break; + #ifdef UART_MODULE_3 + case hal_ll_uart_module_num( UART_MODULE_3 ): + hal_ll_core_enable_irq( UART3_NVIC ); + break; + #endif - case hal_ll_uart_module_num( UART_MODULE_4 ): - hal_ll_core_enable_irq( UART4_NVIC ); - break; + #ifdef UART_MODULE_4 + case hal_ll_uart_module_num( UART_MODULE_4 ): + hal_ll_core_enable_irq( UART4_NVIC ); + break; + #endif default: @@ -664,37 +696,53 @@ void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ) { { switch ( hal_ll_uart_hw_specifics_map_local->module_index ) { + #ifdef USART_MODULE_0 case hal_ll_usart_module_num( USART_MODULE_0 ): hal_ll_core_disable_irq( USART0_NVIC ); break; + #endif + #ifdef USART_MODULE_1 case hal_ll_usart_module_num( USART_MODULE_1 ): hal_ll_core_disable_irq( USART1_NVIC ); break; + #endif + #ifdef USART_MODULE_2 case hal_ll_usart_module_num( USART_MODULE_2 ): hal_ll_core_disable_irq( USART2_NVIC ); break; + #endif + #ifdef UART_MODULE_0 case hal_ll_uart_module_num( UART_MODULE_0 ): hal_ll_core_disable_irq( UART0_NVIC ); break; + #endif + #ifdef UART_MODULE_1 case hal_ll_uart_module_num( UART_MODULE_1 ): hal_ll_core_disable_irq( UART1_NVIC ); break; + #endif + #ifdef UART_MODULE_2 case hal_ll_uart_module_num( UART_MODULE_2 ): hal_ll_core_disable_irq( UART2_NVIC ); break; + #endif + #ifdef UART_MODULE_3 case hal_ll_uart_module_num( UART_MODULE_3 ): hal_ll_core_disable_irq( UART3_NVIC ); break; + #endif + #ifdef UART_MODULE_4 case hal_ll_uart_module_num( UART_MODULE_4 ): hal_ll_core_disable_irq( UART4_NVIC ); break; + #endif default: @@ -719,6 +767,7 @@ uint8_t hal_ll_uart_read( handle_t *handle ) { // ------------------------------------------------------------- DEFAULT EXCEPTION HANDLERS +#ifdef USART_MODULE_0 void USART0_Handler(void) { if( hal_ll_uart_get_status_flags( HAL_LL_USART0_BASE_ADDRESS , HAL_LL_UART_IMR_RXRDY_FLAG ) ) { if( ( hal_ll_uart_get_interrupt_source( HAL_LL_USART0_BASE_ADDRESS, HAL_LL_UART_SR_RXRDY_FLAG ) ) ) { @@ -731,7 +780,9 @@ void USART0_Handler(void) { } } } +#endif +#ifdef USART_MODULE_1 void USART1_Handler(void) { if( hal_ll_uart_get_status_flags( HAL_LL_USART1_BASE_ADDRESS , HAL_LL_UART_IMR_RXRDY_FLAG ) ) { if( ( hal_ll_uart_get_interrupt_source( HAL_LL_USART1_BASE_ADDRESS, HAL_LL_UART_SR_RXRDY_FLAG ) ) ) { @@ -744,7 +795,9 @@ void USART1_Handler(void) { } } } +#endif +#ifdef USART_MODULE_2 void USART2_Handler(void) { if( hal_ll_uart_get_status_flags( HAL_LL_USART2_BASE_ADDRESS , HAL_LL_UART_IMR_RXRDY_FLAG ) ) { if( ( hal_ll_uart_get_interrupt_source( HAL_LL_USART2_BASE_ADDRESS, HAL_LL_UART_SR_RXRDY_FLAG ) ) ) { @@ -757,7 +810,9 @@ void USART2_Handler(void) { } } } +#endif +#ifdef UART_MODULE_0 void UART0_Handler(void) { if( hal_ll_uart_get_status_flags( HAL_LL_UART0_BASE_ADDRESS , HAL_LL_UART_IMR_RXRDY_FLAG ) ) { if( ( hal_ll_uart_get_interrupt_source( HAL_LL_UART0_BASE_ADDRESS, HAL_LL_UART_SR_RXRDY_FLAG ) ) ) { @@ -770,7 +825,9 @@ void UART0_Handler(void) { } } } +#endif +#ifdef UART_MODULE_1 void UART1_Handler(void) { if( hal_ll_uart_get_status_flags( HAL_LL_UART1_BASE_ADDRESS , HAL_LL_UART_IMR_RXRDY_FLAG ) ) { if( ( hal_ll_uart_get_interrupt_source( HAL_LL_UART1_BASE_ADDRESS, HAL_LL_UART_SR_RXRDY_FLAG ) ) ) { @@ -783,7 +840,9 @@ void UART1_Handler(void) { } } } +#endif +#ifdef UART_MODULE_2 void UART2_Handler(void) { if( hal_ll_uart_get_status_flags( HAL_LL_UART2_BASE_ADDRESS , HAL_LL_UART_IMR_RXRDY_FLAG ) ) { if( ( hal_ll_uart_get_interrupt_source( HAL_LL_UART2_BASE_ADDRESS, HAL_LL_UART_SR_RXRDY_FLAG ) ) ) { @@ -796,7 +855,9 @@ void UART2_Handler(void) { } } } +#endif +#ifdef UART_MODULE_3 void UART3_Handler(void) { if( hal_ll_uart_get_status_flags( HAL_LL_UART3_BASE_ADDRESS , HAL_LL_UART_IMR_RXRDY_FLAG ) ) { if( ( hal_ll_uart_get_interrupt_source( HAL_LL_UART3_BASE_ADDRESS, HAL_LL_UART_SR_RXRDY_FLAG ) ) ) { @@ -809,7 +870,9 @@ void UART3_Handler(void) { } } } +#endif +#ifdef UART_MODULE_4 void UART4_Handler(void) { if( hal_ll_uart_get_status_flags( HAL_LL_UART4_BASE_ADDRESS , HAL_LL_UART_IMR_RXRDY_FLAG ) ) { if( ( hal_ll_uart_get_interrupt_source( HAL_LL_UART4_BASE_ADDRESS, HAL_LL_UART_SR_RXRDY_FLAG ) ) ) { @@ -822,6 +885,7 @@ void UART4_Handler(void) { } } } +#endif // ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS static uint8_t hal_ll_uart_find_index( handle_t *handle ) { @@ -897,37 +961,53 @@ static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { switch ( map->module_index ) { + #ifdef USART_MODULE_0 case ( hal_ll_usart_module_num(USART_MODULE_0) ): (hal_ll_state == true)?(set_reg_bit( _PMC_PCER0, HAL_LL_PID_USART0_BIT )):(clear_reg_bit( _PMC_PCER0, HAL_LL_PID_USART0_BIT )); break; + #endif + #ifdef USART_MODULE_1 case ( hal_ll_usart_module_num(USART_MODULE_1) ): (hal_ll_state == true)?(set_reg_bit( _PMC_PCER0, HAL_LL_PID_USART1_BIT )):(clear_reg_bit( _PMC_PCER0, HAL_LL_PID_USART1_BIT )); break; + #endif + #ifdef USART_MODULE_2 case ( hal_ll_usart_module_num(USART_MODULE_2) ): (hal_ll_state == true)?(set_reg_bit( _PMC_PCER0, HAL_LL_PID_USART2_BIT )):(clear_reg_bit( _PMC_PCER0, HAL_LL_PID_USART2_BIT )); break; + #endif + #ifdef UART_MODULE_0 case ( hal_ll_uart_module_num(UART_MODULE_0) ): (hal_ll_state == true)?(set_reg_bit( _PMC_PCER0, HAL_LL_PID_UART0_BIT )):(clear_reg_bit( _PMC_PCER0, HAL_LL_PID_UART0_BIT )); break; + #endif + #ifdef UART_MODULE_1 case ( hal_ll_uart_module_num(UART_MODULE_1) ): (hal_ll_state == true)?(set_reg_bit( _PMC_PCER0, HAL_LL_PID_UART1_BIT )):(clear_reg_bit( _PMC_PCER0, HAL_LL_PID_UART1_BIT )); break; + #endif + #ifdef UART_MODULE_2 case ( hal_ll_uart_module_num(UART_MODULE_2) ): (hal_ll_state == true)?(set_reg_bit( _PMC_PCER1, HAL_LL_PID_UART2_BIT )):(clear_reg_bit( _PMC_PCER1, HAL_LL_PID_UART2_BIT )); break; + #endif + #ifdef UART_MODULE_3 case ( hal_ll_uart_module_num(UART_MODULE_3) ): (hal_ll_state == true)?(set_reg_bit( _PMC_PCER1, HAL_LL_PID_UART3_BIT )):(clear_reg_bit( _PMC_PCER1, HAL_LL_PID_UART3_BIT )); break; + #endif + #ifdef UART_MODULE_4 case ( hal_ll_uart_module_num(UART_MODULE_4) ): (hal_ll_state == true)?(set_reg_bit( _PMC_PCER1, HAL_LL_PID_UART4_BIT )):(clear_reg_bit( _PMC_PCER1, HAL_LL_PID_UART4_BIT )); break; + #endif default: From cfc86515f15a437f240a469598760939f2065065 Mon Sep 17 00:00:00 2001 From: "ivan.ruzavin" Date: Fri, 22 Nov 2024 12:01:57 +0100 Subject: [PATCH 19/56] Added MCU defs for all E7/V7/S7 SAMs --- .../SAM/ATSAME70J19A/LQFP64/mcu_definitions.h | 236 +++++++++++++ .../SAM/ATSAME70J19B/LQFP64/mcu_definitions.h | 236 +++++++++++++ .../SAM/ATSAME70J20A/LQFP64/mcu_definitions.h | 236 +++++++++++++ .../SAM/ATSAME70J20B/LQFP64/mcu_definitions.h | 236 +++++++++++++ .../SAM/ATSAME70J21A/LQFP64/mcu_definitions.h | 236 +++++++++++++ .../SAM/ATSAME70J21B/LQFP64/mcu_definitions.h | 236 +++++++++++++ .../ATSAME70N19A/LQFP100/mcu_definitions.h | 253 ++++++++++++++ .../ATSAME70N19A/TFBGA100/mcu_definitions.h | 253 ++++++++++++++ .../ATSAME70N19B/LQFP100/mcu_definitions.h | 253 ++++++++++++++ .../ATSAME70N19B/TFBGA100/mcu_definitions.h | 253 ++++++++++++++ .../ATSAME70N20A/LQFP100/mcu_definitions.h | 253 ++++++++++++++ .../ATSAME70N20A/TFBGA100/mcu_definitions.h | 253 ++++++++++++++ .../ATSAME70N20B/LQFP100/mcu_definitions.h | 253 ++++++++++++++ .../ATSAME70N20B/TFBGA100/mcu_definitions.h | 253 ++++++++++++++ .../ATSAME70N21A/LQFP100/mcu_definitions.h | 253 ++++++++++++++ .../ATSAME70N21A/TFBGA100/mcu_definitions.h | 253 ++++++++++++++ .../ATSAME70N21B/LQFP100/mcu_definitions.h | 253 ++++++++++++++ .../ATSAME70N21B/TFBGA100/mcu_definitions.h | 253 ++++++++++++++ .../ATSAME70Q19A/LFBGA144/mcu_definitions.h | 328 ++++++++++++++++++ .../ATSAME70Q19A/LQFP144/mcu_definitions.h | 328 ++++++++++++++++++ .../ATSAME70Q19A/UFBGA144/mcu_definitions.h | 328 ++++++++++++++++++ .../ATSAME70Q19B/LFBGA144/mcu_definitions.h | 328 ++++++++++++++++++ .../ATSAME70Q19B/LQFP144/mcu_definitions.h | 328 ++++++++++++++++++ .../ATSAME70Q19B/UFBGA144/mcu_definitions.h | 328 ++++++++++++++++++ .../ATSAME70Q20A/LFBGA144/mcu_definitions.h | 328 ++++++++++++++++++ .../ATSAME70Q20A/LQFP144/mcu_definitions.h | 328 ++++++++++++++++++ .../ATSAME70Q20A/UFBGA144/mcu_definitions.h | 328 ++++++++++++++++++ .../ATSAME70Q20B/LFBGA144/mcu_definitions.h | 328 ++++++++++++++++++ .../ATSAME70Q20B/LQFP144/mcu_definitions.h | 328 ++++++++++++++++++ .../ATSAME70Q20B/UFBGA144/mcu_definitions.h | 328 ++++++++++++++++++ .../ATSAME70Q21A/LFBGA144/mcu_definitions.h | 328 ++++++++++++++++++ .../ATSAME70Q21A/LQFP144/mcu_definitions.h | 328 ++++++++++++++++++ .../ATSAME70Q21A/UFBGA144/mcu_definitions.h | 328 ++++++++++++++++++ .../ATSAME70Q21B/LFBGA144/mcu_definitions.h | 328 ++++++++++++++++++ .../ATSAME70Q21B/LQFP144/mcu_definitions.h | 8 +- .../ATSAME70Q21B/UFBGA144/mcu_definitions.h | 328 ++++++++++++++++++ .../SAM/ATSAMS70J19A/LQFP64/mcu_definitions.h | 236 +++++++++++++ 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44354 insertions(+), 5 deletions(-) create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70J19A/LQFP64/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70J19B/LQFP64/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70J20A/LQFP64/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70J20B/LQFP64/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70J21A/LQFP64/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70J21B/LQFP64/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N19A/LQFP100/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N19A/TFBGA100/mcu_definitions.h create mode 100644 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create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21B/UFBGA144/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J19A/LQFP64/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J19A/QFN64/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J19B/LQFP64/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J19B/QFN64/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J20A/LQFP64/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J20A/QFN64/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J20B/LQFP64/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J20B/QFN64/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J21A/LQFP64/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J21A/QFN64/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J21B/LQFP64/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J21B/QFN64/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N19A/LQFP100/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N19A/TFBGA100/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N19A/VFBGA100/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N19B/LQFP100/mcu_definitions.h create mode 100644 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create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N21A/TFBGA100/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N21A/VFBGA100/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N21B/LQFP100/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N21B/TFBGA100/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N21B/VFBGA100/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q19A/LFBGA144/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q19A/LQFP144/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q19A/UFBGA144/mcu_definitions.h create mode 100644 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create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q21A/LFBGA144/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q21A/LQFP144/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q21A/UFBGA144/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q21B/LFBGA144/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q21B/LQFP144/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q21B/UFBGA144/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70J19A/LQFP64/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70J19B/LQFP64/mcu_definitions.h create mode 100644 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create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N21B/TFBGA100/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q19A/LQFP144/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q19A/TFBGA144/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q19B/LQFP144/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q19B/TFBGA144/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q20A/LQFP144/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q20A/TFBGA144/mcu_definitions.h create mode 100644 targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q20B/LQFP144/mcu_definitions.h create mode 100644 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targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q21B/LQFP144/mcu_reg_addresses.h create mode 100644 targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q21B/TFBGA144/mcu_reg_addresses.h diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70J19A/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70J19A/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..ec1548e2e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70J19A/LQFP64/mcu_definitions.h @@ -0,0 +1,236 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70J19A_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) + +#define USART_MODULE_COUNT (2) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (3) +// EOF UART + +// SPI +#define SPI0_MOSI_PA13_AFA +#define SPI0_MISO_PA12_AFA +#define SPI0_SCK_PA14_AFA + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define UART2_NVIC (44) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70J19B/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70J19B/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..f0d536a33 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70J19B/LQFP64/mcu_definitions.h @@ -0,0 +1,236 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70J19B_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) + +#define USART_MODULE_COUNT (2) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (3) +// EOF UART + +// SPI +#define SPI0_MOSI_PA13_AFA +#define SPI0_MISO_PA12_AFA +#define SPI0_SCK_PA14_AFA + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define UART2_NVIC (44) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70J20A/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70J20A/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..f0269ed27 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70J20A/LQFP64/mcu_definitions.h @@ -0,0 +1,236 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70J20A_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) + +#define USART_MODULE_COUNT (2) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (3) +// EOF UART + +// SPI +#define SPI0_MOSI_PA13_AFA +#define SPI0_MISO_PA12_AFA +#define SPI0_SCK_PA14_AFA + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define UART2_NVIC (44) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70J20B/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70J20B/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..5657d575b --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70J20B/LQFP64/mcu_definitions.h @@ -0,0 +1,236 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70J20B_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) + +#define USART_MODULE_COUNT (2) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (3) +// EOF UART + +// SPI +#define SPI0_MOSI_PA13_AFA +#define SPI0_MISO_PA12_AFA +#define SPI0_SCK_PA14_AFA + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define UART2_NVIC (44) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70J21A/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70J21A/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..6ca408a2e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70J21A/LQFP64/mcu_definitions.h @@ -0,0 +1,236 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70J21A_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) + +#define USART_MODULE_COUNT (2) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (3) +// EOF UART + +// SPI +#define SPI0_MOSI_PA13_AFA +#define SPI0_MISO_PA12_AFA +#define SPI0_SCK_PA14_AFA + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define UART2_NVIC (44) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70J21B/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70J21B/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..a9fa67f1d --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70J21B/LQFP64/mcu_definitions.h @@ -0,0 +1,236 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70J21B_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) + +#define USART_MODULE_COUNT (2) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (3) +// EOF UART + +// SPI +#define SPI0_MOSI_PA13_AFA +#define SPI0_MISO_PA12_AFA +#define SPI0_SCK_PA14_AFA + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define UART2_NVIC (44) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N19A/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N19A/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..b279dc31f --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N19A/LQFP100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70N19A_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N19A/TFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N19A/TFBGA100/mcu_definitions.h new file mode 100644 index 000000000..d8b628ce9 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N19A/TFBGA100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70N19A_TFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N19B/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N19B/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..16f5dc502 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N19B/LQFP100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70N19B_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N19B/TFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N19B/TFBGA100/mcu_definitions.h new file mode 100644 index 000000000..e94d48e24 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N19B/TFBGA100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70N19B_TFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N20A/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N20A/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..ffa5b6f26 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N20A/LQFP100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70N20A_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N20A/TFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N20A/TFBGA100/mcu_definitions.h new file mode 100644 index 000000000..fb2f3dda6 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N20A/TFBGA100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70N20A_TFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N20B/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N20B/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..1704d5da7 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N20B/LQFP100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70N20B_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N20B/TFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N20B/TFBGA100/mcu_definitions.h new file mode 100644 index 000000000..5dc8ab3d3 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N20B/TFBGA100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70N20B_TFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N21A/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N21A/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..a57409a2f --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N21A/LQFP100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70N21A_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N21A/TFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N21A/TFBGA100/mcu_definitions.h new file mode 100644 index 000000000..3affe694e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N21A/TFBGA100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70N21A_TFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N21B/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N21B/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..9be7a4ec9 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N21B/LQFP100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70N21B_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N21B/TFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N21B/TFBGA100/mcu_definitions.h new file mode 100644 index 000000000..4960a55d3 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70N21B/TFBGA100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70N21B_TFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q19A/LFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q19A/LFBGA144/mcu_definitions.h new file mode 100644 index 000000000..091d6f357 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q19A/LFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70Q19A_LFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q19A/LQFP144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q19A/LQFP144/mcu_definitions.h new file mode 100644 index 000000000..f13a27c3d --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q19A/LQFP144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70Q19A_LQFP144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q19A/UFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q19A/UFBGA144/mcu_definitions.h new file mode 100644 index 000000000..474480673 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q19A/UFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70Q19A_UFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q19B/LFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q19B/LFBGA144/mcu_definitions.h new file mode 100644 index 000000000..c45543b5d --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q19B/LFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70Q19B_LFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q19B/LQFP144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q19B/LQFP144/mcu_definitions.h new file mode 100644 index 000000000..1365fb93a --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q19B/LQFP144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70Q19B_LQFP144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q19B/UFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q19B/UFBGA144/mcu_definitions.h new file mode 100644 index 000000000..d18167d37 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q19B/UFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70Q19B_UFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q20A/LFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q20A/LFBGA144/mcu_definitions.h new file mode 100644 index 000000000..6f42b5051 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q20A/LFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70Q20A_LFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q20A/LQFP144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q20A/LQFP144/mcu_definitions.h new file mode 100644 index 000000000..b7c5d6811 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q20A/LQFP144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70Q20A_LQFP144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q20A/UFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q20A/UFBGA144/mcu_definitions.h new file mode 100644 index 000000000..57bdf8181 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q20A/UFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70Q20A_UFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q20B/LFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q20B/LFBGA144/mcu_definitions.h new file mode 100644 index 000000000..1fe7e632c --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q20B/LFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70Q20B_LFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q20B/LQFP144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q20B/LQFP144/mcu_definitions.h new file mode 100644 index 000000000..ecf7674f1 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q20B/LQFP144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70Q20B_LQFP144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q20B/UFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q20B/UFBGA144/mcu_definitions.h new file mode 100644 index 000000000..8c5a589e1 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q20B/UFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70Q20B_UFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21A/LFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21A/LFBGA144/mcu_definitions.h new file mode 100644 index 000000000..cde0d793f --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21A/LFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70Q21A_LFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21A/LQFP144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21A/LQFP144/mcu_definitions.h new file mode 100644 index 000000000..193f3ddcf --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21A/LQFP144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70Q21A_LQFP144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21A/UFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21A/UFBGA144/mcu_definitions.h new file mode 100644 index 000000000..996e451fd --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21A/UFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70Q21A_UFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21B/LFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21B/LFBGA144/mcu_definitions.h new file mode 100644 index 000000000..10bfb4523 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21B/LFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70Q21B_LFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21B/LQFP144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21B/LQFP144/mcu_definitions.h index c9be10acd..14d91abb0 100644 --- a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21B/LQFP144/mcu_definitions.h +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21B/LQFP144/mcu_definitions.h @@ -125,14 +125,14 @@ extern "C"{ #define TIM_MODULE_2 (2) #define TIM_MODULE_3 (3) -#define TIM_CHANNEL_NUMBER (3) -#define TIM_MODULE_COUNT (4) +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) // EOF TIM // USART #define USART0_RX_PB0_AFC #define USART0_TX_PB1_AFC -#define USART1_RX_PA21_AFC +#define USART1_RX_PA21_AFA #define USART1_TX_PB4_AFD #define USART2_RX_PD15_AFB #define USART2_TX_PD16_AFB @@ -150,12 +150,14 @@ extern "C"{ #define UART1_RX_PA5_AFC #define UART1_TX_PA4_AFC #define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD #define UART2_RX_PD25_AFC #define UART2_TX_PD26_AFC #define UART3_RX_PD28_AFA #define UART3_TX_PD30_AFA #define UART3_TX_PD31_AFB #define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC #define UART4_TX_PD19_AFC #define UART_MODULE_0 (0) diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21B/UFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21B/UFBGA144/mcu_definitions.h new file mode 100644 index 000000000..3e1407dae --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAME70Q21B/UFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAME70Q21B_UFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J19A/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J19A/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..3ada8d9ae --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J19A/LQFP64/mcu_definitions.h @@ -0,0 +1,236 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70J19A_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) + +#define USART_MODULE_COUNT (2) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (3) +// EOF UART + +// SPI +#define SPI0_MOSI_PA13_AFA +#define SPI0_MISO_PA12_AFA +#define SPI0_SCK_PA14_AFA + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define UART2_NVIC (44) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J19A/QFN64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J19A/QFN64/mcu_definitions.h new file mode 100644 index 000000000..c1ae8445e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J19A/QFN64/mcu_definitions.h @@ -0,0 +1,236 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70J19A_QFN64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) + +#define USART_MODULE_COUNT (2) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (3) +// EOF UART + +// SPI +#define SPI0_MOSI_PA13_AFA +#define SPI0_MISO_PA12_AFA +#define SPI0_SCK_PA14_AFA + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define UART2_NVIC (44) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J19B/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J19B/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..29d44a1e2 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J19B/LQFP64/mcu_definitions.h @@ -0,0 +1,236 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70J19B_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) + +#define USART_MODULE_COUNT (2) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (3) +// EOF UART + +// SPI +#define SPI0_MOSI_PA13_AFA +#define SPI0_MISO_PA12_AFA +#define SPI0_SCK_PA14_AFA + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define UART2_NVIC (44) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J19B/QFN64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J19B/QFN64/mcu_definitions.h new file mode 100644 index 000000000..ba7cda109 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J19B/QFN64/mcu_definitions.h @@ -0,0 +1,236 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70J19B_QFN64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) + +#define USART_MODULE_COUNT (2) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (3) +// EOF UART + +// SPI +#define SPI0_MOSI_PA13_AFA +#define SPI0_MISO_PA12_AFA +#define SPI0_SCK_PA14_AFA + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define UART2_NVIC (44) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J20A/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J20A/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..9c3fccf0a --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J20A/LQFP64/mcu_definitions.h @@ -0,0 +1,236 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70J20A_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) + +#define USART_MODULE_COUNT (2) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (3) +// EOF UART + +// SPI +#define SPI0_MOSI_PA13_AFA +#define SPI0_MISO_PA12_AFA +#define SPI0_SCK_PA14_AFA + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define UART2_NVIC (44) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J20A/QFN64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J20A/QFN64/mcu_definitions.h new file mode 100644 index 000000000..831556df5 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J20A/QFN64/mcu_definitions.h @@ -0,0 +1,236 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70J20A_QFN64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) + +#define USART_MODULE_COUNT (2) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (3) +// EOF UART + +// SPI +#define SPI0_MOSI_PA13_AFA +#define SPI0_MISO_PA12_AFA +#define SPI0_SCK_PA14_AFA + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define UART2_NVIC (44) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J20B/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J20B/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..aedde3f03 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J20B/LQFP64/mcu_definitions.h @@ -0,0 +1,236 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70J20B_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) + +#define USART_MODULE_COUNT (2) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (3) +// EOF UART + +// SPI +#define SPI0_MOSI_PA13_AFA +#define SPI0_MISO_PA12_AFA +#define SPI0_SCK_PA14_AFA + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define UART2_NVIC (44) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J20B/QFN64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J20B/QFN64/mcu_definitions.h new file mode 100644 index 000000000..3183a631c --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J20B/QFN64/mcu_definitions.h @@ -0,0 +1,236 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70J20B_QFN64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) + +#define USART_MODULE_COUNT (2) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (3) +// EOF UART + +// SPI +#define SPI0_MOSI_PA13_AFA +#define SPI0_MISO_PA12_AFA +#define SPI0_SCK_PA14_AFA + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define UART2_NVIC (44) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J21A/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J21A/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..d3713148a --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J21A/LQFP64/mcu_definitions.h @@ -0,0 +1,236 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70J21A_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) + +#define USART_MODULE_COUNT (2) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (3) +// EOF UART + +// SPI +#define SPI0_MOSI_PA13_AFA +#define SPI0_MISO_PA12_AFA +#define SPI0_SCK_PA14_AFA + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define UART2_NVIC (44) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J21A/QFN64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J21A/QFN64/mcu_definitions.h new file mode 100644 index 000000000..c38816913 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J21A/QFN64/mcu_definitions.h @@ -0,0 +1,236 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70J21A_QFN64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) + +#define USART_MODULE_COUNT (2) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (3) +// EOF UART + +// SPI +#define SPI0_MOSI_PA13_AFA +#define SPI0_MISO_PA12_AFA +#define SPI0_SCK_PA14_AFA + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define UART2_NVIC (44) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J21B/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J21B/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..9fd868126 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J21B/LQFP64/mcu_definitions.h @@ -0,0 +1,236 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70J21B_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) + +#define USART_MODULE_COUNT (2) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (3) +// EOF UART + +// SPI +#define SPI0_MOSI_PA13_AFA +#define SPI0_MISO_PA12_AFA +#define SPI0_SCK_PA14_AFA + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define UART2_NVIC (44) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J21B/QFN64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J21B/QFN64/mcu_definitions.h new file mode 100644 index 000000000..e626ffe3a --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70J21B/QFN64/mcu_definitions.h @@ -0,0 +1,236 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70J21B_QFN64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) + +#define USART_MODULE_COUNT (2) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (3) +// EOF UART + +// SPI +#define SPI0_MOSI_PA13_AFA +#define SPI0_MISO_PA12_AFA +#define SPI0_SCK_PA14_AFA + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define UART2_NVIC (44) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N19A/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N19A/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..d2233b7a0 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N19A/LQFP100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70N19A_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N19A/TFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N19A/TFBGA100/mcu_definitions.h new file mode 100644 index 000000000..48f53b9bb --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N19A/TFBGA100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70N19A_TFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N19A/VFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N19A/VFBGA100/mcu_definitions.h new file mode 100644 index 000000000..ef3bb789b --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N19A/VFBGA100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70N19A_VFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N19B/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N19B/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..e33bcdeb8 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N19B/LQFP100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70N19B_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N19B/TFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N19B/TFBGA100/mcu_definitions.h new file mode 100644 index 000000000..07a2be8b6 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N19B/TFBGA100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70N19B_TFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N19B/VFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N19B/VFBGA100/mcu_definitions.h new file mode 100644 index 000000000..068e154b1 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N19B/VFBGA100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70N19B_VFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N20A/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N20A/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..0818cbca2 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N20A/LQFP100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70N20A_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N20A/TFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N20A/TFBGA100/mcu_definitions.h new file mode 100644 index 000000000..db41d766f --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N20A/TFBGA100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70N20A_TFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N20A/VFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N20A/VFBGA100/mcu_definitions.h new file mode 100644 index 000000000..f64e73ccb --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N20A/VFBGA100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70N20A_VFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N20B/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N20B/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..e00ea7d2e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N20B/LQFP100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70N20B_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N20B/TFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N20B/TFBGA100/mcu_definitions.h new file mode 100644 index 000000000..4cc574fc1 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N20B/TFBGA100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70N20B_TFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N20B/VFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N20B/VFBGA100/mcu_definitions.h new file mode 100644 index 000000000..90b211fd9 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N20B/VFBGA100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70N20B_VFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N21A/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N21A/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..374694824 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N21A/LQFP100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70N21A_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N21A/TFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N21A/TFBGA100/mcu_definitions.h new file mode 100644 index 000000000..ceb3dc804 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N21A/TFBGA100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70N21A_TFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N21A/VFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N21A/VFBGA100/mcu_definitions.h new file mode 100644 index 000000000..442976389 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N21A/VFBGA100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70N21A_VFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N21B/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N21B/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..179044bde --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N21B/LQFP100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70N21B_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N21B/TFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N21B/TFBGA100/mcu_definitions.h new file mode 100644 index 000000000..28c275a90 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N21B/TFBGA100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70N21B_TFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N21B/VFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N21B/VFBGA100/mcu_definitions.h new file mode 100644 index 000000000..f807e16a1 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70N21B/VFBGA100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70N21B_VFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q19A/LFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q19A/LFBGA144/mcu_definitions.h new file mode 100644 index 000000000..0768c93ef --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q19A/LFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70Q19A_LFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q19A/LQFP144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q19A/LQFP144/mcu_definitions.h new file mode 100644 index 000000000..0f66cceb2 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q19A/LQFP144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70Q19A_LQFP144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q19A/UFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q19A/UFBGA144/mcu_definitions.h new file mode 100644 index 000000000..8a75adeed --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q19A/UFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70Q19A_UFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q19B/LFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q19B/LFBGA144/mcu_definitions.h new file mode 100644 index 000000000..72a40f4f2 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q19B/LFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70Q19B_LFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q19B/LQFP144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q19B/LQFP144/mcu_definitions.h new file mode 100644 index 000000000..272dabf8f --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q19B/LQFP144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70Q19B_LQFP144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q19B/UFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q19B/UFBGA144/mcu_definitions.h new file mode 100644 index 000000000..32390e8ed --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q19B/UFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70Q19B_UFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q20A/LFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q20A/LFBGA144/mcu_definitions.h new file mode 100644 index 000000000..d16e82433 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q20A/LFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70Q20A_LFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q20A/LQFP144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q20A/LQFP144/mcu_definitions.h new file mode 100644 index 000000000..b425e6aa9 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q20A/LQFP144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70Q20A_LQFP144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q20A/UFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q20A/UFBGA144/mcu_definitions.h new file mode 100644 index 000000000..e9769db41 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q20A/UFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70Q20A_UFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q20B/LFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q20B/LFBGA144/mcu_definitions.h new file mode 100644 index 000000000..90b64efc5 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q20B/LFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70Q20B_LFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q20B/LQFP144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q20B/LQFP144/mcu_definitions.h new file mode 100644 index 000000000..25a955e77 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q20B/LQFP144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70Q20B_LQFP144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q20B/UFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q20B/UFBGA144/mcu_definitions.h new file mode 100644 index 000000000..0369d5ec3 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q20B/UFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70Q20B_UFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q21A/LFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q21A/LFBGA144/mcu_definitions.h new file mode 100644 index 000000000..61cbfc357 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q21A/LFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70Q21A_LFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q21A/LQFP144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q21A/LQFP144/mcu_definitions.h new file mode 100644 index 000000000..1d83e9f3d --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q21A/LQFP144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70Q21A_LQFP144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q21A/UFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q21A/UFBGA144/mcu_definitions.h new file mode 100644 index 000000000..b837ebe5c --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q21A/UFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70Q21A_UFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q21B/LFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q21B/LFBGA144/mcu_definitions.h new file mode 100644 index 000000000..9024f3c6a --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q21B/LFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70Q21B_LFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q21B/LQFP144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q21B/LQFP144/mcu_definitions.h new file mode 100644 index 000000000..eb2ea5314 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q21B/LQFP144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70Q21B_LQFP144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q21B/UFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q21B/UFBGA144/mcu_definitions.h new file mode 100644 index 000000000..c9607a20b --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMS70Q21B/UFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMS70Q21B_UFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70J19A/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70J19A/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..737abd81b --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70J19A/LQFP64/mcu_definitions.h @@ -0,0 +1,236 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV70J19A_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) + +#define USART_MODULE_COUNT (2) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (3) +// EOF UART + +// SPI +#define SPI0_MOSI_PA13_AFA +#define SPI0_MISO_PA12_AFA +#define SPI0_SCK_PA14_AFA + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define UART2_NVIC (44) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70J19B/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70J19B/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..f23fafd0d --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70J19B/LQFP64/mcu_definitions.h @@ -0,0 +1,236 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV70J19B_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) + +#define USART_MODULE_COUNT (2) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (3) +// EOF UART + +// SPI +#define SPI0_MOSI_PA13_AFA +#define SPI0_MISO_PA12_AFA +#define SPI0_SCK_PA14_AFA + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define UART2_NVIC (44) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70J20A/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70J20A/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..286594edc --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70J20A/LQFP64/mcu_definitions.h @@ -0,0 +1,236 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV70J20A_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) + +#define USART_MODULE_COUNT (2) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (3) +// EOF UART + +// SPI +#define SPI0_MOSI_PA13_AFA +#define SPI0_MISO_PA12_AFA +#define SPI0_SCK_PA14_AFA + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define UART2_NVIC (44) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70J20B/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70J20B/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..9d8d8da80 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70J20B/LQFP64/mcu_definitions.h @@ -0,0 +1,236 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV70J20B_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) + +#define USART_MODULE_COUNT (2) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (3) +// EOF UART + +// SPI +#define SPI0_MOSI_PA13_AFA +#define SPI0_MISO_PA12_AFA +#define SPI0_SCK_PA14_AFA + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define UART2_NVIC (44) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70N19A/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70N19A/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..8c73c036e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70N19A/LQFP100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV70N19A_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70N19A/TFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70N19A/TFBGA100/mcu_definitions.h new file mode 100644 index 000000000..eb396504a --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70N19A/TFBGA100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV70N19A_TFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70N19B/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70N19B/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..02b4c92df --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70N19B/LQFP100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV70N19B_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70N19B/TFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70N19B/TFBGA100/mcu_definitions.h new file mode 100644 index 000000000..d9f4eac0b --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70N19B/TFBGA100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV70N19B_TFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70N20A/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70N20A/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..351affe87 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70N20A/LQFP100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV70N20A_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70N20A/TFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70N20A/TFBGA100/mcu_definitions.h new file mode 100644 index 000000000..9797ae133 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70N20A/TFBGA100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV70N20A_TFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70N20B/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70N20B/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..2d7356265 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70N20B/LQFP100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV70N20B_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70N20B/TFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70N20B/TFBGA100/mcu_definitions.h new file mode 100644 index 000000000..059853f11 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70N20B/TFBGA100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV70N20B_TFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70Q19A/LQFP144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70Q19A/LQFP144/mcu_definitions.h new file mode 100644 index 000000000..1a3bc9390 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70Q19A/LQFP144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV70Q19A_LQFP144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70Q19A/TFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70Q19A/TFBGA144/mcu_definitions.h new file mode 100644 index 000000000..5cab48a5c --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70Q19A/TFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV70Q19A_TFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70Q19B/LQFP144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70Q19B/LQFP144/mcu_definitions.h new file mode 100644 index 000000000..6d1692198 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70Q19B/LQFP144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV70Q19B_LQFP144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70Q19B/TFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70Q19B/TFBGA144/mcu_definitions.h new file mode 100644 index 000000000..6847cb172 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70Q19B/TFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV70Q19B_TFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70Q20A/LQFP144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70Q20A/LQFP144/mcu_definitions.h new file mode 100644 index 000000000..2a1c240d1 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70Q20A/LQFP144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV70Q20A_LQFP144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70Q20A/TFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70Q20A/TFBGA144/mcu_definitions.h new file mode 100644 index 000000000..983c1e18b --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70Q20A/TFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV70Q20A_TFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70Q20B/LQFP144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70Q20B/LQFP144/mcu_definitions.h new file mode 100644 index 000000000..c5301f0a9 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70Q20B/LQFP144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV70Q20B_LQFP144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70Q20B/TFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70Q20B/TFBGA144/mcu_definitions.h new file mode 100644 index 000000000..8771ad53c --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV70Q20B/TFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV70Q20B_TFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71J19A/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71J19A/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..96d84d8a5 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71J19A/LQFP64/mcu_definitions.h @@ -0,0 +1,236 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV71J19A_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) + +#define USART_MODULE_COUNT (2) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (3) +// EOF UART + +// SPI +#define SPI0_MOSI_PA13_AFA +#define SPI0_MISO_PA12_AFA +#define SPI0_SCK_PA14_AFA + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define UART2_NVIC (44) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71J19B/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71J19B/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..7b6afbfa2 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71J19B/LQFP64/mcu_definitions.h @@ -0,0 +1,236 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV71J19B_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) + +#define USART_MODULE_COUNT (2) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (3) +// EOF UART + +// SPI +#define SPI0_MOSI_PA13_AFA +#define SPI0_MISO_PA12_AFA +#define SPI0_SCK_PA14_AFA + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define UART2_NVIC (44) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71J20A/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71J20A/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..eaea0cd5c --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71J20A/LQFP64/mcu_definitions.h @@ -0,0 +1,236 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV71J20A_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) + +#define USART_MODULE_COUNT (2) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (3) +// EOF UART + +// SPI +#define SPI0_MOSI_PA13_AFA +#define SPI0_MISO_PA12_AFA +#define SPI0_SCK_PA14_AFA + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define UART2_NVIC (44) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71J20B/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71J20B/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..0eb5d5934 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71J20B/LQFP64/mcu_definitions.h @@ -0,0 +1,236 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV71J20B_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) + +#define USART_MODULE_COUNT (2) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (3) +// EOF UART + +// SPI +#define SPI0_MOSI_PA13_AFA +#define SPI0_MISO_PA12_AFA +#define SPI0_SCK_PA14_AFA + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define UART2_NVIC (44) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71J21A/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71J21A/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..3961a9013 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71J21A/LQFP64/mcu_definitions.h @@ -0,0 +1,236 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV71J21A_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) + +#define USART_MODULE_COUNT (2) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (3) +// EOF UART + +// SPI +#define SPI0_MOSI_PA13_AFA +#define SPI0_MISO_PA12_AFA +#define SPI0_SCK_PA14_AFA + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define UART2_NVIC (44) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71J21B/LQFP64/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71J21B/LQFP64/mcu_definitions.h new file mode 100644 index 000000000..d87f01bda --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71J21B/LQFP64/mcu_definitions.h @@ -0,0 +1,236 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV71J21B_LQFP64. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) + +#define I2C_MODULE_COUNT (2) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) + +#define USART_MODULE_COUNT (2) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) + +#define UART_MODULE_COUNT (3) +// EOF UART + +// SPI +#define SPI0_MOSI_PA13_AFA +#define SPI0_MISO_PA12_AFA +#define SPI0_SCK_PA14_AFA + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define UART2_NVIC (44) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N19A/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N19A/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..f0efb6359 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N19A/LQFP100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV71N19A_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N19A/TFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N19A/TFBGA100/mcu_definitions.h new file mode 100644 index 000000000..2b98d9ee5 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N19A/TFBGA100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV71N19A_TFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N19B/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N19B/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..5988a6f3e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N19B/LQFP100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV71N19B_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N19B/TFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N19B/TFBGA100/mcu_definitions.h new file mode 100644 index 000000000..f711275ab --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N19B/TFBGA100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV71N19B_TFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N20A/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N20A/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..3555386e7 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N20A/LQFP100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV71N20A_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N20A/TFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N20A/TFBGA100/mcu_definitions.h new file mode 100644 index 000000000..2169d0d22 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N20A/TFBGA100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV71N20A_TFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N20B/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N20B/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..393a6dc1b --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N20B/LQFP100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV71N20B_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N20B/TFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N20B/TFBGA100/mcu_definitions.h new file mode 100644 index 000000000..a71c8f48e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N20B/TFBGA100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV71N20B_TFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N21A/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N21A/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..5e0bf1010 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N21A/LQFP100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV71N21A_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N21A/TFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N21A/TFBGA100/mcu_definitions.h new file mode 100644 index 000000000..cd31ed054 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N21A/TFBGA100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV71N21A_TFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N21B/LQFP100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N21B/LQFP100/mcu_definitions.h new file mode 100644 index 000000000..e44563d5d --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N21B/LQFP100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV71N21B_LQFP100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N21B/TFBGA100/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N21B/TFBGA100/mcu_definitions.h new file mode 100644 index 000000000..0efdb7151 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71N21B/TFBGA100/mcu_definitions.h @@ -0,0 +1,253 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV71N21B_TFBGA100. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (2) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB + +#define SPI_MODULE_0 (0) + +#define SPI_MODULE_COUNT (1) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_D_CN + +#define PORT_COUNT (3) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q19A/LQFP144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q19A/LQFP144/mcu_definitions.h new file mode 100644 index 000000000..2b0490793 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q19A/LQFP144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV71Q19A_LQFP144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q19A/TFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q19A/TFBGA144/mcu_definitions.h new file mode 100644 index 000000000..f8a0be7d1 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q19A/TFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV71Q19A_TFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q19B/LQFP144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q19B/LQFP144/mcu_definitions.h new file mode 100644 index 000000000..8cfbd9a5e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q19B/LQFP144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV71Q19B_LQFP144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q19B/TFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q19B/TFBGA144/mcu_definitions.h new file mode 100644 index 000000000..6fccc9e6f --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q19B/TFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV71Q19B_TFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q20A/LQFP144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q20A/LQFP144/mcu_definitions.h new file mode 100644 index 000000000..cffa0cdf4 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q20A/LQFP144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV71Q20A_LQFP144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q20A/TFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q20A/TFBGA144/mcu_definitions.h new file mode 100644 index 000000000..a71a9034b --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q20A/TFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV71Q20A_TFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q20B/LQFP144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q20B/LQFP144/mcu_definitions.h new file mode 100644 index 000000000..b42c8120d --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q20B/LQFP144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV71Q20B_LQFP144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q20B/TFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q20B/TFBGA144/mcu_definitions.h new file mode 100644 index 000000000..90a27ad94 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q20B/TFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV71Q20B_TFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q21A/LQFP144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q21A/LQFP144/mcu_definitions.h new file mode 100644 index 000000000..8bc916063 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q21A/LQFP144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV71Q21A_LQFP144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q21A/TFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q21A/TFBGA144/mcu_definitions.h new file mode 100644 index 000000000..ea5e49377 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q21A/TFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV71Q21A_TFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q21B/LQFP144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q21B/LQFP144/mcu_definitions.h new file mode 100644 index 000000000..2b414b1f1 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q21B/LQFP144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV71Q21B_LQFP144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q21B/TFBGA144/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q21B/TFBGA144/mcu_definitions.h new file mode 100644 index 000000000..3f0534a5a --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_definitions/SAM/ATSAMV71Q21B/TFBGA144/mcu_definitions.h @@ -0,0 +1,328 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file mcu_definitions.h + * @brief MCU specific pin and module definitions for ATSAMV71Q21B_TFBGA144. + */ + +#ifndef _MCU_DEFINITIONS_H_ +#define _MCU_DEFINITIONS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// ADC +#define ADC0_PD30_CH0 +#define ADC0_PA21_CH1 +#define ADC0_PB3_CH2 +#define ADC0_PE5_CH3 +#define ADC0_PE4_CH4 +#define ADC0_PB2_CH5 +#define ADC0_PA17_CH6 +#define ADC0_PA18_CH7 +#define ADC0_PA19_CH8 +#define ADC0_PA20_CH9 +#define ADC0_PB0_CH10 +#define ADC1_PB1_CH0 +#define ADC1_PC13_CH1 +#define ADC1_PC15_CH2 +#define ADC1_PC12_CH3 +#define ADC1_PC29_CH4 +#define ADC1_PC30_CH5 +#define ADC1_PC31_CH6 +#define ADC1_PC26_CH7 +#define ADC1_PC27_CH8 +#define ADC1_PC0_CH9 +#define ADC1_PE3_CH10 +#define ADC1_PE0_CH11 + +#define ADC_MODULE_0 (0) +#define ADC_MODULE_1 (1) + +#define ADC_MODULE_COUNT (2) +// EOF ADC + +// I2C +#define I2C0_SCL_PA4_AFA +#define I2C0_SDA_PA3_AFA +#define I2C1_SCL_PB5_AFA +#define I2C1_SDA_PB4_AFA +#define I2C2_SCL_PD28_AFC +#define I2C2_SDA_PD27_AFC + +#define I2C_MODULE_0 (0) +#define I2C_MODULE_1 (1) +#define I2C_MODULE_2 (2) + +#define I2C_MODULE_COUNT (3) +// EOF I2C + +// TIM +#define TIM0_CH0_A_PA0_AFB +#define TIM0_CH1_A_PA15_AFB +#define TIM0_CH2_A_PA26_AFB +#define TIM0_CH0_B_PA1_AFB +#define TIM0_CH1_B_PA16_AFB +#define TIM0_CH2_B_PA27_AFB +#define TIM1_CH0_A_PC23_AFB +#define TIM1_CH1_A_PC26_AFB +#define TIM1_CH2_A_PC29_AFB +#define TIM1_CH0_B_PC24_AFB +#define TIM1_CH1_B_PC27_AFB +#define TIM1_CH2_B_PC30_AFB +#define TIM2_CH0_A_PC5_AFB +#define TIM2_CH1_A_PC8_AFB +#define TIM2_CH2_A_PC11_AFB +#define TIM2_CH0_B_PC6_AFB +#define TIM2_CH1_B_PC9_AFB +#define TIM2_CH2_B_PC12_AFB +#define TIM3_CH0_A_PE0_AFB +#define TIM3_CH1_A_PE3_AFB +#define TIM3_CH2_A_PD21_AFC +#define TIM3_CH0_B_PE1_AFB +#define TIM3_CH1_B_PE4_AFB +#define TIM3_CH2_B_PD22_AFC + +#define TIM_MODULE_0 (0) +#define TIM_MODULE_1 (1) +#define TIM_MODULE_2 (2) +#define TIM_MODULE_3 (3) + +#define TIM_CHANNEL_NUMBER (3) +#define TIM_MODULE_COUNT (4) +// EOF TIM + +// USART +#define USART0_RX_PB0_AFC +#define USART0_TX_PB1_AFC +#define USART1_RX_PA21_AFA +#define USART1_TX_PB4_AFD +#define USART2_RX_PD15_AFB +#define USART2_TX_PD16_AFB + +#define USART_MODULE_0 (0) +#define USART_MODULE_1 (1) +#define USART_MODULE_2 (2) + +#define USART_MODULE_COUNT (3) +// EOF USART + +// UART +#define UART0_RX_PA9_AFA +#define UART0_TX_PA10_AFA +#define UART1_RX_PA5_AFC +#define UART1_TX_PA4_AFC +#define UART1_TX_PA6_AFC +#define UART1_TX_PD26_AFD +#define UART2_RX_PD25_AFC +#define UART2_TX_PD26_AFC +#define UART3_RX_PD28_AFA +#define UART3_TX_PD30_AFA +#define UART3_TX_PD31_AFB +#define UART4_RX_PD18_AFC +#define UART4_TX_PD3_AFC +#define UART4_TX_PD19_AFC + +#define UART_MODULE_0 (0) +#define UART_MODULE_1 (1) +#define UART_MODULE_2 (2) +#define UART_MODULE_3 (3) +#define UART_MODULE_4 (4) + +#define UART_MODULE_COUNT (5) +// EOF UART + +// SPI +#define SPI0_MISO_PD20_AFB +#define SPI0_MOSI_PD21_AFB +#define SPI0_SCK_PD22_AFB +#define SPI1_MISO_PC26_AFC +#define SPI1_MOSI_PC27_AFC +#define SPI1_SCK_PC24_AFC + +#define SPI_MODULE_0 (0) +#define SPI_MODULE_1 (1) + +#define SPI_MODULE_COUNT (2) +// EOF SPI + +// GPIO +#define __PA0_CN +#define __PA1_CN +#define __PA2_CN +#define __PA3_CN +#define __PA4_CN +#define __PA5_CN +#define __PA6_CN +#define __PA7_CN +#define __PA8_CN +#define __PA9_CN +#define __PA10_CN +#define __PA11_CN +#define __PA12_CN +#define __PA13_CN +#define __PA14_CN +#define __PA15_CN +#define __PA16_CN +#define __PA17_CN +#define __PA18_CN +#define __PA19_CN +#define __PA20_CN +#define __PA21_CN +#define __PA22_CN +#define __PA23_CN +#define __PA24_CN +#define __PA25_CN +#define __PA26_CN +#define __PA27_CN +#define __PA28_CN +#define __PA29_CN +#define __PA30_CN +#define __PA31_CN +#define __PB0_CN +#define __PB1_CN +#define __PB2_CN +#define __PB3_CN +#define __PB4_CN +#define __PB5_CN +#define __PB6_CN +#define __PB7_CN +#define __PB8_CN +#define __PB9_CN +#define __PB12_CN +#define __PB13_CN +#define __PC0_CN +#define __PC1_CN +#define __PC2_CN +#define __PC3_CN +#define __PC4_CN +#define __PC5_CN +#define __PC6_CN +#define __PC7_CN +#define __PC8_CN +#define __PC9_CN +#define __PC10_CN +#define __PC11_CN +#define __PC12_CN +#define __PC13_CN +#define __PC14_CN +#define __PC15_CN +#define __PC16_CN +#define __PC17_CN +#define __PC18_CN +#define __PC19_CN +#define __PC20_CN +#define __PC21_CN +#define __PC22_CN +#define __PC23_CN +#define __PC24_CN +#define __PC25_CN +#define __PC26_CN +#define __PC27_CN +#define __PC28_CN +#define __PC29_CN +#define __PC30_CN +#define __PC31_CN +#define __PD0_CN +#define __PD1_CN +#define __PD2_CN +#define __PD3_CN +#define __PD4_CN +#define __PD5_CN +#define __PD6_CN +#define __PD7_CN +#define __PD8_CN +#define __PD9_CN +#define __PD10_CN +#define __PD11_CN +#define __PD12_CN +#define __PD13_CN +#define __PD14_CN +#define __PD15_CN +#define __PD16_CN +#define __PD17_CN +#define __PD18_CN +#define __PD19_CN +#define __PD20_CN +#define __PD21_CN +#define __PD22_CN +#define __PD23_CN +#define __PD24_CN +#define __PD25_CN +#define __PD26_CN +#define __PD27_CN +#define __PD28_CN +#define __PD29_CN +#define __PD30_CN +#define __PD31_CN +#define __PE0_CN +#define __PE1_CN +#define __PE2_CN +#define __PE3_CN +#define __PE4_CN +#define __PE5_CN + +#define __PORT_A_CN +#define __PORT_B_CN +#define __PORT_C_CN +#define __PORT_D_CN +#define __PORT_E_CN + +#define PORT_COUNT (5) +#define PORT_SIZE (32) +// EOF GPIO + +// IVT Table +#define UART0_NVIC (7) +#define UART1_NVIC (8) +#define USART0_NVIC (13) +#define USART1_NVIC (14) +#define USART2_NVIC (15) +#define UART2_NVIC (44) +#define UART3_NVIC (45) +#define UART4_NVIC (46) +// EOF IVT Table + +#ifdef __cplusplus +} +#endif + +#endif // _MCU_DEFINITIONS_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70J19A/LQFP64/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70J19A/LQFP64/mcu_reg_addresses.h new file mode 100644 index 000000000..64528f940 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70J19A/LQFP64/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70J19A_LQFP64 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70J19A_LQFP64 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70J19B/LQFP64/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70J19B/LQFP64/mcu_reg_addresses.h new file mode 100644 index 000000000..73cc7939d --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70J19B/LQFP64/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70J19B_LQFP64 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70J19B_LQFP64 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70J20A/LQFP64/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70J20A/LQFP64/mcu_reg_addresses.h new file mode 100644 index 000000000..2d896dad5 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70J20A/LQFP64/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70J20A_LQFP64 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70J20A_LQFP64 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70J20B/LQFP64/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70J20B/LQFP64/mcu_reg_addresses.h new file mode 100644 index 000000000..c6c8994e3 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70J20B/LQFP64/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70J20B_LQFP64 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70J20B_LQFP64 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70J21A/LQFP64/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70J21A/LQFP64/mcu_reg_addresses.h new file mode 100644 index 000000000..7d08ad177 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70J21A/LQFP64/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70J21A_LQFP64 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70J21A_LQFP64 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70J21B/LQFP64/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70J21B/LQFP64/mcu_reg_addresses.h new file mode 100644 index 000000000..aa9bbabe2 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70J21B/LQFP64/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70J21B_LQFP64 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70J21B_LQFP64 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N19A/LQFP100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N19A/LQFP100/mcu_reg_addresses.h new file mode 100644 index 000000000..30f042c5e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N19A/LQFP100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70N19A_LQFP100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70N19A_LQFP100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N19A/TFBGA100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N19A/TFBGA100/mcu_reg_addresses.h new file mode 100644 index 000000000..7093e1a9f --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N19A/TFBGA100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70N19A_TFBGA100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70N19A_TFBGA100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N19B/LQFP100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N19B/LQFP100/mcu_reg_addresses.h new file mode 100644 index 000000000..3bbbd3339 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N19B/LQFP100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70N19B_LQFP100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70N19B_LQFP100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N19B/TFBGA100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N19B/TFBGA100/mcu_reg_addresses.h new file mode 100644 index 000000000..67825b9bd --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N19B/TFBGA100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70N19B_TFBGA100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70N19B_TFBGA100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N20A/LQFP100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N20A/LQFP100/mcu_reg_addresses.h new file mode 100644 index 000000000..e0adb75cd --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N20A/LQFP100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70N20A_LQFP100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70N20A_LQFP100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N20A/TFBGA100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N20A/TFBGA100/mcu_reg_addresses.h new file mode 100644 index 000000000..0ab04378e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N20A/TFBGA100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70N20A_TFBGA100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70N20A_TFBGA100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N20B/LQFP100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N20B/LQFP100/mcu_reg_addresses.h new file mode 100644 index 000000000..80009add9 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N20B/LQFP100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70N20B_LQFP100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70N20B_LQFP100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N20B/TFBGA100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N20B/TFBGA100/mcu_reg_addresses.h new file mode 100644 index 000000000..eddc45452 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N20B/TFBGA100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70N20B_TFBGA100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70N20B_TFBGA100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N21A/LQFP100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N21A/LQFP100/mcu_reg_addresses.h new file mode 100644 index 000000000..0449f43fb --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N21A/LQFP100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70N21A_LQFP100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70N21A_LQFP100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N21A/TFBGA100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N21A/TFBGA100/mcu_reg_addresses.h new file mode 100644 index 000000000..d0c6a831a --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N21A/TFBGA100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70N21A_TFBGA100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70N21A_TFBGA100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N21B/LQFP100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N21B/LQFP100/mcu_reg_addresses.h new file mode 100644 index 000000000..1372f5d66 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N21B/LQFP100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70N21B_LQFP100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70N21B_LQFP100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N21B/TFBGA100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N21B/TFBGA100/mcu_reg_addresses.h new file mode 100644 index 000000000..8d31d2eeb --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70N21B/TFBGA100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70N21B_TFBGA100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70N21B_TFBGA100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q19A/LFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q19A/LFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..ad2969c28 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q19A/LFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70Q19A_LFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70Q19A_LFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q19A/LQFP144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q19A/LQFP144/mcu_reg_addresses.h new file mode 100644 index 000000000..40ce3389c --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q19A/LQFP144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70Q19A_LQFP144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70Q19A_LQFP144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q19A/UFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q19A/UFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..1c7001479 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q19A/UFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70Q19A_UFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70Q19A_UFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q19B/LFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q19B/LFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..3782a7231 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q19B/LFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70Q19B_LFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70Q19B_LFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q19B/LQFP144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q19B/LQFP144/mcu_reg_addresses.h new file mode 100644 index 000000000..f5d1952db --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q19B/LQFP144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70Q19B_LQFP144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70Q19B_LQFP144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q19B/UFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q19B/UFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..4e5bbaead --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q19B/UFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70Q19B_UFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70Q19B_UFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q20A/LFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q20A/LFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..edbb7b6da --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q20A/LFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70Q20A_LFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70Q20A_LFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q20A/LQFP144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q20A/LQFP144/mcu_reg_addresses.h new file mode 100644 index 000000000..a72296cff --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q20A/LQFP144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70Q20A_LQFP144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70Q20A_LQFP144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q20A/UFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q20A/UFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..787a973b9 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q20A/UFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70Q20A_UFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70Q20A_UFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q20B/LFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q20B/LFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..afa7fb25a --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q20B/LFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70Q20B_LFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70Q20B_LFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q20B/LQFP144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q20B/LQFP144/mcu_reg_addresses.h new file mode 100644 index 000000000..ac400ee62 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q20B/LQFP144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70Q20B_LQFP144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70Q20B_LQFP144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q20B/UFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q20B/UFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..75fb7c55f --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q20B/UFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70Q20B_UFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70Q20B_UFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q21A/LFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q21A/LFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..69f7ce669 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q21A/LFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70Q21A_LFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70Q21A_LFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q21A/LQFP144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q21A/LQFP144/mcu_reg_addresses.h new file mode 100644 index 000000000..69e8c2ed6 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q21A/LQFP144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70Q21A_LQFP144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70Q21A_LQFP144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q21A/UFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q21A/UFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..fe336e0d5 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q21A/UFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70Q21A_UFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70Q21A_UFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q21B/LFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q21B/LFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..aa96df2b5 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q21B/LFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70Q21B_LFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70Q21B_LFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q21B/LQFP144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q21B/LQFP144/mcu_reg_addresses.h index aac0a5f8b..815526027 100644 --- a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q21B/LQFP144/mcu_reg_addresses.h +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q21B/LQFP144/mcu_reg_addresses.h @@ -39,13 +39,13 @@ /*! * @file mcu_reg_addresses.h * @brief MCU specific register address definitions. -* @details ATSAME70Q21B register address definitions. +* @details ATSAME70Q21B_LQFP144 register address definitions. */ #ifndef _MCU_REG_ADDRESSES_H_ #define _MCU_REG_ADDRESSES_H_ -// ATSAME70Q21B REGISTER DEFINITIONS +// ATSAME70Q21B_LQFP144 REGISTER DEFINITIONS // TODO - add if any // EOF REGISTER DEFINITIONS diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q21B/UFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q21B/UFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..a7cb9aaf1 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAME70Q21B/UFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAME70Q21B_UFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAME70Q21B_UFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J19A/LQFP64/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J19A/LQFP64/mcu_reg_addresses.h new file mode 100644 index 000000000..84fbd7cbb --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J19A/LQFP64/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70J19A_LQFP64 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70J19A_LQFP64 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J19A/QFN64/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J19A/QFN64/mcu_reg_addresses.h new file mode 100644 index 000000000..c4a2096f7 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J19A/QFN64/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70J19A_QFN64 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70J19A_QFN64 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J19B/LQFP64/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J19B/LQFP64/mcu_reg_addresses.h new file mode 100644 index 000000000..b5df904b2 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J19B/LQFP64/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70J19B_LQFP64 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70J19B_LQFP64 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J19B/QFN64/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J19B/QFN64/mcu_reg_addresses.h new file mode 100644 index 000000000..0e6a6bece --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J19B/QFN64/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70J19B_QFN64 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70J19B_QFN64 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J20A/LQFP64/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J20A/LQFP64/mcu_reg_addresses.h new file mode 100644 index 000000000..130acadca --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J20A/LQFP64/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70J20A_LQFP64 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70J20A_LQFP64 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J20A/QFN64/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J20A/QFN64/mcu_reg_addresses.h new file mode 100644 index 000000000..82931cf2d --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J20A/QFN64/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70J20A_QFN64 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70J20A_QFN64 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J20B/LQFP64/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J20B/LQFP64/mcu_reg_addresses.h new file mode 100644 index 000000000..21445aece --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J20B/LQFP64/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70J20B_LQFP64 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70J20B_LQFP64 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J20B/QFN64/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J20B/QFN64/mcu_reg_addresses.h new file mode 100644 index 000000000..5d7d2098a --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J20B/QFN64/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70J20B_QFN64 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70J20B_QFN64 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J21A/LQFP64/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J21A/LQFP64/mcu_reg_addresses.h new file mode 100644 index 000000000..1ee291bc6 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J21A/LQFP64/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70J21A_LQFP64 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70J21A_LQFP64 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J21A/QFN64/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J21A/QFN64/mcu_reg_addresses.h new file mode 100644 index 000000000..1535d83c7 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J21A/QFN64/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70J21A_QFN64 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70J21A_QFN64 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J21B/LQFP64/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J21B/LQFP64/mcu_reg_addresses.h new file mode 100644 index 000000000..e12ff7c73 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J21B/LQFP64/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70J21B_LQFP64 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70J21B_LQFP64 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J21B/QFN64/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J21B/QFN64/mcu_reg_addresses.h new file mode 100644 index 000000000..7dd2ce78c --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70J21B/QFN64/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70J21B_QFN64 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70J21B_QFN64 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N19A/LQFP100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N19A/LQFP100/mcu_reg_addresses.h new file mode 100644 index 000000000..9c34180e5 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N19A/LQFP100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70N19A_LQFP100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70N19A_LQFP100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N19A/TFBGA100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N19A/TFBGA100/mcu_reg_addresses.h new file mode 100644 index 000000000..cd5930e1d --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N19A/TFBGA100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70N19A_TFBGA100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70N19A_TFBGA100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N19A/VFBGA100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N19A/VFBGA100/mcu_reg_addresses.h new file mode 100644 index 000000000..7b9385bc2 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N19A/VFBGA100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70N19A_VFBGA100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70N19A_VFBGA100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N19B/LQFP100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N19B/LQFP100/mcu_reg_addresses.h new file mode 100644 index 000000000..54a3ddab4 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N19B/LQFP100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70N19B_LQFP100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70N19B_LQFP100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N19B/TFBGA100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N19B/TFBGA100/mcu_reg_addresses.h new file mode 100644 index 000000000..e7bb42af4 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N19B/TFBGA100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70N19B_TFBGA100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70N19B_TFBGA100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N19B/VFBGA100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N19B/VFBGA100/mcu_reg_addresses.h new file mode 100644 index 000000000..dc344227c --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N19B/VFBGA100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70N19B_VFBGA100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70N19B_VFBGA100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N20A/LQFP100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N20A/LQFP100/mcu_reg_addresses.h new file mode 100644 index 000000000..9c8466ad1 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N20A/LQFP100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70N20A_LQFP100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70N20A_LQFP100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N20A/TFBGA100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N20A/TFBGA100/mcu_reg_addresses.h new file mode 100644 index 000000000..bf9d4dbd6 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N20A/TFBGA100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70N20A_TFBGA100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70N20A_TFBGA100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N20A/VFBGA100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N20A/VFBGA100/mcu_reg_addresses.h new file mode 100644 index 000000000..fffa688a1 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N20A/VFBGA100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70N20A_VFBGA100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70N20A_VFBGA100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N20B/LQFP100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N20B/LQFP100/mcu_reg_addresses.h new file mode 100644 index 000000000..2a1e3a79e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N20B/LQFP100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70N20B_LQFP100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70N20B_LQFP100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N20B/TFBGA100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N20B/TFBGA100/mcu_reg_addresses.h new file mode 100644 index 000000000..2e5d28b0f --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N20B/TFBGA100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70N20B_TFBGA100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70N20B_TFBGA100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N20B/VFBGA100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N20B/VFBGA100/mcu_reg_addresses.h new file mode 100644 index 000000000..a78760def --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N20B/VFBGA100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70N20B_VFBGA100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70N20B_VFBGA100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N21A/LQFP100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N21A/LQFP100/mcu_reg_addresses.h new file mode 100644 index 000000000..5068cf7dd --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N21A/LQFP100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70N21A_LQFP100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70N21A_LQFP100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N21A/TFBGA100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N21A/TFBGA100/mcu_reg_addresses.h new file mode 100644 index 000000000..1b11ccd3f --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N21A/TFBGA100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70N21A_TFBGA100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70N21A_TFBGA100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N21A/VFBGA100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N21A/VFBGA100/mcu_reg_addresses.h new file mode 100644 index 000000000..d7cca125c --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N21A/VFBGA100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70N21A_VFBGA100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70N21A_VFBGA100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N21B/LQFP100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N21B/LQFP100/mcu_reg_addresses.h new file mode 100644 index 000000000..daac50623 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N21B/LQFP100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70N21B_LQFP100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70N21B_LQFP100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N21B/TFBGA100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N21B/TFBGA100/mcu_reg_addresses.h new file mode 100644 index 000000000..63466b120 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N21B/TFBGA100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70N21B_TFBGA100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70N21B_TFBGA100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N21B/VFBGA100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N21B/VFBGA100/mcu_reg_addresses.h new file mode 100644 index 000000000..05fb9ef76 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70N21B/VFBGA100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70N21B_VFBGA100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70N21B_VFBGA100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q19A/LFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q19A/LFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..2f60ff077 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q19A/LFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70Q19A_LFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70Q19A_LFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q19A/LQFP144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q19A/LQFP144/mcu_reg_addresses.h new file mode 100644 index 000000000..0b034b893 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q19A/LQFP144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70Q19A_LQFP144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70Q19A_LQFP144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q19A/UFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q19A/UFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..8e64be02c --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q19A/UFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70Q19A_UFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70Q19A_UFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q19B/LFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q19B/LFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..9c592a5fa --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q19B/LFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70Q19B_LFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70Q19B_LFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q19B/LQFP144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q19B/LQFP144/mcu_reg_addresses.h new file mode 100644 index 000000000..caaac30a6 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q19B/LQFP144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70Q19B_LQFP144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70Q19B_LQFP144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q19B/UFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q19B/UFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..4dabb7e7f --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q19B/UFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70Q19B_UFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70Q19B_UFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q20A/LFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q20A/LFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..f4c5274f5 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q20A/LFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70Q20A_LFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70Q20A_LFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q20A/LQFP144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q20A/LQFP144/mcu_reg_addresses.h new file mode 100644 index 000000000..47899f1d4 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q20A/LQFP144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70Q20A_LQFP144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70Q20A_LQFP144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q20A/UFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q20A/UFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..b5dc1c2b2 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q20A/UFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70Q20A_UFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70Q20A_UFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q20B/LFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q20B/LFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..90bb782d3 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q20B/LFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70Q20B_LFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70Q20B_LFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q20B/LQFP144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q20B/LQFP144/mcu_reg_addresses.h new file mode 100644 index 000000000..da9c11f1d --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q20B/LQFP144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70Q20B_LQFP144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70Q20B_LQFP144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q20B/UFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q20B/UFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..dc0e72a55 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q20B/UFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70Q20B_UFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70Q20B_UFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q21A/LFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q21A/LFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..123c2b4ae --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q21A/LFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70Q21A_LFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70Q21A_LFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q21A/LQFP144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q21A/LQFP144/mcu_reg_addresses.h new file mode 100644 index 000000000..cd0505cc5 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q21A/LQFP144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70Q21A_LQFP144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70Q21A_LQFP144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q21A/UFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q21A/UFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..7e75871d8 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q21A/UFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70Q21A_UFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70Q21A_UFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q21B/LFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q21B/LFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..76164c50d --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q21B/LFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70Q21B_LFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70Q21B_LFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q21B/LQFP144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q21B/LQFP144/mcu_reg_addresses.h new file mode 100644 index 000000000..7b7bb0601 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q21B/LQFP144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70Q21B_LQFP144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70Q21B_LQFP144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q21B/UFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q21B/UFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..5a6f4409f --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMS70Q21B/UFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMS70Q21B_UFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMS70Q21B_UFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70J19A/LQFP64/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70J19A/LQFP64/mcu_reg_addresses.h new file mode 100644 index 000000000..98e15b5cd --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70J19A/LQFP64/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV70J19A_LQFP64 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV70J19A_LQFP64 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70J19B/LQFP64/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70J19B/LQFP64/mcu_reg_addresses.h new file mode 100644 index 000000000..fa7ea848b --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70J19B/LQFP64/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV70J19B_LQFP64 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV70J19B_LQFP64 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70J20A/LQFP64/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70J20A/LQFP64/mcu_reg_addresses.h new file mode 100644 index 000000000..68e5ce85a --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70J20A/LQFP64/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV70J20A_LQFP64 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV70J20A_LQFP64 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70J20B/LQFP64/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70J20B/LQFP64/mcu_reg_addresses.h new file mode 100644 index 000000000..c80bd2f9c --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70J20B/LQFP64/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV70J20B_LQFP64 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV70J20B_LQFP64 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70N19A/LQFP100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70N19A/LQFP100/mcu_reg_addresses.h new file mode 100644 index 000000000..cbcc6b281 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70N19A/LQFP100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV70N19A_LQFP100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV70N19A_LQFP100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70N19A/TFBGA100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70N19A/TFBGA100/mcu_reg_addresses.h new file mode 100644 index 000000000..aec887cf7 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70N19A/TFBGA100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV70N19A_TFBGA100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV70N19A_TFBGA100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70N19B/LQFP100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70N19B/LQFP100/mcu_reg_addresses.h new file mode 100644 index 000000000..c2a495356 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70N19B/LQFP100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV70N19B_LQFP100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV70N19B_LQFP100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70N19B/TFBGA100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70N19B/TFBGA100/mcu_reg_addresses.h new file mode 100644 index 000000000..c6fe70b69 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70N19B/TFBGA100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV70N19B_TFBGA100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV70N19B_TFBGA100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70N20A/LQFP100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70N20A/LQFP100/mcu_reg_addresses.h new file mode 100644 index 000000000..0ba0346f0 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70N20A/LQFP100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV70N20A_LQFP100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV70N20A_LQFP100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70N20A/TFBGA100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70N20A/TFBGA100/mcu_reg_addresses.h new file mode 100644 index 000000000..a541e8e71 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70N20A/TFBGA100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV70N20A_TFBGA100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV70N20A_TFBGA100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70N20B/LQFP100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70N20B/LQFP100/mcu_reg_addresses.h new file mode 100644 index 000000000..eb7b5fcb7 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70N20B/LQFP100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV70N20B_LQFP100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV70N20B_LQFP100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70N20B/TFBGA100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70N20B/TFBGA100/mcu_reg_addresses.h new file mode 100644 index 000000000..bfbcc118d --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70N20B/TFBGA100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV70N20B_TFBGA100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV70N20B_TFBGA100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70Q19A/LQFP144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70Q19A/LQFP144/mcu_reg_addresses.h new file mode 100644 index 000000000..29c9d67a3 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70Q19A/LQFP144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV70Q19A_LQFP144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV70Q19A_LQFP144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70Q19A/TFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70Q19A/TFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..d3043dbdd --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70Q19A/TFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV70Q19A_TFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV70Q19A_TFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70Q19B/LQFP144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70Q19B/LQFP144/mcu_reg_addresses.h new file mode 100644 index 000000000..33113814a --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70Q19B/LQFP144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV70Q19B_LQFP144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV70Q19B_LQFP144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70Q19B/TFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70Q19B/TFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..f71bf4077 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70Q19B/TFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV70Q19B_TFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV70Q19B_TFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70Q20A/LQFP144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70Q20A/LQFP144/mcu_reg_addresses.h new file mode 100644 index 000000000..cbb240d93 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70Q20A/LQFP144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV70Q20A_LQFP144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV70Q20A_LQFP144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70Q20A/TFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70Q20A/TFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..4081c52c3 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70Q20A/TFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV70Q20A_TFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV70Q20A_TFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70Q20B/LQFP144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70Q20B/LQFP144/mcu_reg_addresses.h new file mode 100644 index 000000000..88935db53 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70Q20B/LQFP144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV70Q20B_LQFP144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV70Q20B_LQFP144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70Q20B/TFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70Q20B/TFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..7cbeb1b0c --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV70Q20B/TFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV70Q20B_TFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV70Q20B_TFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71J19A/LQFP64/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71J19A/LQFP64/mcu_reg_addresses.h new file mode 100644 index 000000000..fb75daff8 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71J19A/LQFP64/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV71J19A_LQFP64 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV71J19A_LQFP64 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71J19B/LQFP64/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71J19B/LQFP64/mcu_reg_addresses.h new file mode 100644 index 000000000..61c3d5119 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71J19B/LQFP64/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV71J19B_LQFP64 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV71J19B_LQFP64 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71J20A/LQFP64/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71J20A/LQFP64/mcu_reg_addresses.h new file mode 100644 index 000000000..d6df45f79 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71J20A/LQFP64/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV71J20A_LQFP64 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV71J20A_LQFP64 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71J20B/LQFP64/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71J20B/LQFP64/mcu_reg_addresses.h new file mode 100644 index 000000000..5b643a276 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71J20B/LQFP64/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV71J20B_LQFP64 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV71J20B_LQFP64 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71J21A/LQFP64/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71J21A/LQFP64/mcu_reg_addresses.h new file mode 100644 index 000000000..cb23efe9a --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71J21A/LQFP64/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV71J21A_LQFP64 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV71J21A_LQFP64 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71J21B/LQFP64/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71J21B/LQFP64/mcu_reg_addresses.h new file mode 100644 index 000000000..7ca462ff5 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71J21B/LQFP64/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV71J21B_LQFP64 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV71J21B_LQFP64 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N19A/LQFP100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N19A/LQFP100/mcu_reg_addresses.h new file mode 100644 index 000000000..d4c9ed4d3 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N19A/LQFP100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV71N19A_LQFP100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV71N19A_LQFP100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N19A/TFBGA100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N19A/TFBGA100/mcu_reg_addresses.h new file mode 100644 index 000000000..ada5902dd --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N19A/TFBGA100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV71N19A_TFBGA100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV71N19A_TFBGA100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N19B/LQFP100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N19B/LQFP100/mcu_reg_addresses.h new file mode 100644 index 000000000..5dee400b1 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N19B/LQFP100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV71N19B_LQFP100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV71N19B_LQFP100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N19B/TFBGA100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N19B/TFBGA100/mcu_reg_addresses.h new file mode 100644 index 000000000..6ce1c1fd5 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N19B/TFBGA100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV71N19B_TFBGA100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV71N19B_TFBGA100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N20A/LQFP100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N20A/LQFP100/mcu_reg_addresses.h new file mode 100644 index 000000000..f666eca2d --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N20A/LQFP100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV71N20A_LQFP100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV71N20A_LQFP100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N20A/TFBGA100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N20A/TFBGA100/mcu_reg_addresses.h new file mode 100644 index 000000000..c9fcb56f8 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N20A/TFBGA100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV71N20A_TFBGA100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV71N20A_TFBGA100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N20B/LQFP100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N20B/LQFP100/mcu_reg_addresses.h new file mode 100644 index 000000000..be894ce7e --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N20B/LQFP100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV71N20B_LQFP100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV71N20B_LQFP100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N20B/TFBGA100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N20B/TFBGA100/mcu_reg_addresses.h new file mode 100644 index 000000000..8ef21fcee --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N20B/TFBGA100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV71N20B_TFBGA100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV71N20B_TFBGA100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N21A/LQFP100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N21A/LQFP100/mcu_reg_addresses.h new file mode 100644 index 000000000..032336e0b --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N21A/LQFP100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV71N21A_LQFP100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV71N21A_LQFP100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N21A/TFBGA100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N21A/TFBGA100/mcu_reg_addresses.h new file mode 100644 index 000000000..0bb8704ce --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N21A/TFBGA100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV71N21A_TFBGA100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV71N21A_TFBGA100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N21B/LQFP100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N21B/LQFP100/mcu_reg_addresses.h new file mode 100644 index 000000000..74d233873 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N21B/LQFP100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV71N21B_LQFP100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV71N21B_LQFP100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N21B/TFBGA100/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N21B/TFBGA100/mcu_reg_addresses.h new file mode 100644 index 000000000..d6d601499 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71N21B/TFBGA100/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV71N21B_TFBGA100 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV71N21B_TFBGA100 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q19A/LQFP144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q19A/LQFP144/mcu_reg_addresses.h new file mode 100644 index 000000000..282e78dcb --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q19A/LQFP144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV71Q19A_LQFP144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV71Q19A_LQFP144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q19A/TFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q19A/TFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..2bb8f8fb6 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q19A/TFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV71Q19A_TFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV71Q19A_TFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q19B/LQFP144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q19B/LQFP144/mcu_reg_addresses.h new file mode 100644 index 000000000..26d30f3c5 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q19B/LQFP144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV71Q19B_LQFP144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV71Q19B_LQFP144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q19B/TFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q19B/TFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..a76ccaa64 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q19B/TFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV71Q19B_TFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV71Q19B_TFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q20A/LQFP144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q20A/LQFP144/mcu_reg_addresses.h new file mode 100644 index 000000000..b268f64cb --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q20A/LQFP144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV71Q20A_LQFP144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV71Q20A_LQFP144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q20A/TFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q20A/TFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..fd3999db6 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q20A/TFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV71Q20A_TFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV71Q20A_TFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q20B/LQFP144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q20B/LQFP144/mcu_reg_addresses.h new file mode 100644 index 000000000..f560ae08b --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q20B/LQFP144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV71Q20B_LQFP144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV71Q20B_LQFP144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q20B/TFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q20B/TFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..69ad3febd --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q20B/TFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV71Q20B_TFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV71Q20B_TFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q21A/LQFP144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q21A/LQFP144/mcu_reg_addresses.h new file mode 100644 index 000000000..896902ff7 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q21A/LQFP144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV71Q21A_LQFP144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV71Q21A_LQFP144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q21A/TFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q21A/TFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..eecdced18 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q21A/TFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV71Q21A_TFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV71Q21A_TFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q21B/LQFP144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q21B/LQFP144/mcu_reg_addresses.h new file mode 100644 index 000000000..1e110a3f2 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q21B/LQFP144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV71Q21B_LQFP144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV71Q21B_LQFP144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q21B/TFBGA144/mcu_reg_addresses.h b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q21B/TFBGA144/mcu_reg_addresses.h new file mode 100644 index 000000000..b15608684 --- /dev/null +++ b/targets/arm/mikroe/common/include/mcu_reg_addresses/SAM/ATSAMV71Q21B/TFBGA144/mcu_reg_addresses.h @@ -0,0 +1,53 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! +* @file mcu_reg_addresses.h +* @brief MCU specific register address definitions. +* @details ATSAMV71Q21B_TFBGA144 register address definitions. +*/ + +#ifndef _MCU_REG_ADDRESSES_H_ +#define _MCU_REG_ADDRESSES_H_ + +// ATSAMV71Q21B_TFBGA144 REGISTER DEFINITIONS +// TODO - add if any +// EOF REGISTER DEFINITIONS + +#endif // _MCU_REG_ADDRESSES_H_ +// ------------------------------------------------------------------------- END From e18f25edbf9f31130446e9de4622e99d8869c20c Mon Sep 17 00:00:00 2001 From: "ivan.ruzavin" Date: Fri, 22 Nov 2024 12:25:02 +0100 Subject: [PATCH 20/56] Adjusted tim pin map for script --- .../implementation_1/hal_ll_tim_pin_map.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/implementation_1/hal_ll_tim_pin_map.h b/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/implementation_1/hal_ll_tim_pin_map.h index 9e29d4f1f..094ccad4c 100644 --- a/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/implementation_1/hal_ll_tim_pin_map.h +++ b/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/implementation_1/hal_ll_tim_pin_map.h @@ -89,28 +89,28 @@ typedef enum /*!< @brief TIM pins. */ static const hal_ll_tim_pin_map_t _tim_map[] = { {PA0, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x01, hal_ll_tim_module_num(TIM_MODULE_0)}, - {PA1, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x11, hal_ll_tim_module_num(TIM_MODULE_0)}, {PA15, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x01, hal_ll_tim_module_num(TIM_MODULE_0)}, - {PA16, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x11, hal_ll_tim_module_num(TIM_MODULE_0)}, {PA26, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x01, hal_ll_tim_module_num(TIM_MODULE_0)}, + {PA1, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x11, hal_ll_tim_module_num(TIM_MODULE_0)}, + {PA16, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x11, hal_ll_tim_module_num(TIM_MODULE_0)}, {PA27, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x11, hal_ll_tim_module_num(TIM_MODULE_0)}, {PC23, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x01, hal_ll_tim_module_num(TIM_MODULE_1)}, - {PC24, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x11, hal_ll_tim_module_num(TIM_MODULE_1)}, {PC26, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x01, hal_ll_tim_module_num(TIM_MODULE_1)}, - {PC27, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x11, hal_ll_tim_module_num(TIM_MODULE_1)}, {PC29, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x01, hal_ll_tim_module_num(TIM_MODULE_1)}, + {PC24, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x11, hal_ll_tim_module_num(TIM_MODULE_1)}, + {PC27, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x11, hal_ll_tim_module_num(TIM_MODULE_1)}, {PC30, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x11, hal_ll_tim_module_num(TIM_MODULE_1)}, {PC5, HAL_LL_TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x01, hal_ll_tim_module_num(TIM_MODULE_2)}, - {PC6, HAL_LL_TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x11, hal_ll_tim_module_num(TIM_MODULE_2)}, {PC8, HAL_LL_TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x01, hal_ll_tim_module_num(TIM_MODULE_2)}, - {PC9, HAL_LL_TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x11, hal_ll_tim_module_num(TIM_MODULE_2)}, {PC11, HAL_LL_TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x01, hal_ll_tim_module_num(TIM_MODULE_2)}, + {PC6, HAL_LL_TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x11, hal_ll_tim_module_num(TIM_MODULE_2)}, + {PC9, HAL_LL_TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x11, hal_ll_tim_module_num(TIM_MODULE_2)}, {PC12, HAL_LL_TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x11, hal_ll_tim_module_num(TIM_MODULE_2)}, {PE0, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x01, hal_ll_tim_module_num(TIM_MODULE_3)}, - {PE1, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x11, hal_ll_tim_module_num(TIM_MODULE_3)}, {PE3, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x01, hal_ll_tim_module_num(TIM_MODULE_3)}, - {PE4, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x11, hal_ll_tim_module_num(TIM_MODULE_3)}, {PD21, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x02, hal_ll_tim_module_num(TIM_MODULE_3)}, + {PE1, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x11, hal_ll_tim_module_num(TIM_MODULE_3)}, + {PE4, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x11, hal_ll_tim_module_num(TIM_MODULE_3)}, {PD22, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x12, hal_ll_tim_module_num(TIM_MODULE_3)}, { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_CHANNEL_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC } From 5a999a40b02531c10156bc0affecc949a6760fc0 Mon Sep 17 00:00:00 2001 From: "ivan.ruzavin" Date: Fri, 22 Nov 2024 12:58:39 +0100 Subject: [PATCH 21/56] Created pin mappings for ATSAME70Q21B --- .../implementation_1/hal_ll_adc_pin_map.h | 46 +++++++++++++++++ .../implementation_1/hal_ll_i2c_pin_map.h | 14 ++++++ .../hal_ll_spi_master_pin_map.h | 27 +++++++--- .../implementation_1/hal_ll_tim_pin_map.h | 48 ++++++++++++++++++ .../implementation_1/hal_ll_uart_pin_map.h | 50 +++++++++++++++++-- 5 files changed, 176 insertions(+), 9 deletions(-) diff --git a/targets/arm/mikroe/sam/include/adc/hal_ll_adc_pin_map/implementations/implementation_1/hal_ll_adc_pin_map.h b/targets/arm/mikroe/sam/include/adc/hal_ll_adc_pin_map/implementations/implementation_1/hal_ll_adc_pin_map.h index c48db748e..486b5cab8 100644 --- a/targets/arm/mikroe/sam/include/adc/hal_ll_adc_pin_map/implementations/implementation_1/hal_ll_adc_pin_map.h +++ b/targets/arm/mikroe/sam/include/adc/hal_ll_adc_pin_map/implementations/implementation_1/hal_ll_adc_pin_map.h @@ -94,29 +94,75 @@ static const hal_ll_base_addr_t HAL_LL_ADC1_BASE_ADDR = 0x40064000; /*!< ADC input pins. */ static const hal_ll_adc_pin_map_t _adc_map[] = { + #ifdef ADC0_PD30_CH0 {PD30, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_0}, + #endif + #ifdef ADC0_PA21_CH1 {PA21, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC0_PB3_CH2 {PB3, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC0_PE5_CH3 {PE5, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC0_PE4_CH4 {PE4, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC0_PB2_CH5 {PB2, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC0_PA17_CH6 {PA17, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC0_PA18_CH7 {PA18, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC0_PA19_CH8 {PA19, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC0_PA20_CH9 {PA20, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC0_PB0_CH10 {PB0, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC1_PB1_CH0 {PB1, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_0}, + #endif + #ifdef ADC1_PC13_CH1 {PC13, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_1}, + #endif + #ifdef ADC1_PC15_CH2 {PC15, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_2}, + #endif + #ifdef ADC1_PC12_CH3 {PC12, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC1_PC29_CH4 {PC29, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_4}, + #endif + #ifdef ADC1_PC30_CH5 {PC30, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_5}, + #endif + #ifdef ADC1_PC31_CH6 {PC31, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_6}, + #endif + #ifdef ADC1_PC26_CH7 {PC26, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_7}, + #endif + #ifdef ADC1_PC27_CH8 {PC27, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_8}, + #endif + #ifdef ADC1_PC0_CH9 {PC0, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_9}, + #endif + #ifdef ADC1_PE3_CH10 {PE3, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_10}, + #endif + #ifdef ADC1_PE0_CH11 {PE0, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_11}, + #endif {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_CHANNEL_ERROR} }; diff --git a/targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_pin_map/implementations/implementation_1/hal_ll_i2c_pin_map.h b/targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_pin_map/implementations/implementation_1/hal_ll_i2c_pin_map.h index b511763fd..e82f95289 100644 --- a/targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_pin_map/implementations/implementation_1/hal_ll_i2c_pin_map.h +++ b/targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_pin_map/implementations/implementation_1/hal_ll_i2c_pin_map.h @@ -75,9 +75,16 @@ typedef struct /*!< @brief I2C SCL pins */ static const hal_ll_i2c_pin_map_t hal_ll_i2c_scl_map[] = { + #ifdef I2C0_SCL_PA4_AFA {PA4, HAL_LL_I2C0_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_0), 0}, + #endif + #ifdef I2C1_SCL_PB5_AFA {PB5, HAL_LL_I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 0}, + #endif + #ifdef I2C2_SCL_PD28_AFC {PD28, HAL_LL_I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 2}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} //------------ END SCL }; @@ -85,9 +92,16 @@ static const hal_ll_i2c_pin_map_t hal_ll_i2c_scl_map[] = /*!< @brief I2C SDA pins */ static const hal_ll_i2c_pin_map_t hal_ll_i2c_sda_map[] = { + #ifdef I2C0_SDA_PA3_AFA {PA3, HAL_LL_I2C0_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_0), 0}, + #endif + #ifdef I2C1_SDA_PB4_AFA {PB4, HAL_LL_I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 0}, + #endif + #ifdef I2C2_SDA_PD27_AFC {PD27, HAL_LL_I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 2}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} //------------ END SDA }; diff --git a/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master_pin_map/implementations/implementation_1/hal_ll_spi_master_pin_map.h b/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master_pin_map/implementations/implementation_1/hal_ll_spi_master_pin_map.h index 4d73df4c7..e6c4073c5 100644 --- a/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master_pin_map/implementations/implementation_1/hal_ll_spi_master_pin_map.h +++ b/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master_pin_map/implementations/implementation_1/hal_ll_spi_master_pin_map.h @@ -80,24 +80,39 @@ typedef struct /*!< @brief SPI SCK pins. */ static const hal_ll_spi_master_pin_map_t _spi_sck_map[] = { - {PA14, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 0}, - {PC24, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 2}, + #ifdef SPI0_SCK_PD22_AFB + {PD22, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 1}, + #endif + #ifdef SPI1_SCK_PC24_AFC + {PC24, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 2}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} }; /*!< @brief SPI MISO pins. */ static const hal_ll_spi_master_pin_map_t _spi_miso_map[] = { - {PA12, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 0}, - {PC26, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 2}, + #ifdef SPI0_MISO_PD20_AFB + {PD20, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 1}, + #endif + #ifdef SPI1_MISO_PC26_AFC + {PC26, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 2}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} }; /*!< @brief SPI MOSI pins. */ static const hal_ll_spi_master_pin_map_t _spi_mosi_map[] = { - {PA13, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 0}, - {PC27, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 2}, + #ifdef SPI0_MOSI_PD21_AFB + {PD21, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 1}, + #endif + #ifdef SPI1_MOSI_PC27_AFC + {PC27, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 2}, + #endif + {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} }; diff --git a/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/implementation_1/hal_ll_tim_pin_map.h b/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/implementation_1/hal_ll_tim_pin_map.h index 094ccad4c..bf36383f2 100644 --- a/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/implementation_1/hal_ll_tim_pin_map.h +++ b/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/implementation_1/hal_ll_tim_pin_map.h @@ -88,30 +88,78 @@ typedef enum /*!< @brief TIM pins. */ static const hal_ll_tim_pin_map_t _tim_map[] = { + #ifdef TIM0_CH0_A_PA0_AFB {PA0, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x01, hal_ll_tim_module_num(TIM_MODULE_0)}, + #endif + #ifdef TIM0_CH1_A_PA15_AFB {PA15, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x01, hal_ll_tim_module_num(TIM_MODULE_0)}, + #endif + #ifdef TIM0_CH2_A_PA26_AFB {PA26, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x01, hal_ll_tim_module_num(TIM_MODULE_0)}, + #endif + #ifdef TIM0_CH0_B_PA1_AFB {PA1, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x11, hal_ll_tim_module_num(TIM_MODULE_0)}, + #endif + #ifdef TIM0_CH1_B_PA16_AFB {PA16, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x11, hal_ll_tim_module_num(TIM_MODULE_0)}, + #endif + #ifdef TIM0_CH2_B_PA27_AFB {PA27, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x11, hal_ll_tim_module_num(TIM_MODULE_0)}, + #endif + #ifdef TIM1_CH0_A_PC23_AFB {PC23, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x01, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_A_PC26_AFB {PC26, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x01, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_A_PC29_AFB {PC29, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x01, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH0_B_PC24_AFB {PC24, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x11, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH1_B_PC27_AFB {PC27, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x11, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM1_CH2_B_PC30_AFB {PC30, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x11, hal_ll_tim_module_num(TIM_MODULE_1)}, + #endif + #ifdef TIM2_CH0_A_PC5_AFB {PC5, HAL_LL_TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x01, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_A_PC8_AFB {PC8, HAL_LL_TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x01, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_A_PC11_AFB {PC11, HAL_LL_TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x01, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH0_B_PC6_AFB {PC6, HAL_LL_TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x11, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH1_B_PC9_AFB {PC9, HAL_LL_TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x11, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM2_CH2_B_PC12_AFB {PC12, HAL_LL_TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x11, hal_ll_tim_module_num(TIM_MODULE_2)}, + #endif + #ifdef TIM3_CH0_A_PE0_AFB {PE0, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x01, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_A_PE3_AFB {PE3, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x01, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_A_PD21_AFC {PD21, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x02, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH0_B_PE1_AFB {PE1, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x11, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH1_B_PE4_AFB {PE4, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x11, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_B_PD22_AFC {PD22, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x12, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_CHANNEL_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC } }; diff --git a/targets/arm/mikroe/sam/include/uart/hal_ll_uart_pin_map/implementations/implementation_1/hal_ll_uart_pin_map.h b/targets/arm/mikroe/sam/include/uart/hal_ll_uart_pin_map/implementations/implementation_1/hal_ll_uart_pin_map.h index f54b741a8..0ba0d04eb 100644 --- a/targets/arm/mikroe/sam/include/uart/hal_ll_uart_pin_map/implementations/implementation_1/hal_ll_uart_pin_map.h +++ b/targets/arm/mikroe/sam/include/uart/hal_ll_uart_pin_map/implementations/implementation_1/hal_ll_uart_pin_map.h @@ -91,30 +91,74 @@ typedef struct /*!< @brief UART TX pins */ static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = { + #ifdef USART0_TX_PB1_AFC {hal_ll_usart_module_num(USART_MODULE_0), PB1, HAL_LL_USART0_BASE_ADDRESS, 2}, - {hal_ll_usart_module_num(USART_MODULE_1), PB4, HAL_LL_USART0_BASE_ADDRESS, 3}, - {hal_ll_usart_module_num(USART_MODULE_2), PD16, HAL_LL_USART0_BASE_ADDRESS, 1}, + #endif + #ifdef USART1_TX_PB4_AFD + {hal_ll_usart_module_num(USART_MODULE_1), PB4, HAL_LL_USART1_BASE_ADDRESS, 3}, + #endif + #ifdef USART2_TX_PD16_AFB + {hal_ll_usart_module_num(USART_MODULE_2), PD16, HAL_LL_USART2_BASE_ADDRESS, 1}, + #endif + #ifdef UART0_TX_PA10_AFA {hal_ll_uart_module_num(UART_MODULE_0), PA10, HAL_LL_UART0_BASE_ADDRESS, 0}, + #endif + #ifdef UART1_TX_PA4_AFC {hal_ll_uart_module_num(UART_MODULE_1), PA4, HAL_LL_UART1_BASE_ADDRESS, 2}, + #endif + #ifdef UART1_TX_PA6_AFC {hal_ll_uart_module_num(UART_MODULE_1), PA6, HAL_LL_UART1_BASE_ADDRESS, 2}, + #endif + #ifdef UART1_TX_PD26_AFD + {hal_ll_uart_module_num(UART_MODULE_1), PD26, HAL_LL_UART1_BASE_ADDRESS, 3}, + #endif + #ifdef UART2_TX_PD26_AFC {hal_ll_uart_module_num(UART_MODULE_2), PD26, HAL_LL_UART2_BASE_ADDRESS, 2}, + #endif + #ifdef UART3_TX_PD30_AFA {hal_ll_uart_module_num(UART_MODULE_3), PD30, HAL_LL_UART3_BASE_ADDRESS, 0}, + #endif + #ifdef UART3_TX_PD31_AFB {hal_ll_uart_module_num(UART_MODULE_3), PD31, HAL_LL_UART3_BASE_ADDRESS, 1}, + #endif + #ifdef UART4_TX_PD3_AFC + {hal_ll_uart_module_num(UART_MODULE_4), PD3, HAL_LL_UART4_BASE_ADDRESS, 2}, + #endif + #ifdef UART4_TX_PD19_AFC {hal_ll_uart_module_num(UART_MODULE_4), PD19, HAL_LL_UART4_BASE_ADDRESS, 2}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} }; /*!< @brief UART RX pins */ static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = { + #ifdef USART0_RX_PB0_AFC {hal_ll_usart_module_num(USART_MODULE_0), PB0, HAL_LL_USART0_BASE_ADDRESS, 2}, - {hal_ll_usart_module_num(USART_MODULE_1), PA21, HAL_LL_USART1_BASE_ADDRESS, 2}, + #endif + #ifdef USART1_RX_PA21_AFA + {hal_ll_usart_module_num(USART_MODULE_1), PA21, HAL_LL_USART1_BASE_ADDRESS, 0}, + #endif + #ifdef USART2_RX_PD15_AFB {hal_ll_usart_module_num(USART_MODULE_2), PD15, HAL_LL_USART2_BASE_ADDRESS, 1}, + #endif + #ifdef UART0_RX_PA9_AFA {hal_ll_uart_module_num(UART_MODULE_0), PA9, HAL_LL_UART0_BASE_ADDRESS, 0}, + #endif + #ifdef UART1_RX_PA5_AFC {hal_ll_uart_module_num(UART_MODULE_1), PA5, HAL_LL_UART1_BASE_ADDRESS, 2}, + #endif + #ifdef UART2_RX_PD25_AFC {hal_ll_uart_module_num(UART_MODULE_2), PD25, HAL_LL_UART2_BASE_ADDRESS, 2}, + #endif + #ifdef UART3_RX_PD28_AFA {hal_ll_uart_module_num(UART_MODULE_3), PD28, HAL_LL_UART3_BASE_ADDRESS, 0}, + #endif + #ifdef UART4_RX_PD18_AFC {hal_ll_uart_module_num(UART_MODULE_4), PD18, HAL_LL_UART4_BASE_ADDRESS, 2}, + #endif + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} }; From 24caa0e00b0cfbeac7494f8d33d0675f36909490 Mon Sep 17 00:00:00 2001 From: "ivan.ruzavin" Date: Fri, 22 Nov 2024 13:17:44 +0100 Subject: [PATCH 22/56] Added pin mapping for all SAME7 MCUs --- .../implementation_1/hal_ll_adc_pin_map.h | 12 ++++++------ .../implementation_1/hal_ll_spi_master_pin_map.h | 9 +++++++++ .../implementation_1/hal_ll_tim_pin_map.h | 12 ++++++------ 3 files changed, 21 insertions(+), 12 deletions(-) diff --git a/targets/arm/mikroe/sam/include/adc/hal_ll_adc_pin_map/implementations/implementation_1/hal_ll_adc_pin_map.h b/targets/arm/mikroe/sam/include/adc/hal_ll_adc_pin_map/implementations/implementation_1/hal_ll_adc_pin_map.h index 486b5cab8..2ec11b357 100644 --- a/targets/arm/mikroe/sam/include/adc/hal_ll_adc_pin_map/implementations/implementation_1/hal_ll_adc_pin_map.h +++ b/targets/arm/mikroe/sam/include/adc/hal_ll_adc_pin_map/implementations/implementation_1/hal_ll_adc_pin_map.h @@ -103,12 +103,6 @@ static const hal_ll_adc_pin_map_t _adc_map[] = #ifdef ADC0_PB3_CH2 {PB3, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_2}, #endif - #ifdef ADC0_PE5_CH3 - {PE5, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_3}, - #endif - #ifdef ADC0_PE4_CH4 - {PE4, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_4}, - #endif #ifdef ADC0_PB2_CH5 {PB2, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_5}, #endif @@ -130,6 +124,12 @@ static const hal_ll_adc_pin_map_t _adc_map[] = #ifdef ADC1_PB1_CH0 {PB1, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_0}, #endif + #ifdef ADC0_PE5_CH3 + {PE5, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_3}, + #endif + #ifdef ADC0_PE4_CH4 + {PE4, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_4}, + #endif #ifdef ADC1_PC13_CH1 {PC13, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_1}, #endif diff --git a/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master_pin_map/implementations/implementation_1/hal_ll_spi_master_pin_map.h b/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master_pin_map/implementations/implementation_1/hal_ll_spi_master_pin_map.h index e6c4073c5..689a41486 100644 --- a/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master_pin_map/implementations/implementation_1/hal_ll_spi_master_pin_map.h +++ b/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master_pin_map/implementations/implementation_1/hal_ll_spi_master_pin_map.h @@ -80,6 +80,9 @@ typedef struct /*!< @brief SPI SCK pins. */ static const hal_ll_spi_master_pin_map_t _spi_sck_map[] = { + #ifdef SPI0_SCK_PA14_AFA + {PA14, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 0}, + #endif #ifdef SPI0_SCK_PD22_AFB {PD22, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 1}, #endif @@ -93,6 +96,9 @@ static const hal_ll_spi_master_pin_map_t _spi_sck_map[] = /*!< @brief SPI MISO pins. */ static const hal_ll_spi_master_pin_map_t _spi_miso_map[] = { + #ifdef SPI0_MISO_PA12_AFA + {PA12, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 0}, + #endif #ifdef SPI0_MISO_PD20_AFB {PD20, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 1}, #endif @@ -106,6 +112,9 @@ static const hal_ll_spi_master_pin_map_t _spi_miso_map[] = /*!< @brief SPI MOSI pins. */ static const hal_ll_spi_master_pin_map_t _spi_mosi_map[] = { + #ifdef SPI0_MOSI_PA13_AFA + {PA13, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 0}, + #endif #ifdef SPI0_MOSI_PD21_AFB {PD21, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 1}, #endif diff --git a/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/implementation_1/hal_ll_tim_pin_map.h b/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/implementation_1/hal_ll_tim_pin_map.h index bf36383f2..f7b95f010 100644 --- a/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/implementation_1/hal_ll_tim_pin_map.h +++ b/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/implementation_1/hal_ll_tim_pin_map.h @@ -106,6 +106,12 @@ static const hal_ll_tim_pin_map_t _tim_map[] = { #ifdef TIM0_CH2_B_PA27_AFB {PA27, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x11, hal_ll_tim_module_num(TIM_MODULE_0)}, #endif + #ifdef TIM3_CH2_A_PD21_AFC + {PD21, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x02, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif + #ifdef TIM3_CH2_B_PD22_AFC + {PD22, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x12, hal_ll_tim_module_num(TIM_MODULE_3)}, + #endif #ifdef TIM1_CH0_A_PC23_AFB {PC23, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x01, hal_ll_tim_module_num(TIM_MODULE_1)}, #endif @@ -148,18 +154,12 @@ static const hal_ll_tim_pin_map_t _tim_map[] = { #ifdef TIM3_CH1_A_PE3_AFB {PE3, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x01, hal_ll_tim_module_num(TIM_MODULE_3)}, #endif - #ifdef TIM3_CH2_A_PD21_AFC - {PD21, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x02, hal_ll_tim_module_num(TIM_MODULE_3)}, - #endif #ifdef TIM3_CH0_B_PE1_AFB {PE1, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x11, hal_ll_tim_module_num(TIM_MODULE_3)}, #endif #ifdef TIM3_CH1_B_PE4_AFB {PE4, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x11, hal_ll_tim_module_num(TIM_MODULE_3)}, #endif - #ifdef TIM3_CH2_B_PD22_AFC - {PD22, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x12, hal_ll_tim_module_num(TIM_MODULE_3)}, - #endif { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_CHANNEL_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC } }; From a35957942478bd1450efe5e905e611be2c3ce13e Mon Sep 17 00:00:00 2001 From: "ivan.ruzavin" Date: Mon, 25 Nov 2024 10:43:42 +0100 Subject: [PATCH 23/56] Updated ADC implementation to start with valid values --- targets/arm/mikroe/sam/CMakeLists.txt | 9 ------- .../arm/mikroe/sam/include/hal_ll_target.h | 3 +-- .../implementation_1/hal_ll_adc.c | 24 ++++++++++++++----- 3 files changed, 19 insertions(+), 17 deletions(-) diff --git a/targets/arm/mikroe/sam/CMakeLists.txt b/targets/arm/mikroe/sam/CMakeLists.txt index e813459d0..91df5cf37 100644 --- a/targets/arm/mikroe/sam/CMakeLists.txt +++ b/targets/arm/mikroe/sam/CMakeLists.txt @@ -28,12 +28,3 @@ endif() if (msdk_onewire IN_LIST module_list_supported) add_subdirectory(src/one_wire) endif() -if (msdk_can IN_LIST module_list_supported) - # add_subdirectory(src/can) -endif() -if (msdk_dma IN_LIST module_list_supported) - # add_subdirectory(src/dma) -endif() -if (msdk_rtc IN_LIST module_list_supported) - # add_subdirectory(src/rtc) -endif() diff --git a/targets/arm/mikroe/sam/include/hal_ll_target.h b/targets/arm/mikroe/sam/include/hal_ll_target.h index 145b53fb9..9066a6c9f 100644 --- a/targets/arm/mikroe/sam/include/hal_ll_target.h +++ b/targets/arm/mikroe/sam/include/hal_ll_target.h @@ -49,8 +49,7 @@ extern "C"{ #endif #include "hal_ll_pin_names.h" -// TODO - find a way how to include it properly -#include "../../common/include/hal_ll_bit_control.h" +#include "hal_ll_bit_control.h" #include "assembly.h" #include "common_macros.h" #include "common_types.h" diff --git a/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c b/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c index 19244f223..5982ab2e3 100644 --- a/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c +++ b/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c @@ -379,18 +379,18 @@ hal_ll_err_t hal_ll_adc_read( handle_t *handle, uint16_t *readDatabuf ) low_level_handle = hal_ll_adc_get_handle; hal_ll_adc_base_handle_t *afec_regs = ( hal_ll_adc_base_handle_t * )hal_ll_adc_hw_specifics_map_local->base ; - // Start conversion. - set_reg_bit( &afec_regs->cr, HAL_LL_AFEC_CR_START_BIT ); - - // Wait till data is converted. - while ( !( check_reg_bit( &afec_regs->isr, hal_ll_adc_hw_specifics_map_local->channel ) ) ); - // Select the desired channel. write_reg( &afec_regs->cselr, hal_ll_adc_hw_specifics_map_local->channel ); // Select default offset for the converted data. write_reg( &afec_regs->cocr, HAL_LL_AFEC_COCR_OFFSET_MASK ); + // Start conversion. + set_reg_bit( &afec_regs->cr, HAL_LL_AFEC_CR_START_BIT ); + + // Wait till data is converted. + while ( !( check_reg_bit( &afec_regs->isr, hal_ll_adc_hw_specifics_map_local->channel ) ) ); + // Read the conversion result from converted data register. *readDatabuf = read_reg( &afec_regs->cdr ); @@ -522,6 +522,18 @@ static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *afec_regs, uint32_t r // Enable the desired channel. set_reg_bit( &afec_regs->cher, hal_ll_adc_hw_specifics_map_local->channel ); + + // Select the desired channel. + write_reg( &afec_regs->cselr, hal_ll_adc_hw_specifics_map_local->channel ); + + // Select default offset for the converted data. + write_reg( &afec_regs->cocr, HAL_LL_AFEC_COCR_OFFSET_MASK ); + + // Start conversion for dummy data. + set_reg_bit( &afec_regs->cr, HAL_LL_AFEC_CR_START_BIT ); + + // Read dummy data from the converted data register to erase it. + read_reg( &afec_regs->cdr ); } static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ) { From dd2f2ef1ed09aba0a7f9e13abb6d8bbedcc027a3 Mon Sep 17 00:00:00 2001 From: "ivan.ruzavin" Date: Mon, 25 Nov 2024 14:20:57 +0100 Subject: [PATCH 24/56] Updated I2C implementation --- .../implementation_1/hal_ll_i2c_master.c | 37 ++++++++++++++----- 1 file changed, 28 insertions(+), 9 deletions(-) diff --git a/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c b/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c index d576ddd57..fc4b73bec 100644 --- a/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c +++ b/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c @@ -45,7 +45,6 @@ #include "hal_ll_gpio.h" #include "hal_ll_i2c_master.h" #include "hal_ll_i2c_pin_map.h" -#include "mcu.h" /*!< @brief Local handle list */ static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; @@ -53,7 +52,7 @@ static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODU // ------------------------------------------------------------- PRIVATE MACROS /*!< @brief Macros used for calculating speed value and configuring the clock register */ #define hal_ll_get_system_clock (Get_Fosc_kHz() * 1000) -#define hal_ll_i2c_configure_divider_register(_cldiv,_chdiv,_ckdiv) ((0xFF & _cldiv) | (0xFF00 & (_chdiv << 8)) | (0x70000 & (_ckdiv << 16))) +#define hal_ll_i2c_get_divider(temp_div,speed) (hal_ll_get_system_clock / (2 * temp_div * speed)) - 3U /*!< @brief Helper macro for getting hal_ll_module_state address */ #define hal_ll_i2c_get_module_state_address ((hal_ll_i2c_master_handle_register_t *)*handle) /*!< @brief Helper macro for getting module specific control register structure base address // first register address */ @@ -100,9 +99,8 @@ static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODU #define HAL_LL_PID_TWIHS0_BIT 19 #define HAL_LL_PID_TWIHS1_BIT 20 -/*!< @brief Macros defining register bit masks */ -#define HAL_LL_TWIHS_CWGR_100K_MASK 0x3939 -#define HAL_LL_TWIHS_CWGR_400K_MASK 0x0B0C +/*!< @brief Macros for speed calculation */ +#define HAL_LL_TWIHS_CWGR_CLKDIV_MAX 7 /*!< @brief Macros used for module pin checking */ #define HAL_LL_I2C_SCL_PIN 0 @@ -800,22 +798,43 @@ static void hal_ll_i2c_master_alternate_functions_set_state( hal_ll_i2c_hw_speci static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ) { hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base ); - uint32_t ckdiv = 0; - uint32_t cldiv, chdiv, c_lh_div, twihs_cwgr; + uint8_t ckdiv = 0; + uint8_t temp_div; + uint32_t i2c_speed, twihs_cwgr; // High-Speed can be only used in slave mode, 400k is the max speed allowed for master. switch ( map->speed ) { case HAL_LL_I2C_MASTER_SPEED_STANDARD: - write_reg( &hal_ll_hw_reg->cwgr, HAL_LL_TWIHS_CWGR_100K_MASK ); + i2c_speed = HAL_LL_I2C_MASTER_SPEED_100K; break; case HAL_LL_I2C_MASTER_SPEED_FULL: - write_reg( &hal_ll_hw_reg->cwgr, HAL_LL_TWIHS_CWGR_400K_MASK ); + i2c_speed = HAL_LL_I2C_MASTER_LOW_DIVIDER_SPEED_LIMIT; break; default: return HAL_LL_I2C_MASTER_ERROR; } + /* Formula for calculating baud value involves two unknowns. Fix one unknown and calculate the other. + Fix the CKDIV value and see if CLDIV (or CHDIV) fits into the 8-bit register. */ + + /* Calculate CLDIV with CKDIV set to 0 */ + while ( ckdiv <= HAL_LL_TWIHS_CWGR_CLKDIV_MAX ) { + temp_div = 1; + for ( uint8_t i = 1; i <= ckdiv; i++) + temp_div *= 2; + twihs_cwgr = hal_ll_i2c_get_divider( temp_div, i2c_speed ); + if ( twihs_cwgr <= HAL_LL_NIBBLE_LOW_16BIT ) + break; + ckdiv++; + } + + if ( twihs_cwgr > HAL_LL_NIBBLE_LOW_16BIT ) + /* Could not generate CLDIV and CKDIV register values for the requested baud rate */ + return HAL_LL_I2C_MASTER_ERROR; + else + write_reg( &hal_ll_hw_reg->cwgr, ( twihs_cwgr << 8 ) | twihs_cwgr | ckdiv << 16 ); + return HAL_LL_I2C_MASTER_SUCCESS; } From 76f34e8d749fd06296e84b320bf77fbc7a584eaa Mon Sep 17 00:00:00 2001 From: "ivan.ruzavin" Date: Thu, 5 Dec 2024 11:29:30 +0100 Subject: [PATCH 25/56] Prettyfied code --- hal/interface/CMakeLists.txt | 2 +- targets/arm/mikroe/core/CMakeLists.txt | 5 +- .../mikroe/core/include/hal_ll_core_defines.h | 2 + .../sam/include/gpio/hal_ll_gpio_port.h | 1 - .../implementation_1/hal_ll_gpio_constants.h | 153 ------------------ .../arm/mikroe/sam/src/gpio/CMakeLists.txt | 3 +- 6 files changed, 8 insertions(+), 158 deletions(-) delete mode 100644 targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_constants.h diff --git a/hal/interface/CMakeLists.txt b/hal/interface/CMakeLists.txt index 6829f0b0c..6359a32a8 100644 --- a/hal/interface/CMakeLists.txt +++ b/hal/interface/CMakeLists.txt @@ -31,7 +31,7 @@ elseif(${MCU_NAME} MATCHES "(^PIC18(.+)$)") set(vendor_id "pic18") elseif(${MCU_NAME} MATCHES "(^GD32VF(.+)$)") set(vendor_id "gigadevice") -elseif(${MCU_NAME} MATCHES "^(AT)?SAM(.+)$") +elseif(${MCU_NAME} MATCHES "(^(AT)?SAM(.+)$)") set(mcu_defs_path ${MCU_NAME}/${_MSDK_PACKAGE_NAME_}${_MSDK_PACKAGE_PIN_COUNT_}) set(vendor_id "sam") elseif(${MCU_NAME} MATCHES "AT") diff --git a/targets/arm/mikroe/core/CMakeLists.txt b/targets/arm/mikroe/core/CMakeLists.txt index d4e2c5fb3..ffd1bf435 100644 --- a/targets/arm/mikroe/core/CMakeLists.txt +++ b/targets/arm/mikroe/core/CMakeLists.txt @@ -40,7 +40,10 @@ elseif(${MCU_NAME} MATCHES "^TM4C.*") elseif(${MCU_NAME} MATCHES "^(AT)?SAM.*") set(chip_vendor "sam") list(APPEND hal_ll_core_def_list ${chip_vendor}) - set(hal_ll_core_source "m7") + if(${CORE_NAME} MATCHES "M7") + set(hal_ll_core_source "m7") + list(APPEND hal_ll_core_def_list __cortex_m7__) + endif() else() list(hal_ll_core_def_list __vendor_not_supported__) endif() diff --git a/targets/arm/mikroe/core/include/hal_ll_core_defines.h b/targets/arm/mikroe/core/include/hal_ll_core_defines.h index 9db9ff31f..bb03e3d70 100644 --- a/targets/arm/mikroe/core/include/hal_ll_core_defines.h +++ b/targets/arm/mikroe/core/include/hal_ll_core_defines.h @@ -360,6 +360,7 @@ extern "C"{ #define HAL_LL_CORE_NVIC_SYS_PRI_2 (( uint32_t * )0xE000ED1C) #define HAL_LL_CORE_NVIC_SYS_PRI_3 (( uint32_t * )0xE000ED20) #elif defined (sam) +#if defined(__cortex_m7__) typedef enum { HAL_LL_IVT_PRIORITY_LEVEL_0 = 0, @@ -400,6 +401,7 @@ extern "C"{ #define HAL_LL_CORE_NVIC_SCB_SHPR2 (( uint32_t * )0xE000ED1C) #define HAL_LL_CORE_NVIC_SCB_SHPR3 (( uint32_t * )0xE000ED20) #endif +#endif #ifdef __cplusplus } diff --git a/targets/arm/mikroe/sam/include/gpio/hal_ll_gpio_port.h b/targets/arm/mikroe/sam/include/gpio/hal_ll_gpio_port.h index 846706ae4..53b935989 100644 --- a/targets/arm/mikroe/sam/include/gpio/hal_ll_gpio_port.h +++ b/targets/arm/mikroe/sam/include/gpio/hal_ll_gpio_port.h @@ -49,7 +49,6 @@ extern "C"{ #endif #include "hal_ll_target.h" -#include "hal_ll_gpio_constants.h" #include "hal_ll_gpio_struct_type.h" #define RESET_PINS_OFFSET 32 diff --git a/targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_constants.h b/targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_constants.h deleted file mode 100644 index 2804108f0..000000000 --- a/targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_constants.h +++ /dev/null @@ -1,153 +0,0 @@ -/**************************************************************************** -** -** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. -** Contact: https://www.mikroe.com/contact -** -** This file is part of the mikroSDK package -** -** Commercial License Usage -** -** Licensees holding valid commercial NECTO compilers AI licenses may use this -** file in accordance with the commercial license agreement provided with the -** Software or, alternatively, in accordance with the terms contained in -** a written agreement between you and The MikroElektronika Company. -** For licensing terms and conditions see -** https://www.mikroe.com/legal/software-license-agreement. -** For further information use the contact form at -** https://www.mikroe.com/contact. -** -** -** GNU Lesser General Public License Usage -** -** Alternatively, this file may be used for -** non-commercial projects under the terms of the GNU Lesser -** General Public License version 3 as published by the Free Software -** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. -** -** The above copyright notice and this permission notice shall be -** included in all copies or substantial portions of the Software. -** -** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, -** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT -** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE -** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -** -****************************************************************************/ -/*! - * @file hal_ll_gpio_constants.h - * @brief GPIO HAL LL macros. - */ - -#ifndef _HAL_LL_GPIO_CONSTANTS_H_ -#define _HAL_LL_GPIO_CONSTANTS_H_ - -#ifdef __cplusplus -extern "C"{ -#endif - -// Define any specific macros here -// REPLACE_MACROS // - -// Predefined macros if missing -#ifndef GPIO_OSPEEDER_OSPEEDR0 -#define GPIO_OSPEEDER_OSPEEDR0 ( uint32_t )0x03 -#endif -#ifndef GPIO_MODER_MODER0 -#define GPIO_MODER_MODER0 ( uint32_t )0x03 -#endif -#ifndef GPIO_OTYPER_OT_0 -#define GPIO_OTYPER_OT_0 ( uint32_t )0x01 -#endif -#ifndef GPIO_PUPDR_PUPDR0 -#define GPIO_PUPDR_PUPDR0 ( uint32_t )0x03 -#endif - -#ifndef GPIO_PIN_MASK_LOW -#define GPIO_PIN_MASK_LOW ( uint32_t )0x00FF -#endif -#ifndef GPIO_PIN_MASK_HIGH -#define GPIO_PIN_MASK_HIGH ( uint32_t )0xFF00 -#endif -#ifndef GPIO_PIN_MASK_ALL -#define GPIO_PIN_MASK_ALL ( uint32_t )0xFFFF -#endif - -#ifndef GPIO_AF_CONFIG_OFFSET -#define GPIO_AF_CONFIG_OFFSET ( uint32_t )20 -#endif -#ifndef GPIO_AF_MASK -#define GPIO_AF_MASK ( 0x0F ) -#endif -#ifndef GPIO_PIN_NAME_MASK -#define GPIO_PIN_NAME_MASK ( ( uint32_t )0xFF ) -#endif -#ifndef GPIO_AF_CONFIG_MASK -#define GPIO_AF_CONFIG_MASK ( ( uint32_t )0x0F << GPIO_AF_CONFIG_OFFSET ) -#endif - -#ifndef GPIO_CFG_MODE_ANALOG -#define GPIO_CFG_MODE_ANALOG ( uint32_t )0x1 -#endif -#ifndef GPIO_CFG_MODE_INPUT -#define GPIO_CFG_MODE_INPUT ( uint32_t )0x2 -#endif -#ifndef GPIO_CFG_MODE_OUTPUT -#define GPIO_CFG_MODE_OUTPUT ( uint32_t )0x4 -#endif -#ifndef GPIO_CFG_MODE_ALT_FUNCTION -#define GPIO_CFG_MODE_ALT_FUNCTION ( uint32_t )0x8 -#endif -#ifndef GPIO_CFG_OTYPE_PP -#define GPIO_CFG_OTYPE_PP ( uint32_t )0x10 -#endif -#ifndef GPIO_CFG_OTYPE_OD -#define GPIO_CFG_OTYPE_OD ( uint32_t )0x20 -#endif -#ifndef GPIO_CFG_PULL_NO -#define GPIO_CFG_PULL_NO ( uint32_t )0x40 -#endif -#ifndef GPIO_CFG_PULL_UP -#define GPIO_CFG_PULL_UP ( uint32_t )0x80 -#endif -#ifndef GPIO_CFG_PULL_DOWN -#define GPIO_CFG_PULL_DOWN ( uint32_t )0x100 -#endif -#ifndef GPIO_CFG_SPEED_LOW -#define GPIO_CFG_SPEED_LOW ( uint32_t )0x0 -#endif -#ifndef GPIO_CFG_SPEED_MEDIUM -#define GPIO_CFG_SPEED_MEDIUM ( uint32_t )0x200 -#endif -#ifndef GPIO_CFG_SPEED_HIGH -#define GPIO_CFG_SPEED_HIGH ( uint32_t )0x400 -#endif -#ifndef GPIO_CFG_SPEED_VERY_HIGH -#define GPIO_CFG_SPEED_VERY_HIGH ( uint32_t )0x800 -#endif -#ifndef GPIO_CFG_SPEED_MAX -#define GPIO_CFG_SPEED_MAX ( uint32_t )0x80000 -#endif - -#ifndef GPIO_AHB_SHIFT -#define GPIO_AHB_SHIFT 17 -#endif - -#ifndef GPIO_CFG_DIGITAL_OUTPUT -#define GPIO_CFG_DIGITAL_OUTPUT ( GPIO_CFG_MODE_OUTPUT | GPIO_CFG_SPEED_MAX | GPIO_CFG_OTYPE_PP ) -#endif -#ifndef GPIO_CFG_DIGITAL_INPUT -#define GPIO_CFG_DIGITAL_INPUT ( GPIO_CFG_MODE_INPUT | GPIO_CFG_PULL_NO ) -#endif -#ifndef GPIO_CFG_ANALOG_INPUT -#define GPIO_CFG_ANALOG_INPUT ( GPIO_CFG_MODE_ANALOG | GPIO_CFG_PULL_NO ) -#endif - -#ifdef __cplusplus -} -#endif - -#endif // _HAL_LL_GPIO_CONSTANTS_H_ -// ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt b/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt index 4fafdb8c0..d35dac9ce 100644 --- a/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt @@ -24,7 +24,6 @@ mikrosdk_add_library(lib_hal_ll_gpio MikroSDK.HalLowLevel.GPIO # BEGIN GPIO ../../include/gpio/hal_ll_gpio.h ../../include/gpio/hal_ll_gpio_port.h - ../../include/gpio/${gpio_subimplementation}/hal_ll_gpio_constants.h ../../include/gpio/${gpio_subimplementation}/hal_ll_gpio_struct_type.h # END GPIO @@ -58,4 +57,4 @@ target_include_directories(lib_hal_ll_gpio ) mikrosdk_install(MikroSDK.HalLowLevel.GPIO) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.GPIO ../../include/gpio/hal_ll_gpio.h ../../include/gpio/${gpio_subimplementation}/hal_ll_gpio_constants.h ../../include/gpio/${gpio_subimplementation}/hal_ll_gpio_struct_type.h ../../include/gpio/hal_ll_gpio_port.h) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.GPIO ../../include/gpio/hal_ll_gpio.h ../../include/gpio/${gpio_subimplementation}/hal_ll_gpio_struct_type.h ../../include/gpio/hal_ll_gpio_port.h) From dd1714530c0ab2d6e6797b06aa913a2ded293dff Mon Sep 17 00:00:00 2001 From: "ivan.ruzavin" Date: Mon, 16 Dec 2024 09:11:31 +0100 Subject: [PATCH 26/56] Updated changelog and correspondong files --- SUPPORTED_CHIP_LIST.md | 74 ++++++++++ changelog.md | 1 + changelog/v2.13.0/changelog.md | 127 ++++++++++++++++++ .../include/mikrosdk_version.h | 4 +- 4 files changed, 204 insertions(+), 2 deletions(-) create mode 100644 changelog/v2.13.0/changelog.md diff --git a/SUPPORTED_CHIP_LIST.md b/SUPPORTED_CHIP_LIST.md index c72dd902b..13645b688 100644 --- a/SUPPORTED_CHIP_LIST.md +++ b/SUPPORTED_CHIP_LIST.md @@ -6,6 +6,7 @@ - [List of supported chips](#list-of-supported-chips) - [CONTENT](#content) + - [SAM](#sam) - [DSPIC](#dspic) - [AVR](#avr) - [GIGADEVICE](#gigadevice) @@ -17,6 +18,79 @@ --- +### SAM + +| CHIP NAME | ARCHITECTURE | REQUIREMENTS | SUPPORTED IN VERSION | GPIO | ADC | I2C | PWM | SPI | UART | ONE WIRE | +| :------------: | :----------: | :-------------: | :------------------: | :----------------: | :----------------: | :----------------: | :----------------: | :----------------: | :----------------: | :----------------: | +| ATSAME70J19A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAME70J19B | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAME70J20A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAME70J20B | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAME70J21A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAME70J21B | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAME70N19A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAME70N19B | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAME70N20A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAME70N20B | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAME70N21A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAME70N21B | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAME70Q19A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAME70Q19B | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAME70Q20A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAME70Q20B | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAME70Q21A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAME70Q21B | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMS70J19A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMS70J19B | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMS70J20A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMS70J20B | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMS70J21A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMS70J21B | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMS70N19A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMS70N19B | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMS70N20A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMS70N20B | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMS70N21A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMS70N21B | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMS70Q19A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMS70Q19B | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMS70Q20A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMS70Q20B | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMS70Q21A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMS70Q21B | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMV70J19A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMV70J19B | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMV70J20A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMV70J20B | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMV70N19A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMV70N19B | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMV70N20A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMV70N20B | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMV70Q19A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMV70Q19B | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMV70Q20A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMV70Q20B | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMV71J19A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMV71J19B | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMV71J20A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMV71J20B | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMV71J21A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMV71J21B | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMV71N19A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMV71N19B | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMV71N20A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMV71N20A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMV71N21A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMV71N21B | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMV71Q19A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMV71Q19B | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMV71Q20A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMV71Q20B | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMV71Q21A | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| ATSAMV71Q21B | ARM | `FLASH1`;`RAM1` | `2.13.0+` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | + +--- + ### DSPIC | CHIP NAME | ARCHITECTURE | REQUIREMENTS | SUPPORTED IN VERSION | GPIO | ADC | I2C | PWM | SPI | UART | ONE WIRE | CAN | diff --git a/changelog.md b/changelog.md index d988de85c..ec864624b 100644 --- a/changelog.md +++ b/changelog.md @@ -10,6 +10,7 @@ **VERSIONS:** ++ **[v2.13.0](./changelog/v2.13.0/changelog.md)** + **[v2.12.2](./changelog/v2.12.2/changelog.md)** + **[v2.12.1](./changelog/v2.12.1/changelog.md)** + **[v2.12.0](./changelog/v2.12.0/changelog.md)** diff --git a/changelog/v2.13.0/changelog.md b/changelog/v2.13.0/changelog.md new file mode 100644 index 000000000..a8d84facd --- /dev/null +++ b/changelog/v2.13.0/changelog.md @@ -0,0 +1,127 @@ +

+ MikroElektronika +

+ +--- + +**[BACK TO MAIN FILE](../../changelog.md)** + +--- + +# `v2.13.0` + ++ released: 2024-12-20 + +## Changes + ++ [`v2.13.0`](#v2130) + + [Changes](#changes) + + [SAM](#sam) + + [NEW HARDWARE](#new-hardware) + +### SAM + +**SAM MCUs supported!** + +| MCU | MCU | MCU | +| :------------: | :------------: | :------------: | +| ATSAME70J19A | ATSAMS70J21A | ATSAMV70Q19A | +| ATSAME70J19B | ATSAMS70J21B | ATSAMV70Q19B | +| ATSAME70J20A | ATSAMS70N19A | ATSAMV70Q20A | +| ATSAME70J20B | ATSAMS70N19B | ATSAMV70Q20B | +| ATSAME70J21A | ATSAMS70N20A | ATSAMV71J19A | +| ATSAME70J21B | ATSAMS70N20B | ATSAMV71J19B | +| ATSAME70N19A | ATSAMS70N21A | ATSAMV71J20A | +| ATSAME70N19B | ATSAMS70N21B | ATSAMV71J20B | +| ATSAME70N20A | ATSAMS70Q19A | ATSAMV71J21A | +| ATSAME70N20B | ATSAMS70Q19B | ATSAMV71J21B | +| ATSAME70N21A | ATSAMS70Q20A | ATSAMV71N19A | +| ATSAME70N21B | ATSAMS70Q20B | ATSAMV71N19B | +| ATSAME70Q19A | ATSAMS70Q21A | ATSAMV71N20A | +| ATSAME70Q19B | ATSAMS70Q21B | ATSAMV71N20A | +| ATSAME70Q20A | ATSAMV70J19A | ATSAMV71N21A | +| ATSAME70Q20B | ATSAMV70J19B | ATSAMV71N21B | +| ATSAME70Q21A | ATSAMV70J20A | ATSAMV71Q19A | +| ATSAME70Q21B | ATSAMV70J20B | ATSAMV71Q19B | +| ATSAMS70J19A | ATSAMV70N19A | ATSAMV71Q20A | +| ATSAMS70J19B | ATSAMV70N19B | ATSAMV71Q20B | +| ATSAMS70J20A | ATSAMV70N20A | ATSAMV71Q21A | +| ATSAMS70J20B | ATSAMV70N20B | ATSAMV71Q21B | + + +**Supported modules:** + ++ ADC (Full module support) ++ SPI (Full module support) ++ UART (Full module support) ++ I2C (Full module support) ++ PWM (Full module support) ++ GPIO (Full module support) ++ OW (Full module support) + +**Files updated:** ++ Updated due to SAM inclusion in all ARM-related CMake files + + [utils.cmake](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/cmake/utils.cmake) + + [interface/CMakeLists.txt](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/hal/interface/CMakeLists.txt) + + [CMakeLists.txt](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/CMakeLists.txt) + + [common/CMakeLists.txt](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/common/CMakeLists.txt) + + [core/CMakeLists.txt](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/core/CMakeLists.txt) ++ Updated with more register handling macros for ARM architectures + + [hal_ll_bit_control.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/common/include/hal_ll_bit_control.h) ++ Updated with IRQ handling macros and regicters for SAM MCUs + + [hal_ll_core_defines.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/core/include/hal_ll_core_defines.h) + +**Files added:** + ++ [hal_ll_adc.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/include/adc/hal_ll_adc.h) ++ [hal_ll_adc_pin_map.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/include/adc/hal_ll_adc_pin_map/implementations/implementation_1/hal_ll_adc_pin_map.h) ++ [hal_ll_gpio.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/include/gpio/hal_ll_gpio.h) ++ [hal_ll_gpio_port.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/include/gpio/hal_ll_gpio_port.h) ++ [hal_ll_gpio_struct_type.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_struct_type.h) ++ [hal_ll_pin_names.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/include/hal_ll_pin_names.h) ++ [hal_ll_target.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/include/hal_ll_target.h) ++ [hal_ll_target_names.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/include/hal_ll_target_names.h) ++ [hal_ll_i2c_master.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_master.h) ++ [hal_ll_i2c_pin_map.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_pin_map/implementations/implementation_1/hal_ll_i2c_pin_map.h) ++ [hal_ll_one_wire.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/include/one_wire/implementations/implementation_1/hal_ll_one_wire.h) ++ [hal_ll_spi_master.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master.h) ++ [hal_ll_spi_master_pin_map.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master_pin_map/implementations/implementation_1/hal_ll_spi_master_pin_map.h) ++ [hal_ll_tim.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/include/tim/hal_ll_tim.h) ++ [hal_ll_tim_pin_map.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/implementation_1/hal_ll_tim_pin_map.h) ++ [hal_ll_uart.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/include/uart/hal_ll_uart.h) ++ [hal_ll_uart_pin_map.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/include/uart/hal_ll_uart_pin_map/implementations/implementation_1/hal_ll_uart_pin_map.h) ++ [hal_ll_adc.c](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c) ++ [hal_ll_gpio.c](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/src/gpio/hal_ll_gpio.c) ++ [hal_ll_gpio_port.c](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c) ++ [hal_ll_i2c_master.c](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c) ++ [hal_ll_one_wire.c](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/src/one_wire/implementations/implementation_1/hal_ll_one_wire.c) ++ [hal_ll_spi_master.c](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/src/spi_master/implementations/implementation_1/hal_ll_spi_master.c) ++ [hal_ll_tim.c](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c) ++ [hal_ll_uart.c](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c) ++ [hal_ll_core_port.c](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/core/src/sam/m7/hal_ll_core_port.c) ++ [CMakeLists.txt](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/CMakeLists.txt) ++ [hal_ll/CMakeLists.txt](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/src/hal_ll/CMakeLists.txt) ++ [adc/CMakeLists.txt](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/src/adc/CMakeLists.txt) ++ [gpio/CMakeLists.txt](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt) ++ [i2c/CMakeLists.txt](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/src/i2c/CMakeLists.txt) ++ [one_wire/CMakeLists.txt](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/src/one_wire/CMakeLists.txt) ++ [spi_master/CMakeLists.txt](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/src/spi_master/CMakeLists.txt) ++ [tim/CMakeLists.txt](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/src/tim/CMakeLists.txt) ++ [uart/CMakeLists.txt](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/sam/src/uart/CMakeLists.txt) ++ `./mcu_name/mcu_package/mcu_definitions.h` - `https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/common/include/mcu_definitions/SAM/mcu_name/mcu_package/mcu_definitions.h` + + Added for all MCUs in mikroSDK where mcu_name is actual chip full name, i.e. `ATSAME70Q21B` etc. and mcu_package is actual package, i.e. `LQFP64` etc. ++ `./mcu_name/mcu_package/mcu_reg_addresses.h` - `https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/arm/mikroe/common/include/mcu_definitions/SAM/mcu_name/mcu_package/mcu_reg_addresses.h` + + Added for all MCUs in mikroSDK where mcu_name is actual chip full name, i.e. `ATSAME70Q21B` etc. and mcu_package is actual package, i.e. `LQFP64` etc. + +### NEW HARDWARE + +> NOTE: +>> If any new hardware was added to current version, it will be listed here. + +Support added for following hardware: + +--- + +**[BACK TO MAIN FILE](../../changelog.md)** + +--- diff --git a/platform/mikrosdk_version/include/mikrosdk_version.h b/platform/mikrosdk_version/include/mikrosdk_version.h index 5aa22a382..1936cf577 100644 --- a/platform/mikrosdk_version/include/mikrosdk_version.h +++ b/platform/mikrosdk_version/include/mikrosdk_version.h @@ -60,14 +60,14 @@ extern "C"{ * @note changes in minor version indicate that there have been * significant improvements and/or features added */ -#define mikroSDK_MINOR_VERSION 12 +#define mikroSDK_MINOR_VERSION 13 /** * @brief mikroSDK_PATCH_VERSION * @note changes in patch version indicate smaller updates, * bug fixes and improvements */ -#define mikroSDK_PATCH_VERSION 2 +#define mikroSDK_PATCH_VERSION 0 /** * @brief mikroSDK_GET_VERSION From 6ffdf257cfdeb38cd045fd3bf60fd1d33f22b117 Mon Sep 17 00:00:00 2001 From: "ivan.ruzavin" Date: Mon, 16 Dec 2024 09:43:51 +0100 Subject: [PATCH 27/56] Removed unnecessary function declarations --- .../hal_ll_gpio_struct_type.h | 18 +- .../arm/mikroe/sam/include/hal_ll_pin_names.h | 591 ++++++++++++------ .../arm/mikroe/sam/include/uart/hal_ll_uart.h | 4 +- .../implementation_1/hal_ll_adc.c | 3 - .../implementation_1/hal_ll_gpio_port.c | 8 +- .../implementation_1/hal_ll_i2c_master.c | 11 - .../implementation_1/hal_ll_spi_master.c | 22 - .../implementation_1/hal_ll_tim.c | 7 +- .../implementation_1/hal_ll_uart.c | 18 - 9 files changed, 410 insertions(+), 272 deletions(-) diff --git a/targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_struct_type.h b/targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_struct_type.h index 1ae430f74..ff3eddd93 100644 --- a/targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_struct_type.h +++ b/targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_struct_type.h @@ -88,15 +88,15 @@ typedef struct hal_ll_gpio_register_handle */ typedef struct hal_ll_gpio_base_handle { - hal_ll_gpio_register_handle_t pio; /* Parallel input-output controller */ - hal_ll_gpio_register_handle_t output; /* Output configuration controller */ - hal_ll_gpio_register_handle_t filter; /* Input filter controller */ - hal_ll_gpio_signal_register_handle_t signal; /* Output signal controller */ - hal_ll_gpio_interrupt_register_handle_t interrupt; - hal_ll_gpio_register_handle_t multi_driver; - hal_ll_gpio_register_handle_t pullup_off; - uint32_t abcdsr0; /* Peripheral ABCD Select Register 0 */ - uint32_t abcdsr1; /* Peripheral ABCD Select Register 1 */ + hal_ll_gpio_register_handle_t pio; /* Parallel input-output controller */ + hal_ll_gpio_register_handle_t output; /* Output configuration controller */ + hal_ll_gpio_register_handle_t filter; /* Input filter controller */ + hal_ll_gpio_signal_register_handle_t signal; /* Output signal controller */ + hal_ll_gpio_interrupt_register_handle_t interrupt; /* IO interrupt controller */ + hal_ll_gpio_register_handle_t multi_driver; /* Multi-driver controller */ + hal_ll_gpio_register_handle_t pullup_off; /* Pull-up resistor disabling controller */ + uint32_t abcdsr0; /* Peripheral ABCD Select Register 0 */ + uint32_t abcdsr1; /* Peripheral ABCD Select Register 1 */ } hal_ll_gpio_base_handle_t; #ifdef __cplusplus diff --git a/targets/arm/mikroe/sam/include/hal_ll_pin_names.h b/targets/arm/mikroe/sam/include/hal_ll_pin_names.h index bcc332280..691e16381 100644 --- a/targets/arm/mikroe/sam/include/hal_ll_pin_names.h +++ b/targets/arm/mikroe/sam/include/hal_ll_pin_names.h @@ -70,537 +70,734 @@ extern "C"{ #endif #ifdef __PA0_CN -#define PA0 (0x00) +#define GPIO_PA0 (0x00) +#define PA0 GPIO_PA0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA0! #endif #ifdef __PA1_CN -#define PA1 (0x01) +#define GPIO_PA1 (0x01) +#define PA1 GPIO_PA1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA1! #endif #ifdef __PA2_CN -#define PA2 (0x02) +#define GPIO_PA2 (0x02) +#define PA2 GPIO_PA2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA2! #endif #ifdef __PA3_CN -#define PA3 (0x03) +#define GPIO_PA3 (0x03) +#define PA3 GPIO_PA3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA3! #endif #ifdef __PA4_CN -#define PA4 (0x04) +#define GPIO_PA4 (0x04) +#define PA4 GPIO_PA4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA4! #endif #ifdef __PA5_CN -#define PA5 (0x05) +#define GPIO_PA5 (0x05) +#define PA5 GPIO_PA5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA5! #endif #ifdef __PA6_CN -#define PA6 (0x06) +#define GPIO_PA6 (0x06) +#define PA6 GPIO_PA6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA6! #endif #ifdef __PA7_CN -#define PA7 (0x07) +#define GPIO_PA7 (0x07) +#define PA7 GPIO_PA7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA7! #endif #ifdef __PA8_CN -#define PA8 (0x08) +#define GPIO_PA8 (0x08) +#define PA8 GPIO_PA8 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA8! #endif #ifdef __PA9_CN -#define PA9 (0x09) +#define GPIO_PA9 (0x09) +#define PA9 GPIO_PA9 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA9! #endif #ifdef __PA10_CN -#define PA10 (0x0A) +#define GPIO_PA10 (0x0A) +#define PA10 GPIO_PA10 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA10! #endif #ifdef __PA11_CN -#define PA11 (0x0B) +#define GPIO_PA11 (0x0B) +#define PA11 GPIO_PA11 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA11! #endif #ifdef __PA12_CN -#define PA12 (0x0C) +#define GPIO_PA12 (0x0C) +#define PA12 GPIO_PA12 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA12! #endif #ifdef __PA13_CN -#define PA13 (0x0D) +#define GPIO_PA13 (0x0D) +#define PA13 GPIO_PA13 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA13! #endif #ifdef __PA14_CN -#define PA14 (0x0E) +#define GPIO_PA14 (0x0E) +#define PA14 GPIO_PA14 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA14! #endif #ifdef __PA15_CN -#define PA15 (0x0F) +#define GPIO_PA15 (0x0F) +#define PA15 GPIO_PA15 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA15! #endif #ifdef __PA16_CN -#define PA16 (0x10) +#define GPIO_PA16 (0x10) +#define PA16 GPIO_PA16 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA16! #endif #ifdef __PA17_CN -#define PA17 (0x11) +#define GPIO_PA17 (0x11) +#define PA17 GPIO_PA17 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA17! #endif #ifdef __PA18_CN -#define PA18 (0x12) +#define GPIO_PA18 (0x12) +#define PA18 GPIO_PA18 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA18! #endif #ifdef __PA19_CN -#define PA19 (0x13) +#define GPIO_PA19 (0x13) +#define PA19 GPIO_PA19 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA19! #endif #ifdef __PA20_CN -#define PA20 (0x14) +#define GPIO_PA20 (0x14) +#define PA20 GPIO_PA20 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA20! #endif #ifdef __PA21_CN -#define PA21 (0x15) +#define GPIO_PA21 (0x15) +#define PA21 GPIO_PA21 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA21! #endif #ifdef __PA22_CN -#define PA22 (0x16) +#define GPIO_PA22 (0x16) +#define PA22 GPIO_PA22 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA22! #endif #ifdef __PA23_CN -#define PA23 (0x17) +#define GPIO_PA23 (0x17) +#define PA23 GPIO_PA23 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA23! #endif #ifdef __PA24_CN -#define PA24 (0x18) +#define GPIO_PA24 (0x18) +#define PA24 GPIO_PA24 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA24! #endif #ifdef __PA25_CN -#define PA25 (0x19) +#define GPIO_PA25 (0x19) +#define PA25 GPIO_PA25 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA25! #endif #ifdef __PA26_CN -#define PA26 (0x1A) +#define GPIO_PA26 (0x1A) +#define PA26 GPIO_PA26 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA26! #endif #ifdef __PA27_CN -#define PA27 (0x1B) +#define GPIO_PA27 (0x1B) +#define PA27 GPIO_PA27 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA27! #endif #ifdef __PA28_CN -#define PA28 (0x1C) +#define GPIO_PA28 (0x1C) +#define PA28 GPIO_PA28 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA28! #endif #ifdef __PA29_CN -#define PA29 (0x1D) +#define GPIO_PA29 (0x1D) +#define PA29 GPIO_PA29 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA29! #endif #ifdef __PA30_CN -#define PA30 (0x1E) +#define GPIO_PA30 (0x1E) +#define PA30 GPIO_PA30 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA30! #endif #ifdef __PA31_CN -#define PA31 (0x1F) +#define GPIO_PA31 (0x1F) +#define PA31 GPIO_PA31 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PA31! #endif #ifdef __PB0_CN -#define PB0 (0x20) +#define GPIO_PB0 (0x20) +#define PB0 GPIO_PB0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB0! #endif #ifdef __PB1_CN -#define PB1 (0x21) +#define GPIO_PB1 (0x21) +#define PB1 GPIO_PB1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB1! #endif #ifdef __PB2_CN -#define PB2 (0x22) +#define GPIO_PB2 (0x22) +#define PB2 GPIO_PB2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB2! #endif #ifdef __PB3_CN -#define PB3 (0x23) +#define GPIO_PB3 (0x23) +#define PB3 GPIO_PB3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB3! #endif #ifdef __PB4_CN -#define PB4 (0x24) +#define GPIO_PB4 (0x24) +#define PB4 GPIO_PB4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB4! #endif #ifdef __PB5_CN -#define PB5 (0x25) +#define GPIO_PB5 (0x25) +#define PB5 GPIO_PB5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB5! #endif #ifdef __PB6_CN -#define PB6 (0x26) +#define GPIO_PB6 (0x26) +#define PB6 GPIO_PB6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB6! #endif #ifdef __PB7_CN -#define PB7 (0x27) +#define GPIO_PB7 (0x27) +#define PB7 GPIO_PB7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB7! #endif #ifdef __PB8_CN -#define PB8 (0x28) +#define GPIO_PB8 (0x28) +#define PB8 GPIO_PB8 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB8! #endif #ifdef __PB9_CN -#define PB9 (0x29) +#define GPIO_PB9 (0x29) +#define PB9 GPIO_PB9 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB9! #endif #ifdef __PB10_CN -#define PB10 (0x2A) +#define GPIO_PB10 (0x2A) +#define PB10 GPIO_PB10 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB10! #endif #ifdef __PB11_CN -#define PB11 (0x2B) +#define GPIO_PB11 (0x2B) +#define PB11 GPIO_PB11 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB11! #endif #ifdef __PB12_CN -#define PB12 (0x2C) +#define GPIO_PB12 (0x2C) +#define PB12 GPIO_PB12 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB12! #endif #ifdef __PB13_CN -#define PB13 (0x2D) +#define GPIO_PB13 (0x2D) +#define PB13 GPIO_PB13 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB13! #endif #ifdef __PB14_CN -#define PB14 (0x2E) +#define GPIO_PB14 (0x2E) +#define PB14 GPIO_PB14 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB14! #endif #ifdef __PB15_CN -#define PB15 (0x2F) +#define GPIO_PB15 (0x2F) +#define PB15 GPIO_PB15 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB15! #endif #ifdef __PB16_CN -#define PB16 (0x30) +#define GPIO_PB16 (0x30) +#define PB16 GPIO_PB16 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB16! #endif #ifdef __PB17_CN -#define PB17 (0x31) +#define GPIO_PB17 (0x31) +#define PB17 GPIO_PB17 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB17! #endif #ifdef __PB18_CN -#define PB18 (0x32) +#define GPIO_PB18 (0x32) +#define PB18 GPIO_PB18 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB18! #endif #ifdef __PB19_CN -#define PB19 (0x33) +#define GPIO_PB19 (0x33) +#define PB19 GPIO_PB19 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB19! #endif #ifdef __PB20_CN -#define PB20 (0x34) +#define GPIO_PB20 (0x34) +#define PB20 GPIO_PB20 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB20! #endif #ifdef __PB21_CN -#define PB21 (0x35) +#define GPIO_PB21 (0x35) +#define PB21 GPIO_PB21 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB21! #endif #ifdef __PB22_CN -#define PB22 (0x36) +#define GPIO_PB22 (0x36) +#define PB22 GPIO_PB22 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB22! #endif #ifdef __PB23_CN -#define PB23 (0x37) +#define GPIO_PB23 (0x37) +#define PB23 GPIO_PB23 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB23! #endif #ifdef __PB24_CN -#define PB24 (0x38) +#define GPIO_PB24 (0x38) +#define PB24 GPIO_PB24 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB24! #endif #ifdef __PB25_CN -#define PB25 (0x39) +#define GPIO_PB25 (0x39) +#define PB25 GPIO_PB25 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB25! #endif #ifdef __PB26_CN -#define PB26 (0x3A) +#define GPIO_PB26 (0x3A) +#define PB26 GPIO_PB26 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB26! #endif #ifdef __PB27_CN -#define PB27 (0x3B) +#define GPIO_PB27 (0x3B) +#define PB27 GPIO_PB27 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB27! #endif #ifdef __PB28_CN -#define PB28 (0x3C) +#define GPIO_PB28 (0x3C) +#define PB28 GPIO_PB28 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB28! #endif #ifdef __PB29_CN -#define PB29 (0x3D) +#define GPIO_PB29 (0x3D) +#define PB29 GPIO_PB29 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB29! #endif #ifdef __PB30_CN -#define PB30 (0x3E) +#define GPIO_PB30 (0x3E) +#define PB30 GPIO_PB30 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB30! #endif #ifdef __PB31_CN -#define PB31 (0x3F) +#define GPIO_PB31 (0x3F) +#define PB31 GPIO_PB31 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PB31! #endif #ifdef __PC0_CN -#define PC0 (0x40) +#define GPIO_PC0 (0x40) +#define PC0 GPIO_PC0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC0! #endif #ifdef __PC1_CN -#define PC1 (0x41) +#define GPIO_PC1 (0x41) +#define PC1 GPIO_PC1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC1! #endif #ifdef __PC2_CN -#define PC2 (0x42) +#define GPIO_PC2 (0x42) +#define PC2 GPIO_PC2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC2! #endif #ifdef __PC3_CN -#define PC3 (0x43) +#define GPIO_PC3 (0x43) +#define PC3 GPIO_PC3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC3! #endif #ifdef __PC4_CN -#define PC4 (0x44) +#define GPIO_PC4 (0x44) +#define PC4 GPIO_PC4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC4! #endif #ifdef __PC5_CN -#define PC5 (0x45) +#define GPIO_PC5 (0x45) +#define PC5 GPIO_PC5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC5! #endif #ifdef __PC6_CN -#define PC6 (0x46) +#define GPIO_PC6 (0x46) +#define PC6 GPIO_PC6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC6! #endif #ifdef __PC7_CN -#define PC7 (0x47) +#define GPIO_PC7 (0x47) +#define PC7 GPIO_PC7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC7! #endif #ifdef __PC8_CN -#define PC8 (0x48) +#define GPIO_PC8 (0x48) +#define PC8 GPIO_PC8 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC8! #endif #ifdef __PC9_CN -#define PC9 (0x49) +#define GPIO_PC9 (0x49) +#define PC9 GPIO_PC9 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC9! #endif #ifdef __PC10_CN -#define PC10 (0x4A) +#define GPIO_PC10 (0x4A) +#define PC10 GPIO_PC10 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC10! #endif #ifdef __PC11_CN -#define PC11 (0x4B) +#define GPIO_PC11 (0x4B) +#define PC11 GPIO_PC11 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC11! #endif #ifdef __PC12_CN -#define PC12 (0x4C) +#define GPIO_PC12 (0x4C) +#define PC12 GPIO_PC12 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC12! #endif #ifdef __PC13_CN -#define PC13 (0x4D) +#define GPIO_PC13 (0x4D) +#define PC13 GPIO_PC13 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC13! #endif #ifdef __PC14_CN -#define PC14 (0x4E) +#define GPIO_PC14 (0x4E) +#define PC14 GPIO_PC14 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC14! #endif #ifdef __PC15_CN -#define PC15 (0x4F) +#define GPIO_PC15 (0x4F) +#define PC15 GPIO_PC15 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC15! #endif #ifdef __PC16_CN -#define PC16 (0x50) +#define GPIO_PC16 (0x50) +#define PC16 GPIO_PC16 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC16! #endif #ifdef __PC17_CN -#define PC17 (0x51) +#define GPIO_PC17 (0x51) +#define PC17 GPIO_PC17 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC17! #endif #ifdef __PC18_CN -#define PC18 (0x52) +#define GPIO_PC18 (0x52) +#define PC18 GPIO_PC18 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC18! #endif #ifdef __PC19_CN -#define PC19 (0x53) +#define GPIO_PC19 (0x53) +#define PC19 GPIO_PC19 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC19! #endif #ifdef __PC20_CN -#define PC20 (0x54) +#define GPIO_PC20 (0x54) +#define PC20 GPIO_PC20 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC20! #endif #ifdef __PC21_CN -#define PC21 (0x55) +#define GPIO_PC21 (0x55) +#define PC21 GPIO_PC21 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC21! #endif #ifdef __PC22_CN -#define PC22 (0x56) +#define GPIO_PC22 (0x56) +#define PC22 GPIO_PC22 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC22! #endif #ifdef __PC23_CN -#define PC23 (0x57) +#define GPIO_PC23 (0x57) +#define PC23 GPIO_PC23 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC23! #endif #ifdef __PC24_CN -#define PC24 (0x58) +#define GPIO_PC24 (0x58) +#define PC24 GPIO_PC24 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC24! #endif #ifdef __PC25_CN -#define PC25 (0x59) +#define GPIO_PC25 (0x59) +#define PC25 GPIO_PC25 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC25! #endif #ifdef __PC26_CN -#define PC26 (0x5A) +#define GPIO_PC26 (0x5A) +#define PC26 GPIO_PC26 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC26! #endif #ifdef __PC27_CN -#define PC27 (0x5B) +#define GPIO_PC27 (0x5B) +#define PC27 GPIO_PC27 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC27! #endif #ifdef __PC28_CN -#define PC28 (0x5C) +#define GPIO_PC28 (0x5C) +#define PC28 GPIO_PC28 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC28! #endif #ifdef __PC29_CN -#define PC29 (0x5D) +#define GPIO_PC29 (0x5D) +#define PC29 GPIO_PC29 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC29! #endif #ifdef __PC30_CN -#define PC30 (0x5E) +#define GPIO_PC30 (0x5E) +#define PC30 GPIO_PC30 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC30! #endif #ifdef __PC31_CN -#define PC31 (0x5F) +#define GPIO_PC31 (0x5F) +#define PC31 GPIO_PC31 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PC31! #endif #ifdef __PD0_CN -#define PD0 (0x60) +#define GPIO_PD0 (0x60) +#define PD0 GPIO_PD0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD0! #endif #ifdef __PD1_CN -#define PD1 (0x61) +#define GPIO_PD1 (0x61) +#define PD1 GPIO_PD1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD1! #endif #ifdef __PD2_CN -#define PD2 (0x62) +#define GPIO_PD2 (0x62) +#define PD2 GPIO_PD2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD2! #endif #ifdef __PD3_CN -#define PD3 (0x63) +#define GPIO_PD3 (0x63) +#define PD3 GPIO_PD3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD3! #endif #ifdef __PD4_CN -#define PD4 (0x64) +#define GPIO_PD4 (0x64) +#define PD4 GPIO_PD4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD4! #endif #ifdef __PD5_CN -#define PD5 (0x65) +#define GPIO_PD5 (0x65) +#define PD5 GPIO_PD5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD5! #endif #ifdef __PD6_CN -#define PD6 (0x66) +#define GPIO_PD6 (0x66) +#define PD6 GPIO_PD6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD6! #endif #ifdef __PD7_CN -#define PD7 (0x67) +#define GPIO_PD7 (0x67) +#define PD7 GPIO_PD7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD7! #endif #ifdef __PD8_CN -#define PD8 (0x68) +#define GPIO_PD8 (0x68) +#define PD8 GPIO_PD8 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD8! #endif #ifdef __PD9_CN -#define PD9 (0x69) +#define GPIO_PD9 (0x69) +#define PD9 GPIO_PD9 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD9! #endif #ifdef __PD10_CN -#define PD10 (0x6A) +#define GPIO_PD10 (0x6A) +#define PD10 GPIO_PD10 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD10! #endif #ifdef __PD11_CN -#define PD11 (0x6B) +#define GPIO_PD11 (0x6B) +#define PD11 GPIO_PD11 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD11! #endif #ifdef __PD12_CN -#define PD12 (0x6C) +#define GPIO_PD12 (0x6C) +#define PD12 GPIO_PD12 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD12! #endif #ifdef __PD13_CN -#define PD13 (0x6D) +#define GPIO_PD13 (0x6D) +#define PD13 GPIO_PD13 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD13! #endif #ifdef __PD14_CN -#define PD14 (0x6E) +#define GPIO_PD14 (0x6E) +#define PD14 GPIO_PD14 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD14! #endif #ifdef __PD15_CN -#define PD15 (0x6F) +#define GPIO_PD15 (0x6F) +#define PD15 GPIO_PD15 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD15! #endif #ifdef __PD16_CN -#define PD16 (0x70) +#define GPIO_PD16 (0x70) +#define PD16 GPIO_PD16 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD16! #endif #ifdef __PD17_CN -#define PD17 (0x71) +#define GPIO_PD17 (0x71) +#define PD17 GPIO_PD17 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD17! #endif #ifdef __PD18_CN -#define PD18 (0x72) +#define GPIO_PD18 (0x72) +#define PD18 GPIO_PD18 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD18! #endif #ifdef __PD19_CN -#define PD19 (0x73) +#define GPIO_PD19 (0x73) +#define PD19 GPIO_PD19 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD19! #endif #ifdef __PD20_CN -#define PD20 (0x74) +#define GPIO_PD20 (0x74) +#define PD20 GPIO_PD20 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD20! #endif #ifdef __PD21_CN -#define PD21 (0x75) +#define GPIO_PD21 (0x75) +#define PD21 GPIO_PD21 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD21! #endif #ifdef __PD22_CN -#define PD22 (0x76) +#define GPIO_PD22 (0x76) +#define PD22 GPIO_PD22 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD22! #endif #ifdef __PD23_CN -#define PD23 (0x77) +#define GPIO_PD23 (0x77) +#define PD23 GPIO_PD23 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD23! #endif #ifdef __PD24_CN -#define PD24 (0x78) +#define GPIO_PD24 (0x78) +#define PD24 GPIO_PD24 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD24! #endif #ifdef __PD25_CN -#define PD25 (0x79) +#define GPIO_PD25 (0x79) +#define PD25 GPIO_PD25 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD25! #endif #ifdef __PD26_CN -#define PD26 (0x7A) +#define GPIO_PD26 (0x7A) +#define PD26 GPIO_PD26 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD26! #endif #ifdef __PD27_CN -#define PD27 (0x7B) +#define GPIO_PD27 (0x7B) +#define PD27 GPIO_PD27 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD27! #endif #ifdef __PD28_CN -#define PD28 (0x7C) +#define GPIO_PD28 (0x7C) +#define PD28 GPIO_PD28 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD28! #endif #ifdef __PD29_CN -#define PD29 (0x7D) +#define GPIO_PD29 (0x7D) +#define PD29 GPIO_PD29 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD29! #endif #ifdef __PD30_CN -#define PD30 (0x7E) +#define GPIO_PD30 (0x7E) +#define PD30 GPIO_PD30 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD30! #endif #ifdef __PD31_CN -#define PD31 (0x7F) +#define GPIO_PD31 (0x7F) +#define PD31 GPIO_PD31 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PD31! #endif #ifdef __PE0_CN -#define PE0 (0x80) +#define GPIO_PE0 (0x80) +#define PE0 GPIO_PE0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE0! #endif #ifdef __PE1_CN -#define PE1 (0x81) +#define GPIO_PE1 (0x81) +#define PE1 GPIO_PE1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE1! #endif #ifdef __PE2_CN -#define PE2 (0x82) +#define GPIO_PE2 (0x82) +#define PE2 GPIO_PE2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE2! #endif #ifdef __PE3_CN -#define PE3 (0x83) +#define GPIO_PE3 (0x83) +#define PE3 GPIO_PE3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE3! #endif #ifdef __PE4_CN -#define PE4 (0x84) +#define GPIO_PE4 (0x84) +#define PE4 GPIO_PE4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE4! #endif #ifdef __PE5_CN -#define PE5 (0x85) +#define GPIO_PE5 (0x85) +#define PE5 GPIO_PE5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE5! #endif #ifdef __PE6_CN -#define PE6 (0x86) +#define GPIO_PE6 (0x86) +#define PE6 GPIO_PE6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE6! #endif #ifdef __PE7_CN -#define PE7 (0x87) +#define GPIO_PE7 (0x87) +#define PE7 GPIO_PE7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE7! #endif #ifdef __PE8_CN -#define PE8 (0x88) +#define GPIO_PE8 (0x88) +#define PE8 GPIO_PE8 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE8! #endif #ifdef __PE9_CN -#define PE9 (0x89) +#define GPIO_PE9 (0x89) +#define PE9 GPIO_PE9 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE9! #endif #ifdef __PE10_CN -#define PE10 (0x8A) +#define GPIO_PE10 (0x8A) +#define PE10 GPIO_PE10 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE10! #endif #ifdef __PE11_CN -#define PE11 (0x8B) +#define GPIO_PE11 (0x8B) +#define PE11 GPIO_PE11 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE11! #endif #ifdef __PE12_CN -#define PE12 (0x8C) +#define GPIO_PE12 (0x8C) +#define PE12 GPIO_PE12 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE12! #endif #ifdef __PE13_CN -#define PE13 (0x8D) +#define GPIO_PE13 (0x8D) +#define PE13 GPIO_PE13 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE13! #endif #ifdef __PE14_CN -#define PE14 (0x8E) +#define GPIO_PE14 (0x8E) +#define PE14 GPIO_PE14 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE14! #endif #ifdef __PE15_CN -#define PE15 (0x8F) +#define GPIO_PE15 (0x8F) +#define PE15 GPIO_PE15 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE15! #endif #ifdef __PE16_CN -#define PE16 (0x90) +#define GPIO_PE16 (0x90) +#define PE16 GPIO_PE16 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE16! #endif #ifdef __PE17_CN -#define PE17 (0x91) +#define GPIO_PE17 (0x91) +#define PE17 GPIO_PE17 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE17! #endif #ifdef __PE18_CN -#define PE18 (0x92) +#define GPIO_PE18 (0x92) +#define PE18 GPIO_PE18 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE18! #endif #ifdef __PE19_CN -#define PE19 (0x93) +#define GPIO_PE19 (0x93) +#define PE19 GPIO_PE19 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE19! #endif #ifdef __PE20_CN -#define PE20 (0x94) +#define GPIO_PE20 (0x94) +#define PE20 GPIO_PE20 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE20! #endif #ifdef __PE21_CN -#define PE21 (0x95) +#define GPIO_PE21 (0x95) +#define PE21 GPIO_PE21 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE21! #endif #ifdef __PE22_CN -#define PE22 (0x96) +#define GPIO_PE22 (0x96) +#define PE22 GPIO_PE22 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE22! #endif #ifdef __PE23_CN -#define PE23 (0x97) +#define GPIO_PE23 (0x97) +#define PE23 GPIO_PE23 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE23! #endif #ifdef __PE24_CN -#define PE24 (0x98) +#define GPIO_PE24 (0x98) +#define PE24 GPIO_PE24 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE24! #endif #ifdef __PE25_CN -#define PE25 (0x99) +#define GPIO_PE25 (0x99) +#define PE25 GPIO_PE25 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE25! #endif #ifdef __PE26_CN -#define PE26 (0x9A) +#define GPIO_PE26 (0x9A) +#define PE26 GPIO_PE26 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE26! #endif #ifdef __PE27_CN -#define PE27 (0x9B) +#define GPIO_PE27 (0x9B) +#define PE27 GPIO_PE27 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE27! #endif #ifdef __PE28_CN -#define PE28 (0x9C) +#define GPIO_PE28 (0x9C) +#define PE28 GPIO_PE28 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE28! #endif #ifdef __PE29_CN -#define PE29 (0x9D) +#define GPIO_PE29 (0x9D) +#define PE29 GPIO_PE29 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE29! #endif #ifdef __PE30_CN -#define PE30 (0x9E) +#define GPIO_PE30 (0x9E) +#define PE30 GPIO_PE30 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE30! #endif #ifdef __PE31_CN -#define PE31 (0x9F) +#define GPIO_PE31 (0x9F) +#define PE31 GPIO_PE31 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PE31! #endif -#define PIN_0 (0x00) -#define PIN_1 (0x01) -#define PIN_2 (0x02) -#define PIN_3 (0x03) -#define PIN_4 (0x04) -#define PIN_5 (0x05) -#define PIN_6 (0x06) -#define PIN_7 (0x07) -#define PIN_8 (0x08) -#define PIN_9 (0x09) -#define PIN_10 (0x0A) -#define PIN_11 (0x0B) -#define PIN_12 (0x0C) -#define PIN_13 (0x0D) -#define PIN_14 (0x0E) -#define PIN_15 (0x0F) -#define PIN_16 (0x10) -#define PIN_17 (0x11) -#define PIN_18 (0x12) -#define PIN_19 (0x13) -#define PIN_20 (0x14) -#define PIN_21 (0x15) -#define PIN_22 (0x16) -#define PIN_23 (0x17) -#define PIN_24 (0x18) -#define PIN_25 (0x19) -#define PIN_26 (0x1A) -#define PIN_27 (0x1B) -#define PIN_28 (0x1C) -#define PIN_29 (0x1D) -#define PIN_30 (0x1E) -#define PIN_31 (0x1F) +#define GPIO_PIN_0 (0x00) +#define PIN_0 GPIO_PIN_0 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_0! +#define GPIO_PIN_1 (0x01) +#define PIN_1 GPIO_PIN_1 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_1! +#define GPIO_PIN_2 (0x02) +#define PIN_2 GPIO_PIN_2 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_2! +#define GPIO_PIN_3 (0x03) +#define PIN_3 GPIO_PIN_3 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_3! +#define GPIO_PIN_4 (0x04) +#define PIN_4 GPIO_PIN_4 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_4! +#define GPIO_PIN_5 (0x05) +#define PIN_5 GPIO_PIN_5 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_5! +#define GPIO_PIN_6 (0x06) +#define PIN_6 GPIO_PIN_6 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_6! +#define GPIO_PIN_7 (0x07) +#define PIN_7 GPIO_PIN_7 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_7! +#define GPIO_PIN_8 (0x08) +#define PIN_8 GPIO_PIN_8 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_8! +#define GPIO_PIN_9 (0x09) +#define PIN_9 GPIO_PIN_9 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_9! +#define GPIO_PIN_10 (0x0A) +#define PIN_10 GPIO_PIN_10 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_10! +#define GPIO_PIN_11 (0x0B) +#define PIN_11 GPIO_PIN_11 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_11! +#define GPIO_PIN_12 (0x0C) +#define PIN_12 GPIO_PIN_12 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_12! +#define GPIO_PIN_13 (0x0D) +#define PIN_13 GPIO_PIN_13 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_13! +#define GPIO_PIN_14 (0x0E) +#define PIN_14 GPIO_PIN_14 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_14! +#define GPIO_PIN_15 (0x0F) +#define PIN_15 GPIO_PIN_15 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_15! +#define GPIO_PIN_16 (0x10) +#define PIN_16 GPIO_PIN_16 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_16! +#define GPIO_PIN_17 (0x11) +#define PIN_17 GPIO_PIN_17 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_17! +#define GPIO_PIN_18 (0x12) +#define PIN_18 GPIO_PIN_18 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_18! +#define GPIO_PIN_19 (0x13) +#define PIN_19 GPIO_PIN_19 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_19! +#define GPIO_PIN_20 (0x14) +#define PIN_20 GPIO_PIN_20 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_20! +#define GPIO_PIN_21 (0x15) +#define PIN_21 GPIO_PIN_21 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_21! +#define GPIO_PIN_22 (0x16) +#define PIN_22 GPIO_PIN_22 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_22! +#define GPIO_PIN_23 (0x17) +#define PIN_23 GPIO_PIN_23 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_23! +#define GPIO_PIN_24 (0x18) +#define PIN_24 GPIO_PIN_24 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_24! +#define GPIO_PIN_25 (0x19) +#define PIN_25 GPIO_PIN_25 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_25! +#define GPIO_PIN_26 (0x1A) +#define PIN_26 GPIO_PIN_26 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_26! +#define GPIO_PIN_27 (0x1B) +#define PIN_27 GPIO_PIN_27 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_27! +#define GPIO_PIN_28 (0x1C) +#define PIN_28 GPIO_PIN_28 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_28! +#define GPIO_PIN_29 (0x1D) +#define PIN_29 GPIO_PIN_29 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_29! +#define GPIO_PIN_30 (0x1E) +#define PIN_30 GPIO_PIN_30 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_30! +#define GPIO_PIN_31 (0x1F) +#define PIN_31 GPIO_PIN_31 // Notice: Will be removed in one of the upcoming releases. Use GPIO_PIN_31! #ifdef __PORT_A_CN -#define PORT_A (0x00) +#define GPIO_PORT_A (0x00) +#define PORT_A GPIO_PORT_A // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_A! #endif #ifdef __PORT_B_CN -#define PORT_B (0x01) +#define GPIO_PORT_B (0x01) +#define PORT_B GPIO_PORT_B // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_B! #endif #ifdef __PORT_C_CN -#define PORT_C (0x02) +#define GPIO_PORT_C (0x02) +#define PORT_C GPIO_PORT_C // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_C! #endif #ifdef __PORT_D_CN -#define PORT_D (0x03) +#define GPIO_PORT_D (0x03) +#define PORT_D GPIO_PORT_D // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_D! #endif #ifdef __PORT_E_CN -#define PORT_E (0x04) +#define GPIO_PORT_E (0x04) +#define PORT_E GPIO_PORT_E // Notice: Will be removed in one of the upcoming releases. Use GPIO_PORT_E! #endif #ifdef __cplusplus diff --git a/targets/arm/mikroe/sam/include/uart/hal_ll_uart.h b/targets/arm/mikroe/sam/include/uart/hal_ll_uart.h index da7be67a7..4ac093f2b 100644 --- a/targets/arm/mikroe/sam/include/uart/hal_ll_uart.h +++ b/targets/arm/mikroe/sam/include/uart/hal_ll_uart.h @@ -55,8 +55,8 @@ extern "C"{ */ typedef enum { - HAL_LL_UART_IRQ_RX, /**< RX INT */ - HAL_LL_UART_IRQ_TX /**< TX INT */ + HAL_LL_UART_IRQ_RX, /**< RX INT */ + HAL_LL_UART_IRQ_TX /**< TX INT */ } hal_ll_uart_irq_t; /** diff --git a/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c b/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c index 5982ab2e3..8d2df49bc 100644 --- a/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c +++ b/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c @@ -72,14 +72,11 @@ #define HAL_LL_AFEC_EMR_NO_AVERAGE_MASK 0x00000000ul #define HAL_LL_AFEC_ACR_PGAEN12_MASK 0x0000000Cul -#define HAL_LL_AFEC_MR_PRESCAL_1_MASK 0x00000100ul #define HAL_LL_AFEC_COCR_OFFSET_MASK 0x00000200ul #define HAL_LL_AFEC_EMR_LOW_RES_MASK 0x00010000ul #define HAL_LL_AFEC_EMR_OSR16 0x00030000ul #define HAL_LL_AFEC_EMR_OSR256 0x00050000ul -#define HAL_LL_MODULE_INDEX_ERROR 0xFFFFFFFFul - // -------------------------------------------------------------- PRIVATE TYPES /*!< @brief Local handle list */ static hal_ll_adc_handle_register_t hal_ll_module_state[ADC_MODULE_COUNT] = { (handle_t *) NULL, (handle_t *) NULL, false }; diff --git a/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c b/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c index a59f7416b..5bcb10e65 100644 --- a/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c +++ b/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c @@ -243,7 +243,7 @@ static void hal_ll_gpio_config( hal_ll_gpio_base_t *port, hal_ll_gpio_mask_t pin // Set gpio direction as input with filtering. port_ptr->pio.enable |= pin_mask; port_ptr->filter.enable |= pin_mask; - } else { + } else { // Set gpio direction as output and enable Pull Up resistor. port_ptr->pio.enable |= pin_mask; port_ptr->output.enable |= pin_mask; @@ -282,15 +282,15 @@ static void hal_ll_gpio_config_pin_alternate_enable( uint8_t module_pin, uint8_t clear_reg_bit(&port_ptr->abcdsr0, pin_index); clear_reg_bit(&port_ptr->abcdsr1, pin_index); break; - case HAL_LL_PERIPHERAL_B: + case HAL_LL_PERIPHERAL_B: set_reg_bit(&port_ptr->abcdsr0, pin_index); clear_reg_bit(&port_ptr->abcdsr1, pin_index); break; - case HAL_LL_PERIPHERAL_C: + case HAL_LL_PERIPHERAL_C: clear_reg_bit(&port_ptr->abcdsr0, pin_index); set_reg_bit(&port_ptr->abcdsr1, pin_index); break; - case HAL_LL_PERIPHERAL_D: + case HAL_LL_PERIPHERAL_D: set_reg_bit(&port_ptr->abcdsr0, pin_index); set_reg_bit(&port_ptr->abcdsr1, pin_index); break; diff --git a/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c b/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c index fc4b73bec..fc1f86424 100644 --- a/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c +++ b/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c @@ -74,12 +74,6 @@ static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODU /*!< @brief Macro used for timeout */ #define HAL_LL_I2C_LOOP_INDEX 10000U -/*!< @brief Macro used for calculating dividers */ -#define HAL_LL_TWIHS_CLK_DIVIDER 2 -#define HAL_LL_TWIHS_CLK_CALC_ARGU 3 -#define HAL_LL_TWIHS_CLK_DIV_MIN 7 -#define HAL_LL_TWIHS_CLK_DIV_MAX 0xFF - /*!< @brief Macros defining register bit location */ #define HAL_LL_TWIHS_SR_TXCOMP_BIT 0 #define HAL_LL_TWIHS_SR_RXRDY_BIT 1 @@ -102,11 +96,6 @@ static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODU /*!< @brief Macros for speed calculation */ #define HAL_LL_TWIHS_CWGR_CLKDIV_MAX 7 -/*!< @brief Macros used for module pin checking */ -#define HAL_LL_I2C_SCL_PIN 0 -#define HAL_LL_I2C_SDA_PIN 1 -#define HAL_LL_I2C_MODULE_PIN_COUNT 2 - // -------------------------------------------------------------- PRIVATE TYPES /*!< @brief I2C register structure */ typedef struct diff --git a/targets/arm/mikroe/sam/src/spi_master/implementations/implementation_1/hal_ll_spi_master.c b/targets/arm/mikroe/sam/src/spi_master/implementations/implementation_1/hal_ll_spi_master.c index abfd2b676..2c7fd3218 100644 --- a/targets/arm/mikroe/sam/src/spi_master/implementations/implementation_1/hal_ll_spi_master.c +++ b/targets/arm/mikroe/sam/src/spi_master/implementations/implementation_1/hal_ll_spi_master.c @@ -45,8 +45,6 @@ #include "hal_ll_spi_master.h" #include "hal_ll_spi_master_pin_map.h" -#include "mcu.h" - /*!< @brief Local handle list */ static volatile hal_ll_spi_master_handle_register_t hal_ll_module_state[SPI_MODULE_COUNT] = {(handle_t *)NULL, (handle_t *)NULL, false}; @@ -59,8 +57,6 @@ static volatile hal_ll_spi_master_handle_register_t hal_ll_module_state[SPI_MODU #define hal_ll_spi_master_get_module_state_address ((hal_ll_spi_master_handle_register_t *)*handle) /*!< @brief Helper macro for getting module specific control register structure base address // first register address */ #define hal_ll_spi_master_get_handle (hal_ll_spi_master_handle_register_t *)hal_ll_spi_master_get_module_state_address->hal_ll_spi_master_handle -/*!< @brief Helper macro for getting module specific control register structure */ -#define hal_ll_spi_master_get_base_struct(_handle) ((hal_ll_spi_master_base_handle_t *)_handle) /*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */ #define hal_ll_spi_master_get_base_from_hal_handle ((hal_ll_spi_master_hw_specifics_map_t *)((hal_ll_spi_master_handle_register_t *)\ (((hal_ll_spi_master_handle_register_t *)(handle))->hal_ll_spi_master_handle))->hal_ll_spi_master_handle)->base @@ -262,24 +258,6 @@ static void hal_ll_spi_master_read_bare_metal( hal_ll_spi_master_base_handle_t * */ static void hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, size_t write_data_length ); -/** - * @brief Perform a write then read on the SPI Master bus. - * - * Initializes SPI Master module on hardware level, if not initialized beforehand - * and continues to perform a write operation on the bus. - * - * @param[in] *handle - Object specific context handler. - * @param[in] *write_data_buffer - Pointer to data buffer. - * @param[in] length_write_data - Number of data to be written. - * @param[in] *read_data_buffer - Pointer to data buffer. - * @param[in] length_read_data - Number of data to be read. - * @return hal_ll_err_t Module specific error values. - * - * Returns one of pre-defined error values. - * Take into consideration that this is hardware specific. - */ -hal_ll_err_t hal_ll_spi_master_write_then_read( handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data, uint8_t *read_data_buffer, size_t length_read_data ); - /** * @brief Maps new-found module specific values. * diff --git a/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c b/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c index 3850deae6..cc37b4e2e 100644 --- a/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c +++ b/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c @@ -45,16 +45,11 @@ #include "hal_ll_pmc.h" #include "hal_ll_tim.h" #include "hal_ll_tim_pin_map.h" -#include "mcu.h" /*!< @brief Local handle list */ static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COUNT ]; // ------------------------------------------------------------- PRIVATE MACROS -/*!< @brief Timer counter channel signal. */ -#define HAL_LL_TIOA_CHANNEL_SIGNAL 0 -#define HAL_LL_TIOB_CHANNEL_SIGNAL 1 - /*!< @brief Register bits macros. */ #define HAL_LL_TC_CCR_CLKEN_BIT 0 #define HAL_LL_TC_CCR_CLKDIS_BIT 1 @@ -470,7 +465,7 @@ hal_ll_err_t hal_ll_tim_stop( handle_t *handle ) { hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address ); hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base ); - + // Disable counter. set_reg_bit( &hal_ll_hw_reg->channel[ channel_num ].ccr, HAL_LL_TC_CCR_CLKDIS_BIT ); diff --git a/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c b/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c index c83aa3ece..815df80dc 100644 --- a/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c +++ b/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c @@ -47,7 +47,6 @@ #include "hal_ll_core.h" #include "hal_ll_core_defines.h" #include "hal_ll_uart_pin_map.h" -#include "mcu.h" /*!< @brief Local handle list */ static volatile hal_ll_uart_handle_register_t hal_ll_module_state[UART_MODULE_COUNT + USART_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false }; @@ -373,19 +372,6 @@ static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t */ static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); -/** - * @brief Sets module clock value. - * - * Enables/disables specific UART module - * clock gate. - * - * @param[in] hal_ll_hw_reg - UART HW register structure. - * @param[in] pin_state - true(enable clock) / false(disable clock) - * - * @return void None. - */ -static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); - /** * @brief Sets module TX line state. * @@ -1045,10 +1031,6 @@ static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map uint16_t baud_rate_register_divider = hal_ll_baud_rate_register_divider( map->baud_rate.baud ); uint32_t real_baud_rate = hal_ll_uart_real_baud_rate( baud_rate_register_divider ); - SCB->CPACR |= ((3UL << 20) | (3UL << 22)); - - // float check = (float)(real_baud_rate - map->baud_rate.baud) / (float)map->baud_rate.baud; - // If error greater than specified, cancel setting baud rate. if ( HAL_LL_UART_ACCEPTABLE_ERROR < hal_ll_uart_get_baud_error( real_baud_rate, map->baud_rate.baud )) { map->baud_rate.real_baud = hal_ll_uart_get_baud_error( real_baud_rate, map->baud_rate.baud ); From be7b980a235af6090b0f9cb9485c2bb1988ab41f Mon Sep 17 00:00:00 2001 From: Ivan Ruzavin Date: Mon, 16 Dec 2024 20:44:34 +0100 Subject: [PATCH 28/56] Update targets/arm/mikroe/sam/include/gpio/hal_ll_gpio_port.h Co-authored-by: Strahinja Jacimovic --- targets/arm/mikroe/sam/include/gpio/hal_ll_gpio_port.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/arm/mikroe/sam/include/gpio/hal_ll_gpio_port.h b/targets/arm/mikroe/sam/include/gpio/hal_ll_gpio_port.h index 53b935989..ee06a9859 100644 --- a/targets/arm/mikroe/sam/include/gpio/hal_ll_gpio_port.h +++ b/targets/arm/mikroe/sam/include/gpio/hal_ll_gpio_port.h @@ -63,8 +63,8 @@ extern "C"{ */ typedef struct { - uint32_t pins[13]; - uint8_t configs[13]; + uint32_t pins[13]; + uint8_t configs[13]; } module_struct; /** From 070bd63de91b1549479f841c96a458a5e4f059c7 Mon Sep 17 00:00:00 2001 From: Ivan Ruzavin Date: Mon, 16 Dec 2024 20:45:04 +0100 Subject: [PATCH 29/56] Update targets/arm/mikroe/sam/include/hal_ll_pmc.h Co-authored-by: Strahinja Jacimovic --- targets/arm/mikroe/sam/include/hal_ll_pmc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/arm/mikroe/sam/include/hal_ll_pmc.h b/targets/arm/mikroe/sam/include/hal_ll_pmc.h index 94d7dc56e..e13d296b6 100644 --- a/targets/arm/mikroe/sam/include/hal_ll_pmc.h +++ b/targets/arm/mikroe/sam/include/hal_ll_pmc.h @@ -104,8 +104,8 @@ extern "C"{ */ typedef struct pmc_clocks { - uint32_t mck; // Master clock frequency in Hz - uint32_t pck[8]; // Peripheral clock frequency in Hz + uint32_t mck; // Master clock frequency in Hz + uint32_t pck[8]; // Peripheral clock frequency in Hz } pmc_clocks_t; /** From a8b9eb5a62427de613ed142d61b12248076561cb Mon Sep 17 00:00:00 2001 From: Ivan Ruzavin Date: Mon, 16 Dec 2024 20:45:27 +0100 Subject: [PATCH 30/56] Update targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c Co-authored-by: Strahinja Jacimovic --- .../sam/src/uart/implementations/implementation_1/hal_ll_uart.c | 1 - 1 file changed, 1 deletion(-) diff --git a/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c b/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c index 815df80dc..f2ed18e2c 100644 --- a/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c +++ b/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c @@ -652,7 +652,6 @@ void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq ) { break; #endif - default: break; } From 5b08c063290ad6f32f136e3291810626b247a26b Mon Sep 17 00:00:00 2001 From: Ivan Ruzavin Date: Mon, 16 Dec 2024 20:46:01 +0100 Subject: [PATCH 31/56] Update targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master.h Co-authored-by: Strahinja Jacimovic --- targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master.h b/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master.h index f7dedec8c..978045c5b 100644 --- a/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master.h +++ b/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master.h @@ -66,7 +66,7 @@ typedef struct */ typedef struct { - uint8_t default_write_data; + uint8_t default_write_data; hal_ll_pin_name_t sck; hal_ll_pin_name_t miso; hal_ll_pin_name_t mosi; From 142fa0dde85c09a3f347f3579c1fd189d717859f Mon Sep 17 00:00:00 2001 From: Ivan Ruzavin Date: Mon, 16 Dec 2024 20:46:30 +0100 Subject: [PATCH 32/56] Update targets/arm/mikroe/sam/src/i2c/CMakeLists.txt Co-authored-by: Strahinja Jacimovic --- targets/arm/mikroe/sam/src/i2c/CMakeLists.txt | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/targets/arm/mikroe/sam/src/i2c/CMakeLists.txt b/targets/arm/mikroe/sam/src/i2c/CMakeLists.txt index 16db385fb..92d0773fa 100644 --- a/targets/arm/mikroe/sam/src/i2c/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/i2c/CMakeLists.txt @@ -46,13 +46,13 @@ target_link_libraries(lib_hal_ll_i2c_master PUBLIC string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) target_include_directories(lib_hal_ll_i2c_master PRIVATE - ../../include - ../../include/gpio - ../../include/gpio/${i2c_subimplementation} - # BEGIN I2C - ../../include/i2c - ../../include/i2c/hal_ll_i2c_pin_map/${i2c_subimplementation} - # END I2C + ../../include + ../../include/gpio + ../../include/gpio/${i2c_subimplementation} + # BEGIN I2C + ../../include/i2c + ../../include/i2c/hal_ll_i2c_pin_map/${i2c_subimplementation} + # END I2C INTERFACE $ From e6744fbde118dfa8cbf784893e2887b9eee6a730 Mon Sep 17 00:00:00 2001 From: Ivan Ruzavin Date: Mon, 16 Dec 2024 20:46:40 +0100 Subject: [PATCH 33/56] Update targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c Co-authored-by: Strahinja Jacimovic --- .../sam/src/uart/implementations/implementation_1/hal_ll_uart.c | 1 - 1 file changed, 1 deletion(-) diff --git a/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c b/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c index f2ed18e2c..916ae3dd8 100644 --- a/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c +++ b/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c @@ -729,7 +729,6 @@ void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ) { break; #endif - default: break; } From 073c86172b9ee187c9393e056ca463e74f08e72a Mon Sep 17 00:00:00 2001 From: Ivan Ruzavin Date: Mon, 16 Dec 2024 20:46:45 +0100 Subject: [PATCH 34/56] Update targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c Co-authored-by: Strahinja Jacimovic --- .../sam/src/uart/implementations/implementation_1/hal_ll_uart.c | 1 - 1 file changed, 1 deletion(-) diff --git a/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c b/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c index 916ae3dd8..39410b18a 100644 --- a/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c +++ b/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c @@ -993,7 +993,6 @@ static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal break; #endif - default: break; } From 7fd5924b62b4646ec6ea559c9596d10a175dd8a6 Mon Sep 17 00:00:00 2001 From: Ivan Ruzavin Date: Mon, 16 Dec 2024 20:46:50 +0100 Subject: [PATCH 35/56] Update targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c Co-authored-by: Strahinja Jacimovic --- .../sam/src/uart/implementations/implementation_1/hal_ll_uart.c | 1 - 1 file changed, 1 deletion(-) diff --git a/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c b/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c index 39410b18a..8777f030e 100644 --- a/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c +++ b/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c @@ -1071,7 +1071,6 @@ static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t set_reg_bits( &hal_ll_hw_reg->mr, HAL_LL_UART_MR_DATA_LENGTH_8_BIT_MASK ); break; - default: break; } From 951507a88a91d62066b5103636b10febe63dbea7 Mon Sep 17 00:00:00 2001 From: Ivan Ruzavin Date: Mon, 16 Dec 2024 20:47:06 +0100 Subject: [PATCH 36/56] Update targets/arm/mikroe/sam/src/gpio/CMakeLists.txt Co-authored-by: Strahinja Jacimovic --- targets/arm/mikroe/sam/src/gpio/CMakeLists.txt | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt b/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt index d35dac9ce..a9fb08adc 100644 --- a/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt @@ -42,11 +42,11 @@ target_link_libraries(lib_hal_ll_gpio PUBLIC string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) target_include_directories(lib_hal_ll_gpio PRIVATE - ../../include - # BEGIN GPIO - ../../include/gpio - ../../include/gpio/${gpio_subimplementation} - # END GPIO + ../../include + # BEGIN GPIO + ../../include/gpio + ../../include/gpio/${gpio_subimplementation} + # END GPIO INTERFACE $ From 4405f7db70b925d5513b712d46a8b5440459b88c Mon Sep 17 00:00:00 2001 From: Ivan Ruzavin Date: Mon, 16 Dec 2024 20:47:25 +0100 Subject: [PATCH 37/56] Update targets/arm/mikroe/sam/src/uart/CMakeLists.txt Co-authored-by: Strahinja Jacimovic --- targets/arm/mikroe/sam/src/uart/CMakeLists.txt | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/targets/arm/mikroe/sam/src/uart/CMakeLists.txt b/targets/arm/mikroe/sam/src/uart/CMakeLists.txt index 767bc2d46..613c7a16b 100644 --- a/targets/arm/mikroe/sam/src/uart/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/uart/CMakeLists.txt @@ -38,13 +38,13 @@ target_link_libraries(lib_hal_ll_uart PUBLIC string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) target_include_directories(lib_hal_ll_uart PRIVATE - ../../include - ../../include/gpio - ../../include/gpio/${uart_subimplementation} - # BEGIN UART - ../../include/uart - ../../include/uart/hal_ll_uart_pin_map/${uart_subimplementation} - # END UART + ../../include + ../../include/gpio + ../../include/gpio/${uart_subimplementation} + # BEGIN UART + ../../include/uart + ../../include/uart/hal_ll_uart_pin_map/${uart_subimplementation} + # END UART INTERFACE $ From 72718bc0ede86568b981eb61e1075ff1e2538e73 Mon Sep 17 00:00:00 2001 From: Ivan Ruzavin Date: Mon, 16 Dec 2024 20:47:44 +0100 Subject: [PATCH 38/56] Update targets/arm/mikroe/sam/src/tim/CMakeLists.txt Co-authored-by: Strahinja Jacimovic --- targets/arm/mikroe/sam/src/tim/CMakeLists.txt | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/targets/arm/mikroe/sam/src/tim/CMakeLists.txt b/targets/arm/mikroe/sam/src/tim/CMakeLists.txt index 853de6e6d..74490591c 100644 --- a/targets/arm/mikroe/sam/src/tim/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/tim/CMakeLists.txt @@ -38,13 +38,13 @@ target_link_libraries(lib_hal_ll_tim PUBLIC string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) target_include_directories(lib_hal_ll_tim PRIVATE - ../../include - ../../include/gpio - ../../include/gpio/${tim_subimplementation} - # BEGIN TIM - ../../include/tim - ../../include/tim/hal_ll_tim_pin_map/${tim_subimplementation} - # END TIM + ../../include + ../../include/gpio + ../../include/gpio/${tim_subimplementation} + # BEGIN TIM + ../../include/tim + ../../include/tim/hal_ll_tim_pin_map/${tim_subimplementation} + # END TIM INTERFACE $ From df67c83cc6a1f70c66f5f1c3233ce5071035c056 Mon Sep 17 00:00:00 2001 From: Ivan Ruzavin Date: Mon, 16 Dec 2024 20:47:56 +0100 Subject: [PATCH 39/56] Update targets/arm/mikroe/sam/src/spi_master/CMakeLists.txt Co-authored-by: Strahinja Jacimovic --- .../arm/mikroe/sam/src/spi_master/CMakeLists.txt | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/targets/arm/mikroe/sam/src/spi_master/CMakeLists.txt b/targets/arm/mikroe/sam/src/spi_master/CMakeLists.txt index 77a2d3e83..2c5932551 100644 --- a/targets/arm/mikroe/sam/src/spi_master/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/spi_master/CMakeLists.txt @@ -40,13 +40,13 @@ target_link_libraries(lib_hal_ll_spi_master PUBLIC string(TOLOWER ${mcu_header_path} MCU_HEADER_PATH_LOWER) target_include_directories(lib_hal_ll_spi_master PRIVATE - ../../include - ../../include/gpio - ../../include/gpio/${spi_subimplementation} - # BEGIN SPI - ../../include/spi_master - ../../include/spi_master/hal_ll_spi_master_pin_map/${spi_subimplementation} - # END SPI + ../../include + ../../include/gpio + ../../include/gpio/${spi_subimplementation} + # BEGIN SPI + ../../include/spi_master + ../../include/spi_master/hal_ll_spi_master_pin_map/${spi_subimplementation} + # END SPI INTERFACE $ From 840edefcbe6dd66bd4e1a0b3d0ec5a8a4311e958 Mon Sep 17 00:00:00 2001 From: Ivan Ruzavin Date: Mon, 16 Dec 2024 20:48:24 +0100 Subject: [PATCH 40/56] Update targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c Co-authored-by: Strahinja Jacimovic --- .../sam/src/adc/implementations/implementation_1/hal_ll_adc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c b/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c index 8d2df49bc..bbc2dfdd0 100644 --- a/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c +++ b/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c @@ -264,6 +264,7 @@ hal_ll_err_t hal_ll_adc_register_handle( hal_ll_pin_name_t pin, hal_ll_adc_volta case HAL_LL_ADC_RESOLUTION_16_BIT: hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_AFEC_EMR_OSR256; break; + default: return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; } From 6207c0bbb5b601c0c7ed8c42f56dfa44b5d91f8f Mon Sep 17 00:00:00 2001 From: Ivan Ruzavin Date: Mon, 16 Dec 2024 20:48:39 +0100 Subject: [PATCH 41/56] Update targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c Co-authored-by: Strahinja Jacimovic --- .../sam/src/adc/implementations/implementation_1/hal_ll_adc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c b/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c index bbc2dfdd0..c86dddc94 100644 --- a/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c +++ b/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c @@ -330,6 +330,7 @@ hal_ll_err_t hal_ll_adc_set_resolution( handle_t *handle, hal_ll_adc_resolution_ case HAL_LL_ADC_RESOLUTION_16_BIT: hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_AFEC_EMR_OSR256; break; + default: return HAL_LL_ADC_UNSUPPORTED_RESOLUTION; } From 3eb3147226fa27d31e2083e93cab0c40031bbc77 Mon Sep 17 00:00:00 2001 From: Ivan Ruzavin Date: Mon, 16 Dec 2024 20:50:14 +0100 Subject: [PATCH 42/56] Update targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c Co-authored-by: Strahinja Jacimovic --- .../implementation_1/hal_ll_i2c_master.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c b/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c index fc1f86424..91e4b2351 100644 --- a/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c +++ b/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c @@ -794,14 +794,14 @@ static uint32_t hal_ll_i2c_get_speed( hal_ll_i2c_hw_specifics_map_t *map ) { // High-Speed can be only used in slave mode, 400k is the max speed allowed for master. switch ( map->speed ) { case HAL_LL_I2C_MASTER_SPEED_STANDARD: - i2c_speed = HAL_LL_I2C_MASTER_SPEED_100K; - break; + i2c_speed = HAL_LL_I2C_MASTER_SPEED_100K; + break; case HAL_LL_I2C_MASTER_SPEED_FULL: - i2c_speed = HAL_LL_I2C_MASTER_LOW_DIVIDER_SPEED_LIMIT; - break; + i2c_speed = HAL_LL_I2C_MASTER_LOW_DIVIDER_SPEED_LIMIT; + break; default: - return HAL_LL_I2C_MASTER_ERROR; + return HAL_LL_I2C_MASTER_ERROR; } /* Formula for calculating baud value involves two unknowns. Fix one unknown and calculate the other. From 800dfecc699e4ed6ad639f2c5bfe7d6332dc71d7 Mon Sep 17 00:00:00 2001 From: Ivan Ruzavin Date: Mon, 16 Dec 2024 20:50:38 +0100 Subject: [PATCH 43/56] Update targets/arm/mikroe/sam/src/spi_master/implementations/implementation_1/hal_ll_spi_master.c Co-authored-by: Strahinja Jacimovic --- .../implementations/implementation_1/hal_ll_spi_master.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/arm/mikroe/sam/src/spi_master/implementations/implementation_1/hal_ll_spi_master.c b/targets/arm/mikroe/sam/src/spi_master/implementations/implementation_1/hal_ll_spi_master.c index 2c7fd3218..34dd7c210 100644 --- a/targets/arm/mikroe/sam/src/spi_master/implementations/implementation_1/hal_ll_spi_master.c +++ b/targets/arm/mikroe/sam/src/spi_master/implementations/implementation_1/hal_ll_spi_master.c @@ -472,7 +472,7 @@ static void hal_ll_spi_master_read_bare_metal( hal_ll_spi_master_base_handle_t * // Read the first data to be transmitted into the SPI_DR register. for( transfer_counter = 0; transfer_counter < read_data_length; transfer_counter++ ) { - // If we are good to go ( if the value from shift register has been shifted to the rx register ), read the data. + // If we are good to go ( if the value from shift register has been shifted to the rx register ), read the data. read_data_buffer[ transfer_counter ] = hal_ll_spi_master_transfer_bare_metal( hal_ll_hw_reg, dummy_data ); } } From 595efd14449e5717cfce1e245e54a218436c7936 Mon Sep 17 00:00:00 2001 From: "ivan.ruzavin" Date: Fri, 20 Dec 2024 14:21:29 +0100 Subject: [PATCH 44/56] Fixed according to ARs -> PWM AR is left --- targets/arm/mikroe/sam/CMakeLists.txt | 9 +++ .../implementation_1/hal_ll_adc_pin_map.h | 46 +++++++-------- .../implementation_1/hal_ll_i2c_pin_map.h | 12 ++-- .../hal_ll_spi_master_pin_map.h | 18 +++--- .../implementation_1/hal_ll_tim_pin_map.h | 48 +++++++-------- .../implementation_1/hal_ll_uart_pin_map.h | 40 ++++++------- .../implementation_1/hal_ll_adc.c | 59 ++++++++++--------- .../implementation_1/hal_ll_gpio_port.c | 18 +++--- .../implementation_1/hal_ll_i2c_master.c | 4 +- .../implementation_1/hal_ll_spi_master.c | 28 +++++---- .../implementation_1/hal_ll_tim.c | 31 +++++----- .../implementation_1/hal_ll_uart.c | 4 +- 12 files changed, 167 insertions(+), 150 deletions(-) diff --git a/targets/arm/mikroe/sam/CMakeLists.txt b/targets/arm/mikroe/sam/CMakeLists.txt index 91df5cf37..fb947d30b 100644 --- a/targets/arm/mikroe/sam/CMakeLists.txt +++ b/targets/arm/mikroe/sam/CMakeLists.txt @@ -28,3 +28,12 @@ endif() if (msdk_onewire IN_LIST module_list_supported) add_subdirectory(src/one_wire) endif() +if (msdk_can IN_LIST module_list_supported) + add_subdirectory(src/can) +endif() +if (msdk_dma IN_LIST module_list_supported) + add_subdirectory(src/dma) +endif() +if (msdk_rtc IN_LIST module_list_supported) + add_subdirectory(src/rtc) +endif() diff --git a/targets/arm/mikroe/sam/include/adc/hal_ll_adc_pin_map/implementations/implementation_1/hal_ll_adc_pin_map.h b/targets/arm/mikroe/sam/include/adc/hal_ll_adc_pin_map/implementations/implementation_1/hal_ll_adc_pin_map.h index 2ec11b357..30c41c055 100644 --- a/targets/arm/mikroe/sam/include/adc/hal_ll_adc_pin_map/implementations/implementation_1/hal_ll_adc_pin_map.h +++ b/targets/arm/mikroe/sam/include/adc/hal_ll_adc_pin_map/implementations/implementation_1/hal_ll_adc_pin_map.h @@ -95,73 +95,73 @@ static const hal_ll_base_addr_t HAL_LL_ADC1_BASE_ADDR = 0x40064000; static const hal_ll_adc_pin_map_t _adc_map[] = { #ifdef ADC0_PD30_CH0 - {PD30, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_0}, + {GPIO_PD30, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_0}, #endif #ifdef ADC0_PA21_CH1 - {PA21, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_1}, + {GPIO_PA21, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_1}, #endif #ifdef ADC0_PB3_CH2 - {PB3, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_2}, + {GPIO_PB3, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_2}, #endif #ifdef ADC0_PB2_CH5 - {PB2, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_5}, + {GPIO_PB2, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_5}, #endif #ifdef ADC0_PA17_CH6 - {PA17, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_6}, + {GPIO_PA17, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_6}, #endif #ifdef ADC0_PA18_CH7 - {PA18, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_7}, + {GPIO_PA18, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_7}, #endif #ifdef ADC0_PA19_CH8 - {PA19, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_8}, + {GPIO_PA19, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_8}, #endif #ifdef ADC0_PA20_CH9 - {PA20, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_9}, + {GPIO_PA20, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_9}, #endif #ifdef ADC0_PB0_CH10 - {PB0, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_10}, + {GPIO_PB0, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_10}, #endif #ifdef ADC1_PB1_CH0 - {PB1, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_0}, + {GPIO_PB1, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_0}, #endif #ifdef ADC0_PE5_CH3 - {PE5, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_3}, + {GPIO_PE5, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_3}, #endif #ifdef ADC0_PE4_CH4 - {PE4, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_4}, + {GPIO_PE4, HAL_LL_ADC0_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_4}, #endif #ifdef ADC1_PC13_CH1 - {PC13, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_1}, + {GPIO_PC13, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_1}, #endif #ifdef ADC1_PC15_CH2 - {PC15, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_2}, + {GPIO_PC15, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_2}, #endif #ifdef ADC1_PC12_CH3 - {PC12, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_3}, + {GPIO_PC12, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_3}, #endif #ifdef ADC1_PC29_CH4 - {PC29, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_4}, + {GPIO_PC29, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_4}, #endif #ifdef ADC1_PC30_CH5 - {PC30, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_5}, + {GPIO_PC30, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_5}, #endif #ifdef ADC1_PC31_CH6 - {PC31, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_6}, + {GPIO_PC31, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_6}, #endif #ifdef ADC1_PC26_CH7 - {PC26, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_7}, + {GPIO_PC26, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_7}, #endif #ifdef ADC1_PC27_CH8 - {PC27, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_8}, + {GPIO_PC27, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_8}, #endif #ifdef ADC1_PC0_CH9 - {PC0, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_9}, + {GPIO_PC0, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_9}, #endif #ifdef ADC1_PE3_CH10 - {PE3, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_10}, + {GPIO_PE3, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_10}, #endif #ifdef ADC1_PE0_CH11 - {PE0, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_11}, + {GPIO_PE0, HAL_LL_ADC1_BASE_ADDR, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_11}, #endif {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_CHANNEL_ERROR} diff --git a/targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_pin_map/implementations/implementation_1/hal_ll_i2c_pin_map.h b/targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_pin_map/implementations/implementation_1/hal_ll_i2c_pin_map.h index e82f95289..ebb82948e 100644 --- a/targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_pin_map/implementations/implementation_1/hal_ll_i2c_pin_map.h +++ b/targets/arm/mikroe/sam/include/i2c/hal_ll_i2c_pin_map/implementations/implementation_1/hal_ll_i2c_pin_map.h @@ -76,13 +76,13 @@ typedef struct static const hal_ll_i2c_pin_map_t hal_ll_i2c_scl_map[] = { #ifdef I2C0_SCL_PA4_AFA - {PA4, HAL_LL_I2C0_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_0), 0}, + {GPIO_PA4, HAL_LL_I2C0_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_0), 0}, #endif #ifdef I2C1_SCL_PB5_AFA - {PB5, HAL_LL_I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 0}, + {GPIO_PB5, HAL_LL_I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 0}, #endif #ifdef I2C2_SCL_PD28_AFC - {PD28, HAL_LL_I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 2}, + {GPIO_PD28, HAL_LL_I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 2}, #endif {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} @@ -93,13 +93,13 @@ static const hal_ll_i2c_pin_map_t hal_ll_i2c_scl_map[] = static const hal_ll_i2c_pin_map_t hal_ll_i2c_sda_map[] = { #ifdef I2C0_SDA_PA3_AFA - {PA3, HAL_LL_I2C0_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_0), 0}, + {GPIO_PA3, HAL_LL_I2C0_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_0), 0}, #endif #ifdef I2C1_SDA_PB4_AFA - {PB4, HAL_LL_I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 0}, + {GPIO_PB4, HAL_LL_I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_1), 0}, #endif #ifdef I2C2_SDA_PD27_AFC - {PD27, HAL_LL_I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 2}, + {GPIO_PD27, HAL_LL_I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(I2C_MODULE_2), 2}, #endif {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} diff --git a/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master_pin_map/implementations/implementation_1/hal_ll_spi_master_pin_map.h b/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master_pin_map/implementations/implementation_1/hal_ll_spi_master_pin_map.h index 689a41486..02685190c 100644 --- a/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master_pin_map/implementations/implementation_1/hal_ll_spi_master_pin_map.h +++ b/targets/arm/mikroe/sam/include/spi_master/hal_ll_spi_master_pin_map/implementations/implementation_1/hal_ll_spi_master_pin_map.h @@ -81,13 +81,13 @@ typedef struct static const hal_ll_spi_master_pin_map_t _spi_sck_map[] = { #ifdef SPI0_SCK_PA14_AFA - {PA14, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 0}, + {GPIO_PA14, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 0}, #endif #ifdef SPI0_SCK_PD22_AFB - {PD22, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 1}, + {GPIO_PD22, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 1}, #endif #ifdef SPI1_SCK_PC24_AFC - {PC24, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 2}, + {GPIO_PC24, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 2}, #endif {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} @@ -97,13 +97,13 @@ static const hal_ll_spi_master_pin_map_t _spi_sck_map[] = static const hal_ll_spi_master_pin_map_t _spi_miso_map[] = { #ifdef SPI0_MISO_PA12_AFA - {PA12, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 0}, + {GPIO_PA12, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 0}, #endif #ifdef SPI0_MISO_PD20_AFB - {PD20, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 1}, + {GPIO_PD20, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 1}, #endif #ifdef SPI1_MISO_PC26_AFC - {PC26, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 2}, + {GPIO_PC26, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 2}, #endif {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} @@ -113,13 +113,13 @@ static const hal_ll_spi_master_pin_map_t _spi_miso_map[] = static const hal_ll_spi_master_pin_map_t _spi_mosi_map[] = { #ifdef SPI0_MOSI_PA13_AFA - {PA13, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 0}, + {GPIO_PA13, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 0}, #endif #ifdef SPI0_MOSI_PD21_AFB - {PD21, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 1}, + {GPIO_PD21, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), 1}, #endif #ifdef SPI1_MOSI_PC27_AFC - {PC27, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 2}, + {GPIO_PC27, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), 2}, #endif {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} diff --git a/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/implementation_1/hal_ll_tim_pin_map.h b/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/implementation_1/hal_ll_tim_pin_map.h index f7b95f010..4beb0a627 100644 --- a/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/implementation_1/hal_ll_tim_pin_map.h +++ b/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/implementation_1/hal_ll_tim_pin_map.h @@ -89,76 +89,76 @@ typedef enum /*!< @brief TIM pins. */ static const hal_ll_tim_pin_map_t _tim_map[] = { #ifdef TIM0_CH0_A_PA0_AFB - {PA0, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x01, hal_ll_tim_module_num(TIM_MODULE_0)}, + {GPIO_PA0, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x01, hal_ll_tim_module_num(TIM_MODULE_0)}, #endif #ifdef TIM0_CH1_A_PA15_AFB - {PA15, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x01, hal_ll_tim_module_num(TIM_MODULE_0)}, + {GPIO_PA15, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x01, hal_ll_tim_module_num(TIM_MODULE_0)}, #endif #ifdef TIM0_CH2_A_PA26_AFB - {PA26, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x01, hal_ll_tim_module_num(TIM_MODULE_0)}, + {GPIO_PA26, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x01, hal_ll_tim_module_num(TIM_MODULE_0)}, #endif #ifdef TIM0_CH0_B_PA1_AFB - {PA1, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x11, hal_ll_tim_module_num(TIM_MODULE_0)}, + {GPIO_PA1, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x11, hal_ll_tim_module_num(TIM_MODULE_0)}, #endif #ifdef TIM0_CH1_B_PA16_AFB - {PA16, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x11, hal_ll_tim_module_num(TIM_MODULE_0)}, + {GPIO_PA16, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x11, hal_ll_tim_module_num(TIM_MODULE_0)}, #endif #ifdef TIM0_CH2_B_PA27_AFB - {PA27, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x11, hal_ll_tim_module_num(TIM_MODULE_0)}, + {GPIO_PA27, HAL_LL_TIM0_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x11, hal_ll_tim_module_num(TIM_MODULE_0)}, #endif #ifdef TIM3_CH2_A_PD21_AFC - {PD21, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x02, hal_ll_tim_module_num(TIM_MODULE_3)}, + {GPIO_PD21, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x02, hal_ll_tim_module_num(TIM_MODULE_3)}, #endif #ifdef TIM3_CH2_B_PD22_AFC - {PD22, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x12, hal_ll_tim_module_num(TIM_MODULE_3)}, + {GPIO_PD22, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x12, hal_ll_tim_module_num(TIM_MODULE_3)}, #endif #ifdef TIM1_CH0_A_PC23_AFB - {PC23, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x01, hal_ll_tim_module_num(TIM_MODULE_1)}, + {GPIO_PC23, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x01, hal_ll_tim_module_num(TIM_MODULE_1)}, #endif #ifdef TIM1_CH1_A_PC26_AFB - {PC26, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x01, hal_ll_tim_module_num(TIM_MODULE_1)}, + {GPIO_PC26, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x01, hal_ll_tim_module_num(TIM_MODULE_1)}, #endif #ifdef TIM1_CH2_A_PC29_AFB - {PC29, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x01, hal_ll_tim_module_num(TIM_MODULE_1)}, + {GPIO_PC29, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x01, hal_ll_tim_module_num(TIM_MODULE_1)}, #endif #ifdef TIM1_CH0_B_PC24_AFB - {PC24, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x11, hal_ll_tim_module_num(TIM_MODULE_1)}, + {GPIO_PC24, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x11, hal_ll_tim_module_num(TIM_MODULE_1)}, #endif #ifdef TIM1_CH1_B_PC27_AFB - {PC27, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x11, hal_ll_tim_module_num(TIM_MODULE_1)}, + {GPIO_PC27, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x11, hal_ll_tim_module_num(TIM_MODULE_1)}, #endif #ifdef TIM1_CH2_B_PC30_AFB - {PC30, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x11, hal_ll_tim_module_num(TIM_MODULE_1)}, + {GPIO_PC30, HAL_LL_TIM1_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x11, hal_ll_tim_module_num(TIM_MODULE_1)}, #endif #ifdef TIM2_CH0_A_PC5_AFB - {PC5, HAL_LL_TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x01, hal_ll_tim_module_num(TIM_MODULE_2)}, + {GPIO_PC5, HAL_LL_TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x01, hal_ll_tim_module_num(TIM_MODULE_2)}, #endif #ifdef TIM2_CH1_A_PC8_AFB - {PC8, HAL_LL_TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x01, hal_ll_tim_module_num(TIM_MODULE_2)}, + {GPIO_PC8, HAL_LL_TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x01, hal_ll_tim_module_num(TIM_MODULE_2)}, #endif #ifdef TIM2_CH2_A_PC11_AFB - {PC11, HAL_LL_TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x01, hal_ll_tim_module_num(TIM_MODULE_2)}, + {GPIO_PC11, HAL_LL_TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x01, hal_ll_tim_module_num(TIM_MODULE_2)}, #endif #ifdef TIM2_CH0_B_PC6_AFB - {PC6, HAL_LL_TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x11, hal_ll_tim_module_num(TIM_MODULE_2)}, + {GPIO_PC6, HAL_LL_TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x11, hal_ll_tim_module_num(TIM_MODULE_2)}, #endif #ifdef TIM2_CH1_B_PC9_AFB - {PC9, HAL_LL_TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x11, hal_ll_tim_module_num(TIM_MODULE_2)}, + {GPIO_PC9, HAL_LL_TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x11, hal_ll_tim_module_num(TIM_MODULE_2)}, #endif #ifdef TIM2_CH2_B_PC12_AFB - {PC12, HAL_LL_TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x11, hal_ll_tim_module_num(TIM_MODULE_2)}, + {GPIO_PC12, HAL_LL_TIM2_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_2, 0x11, hal_ll_tim_module_num(TIM_MODULE_2)}, #endif #ifdef TIM3_CH0_A_PE0_AFB - {PE0, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x01, hal_ll_tim_module_num(TIM_MODULE_3)}, + {GPIO_PE0, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x01, hal_ll_tim_module_num(TIM_MODULE_3)}, #endif #ifdef TIM3_CH1_A_PE3_AFB - {PE3, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x01, hal_ll_tim_module_num(TIM_MODULE_3)}, + {GPIO_PE3, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x01, hal_ll_tim_module_num(TIM_MODULE_3)}, #endif #ifdef TIM3_CH0_B_PE1_AFB - {PE1, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x11, hal_ll_tim_module_num(TIM_MODULE_3)}, + {GPIO_PE1, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_0, 0x11, hal_ll_tim_module_num(TIM_MODULE_3)}, #endif #ifdef TIM3_CH1_B_PE4_AFB - {PE4, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x11, hal_ll_tim_module_num(TIM_MODULE_3)}, + {GPIO_PE4, HAL_LL_TIM3_BASE_ADDRESS, HAL_LL_TIM_CHANNEL_1, 0x11, hal_ll_tim_module_num(TIM_MODULE_3)}, #endif { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_CHANNEL_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC } diff --git a/targets/arm/mikroe/sam/include/uart/hal_ll_uart_pin_map/implementations/implementation_1/hal_ll_uart_pin_map.h b/targets/arm/mikroe/sam/include/uart/hal_ll_uart_pin_map/implementations/implementation_1/hal_ll_uart_pin_map.h index 0ba0d04eb..fb293ca59 100644 --- a/targets/arm/mikroe/sam/include/uart/hal_ll_uart_pin_map/implementations/implementation_1/hal_ll_uart_pin_map.h +++ b/targets/arm/mikroe/sam/include/uart/hal_ll_uart_pin_map/implementations/implementation_1/hal_ll_uart_pin_map.h @@ -92,40 +92,40 @@ typedef struct static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = { #ifdef USART0_TX_PB1_AFC - {hal_ll_usart_module_num(USART_MODULE_0), PB1, HAL_LL_USART0_BASE_ADDRESS, 2}, + {hal_ll_usart_module_num(USART_MODULE_0), GPIO_PB1, HAL_LL_USART0_BASE_ADDRESS, 2}, #endif #ifdef USART1_TX_PB4_AFD - {hal_ll_usart_module_num(USART_MODULE_1), PB4, HAL_LL_USART1_BASE_ADDRESS, 3}, + {hal_ll_usart_module_num(USART_MODULE_1), GPIO_PB4, HAL_LL_USART1_BASE_ADDRESS, 3}, #endif #ifdef USART2_TX_PD16_AFB - {hal_ll_usart_module_num(USART_MODULE_2), PD16, HAL_LL_USART2_BASE_ADDRESS, 1}, + {hal_ll_usart_module_num(USART_MODULE_2), GPIO_PD16, HAL_LL_USART2_BASE_ADDRESS, 1}, #endif #ifdef UART0_TX_PA10_AFA - {hal_ll_uart_module_num(UART_MODULE_0), PA10, HAL_LL_UART0_BASE_ADDRESS, 0}, + {hal_ll_uart_module_num(UART_MODULE_0), GPIO_PA10, HAL_LL_UART0_BASE_ADDRESS, 0}, #endif #ifdef UART1_TX_PA4_AFC - {hal_ll_uart_module_num(UART_MODULE_1), PA4, HAL_LL_UART1_BASE_ADDRESS, 2}, + {hal_ll_uart_module_num(UART_MODULE_1), GPIO_PA4, HAL_LL_UART1_BASE_ADDRESS, 2}, #endif #ifdef UART1_TX_PA6_AFC - {hal_ll_uart_module_num(UART_MODULE_1), PA6, HAL_LL_UART1_BASE_ADDRESS, 2}, + {hal_ll_uart_module_num(UART_MODULE_1), GPIO_PA6, HAL_LL_UART1_BASE_ADDRESS, 2}, #endif #ifdef UART1_TX_PD26_AFD - {hal_ll_uart_module_num(UART_MODULE_1), PD26, HAL_LL_UART1_BASE_ADDRESS, 3}, + {hal_ll_uart_module_num(UART_MODULE_1), GPIO_PD26, HAL_LL_UART1_BASE_ADDRESS, 3}, #endif #ifdef UART2_TX_PD26_AFC - {hal_ll_uart_module_num(UART_MODULE_2), PD26, HAL_LL_UART2_BASE_ADDRESS, 2}, + {hal_ll_uart_module_num(UART_MODULE_2), GPIO_PD26, HAL_LL_UART2_BASE_ADDRESS, 2}, #endif #ifdef UART3_TX_PD30_AFA - {hal_ll_uart_module_num(UART_MODULE_3), PD30, HAL_LL_UART3_BASE_ADDRESS, 0}, + {hal_ll_uart_module_num(UART_MODULE_3), GPIO_PD30, HAL_LL_UART3_BASE_ADDRESS, 0}, #endif #ifdef UART3_TX_PD31_AFB - {hal_ll_uart_module_num(UART_MODULE_3), PD31, HAL_LL_UART3_BASE_ADDRESS, 1}, + {hal_ll_uart_module_num(UART_MODULE_3), GPIO_PD31, HAL_LL_UART3_BASE_ADDRESS, 1}, #endif #ifdef UART4_TX_PD3_AFC - {hal_ll_uart_module_num(UART_MODULE_4), PD3, HAL_LL_UART4_BASE_ADDRESS, 2}, + {hal_ll_uart_module_num(UART_MODULE_4), GPIO_PD3, HAL_LL_UART4_BASE_ADDRESS, 2}, #endif #ifdef UART4_TX_PD19_AFC - {hal_ll_uart_module_num(UART_MODULE_4), PD19, HAL_LL_UART4_BASE_ADDRESS, 2}, + {hal_ll_uart_module_num(UART_MODULE_4), GPIO_PD19, HAL_LL_UART4_BASE_ADDRESS, 2}, #endif {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} @@ -135,28 +135,28 @@ static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = { #ifdef USART0_RX_PB0_AFC - {hal_ll_usart_module_num(USART_MODULE_0), PB0, HAL_LL_USART0_BASE_ADDRESS, 2}, + {hal_ll_usart_module_num(USART_MODULE_0), GPIO_PB0, HAL_LL_USART0_BASE_ADDRESS, 2}, #endif #ifdef USART1_RX_PA21_AFA - {hal_ll_usart_module_num(USART_MODULE_1), PA21, HAL_LL_USART1_BASE_ADDRESS, 0}, + {hal_ll_usart_module_num(USART_MODULE_1), GPIO_PA21, HAL_LL_USART1_BASE_ADDRESS, 0}, #endif #ifdef USART2_RX_PD15_AFB - {hal_ll_usart_module_num(USART_MODULE_2), PD15, HAL_LL_USART2_BASE_ADDRESS, 1}, + {hal_ll_usart_module_num(USART_MODULE_2), GPIO_PD15, HAL_LL_USART2_BASE_ADDRESS, 1}, #endif #ifdef UART0_RX_PA9_AFA - {hal_ll_uart_module_num(UART_MODULE_0), PA9, HAL_LL_UART0_BASE_ADDRESS, 0}, + {hal_ll_uart_module_num(UART_MODULE_0), GPIO_PA9, HAL_LL_UART0_BASE_ADDRESS, 0}, #endif #ifdef UART1_RX_PA5_AFC - {hal_ll_uart_module_num(UART_MODULE_1), PA5, HAL_LL_UART1_BASE_ADDRESS, 2}, + {hal_ll_uart_module_num(UART_MODULE_1), GPIO_PA5, HAL_LL_UART1_BASE_ADDRESS, 2}, #endif #ifdef UART2_RX_PD25_AFC - {hal_ll_uart_module_num(UART_MODULE_2), PD25, HAL_LL_UART2_BASE_ADDRESS, 2}, + {hal_ll_uart_module_num(UART_MODULE_2), GPIO_PD25, HAL_LL_UART2_BASE_ADDRESS, 2}, #endif #ifdef UART3_RX_PD28_AFA - {hal_ll_uart_module_num(UART_MODULE_3), PD28, HAL_LL_UART3_BASE_ADDRESS, 0}, + {hal_ll_uart_module_num(UART_MODULE_3), GPIO_PD28, HAL_LL_UART3_BASE_ADDRESS, 0}, #endif #ifdef UART4_RX_PD18_AFC - {hal_ll_uart_module_num(UART_MODULE_4), PD18, HAL_LL_UART4_BASE_ADDRESS, 2}, + {hal_ll_uart_module_num(UART_MODULE_4), GPIO_PD18, HAL_LL_UART4_BASE_ADDRESS, 2}, #endif {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} diff --git a/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c b/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c index c86dddc94..28894a797 100644 --- a/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c +++ b/targets/arm/mikroe/sam/src/adc/implementations/implementation_1/hal_ll_adc.c @@ -110,38 +110,38 @@ typedef enum /*!< @brief AFEC register structure. */ typedef struct { - uint32_t cr; /**< (AFEC Offset: 0x00) AFEC Control Register */ - uint32_t mr; /**< (AFEC Offset: 0x04) AFEC Mode Register */ - uint32_t emr; /**< (AFEC Offset: 0x08) AFEC Extended Mode Register */ - uint32_t seq1r; /**< (AFEC Offset: 0x0C) AFEC Channel Sequence 1 Register */ - uint32_t seq2r; /**< (AFEC Offset: 0x10) AFEC Channel Sequence 2 Register */ - uint32_t cher; /**< (AFEC Offset: 0x14) AFEC Channel Enable Register */ - uint32_t chdr; /**< (AFEC Offset: 0x18) AFEC Channel Disable Register */ - uint32_t chsr; /**< (AFEC Offset: 0x1C) AFEC Channel Status Register */ - uint32_t lcdr; /**< (AFEC Offset: 0x20) AFEC Last Converted Data Register */ - uint32_t ier; /**< (AFEC Offset: 0x24) AFEC Interrupt Enable Register */ - uint32_t idr; /**< (AFEC Offset: 0x28) AFEC Interrupt Disable Register */ - uint32_t imr; /**< (AFEC Offset: 0x2C) AFEC Interrupt Mask Register */ - uint32_t isr; /**< (AFEC Offset: 0x30) AFEC Interrupt Status Register */ - uint32_t _unused1[6]; /** Reserved 0x34 - 0x4B **/ - uint32_t over; /**< (AFEC Offset: 0x4C) AFEC Overrun Status Register */ - uint32_t cwr; /**< (AFEC Offset: 0x50) AFEC Compare Window Register */ - uint32_t cgr; /**< (AFEC Offset: 0x54) AFEC Channel Gain Register */ - uint32_t _unused2[2]; /** Reserved 0x58 - 0x5F **/ - uint32_t diffr; /**< (AFEC Offset: 0x60) AFEC Channel Differential Register */ - uint32_t cselr; /**< (AFEC Offset: 0x64) AFEC Channel Selection Register */ - uint32_t cdr; /**< (AFEC Offset: 0x68) AFEC Channel Data Register */ - uint32_t cocr; /**< (AFEC Offset: 0x6C) AFEC Channel Offset Compensation Register */ - uint32_t tempmr; /**< (AFEC Offset: 0x70) AFEC Temperature Sensor Mode Register */ - uint32_t tempcwr; /**< (AFEC Offset: 0x74) AFEC Temperature Compare Window Register */ - uint32_t _unused3[7]; /** Reserved 0x78 - 0x93 **/ - uint32_t acr; /**< (AFEC Offset: 0x94) AFEC Analog Control Register */ + hal_ll_base_addr_t cr; /**< (AFEC Offset: 0x00) AFEC Control Register */ + hal_ll_base_addr_t mr; /**< (AFEC Offset: 0x04) AFEC Mode Register */ + hal_ll_base_addr_t emr; /**< (AFEC Offset: 0x08) AFEC Extended Mode Register */ + hal_ll_base_addr_t seq1r; /**< (AFEC Offset: 0x0C) AFEC Channel Sequence 1 Register */ + hal_ll_base_addr_t seq2r; /**< (AFEC Offset: 0x10) AFEC Channel Sequence 2 Register */ + hal_ll_base_addr_t cher; /**< (AFEC Offset: 0x14) AFEC Channel Enable Register */ + hal_ll_base_addr_t chdr; /**< (AFEC Offset: 0x18) AFEC Channel Disable Register */ + hal_ll_base_addr_t chsr; /**< (AFEC Offset: 0x1C) AFEC Channel Status Register */ + hal_ll_base_addr_t lcdr; /**< (AFEC Offset: 0x20) AFEC Last Converted Data Register */ + hal_ll_base_addr_t ier; /**< (AFEC Offset: 0x24) AFEC Interrupt Enable Register */ + hal_ll_base_addr_t idr; /**< (AFEC Offset: 0x28) AFEC Interrupt Disable Register */ + hal_ll_base_addr_t imr; /**< (AFEC Offset: 0x2C) AFEC Interrupt Mask Register */ + hal_ll_base_addr_t isr; /**< (AFEC Offset: 0x30) AFEC Interrupt Status Register */ + hal_ll_base_addr_t _unused1[6]; /** Reserved 0x34 - 0x4B **/ + hal_ll_base_addr_t over; /**< (AFEC Offset: 0x4C) AFEC Overrun Status Register */ + hal_ll_base_addr_t cwr; /**< (AFEC Offset: 0x50) AFEC Compare Window Register */ + hal_ll_base_addr_t cgr; /**< (AFEC Offset: 0x54) AFEC Channel Gain Register */ + hal_ll_base_addr_t _unused2[2]; /** Reserved 0x58 - 0x5F **/ + hal_ll_base_addr_t diffr; /**< (AFEC Offset: 0x60) AFEC Channel Differential Register */ + hal_ll_base_addr_t cselr; /**< (AFEC Offset: 0x64) AFEC Channel Selection Register */ + hal_ll_base_addr_t cdr; /**< (AFEC Offset: 0x68) AFEC Channel Data Register */ + hal_ll_base_addr_t cocr; /**< (AFEC Offset: 0x6C) AFEC Channel Offset Compensation Register */ + hal_ll_base_addr_t tempmr; /**< (AFEC Offset: 0x70) AFEC Temperature Sensor Mode Register */ + hal_ll_base_addr_t tempcwr; /**< (AFEC Offset: 0x74) AFEC Temperature Compare Window Register */ + hal_ll_base_addr_t _unused3[7]; /** Reserved 0x78 - 0x93 **/ + hal_ll_base_addr_t acr; /**< (AFEC Offset: 0x94) AFEC Analog Control Register */ } hal_ll_adc_base_handle_t; /*!< @brief ADC hw specific module values */ typedef struct { - uint16_t pin_an[ADC_MODULE_COUNT]; + hal_ll_pin_name_t pin_an[ADC_MODULE_COUNT]; } hal_ll_adc_pin_id; static hal_ll_adc_hw_specifics_map_t hal_ll_adc_hw_specifics_map[] = @@ -243,7 +243,7 @@ static void _hal_ll_adc_hw_init( hal_ll_adc_base_handle_t *base, uint32_t resolu // ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS hal_ll_err_t hal_ll_adc_register_handle( hal_ll_pin_name_t pin, hal_ll_adc_voltage_reference_t vref_input, hal_ll_adc_resolution_t resolution, hal_ll_adc_handle_register_t *handle_map, uint8_t *hal_module_id ) { - uint16_t pin_check_result; + hal_ll_pin_name_t pin_check_result; hal_ll_adc_pin_id index = {HAL_LL_PIN_NC}; if ( ( pin_check_result = hal_ll_adc_check_pins( pin, &index, handle_map ) ) == HAL_LL_PIN_NC ) { @@ -496,6 +496,9 @@ static void _hal_ll_adc_enable_clock( uint8_t module_index ) adc1_enable_clock(); break; #endif + + default: + break; } } diff --git a/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c b/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c index 5bcb10e65..dcdb2fb75 100644 --- a/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c +++ b/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c @@ -85,7 +85,7 @@ /*!< @brief GPIO PORT array */ -static const uint32_t _hal_ll_gpio_port_base [ 5 ] = +static const hal_ll_base_addr_t _hal_ll_gpio_port_base [ PORT_COUNT ] = { #ifdef __PORT_A_CN HAL_LL_GPIOA_BASE_ADDR, @@ -156,12 +156,12 @@ uint8_t hal_ll_gpio_port_index( hal_ll_pin_name_t name ) return ( hal_ll_port_name_t )name / PORT_SIZE; } -uint32_t hal_ll_gpio_pin_mask( hal_ll_pin_name_t name ) +hal_ll_gpio_mask_t hal_ll_gpio_pin_mask( hal_ll_pin_name_t name ) { - return ( ( uint32_t )0x01 << hal_ll_gpio_pin_index( name ) ); + return ( ( hal_ll_gpio_mask_t )0x01 << hal_ll_gpio_pin_index( name ) ); } -uint32_t hal_ll_gpio_port_base( hal_ll_port_name_t name ) +hal_ll_base_addr_t hal_ll_gpio_port_base( hal_ll_port_name_t name ) { return _hal_ll_gpio_port_base[ name ]; } @@ -200,9 +200,9 @@ void hal_ll_gpio_module_struct_init( module_struct const *module, bool state ) */ static void hal_ll_gpio_clock_enable( hal_ll_gpio_base_t *port ) { - uint32_t pos = 0; + hal_ll_gpio_mask_t pos = 0; - switch ( ( uint32_t )port ) + switch ( ( hal_ll_base_addr_t )port ) { #ifdef __PORT_A_CN case HAL_LL_GPIOA_BASE_ADDR: pos = HAL_LL_PMC_ID_PIOA_BIT; break; @@ -227,9 +227,9 @@ static void hal_ll_gpio_clock_enable( hal_ll_gpio_base_t *port ) static void hal_ll_gpio_config( hal_ll_gpio_base_t *port, hal_ll_gpio_mask_t pin_mask, uint32_t config ) { uint8_t pin_num = 0; - uint32_t pin_pos = 0; - uint32_t current_pin = 0; - uint32_t port_base = 0; + hal_ll_gpio_mask_t pin_pos = 0; + hal_ll_gpio_mask_t current_pin = 0; + hal_ll_base_addr_t port_base = 0; hal_ll_gpio_base_handle_t *port_ptr; diff --git a/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c b/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c index 91e4b2351..3a2b48c34 100644 --- a/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c +++ b/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c @@ -129,8 +129,8 @@ typedef struct /*!< @brief I2C hw specific module values */ typedef struct { - uint16_t pin_scl; - uint16_t pin_sda; + hal_ll_pin_name_t pin_scl; + hal_ll_pin_name_t pin_sda; } hal_ll_i2c_pin_id; /*!< @brief I2C hw specific error values */ diff --git a/targets/arm/mikroe/sam/src/spi_master/implementations/implementation_1/hal_ll_spi_master.c b/targets/arm/mikroe/sam/src/spi_master/implementations/implementation_1/hal_ll_spi_master.c index 34dd7c210..1c2bb14b9 100644 --- a/targets/arm/mikroe/sam/src/spi_master/implementations/implementation_1/hal_ll_spi_master.c +++ b/targets/arm/mikroe/sam/src/spi_master/implementations/implementation_1/hal_ll_spi_master.c @@ -91,18 +91,18 @@ static volatile hal_ll_spi_master_handle_register_t hal_ll_module_state[SPI_MODU /*!< @brief SPI register structure. */ typedef struct { - uint32_t cr; - uint32_t mr; - uint32_t rdr; - uint32_t tdr; - uint32_t sr; - uint32_t ier; - uint32_t idr; - uint32_t imr; + hal_ll_base_addr_t cr; + hal_ll_base_addr_t mr; + hal_ll_base_addr_t rdr; + hal_ll_base_addr_t tdr; + hal_ll_base_addr_t sr; + hal_ll_base_addr_t ier; + hal_ll_base_addr_t idr; + hal_ll_base_addr_t imr; #ifndef QSPI_SPI - uint32_t _unused[4]; + hal_ll_base_addr_t _unused[4]; #endif - uint32_t csr; + hal_ll_base_addr_t csr; } hal_ll_spi_master_base_handle_t; /*!< @brief SPI Master hardware specific structure */ @@ -119,9 +119,9 @@ typedef struct { /*!< @brief SPI hw specific module values */ typedef struct { - uint16_t pin_sck; - uint16_t pin_miso; - uint16_t pin_mosi; + hal_ll_pin_name_t pin_sck; + hal_ll_pin_name_t pin_miso; + hal_ll_pin_name_t pin_mosi; } hal_ll_spi_pin_id; /*!< @brief SPI Master hw specific error values */ @@ -570,6 +570,8 @@ static void hal_ll_spi_master_set_clock( hal_ll_spi_master_hw_specifics_map_t *m break; #endif + default: + break; } *clock_value = hal_ll_get_system_clock; diff --git a/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c b/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c index cc37b4e2e..a043b5bdd 100644 --- a/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c +++ b/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c @@ -103,20 +103,20 @@ static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COU /*!< @brief TIM channel register ctructure. */ typedef struct { - uint32_t ccr; - uint32_t cmr; - uint32_t smmr; - uint32_t rab; - uint32_t cv; - uint32_t ra; - uint32_t rb; - uint32_t rc; - uint32_t sr; - uint32_t ier; - uint32_t idr; - uint32_t imr; - uint32_t emr; - uint32_t _unused[3]; + hal_ll_base_addr_t ccr; + hal_ll_base_addr_t cmr; + hal_ll_base_addr_t smmr; + hal_ll_base_addr_t rab; + hal_ll_base_addr_t cv; + hal_ll_base_addr_t ra; + hal_ll_base_addr_t rb; + hal_ll_base_addr_t rc; + hal_ll_base_addr_t sr; + hal_ll_base_addr_t ier; + hal_ll_base_addr_t idr; + hal_ll_base_addr_t imr; + hal_ll_base_addr_t emr; + hal_ll_base_addr_t _unused[3]; } hal_ll_tim_channel_handle_t; /*!< @brief TIM register structure. */ @@ -666,6 +666,9 @@ static void _hal_ll_tim_set_clock( hal_ll_tim_hw_specifics_map_t *map, bool hal_ _hal_ll_tim3_set_clock( map->config.channel, hal_ll_state ); break; #endif + + default: + break; } } diff --git a/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c b/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c index 8777f030e..4452a1f58 100644 --- a/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c +++ b/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c @@ -157,8 +157,8 @@ typedef struct /*!< @brief UART hw specific module values */ typedef struct { - uint16_t pin_tx; - uint16_t pin_rx; + hal_ll_pin_name_t pin_tx; + hal_ll_pin_name_t pin_rx; } hal_ll_uart_pin_id; /*!< @brief UART hw specific error values */ From b7c08a292161769e1122782cc300960b8b3633a7 Mon Sep 17 00:00:00 2001 From: "ivan.ruzavin" Date: Fri, 20 Dec 2024 15:05:02 +0100 Subject: [PATCH 45/56] Updated TIM implementaion -> testing required --- .../implementation_1/hal_ll_tim.c | 37 ++++++++++--------- 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c b/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c index a043b5bdd..21a938c31 100644 --- a/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c +++ b/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c @@ -348,6 +348,9 @@ hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle ) { _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + if ( HAL_LL_TIM_MODULE_ERROR == hal_ll_tim_hw_specifics_map_local->max_period ) + return HAL_LL_TIM_MODULE_ERROR; + hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = ( handle_t *)&hal_ll_tim_hw_specifics_map[ pin_check_result ].base; hal_ll_module_state[ pin_check_result ].init_ll_state = true; hal_handle->init_ll_state = true; @@ -387,6 +390,9 @@ uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz ) { _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local ); + if ( HAL_LL_TIM_MODULE_ERROR == hal_ll_tim_hw_specifics_map_local->max_period ) + return HAL_LL_TIM_MODULE_ERROR; + low_level_handle->init_ll_state = true; return tmp_freq; @@ -701,29 +707,24 @@ static uint32_t _hal_ll_tim_get_clock_speed( hal_ll_tim_hw_specifics_map_t *map if ( UINT16_MAX < hal_ll_get_system_clock / map->freq_hz ) { if ( UINT16_MAX < hal_ll_tim_timer_clock_2 / map->freq_hz ) { if ( UINT16_MAX < hal_ll_tim_timer_clock_3 / map->freq_hz ) { - if ( UINT16_MAX < hal_ll_tim_timer_clock_4 / map->freq_hz ) { + if ( UINT16_MAX < hal_ll_tim_timer_clock_4 / map->freq_hz ) // Clock divider can't be more than 16-bit field can handle. return HAL_LL_TIM_MODULE_ERROR; - } else { - // Set TIM clock to be FOSC / 128. - set_reg_bits( &hal_ll_hw_reg->channel[ channel_num ].cmr, HAL_LL_TC_CMR_TIMER_CLOCK4_MASK ); - return hal_ll_tim_timer_clock_4; - } - } else { - // Set TIM clock to be FOSC / 32. - set_reg_bits( &hal_ll_hw_reg->channel[ channel_num ].cmr, HAL_LL_TC_CMR_TIMER_CLOCK3_MASK ); - return hal_ll_tim_timer_clock_3; + // Set TIM clock to be FOSC / 128. + set_reg_bits( &hal_ll_hw_reg->channel[ channel_num ].cmr, HAL_LL_TC_CMR_TIMER_CLOCK4_MASK ); + return hal_ll_tim_timer_clock_4; } - } else { - // Set TIM clock to be FOSC / 8. - set_reg_bits( &hal_ll_hw_reg->channel[ channel_num ].cmr, HAL_LL_TC_CMR_TIMER_CLOCK2_MASK ); - return hal_ll_tim_timer_clock_2; + // Set TIM clock to be FOSC / 32. + set_reg_bits( &hal_ll_hw_reg->channel[ channel_num ].cmr, HAL_LL_TC_CMR_TIMER_CLOCK3_MASK ); + return hal_ll_tim_timer_clock_3; } - } else { - // Set TIM clock to be FOSC. - set_reg_bit( &hal_ll_hw_reg->channel[ channel_num ].emr, HAL_LL_TC_EMR_NODIVCLK_BIT ); - return hal_ll_get_system_clock; + // Set TIM clock to be FOSC / 8. + set_reg_bits( &hal_ll_hw_reg->channel[ channel_num ].cmr, HAL_LL_TC_CMR_TIMER_CLOCK2_MASK ); + return hal_ll_tim_timer_clock_2; } + // Set TIM clock to be FOSC. + set_reg_bit( &hal_ll_hw_reg->channel[ channel_num ].emr, HAL_LL_TC_EMR_NODIVCLK_BIT ); + return hal_ll_get_system_clock; } static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { From b11e036b284271c1af770a7ddd98accb49e82d36 Mon Sep 17 00:00:00 2001 From: strahi-linux Date: Mon, 23 Dec 2024 09:02:54 +0100 Subject: [PATCH 46/56] Fixed header inclusion for LVGL fonts --- thirdparty/lvgl/CMakeLists.txt | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/thirdparty/lvgl/CMakeLists.txt b/thirdparty/lvgl/CMakeLists.txt index 2e9187332..5495428a9 100644 --- a/thirdparty/lvgl/CMakeLists.txt +++ b/thirdparty/lvgl/CMakeLists.txt @@ -19,10 +19,10 @@ if(${ENOUGH_MEMORY}) # 128KB RAM # 512KB FLASH message(INFO "LVGL: HEAVY CONFIGURATION") - set(LV_CONF_PATH "${CMAKE_CURRENT_LIST_DIR}/lv_conf/heavy/lv_conf.h") + set(LV_CONF_PATH "${CMAKE_CURRENT_SOURCE_DIR}/lv_conf/heavy/lv_conf.h") else() message(INFO "LVGL: LIGHT CONFIGURATION") - set(LV_CONF_PATH "${CMAKE_CURRENT_LIST_DIR}/lv_conf/light/lv_conf.h") + set(LV_CONF_PATH "${CMAKE_CURRENT_SOURCE_DIR}/lv_conf/light/lv_conf.h") endif() get_filename_component(LV_CONF_DIR ${LV_CONF_PATH} DIRECTORY) @@ -46,11 +46,12 @@ endif() target_compile_definitions(lvgl PUBLIC - LV_CONF_PATH=${LV_CONF_PATH} + $<$:LV_LVGL_H_INCLUDE_SIMPLE> + $<$:LV_CONF_INCLUDE_SIMPLE> ) # Lbrary and headers can be installed to system using make install. -file(GLOB LVGL_PUBLIC_HEADERS "${CMAKE_CURRENT_SOURCE_DIR}/lv_conf.h" "${CMAKE_CURRENT_SOURCE_DIR}/lvgl.h") +file(GLOB LVGL_PUBLIC_HEADERS "${LV_CONF_PATH}" "${CMAKE_CURRENT_SOURCE_DIR}/lvgl.h") target_include_directories(lvgl PUBLIC From 55facb7da463d25e7805cbd9f212b714960ff6bc Mon Sep 17 00:00:00 2001 From: "ivan.ruzavin" Date: Mon, 23 Dec 2024 10:35:53 +0100 Subject: [PATCH 47/56] Added gpio macros for defining the analog/digital pin state --- .../sam/include/gpio/hal_ll_gpio_port.h | 1 + .../implementation_1/hal_ll_gpio_constants.h | 67 +++++++++++++++++++ .../arm/mikroe/sam/src/gpio/CMakeLists.txt | 3 +- .../implementation_1/hal_ll_gpio_port.c | 24 +++---- 4 files changed, 82 insertions(+), 13 deletions(-) create mode 100644 targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_constants.h diff --git a/targets/arm/mikroe/sam/include/gpio/hal_ll_gpio_port.h b/targets/arm/mikroe/sam/include/gpio/hal_ll_gpio_port.h index ee06a9859..2f63ac7bb 100644 --- a/targets/arm/mikroe/sam/include/gpio/hal_ll_gpio_port.h +++ b/targets/arm/mikroe/sam/include/gpio/hal_ll_gpio_port.h @@ -49,6 +49,7 @@ extern "C"{ #endif #include "hal_ll_target.h" +#include "hal_ll_gpio_constants.h" #include "hal_ll_gpio_struct_type.h" #define RESET_PINS_OFFSET 32 diff --git a/targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_constants.h b/targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_constants.h new file mode 100644 index 000000000..7afb892e5 --- /dev/null +++ b/targets/arm/mikroe/sam/include/gpio/implementations/implementation_1/hal_ll_gpio_constants.h @@ -0,0 +1,67 @@ +/**************************************************************************** +** +** Copyright (C) ${COPYRIGHT_YEAR} MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** This file is part of the mikroSDK package +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file hal_ll_gpio_constants.h + * @brief GPIO HAL LL macros. + */ + +#ifndef _HAL_LL_GPIO_CONSTANTS_H_ +#define _HAL_LL_GPIO_CONSTANTS_H_ + +#ifdef __cplusplus +extern "C"{ +#endif + +// Predefined macros +#ifndef GPIO_CFG_MODE_ANALOG +#define GPIO_CFG_MODE_ANALOG 0x1 +#endif +#ifndef GPIO_CFG_MODE_INPUT +#define GPIO_CFG_MODE_INPUT 0x2 +#endif +#ifndef GPIO_CFG_MODE_OUTPUT +#define GPIO_CFG_MODE_OUTPUT 0x4 +#endif + +#ifdef __cplusplus +} +#endif + +#endif // _HAL_LL_GPIO_CONSTANTS_H_ +// ------------------------------------------------------------------------- END \ No newline at end of file diff --git a/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt b/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt index a9fb08adc..ebc1bf0a8 100644 --- a/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt +++ b/targets/arm/mikroe/sam/src/gpio/CMakeLists.txt @@ -24,6 +24,7 @@ mikrosdk_add_library(lib_hal_ll_gpio MikroSDK.HalLowLevel.GPIO # BEGIN GPIO ../../include/gpio/hal_ll_gpio.h ../../include/gpio/hal_ll_gpio_port.h + ../../include/gpio/${gpio_subimplementation}/hal_ll_gpio_constants.h ../../include/gpio/${gpio_subimplementation}/hal_ll_gpio_struct_type.h # END GPIO @@ -57,4 +58,4 @@ target_include_directories(lib_hal_ll_gpio ) mikrosdk_install(MikroSDK.HalLowLevel.GPIO) -install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.GPIO ../../include/gpio/hal_ll_gpio.h ../../include/gpio/${gpio_subimplementation}/hal_ll_gpio_struct_type.h ../../include/gpio/hal_ll_gpio_port.h) +install_headers(${CMAKE_INSTALL_PREFIX}/include/hal_ll_port MikroSDK.HalLowLevel.GPIO ../../include/gpio/hal_ll_gpio.h ../../include/gpio/${gpio_subimplementation}/hal_ll_gpio_constants.h ../../include/gpio/${gpio_subimplementation}/hal_ll_gpio_struct_type.h ../../include/gpio/hal_ll_gpio_port.h) diff --git a/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c b/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c index dcdb2fb75..e633ec481 100644 --- a/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c +++ b/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c @@ -114,7 +114,7 @@ static const hal_ll_base_addr_t _hal_ll_gpio_port_base [ PORT_COUNT ] = * @param[in] config - pin settings * @return none */ -static void hal_ll_gpio_config( hal_ll_gpio_base_t *port, hal_ll_gpio_mask_t pin_mask, uint32_t config ); +static void hal_ll_gpio_config( hal_ll_gpio_base_t *port, hal_ll_gpio_mask_t pin_mask, uint8_t config ); /** * @brief Configure pin that has analog function. @@ -224,7 +224,7 @@ static void hal_ll_gpio_clock_enable( hal_ll_gpio_base_t *port ) set_reg_bit( _PMC_PCER0, pos ); } -static void hal_ll_gpio_config( hal_ll_gpio_base_t *port, hal_ll_gpio_mask_t pin_mask, uint32_t config ) +static void hal_ll_gpio_config( hal_ll_gpio_base_t *port, hal_ll_gpio_mask_t pin_mask, uint8_t config ) { uint8_t pin_num = 0; hal_ll_gpio_mask_t pin_pos = 0; @@ -238,8 +238,8 @@ static void hal_ll_gpio_config( hal_ll_gpio_base_t *port, hal_ll_gpio_mask_t pin hal_ll_gpio_clock_enable( port ); // Check if it is a digital signal or alternate function - if ( ( config & GPIO_CFG_MODE_ANALOG ) != GPIO_CFG_MODE_ANALOG ) { - if ( config & GPIO_CFG_MODE_INPUT ) { + if ( config != GPIO_CFG_MODE_ANALOG ) { + if ( config == GPIO_CFG_MODE_INPUT ) { // Set gpio direction as input with filtering. port_ptr->pio.enable |= pin_mask; port_ptr->filter.enable |= pin_mask; @@ -279,20 +279,20 @@ static void hal_ll_gpio_config_pin_alternate_enable( uint8_t module_pin, uint8_t switch ( module_config ) { case HAL_LL_PERIPHERAL_A: - clear_reg_bit(&port_ptr->abcdsr0, pin_index); - clear_reg_bit(&port_ptr->abcdsr1, pin_index); + clear_reg_bit( &port_ptr->abcdsr0, pin_index ); + clear_reg_bit( &port_ptr->abcdsr1, pin_index ); break; case HAL_LL_PERIPHERAL_B: - set_reg_bit(&port_ptr->abcdsr0, pin_index); - clear_reg_bit(&port_ptr->abcdsr1, pin_index); + set_reg_bit( &port_ptr->abcdsr0, pin_index ); + clear_reg_bit( &port_ptr->abcdsr1, pin_index ); break; case HAL_LL_PERIPHERAL_C: - clear_reg_bit(&port_ptr->abcdsr0, pin_index); - set_reg_bit(&port_ptr->abcdsr1, pin_index); + clear_reg_bit( &port_ptr->abcdsr0, pin_index ); + set_reg_bit( &port_ptr->abcdsr1, pin_index ); break; case HAL_LL_PERIPHERAL_D: - set_reg_bit(&port_ptr->abcdsr0, pin_index); - set_reg_bit(&port_ptr->abcdsr1, pin_index); + set_reg_bit( &port_ptr->abcdsr0, pin_index ); + set_reg_bit( &port_ptr->abcdsr1, pin_index ); break; } } From 3867456b9b953cfa13ae6e8559f492f2b061b0d0 Mon Sep 17 00:00:00 2001 From: "ivan.ruzavin" Date: Mon, 23 Dec 2024 10:41:38 +0100 Subject: [PATCH 48/56] Fixed macros for analog/digital pins --- .../implementations/implementation_1/hal_ll_gpio_port.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c b/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c index e633ec481..be9779cff 100644 --- a/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c +++ b/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c @@ -168,17 +168,17 @@ hal_ll_base_addr_t hal_ll_gpio_port_base( hal_ll_port_name_t name ) void hal_ll_gpio_analog_input( hal_ll_gpio_base_t *port, hal_ll_gpio_mask_t pin_mask ) { - hal_ll_gpio_config( port, pin_mask, GPIO_CFG_ANALOG_INPUT ); + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_MODE_ANALOG ); } void hal_ll_gpio_digital_input( hal_ll_gpio_base_t *port, hal_ll_gpio_mask_t pin_mask ) { - hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_INPUT ); + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_MODE_INPUT ); } void hal_ll_gpio_digital_output( hal_ll_gpio_base_t *port, hal_ll_gpio_mask_t pin_mask ) { - hal_ll_gpio_config( port, pin_mask, GPIO_CFG_DIGITAL_OUTPUT ); + hal_ll_gpio_config( port, pin_mask, GPIO_CFG_MODE_OUTPUT ); } void hal_ll_gpio_module_struct_init( module_struct const *module, bool state ) From 683aa8bf45e32f63ddddb8861521e2e71f58a2f2 Mon Sep 17 00:00:00 2001 From: "ivan.ruzavin" Date: Mon, 23 Dec 2024 11:13:50 +0100 Subject: [PATCH 49/56] added missing default cases for switches --- .../implementation_1/hal_ll_gpio_port.c | 3 +++ .../implementations/implementation_1/hal_ll_tim.c | 12 ++++++++++++ .../implementations/implementation_1/hal_ll_uart.c | 2 +- 3 files changed, 16 insertions(+), 1 deletion(-) diff --git a/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c b/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c index be9779cff..449d5e0ea 100644 --- a/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c +++ b/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c @@ -219,6 +219,9 @@ static void hal_ll_gpio_clock_enable( hal_ll_gpio_base_t *port ) #ifdef __PORT_E_CN case HAL_LL_GPIOE_BASE_ADDR: pos = HAL_LL_PMC_ID_PIOE_BIT; break; #endif + + default: + break; } set_reg_bit( _PMC_PCER0, pos ); diff --git a/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c b/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c index 21a938c31..c0e0d2171 100644 --- a/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c +++ b/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c @@ -518,6 +518,9 @@ static inline void _hal_ll_tim0_set_clock( hal_ll_channel_t channel_num, bool ha case HAL_LL_TIM_CHANNEL_2: id_pos = HAL_LL_PID_TC2_BIT; break; + + default: + break; } // Enable/disable clock for appropriate channel and timer. @@ -543,6 +546,9 @@ static inline void _hal_ll_tim1_set_clock( hal_ll_channel_t channel_num, bool ha case HAL_LL_TIM_CHANNEL_2: id_pos = HAL_LL_PID_TC5_BIT; break; + + default: + break; } // Enable/disable clock for appropriate channel and timer. @@ -568,6 +574,9 @@ static inline void _hal_ll_tim2_set_clock( hal_ll_channel_t channel_num, bool ha case HAL_LL_TIM_CHANNEL_2: id_pos = HAL_LL_PID_TC8_BIT; break; + + default: + break; } // Enable/disable clock for appropriate channel and timer. @@ -593,6 +602,9 @@ static inline void _hal_ll_tim3_set_clock( hal_ll_channel_t channel_num, bool ha case HAL_LL_TIM_CHANNEL_2: id_pos = HAL_LL_PID_TC11_BIT; break; + + default: + break; } // Enable/disable clock for appropriate channel and timer. diff --git a/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c b/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c index 4452a1f58..e7adf3d89 100644 --- a/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c +++ b/targets/arm/mikroe/sam/src/uart/implementations/implementation_1/hal_ll_uart.c @@ -146,7 +146,7 @@ typedef struct typedef struct { hal_ll_base_addr_t base; - hal_ll_pin_name_t module_index; + uint8_t module_index; hal_ll_uart_pins_t pins; hal_ll_uart_baud_t baud_rate; hal_ll_uart_parity_t parity; From 8e66784f4193f33a37f9eafeda1141040f573520 Mon Sep 17 00:00:00 2001 From: Ivan Ruzavin Date: Mon, 23 Dec 2024 11:16:55 +0100 Subject: [PATCH 50/56] Update targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/implementation_1/hal_ll_tim_pin_map.h Co-authored-by: Strahinja Jacimovic --- .../implementations/implementation_1/hal_ll_tim_pin_map.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/implementation_1/hal_ll_tim_pin_map.h b/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/implementation_1/hal_ll_tim_pin_map.h index 4beb0a627..d2cab6e83 100644 --- a/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/implementation_1/hal_ll_tim_pin_map.h +++ b/targets/arm/mikroe/sam/include/tim/hal_ll_tim_pin_map/implementations/implementation_1/hal_ll_tim_pin_map.h @@ -60,7 +60,7 @@ typedef struct hal_ll_base_addr_t base; hal_ll_channel_t channel; uint8_t af; - hal_ll_pin_name_t module_index; + uint8_t module_index; } hal_ll_tim_pin_map_t; typedef enum From 656cee72552d75dbdef8762f04e65cec1cc12243 Mon Sep 17 00:00:00 2001 From: Ivan Ruzavin Date: Mon, 23 Dec 2024 11:17:04 +0100 Subject: [PATCH 51/56] Update targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c Co-authored-by: Strahinja Jacimovic --- .../i2c/implementations/implementation_1/hal_ll_i2c_master.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c b/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c index 3a2b48c34..4089c674c 100644 --- a/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c +++ b/targets/arm/mikroe/sam/src/i2c/implementations/implementation_1/hal_ll_i2c_master.c @@ -119,7 +119,7 @@ typedef struct typedef struct { hal_ll_base_addr_t base; - hal_ll_pin_name_t module_index; + uint8_t module_index; hal_ll_i2c_pins_t pins; uint32_t speed; uint8_t address; From c9c7fc2fe3d248ee1b47efaa319c93c4e281b2c8 Mon Sep 17 00:00:00 2001 From: Ivan Ruzavin Date: Mon, 23 Dec 2024 11:18:04 +0100 Subject: [PATCH 52/56] Update targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c Co-authored-by: Strahinja Jacimovic --- .../sam/src/tim/implementations/implementation_1/hal_ll_tim.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c b/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c index c0e0d2171..1397ec2f3 100644 --- a/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c +++ b/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c @@ -140,7 +140,7 @@ typedef struct hal_ll_tim_t config; uint16_t max_period; uint32_t freq_hz; - hal_ll_pin_name_t module_index; + uint8_t module_index; } hal_ll_tim_hw_specifics_map_t; /*!< @brief TIM hw specific error values */ From 7051cf905f05648e92c62c02405464f7219c69ad Mon Sep 17 00:00:00 2001 From: "ivan.ruzavin" Date: Mon, 23 Dec 2024 11:28:35 +0100 Subject: [PATCH 53/56] Added seconf default case for gpio --- .../gpio/implementations/implementation_1/hal_ll_gpio_port.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c b/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c index 449d5e0ea..43e2bc133 100644 --- a/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c +++ b/targets/arm/mikroe/sam/src/gpio/implementations/implementation_1/hal_ll_gpio_port.c @@ -297,6 +297,9 @@ static void hal_ll_gpio_config_pin_alternate_enable( uint8_t module_pin, uint8_t set_reg_bit( &port_ptr->abcdsr0, pin_index ); set_reg_bit( &port_ptr->abcdsr1, pin_index ); break; + + default: + break; } } // ------------------------------------------------------------------------- END From f8c2f13e9262ccba1bbfacb932b8bc411d992579 Mon Sep 17 00:00:00 2001 From: Ivan Ruzavin Date: Mon, 23 Dec 2024 12:12:41 +0100 Subject: [PATCH 54/56] Update targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c Co-authored-by: Strahinja Jacimovic --- .../sam/src/tim/implementations/implementation_1/hal_ll_tim.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c b/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c index 1397ec2f3..f9c9c570a 100644 --- a/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c +++ b/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c @@ -140,7 +140,7 @@ typedef struct hal_ll_tim_t config; uint16_t max_period; uint32_t freq_hz; - uint8_t module_index; + uint8_t module_index; } hal_ll_tim_hw_specifics_map_t; /*!< @brief TIM hw specific error values */ From 2c300bf34503601368046d28a706f2a8a79ada89 Mon Sep 17 00:00:00 2001 From: "ivan.ruzavin" Date: Mon, 23 Dec 2024 12:20:17 +0100 Subject: [PATCH 55/56] add default value for id_pos --- .../implementation_1/hal_ll_tim.c | 48 +++++++++++-------- 1 file changed, 28 insertions(+), 20 deletions(-) diff --git a/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c b/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c index f9c9c570a..a5ede25a6 100644 --- a/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c +++ b/targets/arm/mikroe/sam/src/tim/implementations/implementation_1/hal_ll_tim.c @@ -504,7 +504,7 @@ void hal_ll_tim_close( handle_t *handle ) { // ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS static inline void _hal_ll_tim0_set_clock( hal_ll_channel_t channel_num, bool hal_ll_state ) { - uint8_t id_pos; + uint8_t id_pos = HAL_LL_TIM_MODULE_ERROR; // Get the appropriate PID number. switch ( channel_num ) @@ -524,15 +524,17 @@ static inline void _hal_ll_tim0_set_clock( hal_ll_channel_t channel_num, bool ha } // Enable/disable clock for appropriate channel and timer. - if( hal_ll_state ) { - set_reg_bit( _PMC_PCER0, id_pos ); - } else { - set_reg_bit( _PMC_PCDR0, id_pos ); + if ( HAL_LL_TIM_MODULE_ERROR != id_pos ) { + if( hal_ll_state ) { + set_reg_bit( _PMC_PCER0, id_pos ); + } else { + set_reg_bit( _PMC_PCDR0, id_pos ); + } } } static inline void _hal_ll_tim1_set_clock( hal_ll_channel_t channel_num, bool hal_ll_state ) { - uint8_t id_pos; + uint8_t id_pos = HAL_LL_TIM_MODULE_ERROR; // Get the appropriate PID number. switch ( channel_num ) @@ -552,15 +554,17 @@ static inline void _hal_ll_tim1_set_clock( hal_ll_channel_t channel_num, bool ha } // Enable/disable clock for appropriate channel and timer. - if( hal_ll_state ) { - set_reg_bit( _PMC_PCER0, id_pos ); - } else { - set_reg_bit( _PMC_PCDR0, id_pos ); + if ( HAL_LL_TIM_MODULE_ERROR != id_pos ) { + if( hal_ll_state ) { + set_reg_bit( _PMC_PCER0, id_pos ); + } else { + set_reg_bit( _PMC_PCDR0, id_pos ); + } } } static inline void _hal_ll_tim2_set_clock( hal_ll_channel_t channel_num, bool hal_ll_state ) { - uint8_t id_pos; + uint8_t id_pos = HAL_LL_TIM_MODULE_ERROR; // Get the appropriate PID number. switch ( channel_num ) @@ -580,15 +584,17 @@ static inline void _hal_ll_tim2_set_clock( hal_ll_channel_t channel_num, bool ha } // Enable/disable clock for appropriate channel and timer. - if( hal_ll_state ) { - set_reg_bit( _PMC_PCER1, id_pos ); - } else { - set_reg_bit( _PMC_PCDR1, id_pos ); + if ( HAL_LL_TIM_MODULE_ERROR != id_pos ) { + if( hal_ll_state ) { + set_reg_bit( _PMC_PCER1, id_pos ); + } else { + set_reg_bit( _PMC_PCDR1, id_pos ); + } } } static inline void _hal_ll_tim3_set_clock( hal_ll_channel_t channel_num, bool hal_ll_state ) { - uint8_t id_pos; + uint8_t id_pos = HAL_LL_TIM_MODULE_ERROR; // Get the appropriate PID number. switch ( channel_num ) @@ -608,10 +614,12 @@ static inline void _hal_ll_tim3_set_clock( hal_ll_channel_t channel_num, bool ha } // Enable/disable clock for appropriate channel and timer. - if( hal_ll_state ) { - set_reg_bit( _PMC_PCER1, id_pos ); - } else { - set_reg_bit( _PMC_PCDR1, id_pos ); + if ( HAL_LL_TIM_MODULE_ERROR != id_pos ) { + if( hal_ll_state ) { + set_reg_bit( _PMC_PCER1, id_pos ); + } else { + set_reg_bit( _PMC_PCDR1, id_pos ); + } } } From be9a609bd2d66e73005602369680d857a00ad394 Mon Sep 17 00:00:00 2001 From: "ivan.ruzavin" Date: Mon, 23 Dec 2024 12:56:45 +0100 Subject: [PATCH 56/56] Updated release date --- changelog/v2.13.0/changelog.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/changelog/v2.13.0/changelog.md b/changelog/v2.13.0/changelog.md index a8d84facd..85b288121 100644 --- a/changelog/v2.13.0/changelog.md +++ b/changelog/v2.13.0/changelog.md @@ -10,7 +10,7 @@ # `v2.13.0` -+ released: 2024-12-20 ++ released: 2024-12-24 ## Changes