diff --git a/ARM/gcc_clang/schemas/STM32L4P5AE/STM32L4P5AE_CAN.schema b/ARM/gcc_clang/schemas/STM32L4P5AE/STM32L4P5AE_CAN.schema new file mode 100644 index 000000000..4b96741e6 --- /dev/null +++ b/ARM/gcc_clang/schemas/STM32L4P5AE/STM32L4P5AE_CAN.schema @@ -0,0 +1,234 @@ +{ + "compiler_flags": "", + "linker_flags": "", + "def_path": "ARM/gcc_clang/def/STM32L4P5AE.json", + "flash": 0, + "ram": 0, + "settings": { + "clock": "120", + "scheme": "STM32L4P5AE_CAN", + "mcu": "STM32L4P5AE", + "core": "M4EF", + "delay_src_path": "delays/m4ef/__lib_delays.c", + "name": null, + "config_registers": [ + { + "fields": [ + { + "key": "PLLSAI2ON", + "value": "0" + }, + { + "key": "PLLSAI1ON", + "value": "0" + }, + { + "key": "PLLON", + "value": "1000000" + }, + { + "key": "CSSON", + "value": "0" + }, + { + "key": "HSEBYP", + "value": "0" + }, + { + "key": "HSEON", + "value": "0" + }, + { + "key": "HSIASFS", + "value": "0" + }, + { + "key": "HSIKERON", + "value": "0" + }, + { + "key": "HSION", + "value": "100" + }, + { + "key": "MSIRANGE", + "value": "00000060" + }, + { + "key": "MSIRGSEL", + "value": "0" + }, + { + "key": "MSIPLLEN", + "value": "0" + }, + { + "key": "MSION", + "value": "0" + } + ], + "key": "RCC_CR" + }, + { + "fields": [ + { + "key": "HSITRIM", + "value": "40000000" + }, + { + "key": "MSITRIM", + "value": "00000000" + } + ], + "key": "RCC_ICSCR" + }, + { + "fields": [ + { + "key": "MCOSEL", + "value": "00000000" + }, + { + "key": "STOPWUCK", + "value": "00000000" + }, + { + "key": "PPRE2", + "value": "00000000" + }, + { + "key": "PPRE1", + "value": "00000000" + }, + { + "key": "HPRE", + "value": "00000000" + }, + { + "key": "SW", + "value": "3" + } + ], + "key": "RCC_CFGR" + }, + { + "fields": [ + { + "key": "PLLPDIV", + "value": "00000000" + }, + { + "key": "PLLR", + "value": "00000000" + }, + { + "key": "PLLREN", + "value": "00000000" + }, + { + "key": "PLLQ", + "value": "00000000" + }, + { + "key": "PLLQEN", + "value": "00000000" + }, + { + "key": "PLLP", + "value": "00000000" + }, + { + "key": "PLLPEN", + "value": "00000000" + }, + { + "key": "PLLN", + "value": "00000f00" + }, + { + "key": "PLLM", + "value": "00000000" + }, + { + "key": "PLLSRC", + "value": "2" + } + ], + "key": "RCC_PLLCFGR" + }, + { + "fields": [ + { + "key": "LSCOSEL", + "value": "00000000" + }, + { + "key": "LSCOEN", + "value": "00000000" + }, + { + "key": "BDRST", + "value": "00000000" + }, + { + "key": "RTCEN", + "value": "00000000" + }, + { + "key": "RTCSEL", + "value": "00000000" + }, + { + "key": "LSESYSDIS", + "value": "00000000" + }, + { + "key": "LSECSSON", + "value": "00000000" + }, + { + "key": "LSEDRV", + "value": "00000000" + }, + { + "key": "LSEBYP", + "value": "00000000" + }, + { + "key": "LSEON", + "value": "00000000" + } + ], + "key": "RCC_BDCR" + }, + { + "fields": [ + { + "key": "RMVF", + "value": "00000000" + }, + { + "key": "MSISRANGE", + "value": "00000600" + }, + { + "key": "LSIPREDIV", + "value": "00000000" + }, + { + "key": "LSION", + "value": "00000000" + } + ], + "key": "RCC_CSR" + }, + { + "fields": { + "key": "HSI48ON", + "value": "00000000" + }, + "key": "RCC_CRRCR" + } + ] + } +} diff --git a/ARM/gcc_clang/schemas/STM32L4P5AG/STM32L4P5AG_CAN.schema b/ARM/gcc_clang/schemas/STM32L4P5AG/STM32L4P5AG_CAN.schema new file mode 100644 index 000000000..c807b7933 --- /dev/null +++ b/ARM/gcc_clang/schemas/STM32L4P5AG/STM32L4P5AG_CAN.schema @@ -0,0 +1,234 @@ +{ + "compiler_flags": "", + "linker_flags": "", + "def_path": "ARM/gcc_clang/def/STM32L4P5AG.json", + "flash": 0, + "ram": 0, + "settings": { + "clock": "120", + "scheme": "STM32L4P5AG_CAN", + "mcu": "STM32L4P5AG", + "core": "M4EF", + "delay_src_path": "delays/m4ef/__lib_delays.c", + "name": null, + "config_registers": [ + { + "fields": [ + { + "key": "PLLSAI2ON", + "value": "0" + }, + { + "key": "PLLSAI1ON", + "value": "0" + }, + { + "key": "PLLON", + "value": "1000000" + }, + { + "key": "CSSON", + "value": "0" + }, + { + "key": "HSEBYP", + "value": "0" + }, + { + "key": "HSEON", + "value": "0" + }, + { + "key": "HSIASFS", + "value": "0" + }, + { + "key": "HSIKERON", + "value": "0" + }, + { + "key": "HSION", + "value": "100" + }, + { + "key": "MSIRANGE", + "value": "00000060" + }, + { + "key": "MSIRGSEL", + "value": "0" + }, + { + "key": "MSIPLLEN", + "value": "0" + }, + { + "key": "MSION", + "value": "0" + } + ], + "key": "RCC_CR" + }, + { + "fields": [ + { + "key": "HSITRIM", + "value": "40000000" + }, + { + "key": "MSITRIM", + "value": "00000000" + } + ], + "key": "RCC_ICSCR" + }, + { + "fields": [ + { + "key": "MCOSEL", + "value": "00000000" + }, + { + "key": "STOPWUCK", + "value": "00000000" + }, + { + "key": "PPRE2", + "value": "00000000" + }, + { + "key": "PPRE1", + "value": "00000000" + }, + { + "key": "HPRE", + "value": "00000000" + }, + { + "key": "SW", + "value": "3" + } + ], + "key": "RCC_CFGR" + }, + { + "fields": [ + { + "key": "PLLPDIV", + "value": "00000000" + }, + { + "key": "PLLR", + "value": "00000000" + }, + { + "key": "PLLREN", + "value": "00000000" + }, + { + "key": "PLLQ", + "value": "00000000" + }, + { + "key": "PLLQEN", + "value": "00000000" + }, + { + "key": "PLLP", + "value": "00000000" + }, + { + "key": "PLLPEN", + "value": "00000000" + }, + { + "key": "PLLN", + "value": "00000f00" + }, + { + "key": "PLLM", + "value": "00000000" + }, + { + "key": "PLLSRC", + "value": "2" + } + ], + "key": "RCC_PLLCFGR" + }, + { + "fields": [ + { + "key": "LSCOSEL", + "value": "00000000" + }, + { + "key": "LSCOEN", + "value": "00000000" + }, + { + "key": "BDRST", + "value": "00000000" + }, + { + "key": "RTCEN", + "value": "00000000" + }, + { + "key": "RTCSEL", + "value": "00000000" + }, + { + "key": "LSESYSDIS", + "value": "00000000" + }, + { + "key": "LSECSSON", + "value": "00000000" + }, + { + "key": "LSEDRV", + "value": "00000000" + }, + { + "key": "LSEBYP", + "value": "00000000" + }, + { + "key": "LSEON", + "value": "00000000" + } + ], + "key": "RCC_BDCR" + }, + { + "fields": [ + { + "key": "RMVF", + "value": "00000000" + }, + { + "key": "MSISRANGE", + "value": "00000600" + }, + { + "key": "LSIPREDIV", + "value": "00000000" + }, + { + "key": "LSION", + "value": "00000000" + } + ], + "key": "RCC_CSR" + }, + { + "fields": { + "key": "HSI48ON", + "value": "00000000" + }, + "key": "RCC_CRRCR" + } + ] + } +} diff --git a/ARM/gcc_clang/schemas/STM32L4P5CE/STM32L4P5CE_CAN.schema b/ARM/gcc_clang/schemas/STM32L4P5CE/STM32L4P5CE_CAN.schema new file mode 100644 index 000000000..f0ead45e3 --- /dev/null +++ b/ARM/gcc_clang/schemas/STM32L4P5CE/STM32L4P5CE_CAN.schema @@ -0,0 +1,234 @@ +{ + "compiler_flags": "", + "linker_flags": "", + "def_path": "ARM/gcc_clang/def/STM32L4P5CE.json", + "flash": 0, + "ram": 0, + "settings": { + "clock": "120", + "scheme": "STM32L4P5CE_CAN", + "mcu": "STM32L4P5CE", + "core": "M4EF", + "delay_src_path": "delays/m4ef/__lib_delays.c", + "name": null, + "config_registers": [ + { + "fields": [ + { + "key": "PLLSAI2ON", + "value": "0" + }, + { + "key": "PLLSAI1ON", + "value": "0" + }, + { + "key": "PLLON", + "value": "1000000" + }, + { + "key": "CSSON", + "value": "0" + }, + { + "key": "HSEBYP", + "value": "0" + }, + { + "key": "HSEON", + "value": "0" + }, + { + "key": "HSIASFS", + "value": "0" + }, + { + "key": "HSIKERON", + "value": "0" + }, + { + "key": "HSION", + "value": "100" + }, + { + "key": "MSIRANGE", + "value": "00000060" + }, + { + "key": "MSIRGSEL", + "value": "0" + }, + { + "key": "MSIPLLEN", + "value": "0" + }, + { + "key": "MSION", + "value": "0" + } + ], + "key": "RCC_CR" + }, + { + "fields": [ + { + "key": "HSITRIM", + "value": "40000000" + }, + { + "key": "MSITRIM", + "value": "00000000" + } + ], + "key": "RCC_ICSCR" + }, + { + "fields": [ + { + "key": "MCOSEL", + "value": "00000000" + }, + { + "key": "STOPWUCK", + "value": "00000000" + }, + { + "key": "PPRE2", + "value": "00000000" + }, + { + "key": "PPRE1", + "value": "00000000" + }, + { + "key": "HPRE", + "value": "00000000" + }, + { + "key": "SW", + "value": "3" + } + ], + "key": "RCC_CFGR" + }, + { + "fields": [ + { + "key": "PLLPDIV", + "value": "00000000" + }, + { + "key": "PLLR", + "value": "00000000" + }, + { + "key": "PLLREN", + "value": "00000000" + }, + { + "key": "PLLQ", + "value": "00000000" + }, + { + "key": "PLLQEN", + "value": "00000000" + }, + { + "key": "PLLP", + "value": "00000000" + }, + { + "key": "PLLPEN", + "value": "00000000" + }, + { + "key": "PLLN", + "value": "00000f00" + }, + { + "key": "PLLM", + "value": "00000000" + }, + { + "key": "PLLSRC", + "value": "2" + } + ], + "key": "RCC_PLLCFGR" + }, + { + "fields": [ + { + "key": "LSCOSEL", + "value": "00000000" + }, + { + "key": "LSCOEN", + "value": "00000000" + }, + { + "key": "BDRST", + "value": "00000000" + }, + { + "key": "RTCEN", + "value": "00000000" + }, + { + "key": "RTCSEL", + "value": "00000000" + }, + { + "key": "LSESYSDIS", + "value": "00000000" + }, + { + "key": "LSECSSON", + "value": "00000000" + }, + { + "key": "LSEDRV", + "value": "00000000" + }, + { + "key": "LSEBYP", + "value": "00000000" + }, + { + "key": "LSEON", + "value": "00000000" + } + ], + "key": "RCC_BDCR" + }, + { + "fields": [ + { + "key": "RMVF", + "value": "00000000" + }, + { + "key": "MSISRANGE", + "value": "00000600" + }, + { + "key": "LSIPREDIV", + "value": "00000000" + }, + { + "key": "LSION", + "value": "00000000" + } + ], + "key": "RCC_CSR" + }, + { + "fields": { + "key": "HSI48ON", + "value": "00000000" + }, + "key": "RCC_CRRCR" + } + ] + } +} diff --git a/ARM/gcc_clang/schemas/STM32L4P5CG/STM32L4P5CG_CAN.schema b/ARM/gcc_clang/schemas/STM32L4P5CG/STM32L4P5CG_CAN.schema new file mode 100644 index 000000000..ff28c1b6b --- /dev/null +++ b/ARM/gcc_clang/schemas/STM32L4P5CG/STM32L4P5CG_CAN.schema @@ -0,0 +1,234 @@ +{ + "compiler_flags": "", + "linker_flags": "", + "def_path": "ARM/gcc_clang/def/STM32L4P5CG.json", + "flash": 0, + "ram": 0, + "settings": { + "clock": "120", + "scheme": "STM32L4P5CG_CAN", + "mcu": "STM32L4P5CG", + "core": "M4EF", + "delay_src_path": "delays/m4ef/__lib_delays.c", + "name": null, + "config_registers": [ + { + "fields": [ + { + "key": "PLLSAI2ON", + "value": "0" + }, + { + "key": "PLLSAI1ON", + "value": "0" + }, + { + "key": "PLLON", + "value": "1000000" + }, + { + "key": "CSSON", + "value": "0" + }, + { + "key": "HSEBYP", + "value": "0" + }, + { + "key": "HSEON", + "value": "0" + }, + { + "key": "HSIASFS", + "value": "0" + }, + { + "key": "HSIKERON", + "value": "0" + }, + { + "key": "HSION", + "value": "100" + }, + { + "key": "MSIRANGE", + "value": "00000060" + }, + { + "key": "MSIRGSEL", + "value": "0" + }, + { + "key": "MSIPLLEN", + "value": "0" + }, + { + "key": "MSION", + "value": "0" + } + ], + "key": "RCC_CR" + }, + { + "fields": [ + { + "key": "HSITRIM", + "value": "40000000" + }, + { + "key": "MSITRIM", + "value": "00000000" + } + ], + "key": "RCC_ICSCR" + }, + { + "fields": [ + { + "key": "MCOSEL", + "value": "00000000" + }, + { + "key": "STOPWUCK", + "value": "00000000" + }, + { + "key": "PPRE2", + "value": "00000000" + }, + { + "key": "PPRE1", + "value": "00000000" + }, + { + "key": "HPRE", + "value": "00000000" + }, + { + "key": "SW", + "value": "3" + } + ], + "key": "RCC_CFGR" + }, + { + "fields": [ + { + "key": "PLLPDIV", + "value": "00000000" + }, + { + "key": "PLLR", + "value": "00000000" + }, + { + "key": "PLLREN", + "value": "00000000" + }, + { + "key": "PLLQ", + "value": "00000000" + }, + { + "key": "PLLQEN", + "value": "00000000" + }, + { + "key": "PLLP", + "value": "00000000" + }, + { + "key": "PLLPEN", + "value": "00000000" + }, + { + "key": "PLLN", + "value": "00000f00" + }, + { + "key": "PLLM", + "value": "00000000" + }, + { + "key": "PLLSRC", + "value": "2" + } + ], + "key": "RCC_PLLCFGR" + }, + { + "fields": [ + { + "key": "LSCOSEL", + "value": "00000000" + }, + { + "key": "LSCOEN", + "value": "00000000" + }, + { + "key": "BDRST", + "value": "00000000" + }, + { + "key": "RTCEN", + "value": "00000000" + }, + { + "key": "RTCSEL", + "value": "00000000" + }, + { + "key": "LSESYSDIS", + "value": "00000000" + }, + { + "key": "LSECSSON", + "value": "00000000" + }, + { + "key": "LSEDRV", + "value": "00000000" + }, + { + "key": "LSEBYP", + "value": "00000000" + }, + { + "key": "LSEON", + "value": "00000000" + } + ], + "key": "RCC_BDCR" + }, + { + "fields": [ + { + "key": "RMVF", + "value": "00000000" + }, + { + "key": "MSISRANGE", + "value": "00000600" + }, + { + "key": "LSIPREDIV", + "value": "00000000" + }, + { + "key": "LSION", + "value": "00000000" + } + ], + "key": "RCC_CSR" + }, + { + "fields": { + "key": "HSI48ON", + "value": "00000000" + }, + "key": "RCC_CRRCR" + } + ] + } +} diff --git a/ARM/gcc_clang/schemas/STM32L4P5QE/STM32L4P5QE_CAN.schema b/ARM/gcc_clang/schemas/STM32L4P5QE/STM32L4P5QE_CAN.schema new file mode 100644 index 000000000..7224f2a05 --- /dev/null +++ b/ARM/gcc_clang/schemas/STM32L4P5QE/STM32L4P5QE_CAN.schema @@ -0,0 +1,234 @@ +{ + "compiler_flags": "", + "linker_flags": "", + "def_path": "ARM/gcc_clang/def/STM32L4P5QE.json", + "flash": 0, + "ram": 0, + "settings": { + "clock": "120", + "scheme": "STM32L4P5QE_CAN", + "mcu": "STM32L4P5QE", + "core": "M4EF", + "delay_src_path": "delays/m4ef/__lib_delays.c", + "name": null, + "config_registers": [ + { + "fields": [ + { + "key": "PLLSAI2ON", + "value": "0" + }, + { + "key": "PLLSAI1ON", + "value": "0" + }, + { + "key": "PLLON", + "value": "1000000" + }, + { + "key": "CSSON", + "value": "0" + }, + { + "key": "HSEBYP", + "value": "0" + }, + { + "key": "HSEON", + "value": "0" + }, + { + "key": "HSIASFS", + "value": "0" + }, + { + "key": "HSIKERON", + "value": "0" + }, + { + "key": "HSION", + "value": "100" + }, + { + "key": "MSIRANGE", + "value": "00000060" + }, + { + "key": "MSIRGSEL", + "value": "0" + }, + { + "key": "MSIPLLEN", + "value": "0" + }, + { + "key": "MSION", + "value": "0" + } + ], + "key": "RCC_CR" + }, + { + "fields": [ + { + "key": "HSITRIM", + "value": "40000000" + }, + { + "key": "MSITRIM", + "value": "00000000" + } + ], + "key": "RCC_ICSCR" + }, + { + "fields": [ + { + "key": "MCOSEL", + "value": "00000000" + }, + { + "key": "STOPWUCK", + "value": "00000000" + }, + { + "key": "PPRE2", + "value": "00000000" + }, + { + "key": "PPRE1", + "value": "00000000" + }, + { + "key": "HPRE", + "value": "00000000" + }, + { + "key": "SW", + "value": "3" + } + ], + "key": "RCC_CFGR" + }, + { + "fields": [ + { + "key": "PLLPDIV", + "value": "00000000" + }, + { + "key": "PLLR", + "value": "00000000" + }, + { + "key": "PLLREN", + "value": "00000000" + }, + { + "key": "PLLQ", + "value": "00000000" + }, + { + "key": "PLLQEN", + "value": "00000000" + }, + { + "key": "PLLP", + "value": "00000000" + }, + { + "key": "PLLPEN", + "value": "00000000" + }, + { + "key": "PLLN", + "value": "00000f00" + }, + { + "key": "PLLM", + "value": "00000000" + }, + { + "key": "PLLSRC", + "value": "2" + } + ], + "key": "RCC_PLLCFGR" + }, + { + "fields": [ + { + "key": "LSCOSEL", + "value": "00000000" + }, + { + "key": "LSCOEN", + "value": "00000000" + }, + { + "key": "BDRST", + "value": "00000000" + }, + { + "key": "RTCEN", + "value": "00000000" + }, + { + "key": "RTCSEL", + "value": "00000000" + }, + { + "key": "LSESYSDIS", + "value": "00000000" + }, + { + "key": "LSECSSON", + "value": "00000000" + }, + { + "key": "LSEDRV", + "value": "00000000" + }, + { + "key": "LSEBYP", + "value": "00000000" + }, + { + "key": "LSEON", + "value": "00000000" + } + ], + "key": "RCC_BDCR" + }, + { + "fields": [ + { + "key": "RMVF", + "value": "00000000" + }, + { + "key": "MSISRANGE", + "value": "00000600" + }, + { + "key": "LSIPREDIV", + "value": "00000000" + }, + { + "key": "LSION", + "value": "00000000" + } + ], + "key": "RCC_CSR" + }, + { + "fields": { + "key": "HSI48ON", + "value": "00000000" + }, + "key": "RCC_CRRCR" + } + ] + } +} diff --git a/ARM/gcc_clang/schemas/STM32L4P5QG/STM32L4P5QG_CAN.schema b/ARM/gcc_clang/schemas/STM32L4P5QG/STM32L4P5QG_CAN.schema new file mode 100644 index 000000000..9734984c9 --- /dev/null +++ b/ARM/gcc_clang/schemas/STM32L4P5QG/STM32L4P5QG_CAN.schema @@ -0,0 +1,234 @@ +{ + "compiler_flags": "", + "linker_flags": "", + "def_path": "ARM/gcc_clang/def/STM32L4P5QG.json", + "flash": 0, + "ram": 0, + "settings": { + "clock": "120", + "scheme": "STM32L4P5QG_CAN", + "mcu": "STM32L4P5QG", + "core": "M4EF", + "delay_src_path": "delays/m4ef/__lib_delays.c", + "name": null, + "config_registers": [ + { + "fields": [ + { + "key": "PLLSAI2ON", + "value": "0" + }, + { + "key": "PLLSAI1ON", + "value": "0" + }, + { + "key": "PLLON", + "value": "1000000" + }, + { + "key": "CSSON", + "value": "0" + }, + { + "key": "HSEBYP", + "value": "0" + }, + { + "key": "HSEON", + "value": "0" + }, + { + "key": "HSIASFS", + "value": "0" + }, + { + "key": "HSIKERON", + "value": "0" + }, + { + "key": "HSION", + "value": "100" + }, + { + "key": "MSIRANGE", + "value": "00000060" + }, + { + "key": "MSIRGSEL", + "value": "0" + }, + { + "key": "MSIPLLEN", + "value": "0" + }, + { + "key": "MSION", + "value": "0" + } + ], + "key": "RCC_CR" + }, + { + "fields": [ + { + "key": "HSITRIM", + "value": "40000000" + }, + { + "key": "MSITRIM", + "value": "00000000" + } + ], + "key": "RCC_ICSCR" + }, + { + "fields": [ + { + "key": "MCOSEL", + "value": "00000000" + }, + { + "key": "STOPWUCK", + "value": "00000000" + }, + { + "key": "PPRE2", + "value": "00000000" + }, + { + "key": "PPRE1", + "value": "00000000" + }, + { + "key": "HPRE", + "value": "00000000" + }, + { + "key": "SW", + "value": "3" + } + ], + "key": "RCC_CFGR" + }, + { + "fields": [ + { + "key": "PLLPDIV", + "value": "00000000" + }, + { + "key": "PLLR", + "value": "00000000" + }, + { + "key": "PLLREN", + "value": "00000000" + }, + { + "key": "PLLQ", + "value": "00000000" + }, + { + "key": "PLLQEN", + "value": "00000000" + }, + { + "key": "PLLP", + "value": "00000000" + }, + { + "key": "PLLPEN", + "value": "00000000" + }, + { + "key": "PLLN", + "value": "00000f00" + }, + { + "key": "PLLM", + "value": "00000000" + }, + { + "key": "PLLSRC", + "value": "2" + } + ], + "key": "RCC_PLLCFGR" + }, + { + "fields": [ + { + "key": "LSCOSEL", + "value": "00000000" + }, + { + "key": "LSCOEN", + "value": "00000000" + }, + { + "key": "BDRST", + "value": "00000000" + }, + { + "key": "RTCEN", + "value": "00000000" + }, + { + "key": "RTCSEL", + "value": "00000000" + }, + { + "key": "LSESYSDIS", + "value": "00000000" + }, + { + "key": "LSECSSON", + "value": "00000000" + }, + { + "key": "LSEDRV", + "value": "00000000" + }, + { + "key": "LSEBYP", + "value": "00000000" + }, + { + "key": "LSEON", + "value": "00000000" + } + ], + "key": "RCC_BDCR" + }, + { + "fields": [ + { + "key": "RMVF", + "value": "00000000" + }, + { + "key": "MSISRANGE", + "value": "00000600" + }, + { + "key": "LSIPREDIV", + "value": "00000000" + }, + { + "key": "LSION", + "value": "00000000" + } + ], + "key": "RCC_CSR" + }, + { + "fields": { + "key": "HSI48ON", + "value": "00000000" + }, + "key": "RCC_CRRCR" + } + ] + } +} diff --git a/ARM/gcc_clang/schemas/STM32L4P5RE/STM32L4P5RE_CAN.schema b/ARM/gcc_clang/schemas/STM32L4P5RE/STM32L4P5RE_CAN.schema new file mode 100644 index 000000000..795746d72 --- /dev/null +++ b/ARM/gcc_clang/schemas/STM32L4P5RE/STM32L4P5RE_CAN.schema @@ -0,0 +1,234 @@ +{ + "compiler_flags": "", + "linker_flags": "", + "def_path": "ARM/gcc_clang/def/STM32L4P5RE.json", + "flash": 0, + "ram": 0, + "settings": { + "clock": "120", + "scheme": "STM32L4P5RE_CAN", + "mcu": "STM32L4P5RE", + "core": "M4EF", + "delay_src_path": "delays/m4ef/__lib_delays.c", + "name": null, + "config_registers": [ + { + "fields": [ + { + "key": "PLLSAI2ON", + "value": "0" + }, + { + "key": "PLLSAI1ON", + "value": "0" + }, + { + "key": "PLLON", + "value": "1000000" + }, + { + "key": "CSSON", + "value": "0" + }, + { + "key": "HSEBYP", + "value": "0" + }, + { + "key": "HSEON", + "value": "0" + }, + { + "key": "HSIASFS", + "value": "0" + }, + { + "key": "HSIKERON", + "value": "0" + }, + { + "key": "HSION", + "value": "100" + }, + { + "key": "MSIRANGE", + "value": "00000060" + }, + { + "key": "MSIRGSEL", + "value": "0" + }, + { + "key": "MSIPLLEN", + "value": "0" + }, + { + "key": "MSION", + "value": "0" + } + ], + "key": "RCC_CR" + }, + { + "fields": [ + { + "key": "HSITRIM", + "value": "40000000" + }, + { + "key": "MSITRIM", + "value": "00000000" + } + ], + "key": "RCC_ICSCR" + }, + { + "fields": [ + { + "key": "MCOSEL", + "value": "00000000" + }, + { + "key": "STOPWUCK", + "value": "00000000" + }, + { + "key": "PPRE2", + "value": "00000000" + }, + { + "key": "PPRE1", + "value": "00000000" + }, + { + "key": "HPRE", + "value": "00000000" + }, + { + "key": "SW", + "value": "3" + } + ], + "key": "RCC_CFGR" + }, + { + "fields": [ + { + "key": "PLLPDIV", + "value": "00000000" + }, + { + "key": "PLLR", + "value": "00000000" + }, + { + "key": "PLLREN", + "value": "00000000" + }, + { + "key": "PLLQ", + "value": "00000000" + }, + { + "key": "PLLQEN", + "value": "00000000" + }, + { + "key": "PLLP", + "value": "00000000" + }, + { + "key": "PLLPEN", + "value": "00000000" + }, + { + "key": "PLLN", + "value": "00000f00" + }, + { + "key": "PLLM", + "value": "00000000" + }, + { + "key": "PLLSRC", + "value": "2" + } + ], + "key": "RCC_PLLCFGR" + }, + { + "fields": [ + { + "key": "LSCOSEL", + "value": "00000000" + }, + { + "key": "LSCOEN", + "value": "00000000" + }, + { + "key": "BDRST", + "value": "00000000" + }, + { + "key": "RTCEN", + "value": "00000000" + }, + { + "key": "RTCSEL", + "value": "00000000" + }, + { + "key": "LSESYSDIS", + "value": "00000000" + }, + { + "key": "LSECSSON", + "value": "00000000" + }, + { + "key": "LSEDRV", + "value": "00000000" + }, + { + "key": "LSEBYP", + "value": "00000000" + }, + { + "key": "LSEON", + "value": "00000000" + } + ], + "key": "RCC_BDCR" + }, + { + "fields": [ + { + "key": "RMVF", + "value": "00000000" + }, + { + "key": "MSISRANGE", + "value": "00000600" + }, + { + "key": "LSIPREDIV", + "value": "00000000" + }, + { + "key": "LSION", + "value": "00000000" + } + ], + "key": "RCC_CSR" + }, + { + "fields": { + "key": "HSI48ON", + "value": "00000000" + }, + "key": "RCC_CRRCR" + } + ] + } +} diff --git a/ARM/gcc_clang/schemas/STM32L4P5RG/STM32L4P5RG_CAN.schema b/ARM/gcc_clang/schemas/STM32L4P5RG/STM32L4P5RG_CAN.schema new file mode 100644 index 000000000..40d7aff8b --- /dev/null +++ b/ARM/gcc_clang/schemas/STM32L4P5RG/STM32L4P5RG_CAN.schema @@ -0,0 +1,234 @@ +{ + "compiler_flags": "", + "linker_flags": "", + "def_path": "ARM/gcc_clang/def/STM32L4P5RG.json", + "flash": 0, + "ram": 0, + "settings": { + "clock": "120", + "scheme": "STM32L4P5RG_CAN", + "mcu": "STM32L4P5RG", + "core": "M4EF", + "delay_src_path": "delays/m4ef/__lib_delays.c", + "name": null, + "config_registers": [ + { + "fields": [ + { + "key": "PLLSAI2ON", + "value": "0" + }, + { + "key": "PLLSAI1ON", + "value": "0" + }, + { + "key": "PLLON", + "value": "1000000" + }, + { + "key": "CSSON", + "value": "0" + }, + { + "key": "HSEBYP", + "value": "0" + }, + { + "key": "HSEON", + "value": "0" + }, + { + "key": "HSIASFS", + "value": "0" + }, + { + "key": "HSIKERON", + "value": "0" + }, + { + "key": "HSION", + "value": "100" + }, + { + "key": "MSIRANGE", + "value": "00000060" + }, + { + "key": "MSIRGSEL", + "value": "0" + }, + { + "key": "MSIPLLEN", + "value": "0" + }, + { + "key": "MSION", + "value": "0" + } + ], + "key": "RCC_CR" + }, + { + "fields": [ + { + "key": "HSITRIM", + "value": "40000000" + }, + { + "key": "MSITRIM", + "value": "00000000" + } + ], + "key": "RCC_ICSCR" + }, + { + "fields": [ + { + "key": "MCOSEL", + "value": "00000000" + }, + { + "key": "STOPWUCK", + "value": "00000000" + }, + { + "key": "PPRE2", + "value": "00000000" + }, + { + "key": "PPRE1", + "value": "00000000" + }, + { + "key": "HPRE", + "value": "00000000" + }, + { + "key": "SW", + "value": "3" + } + ], + "key": "RCC_CFGR" + }, + { + "fields": [ + { + "key": "PLLPDIV", + "value": "00000000" + }, + { + "key": "PLLR", + "value": "00000000" + }, + { + "key": "PLLREN", + "value": "00000000" + }, + { + "key": "PLLQ", + "value": "00000000" + }, + { + "key": "PLLQEN", + "value": "00000000" + }, + { + "key": "PLLP", + "value": "00000000" + }, + { + "key": "PLLPEN", + "value": "00000000" + }, + { + "key": "PLLN", + "value": "00000f00" + }, + { + "key": "PLLM", + "value": "00000000" + }, + { + "key": "PLLSRC", + "value": "2" + } + ], + "key": "RCC_PLLCFGR" + }, + { + "fields": [ + { + "key": "LSCOSEL", + "value": "00000000" + }, + { + "key": "LSCOEN", + "value": "00000000" + }, + { + "key": "BDRST", + "value": "00000000" + }, + { + "key": "RTCEN", + "value": "00000000" + }, + { + "key": "RTCSEL", + "value": "00000000" + }, + { + "key": "LSESYSDIS", + "value": "00000000" + }, + { + "key": "LSECSSON", + "value": "00000000" + }, + { + "key": "LSEDRV", + "value": "00000000" + }, + { + "key": "LSEBYP", + "value": "00000000" + }, + { + "key": "LSEON", + "value": "00000000" + } + ], + "key": "RCC_BDCR" + }, + { + "fields": [ + { + "key": "RMVF", + "value": "00000000" + }, + { + "key": "MSISRANGE", + "value": "00000600" + }, + { + "key": "LSIPREDIV", + "value": "00000000" + }, + { + "key": "LSION", + "value": "00000000" + } + ], + "key": "RCC_CSR" + }, + { + "fields": { + "key": "HSI48ON", + "value": "00000000" + }, + "key": "RCC_CRRCR" + } + ] + } +} diff --git a/ARM/gcc_clang/schemas/STM32L4P5VE/STM32L4P5VE_CAN.schema b/ARM/gcc_clang/schemas/STM32L4P5VE/STM32L4P5VE_CAN.schema new file mode 100644 index 000000000..17a4c4492 --- /dev/null +++ b/ARM/gcc_clang/schemas/STM32L4P5VE/STM32L4P5VE_CAN.schema @@ -0,0 +1,234 @@ +{ + "compiler_flags": "", + "linker_flags": "", + "def_path": "ARM/gcc_clang/def/STM32L4P5VE.json", + "flash": 0, + "ram": 0, + "settings": { + "clock": "120", + "scheme": "STM32L4P5VE_CAN", + "mcu": "STM32L4P5VE", + "core": "M4EF", + "delay_src_path": "delays/m4ef/__lib_delays.c", + "name": null, + "config_registers": [ + { + "fields": [ + { + "key": "PLLSAI2ON", + "value": "0" + }, + { + "key": "PLLSAI1ON", + "value": "0" + }, + { + "key": "PLLON", + "value": "1000000" + }, + { + "key": "CSSON", + "value": "0" + }, + { + "key": "HSEBYP", + "value": "0" + }, + { + "key": "HSEON", + "value": "0" + }, + { + "key": "HSIASFS", + "value": "0" + }, + { + "key": "HSIKERON", + "value": "0" + }, + { + "key": "HSION", + "value": "100" + }, + { + "key": "MSIRANGE", + "value": "00000060" + }, + { + "key": "MSIRGSEL", + "value": "0" + }, + { + "key": "MSIPLLEN", + "value": "0" + }, + { + "key": "MSION", + "value": "0" + } + ], + "key": "RCC_CR" + }, + { + "fields": [ + { + "key": "HSITRIM", + "value": "40000000" + }, + { + "key": "MSITRIM", + "value": "00000000" + } + ], + "key": "RCC_ICSCR" + }, + { + "fields": [ + { + "key": "MCOSEL", + "value": "00000000" + }, + { + "key": "STOPWUCK", + "value": "00000000" + }, + { + "key": "PPRE2", + "value": "00000000" + }, + { + "key": "PPRE1", + "value": "00000000" + }, + { + "key": "HPRE", + "value": "00000000" + }, + { + "key": "SW", + "value": "3" + } + ], + "key": "RCC_CFGR" + }, + { + "fields": [ + { + "key": "PLLPDIV", + "value": "00000000" + }, + { + "key": "PLLR", + "value": "00000000" + }, + { + "key": "PLLREN", + "value": "00000000" + }, + { + "key": "PLLQ", + "value": "00000000" + }, + { + "key": "PLLQEN", + "value": "00000000" + }, + { + "key": "PLLP", + "value": "00000000" + }, + { + "key": "PLLPEN", + "value": "00000000" + }, + { + "key": "PLLN", + "value": "00000f00" + }, + { + "key": "PLLM", + "value": "00000000" + }, + { + "key": "PLLSRC", + "value": "2" + } + ], + "key": "RCC_PLLCFGR" + }, + { + "fields": [ + { + "key": "LSCOSEL", + "value": "00000000" + }, + { + "key": "LSCOEN", + "value": "00000000" + }, + { + "key": "BDRST", + "value": "00000000" + }, + { + "key": "RTCEN", + "value": "00000000" + }, + { + "key": "RTCSEL", + "value": "00000000" + }, + { + "key": "LSESYSDIS", + "value": "00000000" + }, + { + "key": "LSECSSON", + "value": "00000000" + }, + { + "key": "LSEDRV", + "value": "00000000" + }, + { + "key": "LSEBYP", + "value": "00000000" + }, + { + "key": "LSEON", + "value": "00000000" + } + ], + "key": "RCC_BDCR" + }, + { + "fields": [ + { + "key": "RMVF", + "value": "00000000" + }, + { + "key": "MSISRANGE", + "value": "00000600" + }, + { + "key": "LSIPREDIV", + "value": "00000000" + }, + { + "key": "LSION", + "value": "00000000" + } + ], + "key": "RCC_CSR" + }, + { + "fields": { + "key": "HSI48ON", + "value": "00000000" + }, + "key": "RCC_CRRCR" + } + ] + } +} diff --git a/ARM/gcc_clang/schemas/STM32L4P5VG/STM32L4P5VG_CAN.schema b/ARM/gcc_clang/schemas/STM32L4P5VG/STM32L4P5VG_CAN.schema new file mode 100644 index 000000000..3b8906ca9 --- /dev/null +++ b/ARM/gcc_clang/schemas/STM32L4P5VG/STM32L4P5VG_CAN.schema @@ -0,0 +1,234 @@ +{ + "compiler_flags": "", + "linker_flags": "", + "def_path": "ARM/gcc_clang/def/STM32L4P5VG.json", + "flash": 0, + "ram": 0, + "settings": { + "clock": "120", + "scheme": "STM32L4P5VG_CAN", + "mcu": "STM32L4P5VG", + "core": "M4EF", + "delay_src_path": "delays/m4ef/__lib_delays.c", + "name": null, + "config_registers": [ + { + "fields": [ + { + "key": "PLLSAI2ON", + "value": "0" + }, + { + "key": "PLLSAI1ON", + "value": "0" + }, + { + "key": "PLLON", + "value": "1000000" + }, + { + "key": "CSSON", + "value": "0" + }, + { + "key": "HSEBYP", + "value": "0" + }, + { + "key": "HSEON", + "value": "0" + }, + { + "key": "HSIASFS", + "value": "0" + }, + { + "key": "HSIKERON", + "value": "0" + }, + { + "key": "HSION", + "value": "100" + }, + { + "key": "MSIRANGE", + "value": "00000060" + }, + { + "key": "MSIRGSEL", + "value": "0" + }, + { + "key": "MSIPLLEN", + "value": "0" + }, + { + "key": "MSION", + "value": "0" + } + ], + "key": "RCC_CR" + }, + { + "fields": [ + { + "key": "HSITRIM", + "value": "40000000" + }, + { + "key": "MSITRIM", + "value": "00000000" + } + ], + "key": "RCC_ICSCR" + }, + { + "fields": [ + { + "key": "MCOSEL", + "value": "00000000" + }, + { + "key": "STOPWUCK", + "value": "00000000" + }, + { + "key": "PPRE2", + "value": "00000000" + }, + { + "key": "PPRE1", + "value": "00000000" + }, + { + "key": "HPRE", + "value": "00000000" + }, + { + "key": "SW", + "value": "3" + } + ], + "key": "RCC_CFGR" + }, + { + "fields": [ + { + "key": "PLLPDIV", + "value": "00000000" + }, + { + "key": "PLLR", + "value": "00000000" + }, + { + "key": "PLLREN", + "value": "00000000" + }, + { + "key": "PLLQ", + "value": "00000000" + }, + { + "key": "PLLQEN", + "value": "00000000" + }, + { + "key": "PLLP", + "value": "00000000" + }, + { + "key": "PLLPEN", + "value": "00000000" + }, + { + "key": "PLLN", + "value": "00000f00" + }, + { + "key": "PLLM", + "value": "00000000" + }, + { + "key": "PLLSRC", + "value": "2" + } + ], + "key": "RCC_PLLCFGR" + }, + { + "fields": [ + { + "key": "LSCOSEL", + "value": "00000000" + }, + { + "key": "LSCOEN", + "value": "00000000" + }, + { + "key": "BDRST", + "value": "00000000" + }, + { + "key": "RTCEN", + "value": "00000000" + }, + { + "key": "RTCSEL", + "value": "00000000" + }, + { + "key": "LSESYSDIS", + "value": "00000000" + }, + { + "key": "LSECSSON", + "value": "00000000" + }, + { + "key": "LSEDRV", + "value": "00000000" + }, + { + "key": "LSEBYP", + "value": "00000000" + }, + { + "key": "LSEON", + "value": "00000000" + } + ], + "key": "RCC_BDCR" + }, + { + "fields": [ + { + "key": "RMVF", + "value": "00000000" + }, + { + "key": "MSISRANGE", + "value": "00000600" + }, + { + "key": "LSIPREDIV", + "value": "00000000" + }, + { + "key": "LSION", + "value": "00000000" + } + ], + "key": "RCC_CSR" + }, + { + "fields": { + "key": "HSI48ON", + "value": "00000000" + }, + "key": "RCC_CRRCR" + } + ] + } +} diff --git a/ARM/gcc_clang/schemas/STM32L4P5ZE/STM32L4P5ZE_CAN.schema b/ARM/gcc_clang/schemas/STM32L4P5ZE/STM32L4P5ZE_CAN.schema new file mode 100644 index 000000000..02b6cd2ff --- /dev/null +++ b/ARM/gcc_clang/schemas/STM32L4P5ZE/STM32L4P5ZE_CAN.schema @@ -0,0 +1,234 @@ +{ + "compiler_flags": "", + "linker_flags": "", + "def_path": "ARM/gcc_clang/def/STM32L4P5ZE.json", + "flash": 0, + "ram": 0, + "settings": { + "clock": "120", + "scheme": "STM32L4P5ZE_CAN", + "mcu": "STM32L4P5ZE", + "core": "M4EF", + "delay_src_path": "delays/m4ef/__lib_delays.c", + "name": null, + "config_registers": [ + { + "fields": [ + { + "key": "PLLSAI2ON", + "value": "0" + }, + { + "key": "PLLSAI1ON", + "value": "0" + }, + { + "key": "PLLON", + "value": "1000000" + }, + { + "key": "CSSON", + "value": "0" + }, + { + "key": "HSEBYP", + "value": "0" + }, + { + "key": "HSEON", + "value": "0" + }, + { + "key": "HSIASFS", + "value": "0" + }, + { + "key": "HSIKERON", + "value": "0" + }, + { + "key": "HSION", + "value": "100" + }, + { + "key": "MSIRANGE", + "value": "00000060" + }, + { + "key": "MSIRGSEL", + "value": "0" + }, + { + "key": "MSIPLLEN", + "value": "0" + }, + { + "key": "MSION", + "value": "0" + } + ], + "key": "RCC_CR" + }, + { + "fields": [ + { + "key": "HSITRIM", + "value": "40000000" + }, + { + "key": "MSITRIM", + "value": "00000000" + } + ], + "key": "RCC_ICSCR" + }, + { + "fields": [ + { + "key": "MCOSEL", + "value": "00000000" + }, + { + "key": "STOPWUCK", + "value": "00000000" + }, + { + "key": "PPRE2", + "value": "00000000" + }, + { + "key": "PPRE1", + "value": "00000000" + }, + { + "key": "HPRE", + "value": "00000000" + }, + { + "key": "SW", + "value": "3" + } + ], + "key": "RCC_CFGR" + }, + { + "fields": [ + { + "key": "PLLPDIV", + "value": "00000000" + }, + { + "key": "PLLR", + "value": "00000000" + }, + { + "key": "PLLREN", + "value": "00000000" + }, + { + "key": "PLLQ", + "value": "00000000" + }, + { + "key": "PLLQEN", + "value": "00000000" + }, + { + "key": "PLLP", + "value": "00000000" + }, + { + "key": "PLLPEN", + "value": "00000000" + }, + { + "key": "PLLN", + "value": "00000f00" + }, + { + "key": "PLLM", + "value": "00000000" + }, + { + "key": "PLLSRC", + "value": "2" + } + ], + "key": "RCC_PLLCFGR" + }, + { + "fields": [ + { + "key": "LSCOSEL", + "value": "00000000" + }, + { + "key": "LSCOEN", + "value": "00000000" + }, + { + "key": "BDRST", + "value": "00000000" + }, + { + "key": "RTCEN", + "value": "00000000" + }, + { + "key": "RTCSEL", + "value": "00000000" + }, + { + "key": "LSESYSDIS", + "value": "00000000" + }, + { + "key": "LSECSSON", + "value": "00000000" + }, + { + "key": "LSEDRV", + "value": "00000000" + }, + { + "key": "LSEBYP", + "value": "00000000" + }, + { + "key": "LSEON", + "value": "00000000" + } + ], + "key": "RCC_BDCR" + }, + { + "fields": [ + { + "key": "RMVF", + "value": "00000000" + }, + { + "key": "MSISRANGE", + "value": "00000600" + }, + { + "key": "LSIPREDIV", + "value": "00000000" + }, + { + "key": "LSION", + "value": "00000000" + } + ], + "key": "RCC_CSR" + }, + { + "fields": { + "key": "HSI48ON", + "value": "00000000" + }, + "key": "RCC_CRRCR" + } + ] + } +} diff --git a/ARM/gcc_clang/schemas/STM32L4P5ZG/STM32L4P5ZG_CAN.schema b/ARM/gcc_clang/schemas/STM32L4P5ZG/STM32L4P5ZG_CAN.schema new file mode 100644 index 000000000..8442b71a4 --- /dev/null +++ b/ARM/gcc_clang/schemas/STM32L4P5ZG/STM32L4P5ZG_CAN.schema @@ -0,0 +1,234 @@ +{ + "compiler_flags": "", + "linker_flags": "", + "def_path": "ARM/gcc_clang/def/STM32L4P5ZG.json", + "flash": 0, + "ram": 0, + "settings": { + "clock": "120", + "scheme": "STM32L4P5ZG_CAN", + "mcu": "STM32L4P5ZG", + "core": "M4EF", + "delay_src_path": "delays/m4ef/__lib_delays.c", + "name": null, + "config_registers": [ + { + "fields": [ + { + "key": "PLLSAI2ON", + "value": "0" + }, + { + "key": "PLLSAI1ON", + "value": "0" + }, + { + "key": "PLLON", + "value": "1000000" + }, + { + "key": "CSSON", + "value": "0" + }, + { + "key": "HSEBYP", + "value": "0" + }, + { + "key": "HSEON", + "value": "0" + }, + { + "key": "HSIASFS", + "value": "0" + }, + { + "key": "HSIKERON", + "value": "0" + }, + { + "key": "HSION", + "value": "100" + }, + { + "key": "MSIRANGE", + "value": "00000060" + }, + { + "key": "MSIRGSEL", + "value": "0" + }, + { + "key": "MSIPLLEN", + "value": "0" + }, + { + "key": "MSION", + "value": "0" + } + ], + "key": "RCC_CR" + }, + { + "fields": [ + { + "key": "HSITRIM", + "value": "40000000" + }, + { + "key": "MSITRIM", + "value": "00000000" + } + ], + "key": "RCC_ICSCR" + }, + { + "fields": [ + { + "key": "MCOSEL", + "value": "00000000" + }, + { + "key": "STOPWUCK", + "value": "00000000" + }, + { + "key": "PPRE2", + "value": "00000000" + }, + { + "key": "PPRE1", + "value": "00000000" + }, + { + "key": "HPRE", + "value": "00000000" + }, + { + "key": "SW", + "value": "3" + } + ], + "key": "RCC_CFGR" + }, + { + "fields": [ + { + "key": "PLLPDIV", + "value": "00000000" + }, + { + "key": "PLLR", + "value": "00000000" + }, + { + "key": "PLLREN", + "value": "00000000" + }, + { + "key": "PLLQ", + "value": "00000000" + }, + { + "key": "PLLQEN", + "value": "00000000" + }, + { + "key": "PLLP", + "value": "00000000" + }, + { + "key": "PLLPEN", + "value": "00000000" + }, + { + "key": "PLLN", + "value": "00000f00" + }, + { + "key": "PLLM", + "value": "00000000" + }, + { + "key": "PLLSRC", + "value": "2" + } + ], + "key": "RCC_PLLCFGR" + }, + { + "fields": [ + { + "key": "LSCOSEL", + "value": "00000000" + }, + { + "key": "LSCOEN", + "value": "00000000" + }, + { + "key": "BDRST", + "value": "00000000" + }, + { + "key": "RTCEN", + "value": "00000000" + }, + { + "key": "RTCSEL", + "value": "00000000" + }, + { + "key": "LSESYSDIS", + "value": "00000000" + }, + { + "key": "LSECSSON", + "value": "00000000" + }, + { + "key": "LSEDRV", + "value": "00000000" + }, + { + "key": "LSEBYP", + "value": "00000000" + }, + { + "key": "LSEON", + "value": "00000000" + } + ], + "key": "RCC_BDCR" + }, + { + "fields": [ + { + "key": "RMVF", + "value": "00000000" + }, + { + "key": "MSISRANGE", + "value": "00000600" + }, + { + "key": "LSIPREDIV", + "value": "00000000" + }, + { + "key": "LSION", + "value": "00000000" + } + ], + "key": "RCC_CSR" + }, + { + "fields": { + "key": "HSI48ON", + "value": "00000000" + }, + "key": "RCC_CRRCR" + } + ] + } +} diff --git a/ARM/gcc_clang/schemas/STM32L4Q5AG/STM32L4Q5AG_CAN.schema b/ARM/gcc_clang/schemas/STM32L4Q5AG/STM32L4Q5AG_CAN.schema new file mode 100644 index 000000000..a00b2bd6a --- /dev/null +++ b/ARM/gcc_clang/schemas/STM32L4Q5AG/STM32L4Q5AG_CAN.schema @@ -0,0 +1,234 @@ +{ + "compiler_flags": "", + "linker_flags": "", + "def_path": "ARM/gcc_clang/def/STM32L4Q5AG.json", + "flash": 0, + "ram": 0, + "settings": { + "clock": "120", + "scheme": "STM32L4Q5AG_CAN", + "mcu": "STM32L4Q5AG", + "core": "M4EF", + "delay_src_path": "delays/m4ef/__lib_delays.c", + "name": null, + "config_registers": [ + { + "fields": [ + { + "key": "PLLSAI2ON", + "value": "0" + }, + { + "key": "PLLSAI1ON", + "value": "0" + }, + { + "key": "PLLON", + "value": "1000000" + }, + { + "key": "CSSON", + "value": "0" + }, + { + "key": "HSEBYP", + "value": "0" + }, + { + "key": "HSEON", + "value": "0" + }, + { + "key": "HSIASFS", + "value": "0" + }, + { + "key": "HSIKERON", + "value": "0" + }, + { + "key": "HSION", + "value": "100" + }, + { + "key": "MSIRANGE", + "value": "00000060" + }, + { + "key": "MSIRGSEL", + "value": "0" + }, + { + "key": "MSIPLLEN", + "value": "0" + }, + { + "key": "MSION", + "value": "0" + } + ], + "key": "RCC_CR" + }, + { + "fields": [ + { + "key": "HSITRIM", + "value": "40000000" + }, + { + "key": "MSITRIM", + "value": "00000000" + } + ], + "key": "RCC_ICSCR" + }, + { + "fields": [ + { + "key": "MCOSEL", + "value": "00000000" + }, + { + "key": "STOPWUCK", + "value": "00000000" + }, + { + "key": "PPRE2", + "value": "00000000" + }, + { + "key": "PPRE1", + "value": "00000000" + }, + { + "key": "HPRE", + "value": "00000000" + }, + { + "key": "SW", + "value": "3" + } + ], + "key": "RCC_CFGR" + }, + { + "fields": [ + { + "key": "PLLPDIV", + "value": "00000000" + }, + { + "key": "PLLR", + "value": "00000000" + }, + { + "key": "PLLREN", + "value": "00000000" + }, + { + "key": "PLLQ", + "value": "00000000" + }, + { + "key": "PLLQEN", + "value": "00000000" + }, + { + "key": "PLLP", + "value": "00000000" + }, + { + "key": "PLLPEN", + "value": "00000000" + }, + { + "key": "PLLN", + "value": "00000f00" + }, + { + "key": "PLLM", + "value": "00000000" + }, + { + "key": "PLLSRC", + "value": "2" + } + ], + "key": "RCC_PLLCFGR" + }, + { + "fields": [ + { + "key": "LSCOSEL", + "value": "00000000" + }, + { + "key": "LSCOEN", + "value": "00000000" + }, + { + "key": "BDRST", + "value": "00000000" + }, + { + "key": "RTCEN", + "value": "00000000" + }, + { + "key": "RTCSEL", + "value": "00000000" + }, + { + "key": "LSESYSDIS", + "value": "00000000" + }, + { + "key": "LSECSSON", + "value": "00000000" + }, + { + "key": "LSEDRV", + "value": "00000000" + }, + { + "key": "LSEBYP", + "value": "00000000" + }, + { + "key": "LSEON", + "value": "00000000" + } + ], + "key": "RCC_BDCR" + }, + { + "fields": [ + { + "key": "RMVF", + "value": "00000000" + }, + { + "key": "MSISRANGE", + "value": "00000600" + }, + { + "key": "LSIPREDIV", + "value": "00000000" + }, + { + "key": "LSION", + "value": "00000000" + } + ], + "key": "RCC_CSR" + }, + { + "fields": { + "key": "HSI48ON", + "value": "00000000" + }, + "key": "RCC_CRRCR" + } + ] + } +} diff --git a/ARM/gcc_clang/schemas/STM32L4Q5CG/STM32L4Q5CG_CAN.schema b/ARM/gcc_clang/schemas/STM32L4Q5CG/STM32L4Q5CG_CAN.schema new file mode 100644 index 000000000..20fe0c27f --- /dev/null +++ b/ARM/gcc_clang/schemas/STM32L4Q5CG/STM32L4Q5CG_CAN.schema @@ -0,0 +1,234 @@ +{ + "compiler_flags": "", + "linker_flags": "", + "def_path": "ARM/gcc_clang/def/STM32L4Q5CG.json", + "flash": 0, + "ram": 0, + "settings": { + "clock": "120", + "scheme": "STM32L4Q5CG_CAN", + "mcu": "STM32L4Q5CG", + "core": "M4EF", + "delay_src_path": "delays/m4ef/__lib_delays.c", + "name": null, + "config_registers": [ + { + "fields": [ + { + "key": "PLLSAI2ON", + "value": "0" + }, + { + "key": "PLLSAI1ON", + "value": "0" + }, + { + "key": "PLLON", + "value": "1000000" + }, + { + "key": "CSSON", + "value": "0" + }, + { + "key": "HSEBYP", + "value": "0" + }, + { + "key": "HSEON", + "value": "0" + }, + { + "key": "HSIASFS", + "value": "0" + }, + { + "key": "HSIKERON", + "value": "0" + }, + { + "key": "HSION", + "value": "100" + }, + { + "key": "MSIRANGE", + "value": "00000060" + }, + { + "key": "MSIRGSEL", + "value": "0" + }, + { + "key": "MSIPLLEN", + "value": "0" + }, + { + "key": "MSION", + "value": "0" + } + ], + "key": "RCC_CR" + }, + { + "fields": [ + { + "key": "HSITRIM", + "value": "40000000" + }, + { + "key": "MSITRIM", + "value": "00000000" + } + ], + "key": "RCC_ICSCR" + }, + { + "fields": [ + { + "key": "MCOSEL", + "value": "00000000" + }, + { + "key": "STOPWUCK", + "value": "00000000" + }, + { + "key": "PPRE2", + "value": "00000000" + }, + { + "key": "PPRE1", + "value": "00000000" + }, + { + "key": "HPRE", + "value": "00000000" + }, + { + "key": "SW", + "value": "3" + } + ], + "key": "RCC_CFGR" + }, + { + "fields": [ + { + "key": "PLLPDIV", + "value": "00000000" + }, + { + "key": "PLLR", + "value": "00000000" + }, + { + "key": "PLLREN", + "value": "00000000" + }, + { + "key": "PLLQ", + "value": "00000000" + }, + { + "key": "PLLQEN", + "value": "00000000" + }, + { + "key": "PLLP", + "value": "00000000" + }, + { + "key": "PLLPEN", + "value": "00000000" + }, + { + "key": "PLLN", + "value": "00000f00" + }, + { + "key": "PLLM", + "value": "00000000" + }, + { + "key": "PLLSRC", + "value": "2" + } + ], + "key": "RCC_PLLCFGR" + }, + { + "fields": [ + { + "key": "LSCOSEL", + "value": "00000000" + }, + { + "key": "LSCOEN", + "value": "00000000" + }, + { + "key": "BDRST", + "value": "00000000" + }, + { + "key": "RTCEN", + "value": "00000000" + }, + { + "key": "RTCSEL", + "value": "00000000" + }, + { + "key": "LSESYSDIS", + "value": "00000000" + }, + { + "key": "LSECSSON", + "value": "00000000" + }, + { + "key": "LSEDRV", + "value": "00000000" + }, + { + "key": "LSEBYP", + "value": "00000000" + }, + { + "key": "LSEON", + "value": "00000000" + } + ], + "key": "RCC_BDCR" + }, + { + "fields": [ + { + "key": "RMVF", + "value": "00000000" + }, + { + "key": "MSISRANGE", + "value": "00000600" + }, + { + "key": "LSIPREDIV", + "value": "00000000" + }, + { + "key": "LSION", + "value": "00000000" + } + ], + "key": "RCC_CSR" + }, + { + "fields": { + "key": "HSI48ON", + "value": "00000000" + }, + "key": "RCC_CRRCR" + } + ] + } +} diff --git a/ARM/gcc_clang/schemas/STM32L4Q5QG/STM32L4Q5QG_CAN.schema b/ARM/gcc_clang/schemas/STM32L4Q5QG/STM32L4Q5QG_CAN.schema new file mode 100644 index 000000000..c8d41bd09 --- /dev/null +++ b/ARM/gcc_clang/schemas/STM32L4Q5QG/STM32L4Q5QG_CAN.schema @@ -0,0 +1,234 @@ +{ + "compiler_flags": "", + "linker_flags": "", + "def_path": "ARM/gcc_clang/def/STM32L4Q5QG.json", + "flash": 0, + "ram": 0, + "settings": { + "clock": "120", + "scheme": "STM32L4Q5QG_CAN", + "mcu": "STM32L4Q5QG", + "core": "M4EF", + "delay_src_path": "delays/m4ef/__lib_delays.c", + "name": null, + "config_registers": [ + { + "fields": [ + { + "key": "PLLSAI2ON", + "value": "0" + }, + { + "key": "PLLSAI1ON", + "value": "0" + }, + { + "key": "PLLON", + "value": "1000000" + }, + { + "key": "CSSON", + "value": "0" + }, + { + "key": "HSEBYP", + "value": "0" + }, + { + "key": "HSEON", + "value": "0" + }, + { + "key": "HSIASFS", + "value": "0" + }, + { + "key": "HSIKERON", + "value": "0" + }, + { + "key": "HSION", + "value": "100" + }, + { + "key": "MSIRANGE", + "value": "00000060" + }, + { + "key": "MSIRGSEL", + "value": "0" + }, + { + "key": "MSIPLLEN", + "value": "0" + }, + { + "key": "MSION", + "value": "0" + } + ], + "key": "RCC_CR" + }, + { + "fields": [ + { + "key": "HSITRIM", + "value": "40000000" + }, + { + "key": "MSITRIM", + "value": "00000000" + } + ], + "key": "RCC_ICSCR" + }, + { + "fields": [ + { + "key": "MCOSEL", + "value": "00000000" + }, + { + "key": "STOPWUCK", + "value": "00000000" + }, + { + "key": "PPRE2", + "value": "00000000" + }, + { + "key": "PPRE1", + "value": "00000000" + }, + { + "key": "HPRE", + "value": "00000000" + }, + { + "key": "SW", + "value": "3" + } + ], + "key": "RCC_CFGR" + }, + { + "fields": [ + { + "key": "PLLPDIV", + "value": "00000000" + }, + { + "key": "PLLR", + "value": "00000000" + }, + { + "key": "PLLREN", + "value": "00000000" + }, + { + "key": "PLLQ", + "value": "00000000" + }, + { + "key": "PLLQEN", + "value": "00000000" + }, + { + "key": "PLLP", + "value": "00000000" + }, + { + "key": "PLLPEN", + "value": "00000000" + }, + { + "key": "PLLN", + "value": "00000f00" + }, + { + "key": "PLLM", + "value": "00000000" + }, + { + "key": "PLLSRC", + "value": "2" + } + ], + "key": "RCC_PLLCFGR" + }, + { + "fields": [ + { + "key": "LSCOSEL", + "value": "00000000" + }, + { + "key": "LSCOEN", + "value": "00000000" + }, + { + "key": "BDRST", + "value": "00000000" + }, + { + "key": "RTCEN", + "value": "00000000" + }, + { + "key": "RTCSEL", + "value": "00000000" + }, + { + "key": "LSESYSDIS", + "value": "00000000" + }, + { + "key": "LSECSSON", + "value": "00000000" + }, + { + "key": "LSEDRV", + "value": "00000000" + }, + { + "key": "LSEBYP", + "value": "00000000" + }, + { + "key": "LSEON", + "value": "00000000" + } + ], + "key": "RCC_BDCR" + }, + { + "fields": [ + { + "key": "RMVF", + "value": "00000000" + }, + { + "key": "MSISRANGE", + "value": "00000600" + }, + { + "key": "LSIPREDIV", + "value": "00000000" + }, + { + "key": "LSION", + "value": "00000000" + } + ], + "key": "RCC_CSR" + }, + { + "fields": { + "key": "HSI48ON", + "value": "00000000" + }, + "key": "RCC_CRRCR" + } + ] + } +} diff --git a/ARM/gcc_clang/schemas/STM32L4Q5RG/STM32L4Q5RG_CAN.schema b/ARM/gcc_clang/schemas/STM32L4Q5RG/STM32L4Q5RG_CAN.schema new file mode 100644 index 000000000..f51b9061f --- /dev/null +++ b/ARM/gcc_clang/schemas/STM32L4Q5RG/STM32L4Q5RG_CAN.schema @@ -0,0 +1,234 @@ +{ + "compiler_flags": "", + "linker_flags": "", + "def_path": "ARM/gcc_clang/def/STM32L4Q5RG.json", + "flash": 0, + "ram": 0, + "settings": { + "clock": "120", + "scheme": "STM32L4Q5RG_CAN", + "mcu": "STM32L4Q5RG", + "core": "M4EF", + "delay_src_path": "delays/m4ef/__lib_delays.c", + "name": null, + "config_registers": [ + { + "fields": [ + { + "key": "PLLSAI2ON", + "value": "0" + }, + { + "key": "PLLSAI1ON", + "value": "0" + }, + { + "key": "PLLON", + "value": "1000000" + }, + { + "key": "CSSON", + "value": "0" + }, + { + "key": "HSEBYP", + "value": "0" + }, + { + "key": "HSEON", + "value": "0" + }, + { + "key": "HSIASFS", + "value": "0" + }, + { + "key": "HSIKERON", + "value": "0" + }, + { + "key": "HSION", + "value": "100" + }, + { + "key": "MSIRANGE", + "value": "00000060" + }, + { + "key": "MSIRGSEL", + "value": "0" + }, + { + "key": "MSIPLLEN", + "value": "0" + }, + { + "key": "MSION", + "value": "0" + } + ], + "key": "RCC_CR" + }, + { + "fields": [ + { + "key": "HSITRIM", + "value": "40000000" + }, + { + "key": "MSITRIM", + "value": "00000000" + } + ], + "key": "RCC_ICSCR" + }, + { + "fields": [ + { + "key": "MCOSEL", + "value": "00000000" + }, + { + "key": "STOPWUCK", + "value": "00000000" + }, + { + "key": "PPRE2", + "value": "00000000" + }, + { + "key": "PPRE1", + "value": "00000000" + }, + { + "key": "HPRE", + "value": "00000000" + }, + { + "key": "SW", + "value": "3" + } + ], + "key": "RCC_CFGR" + }, + { + "fields": [ + { + "key": "PLLPDIV", + "value": "00000000" + }, + { + "key": "PLLR", + "value": "00000000" + }, + { + "key": "PLLREN", + "value": "00000000" + }, + { + "key": "PLLQ", + "value": "00000000" + }, + { + "key": "PLLQEN", + "value": "00000000" + }, + { + "key": "PLLP", + "value": "00000000" + }, + { + "key": "PLLPEN", + "value": "00000000" + }, + { + "key": "PLLN", + "value": "00000f00" + }, + { + "key": "PLLM", + "value": "00000000" + }, + { + "key": "PLLSRC", + "value": "2" + } + ], + "key": "RCC_PLLCFGR" + }, + { + "fields": [ + { + "key": "LSCOSEL", + "value": "00000000" + }, + { + "key": "LSCOEN", + "value": "00000000" + }, + { + "key": "BDRST", + "value": "00000000" + }, + { + "key": "RTCEN", + "value": "00000000" + }, + { + "key": "RTCSEL", + "value": "00000000" + }, + { + "key": "LSESYSDIS", + "value": "00000000" + }, + { + "key": "LSECSSON", + "value": "00000000" + }, + { + "key": "LSEDRV", + "value": "00000000" + }, + { + "key": "LSEBYP", + "value": "00000000" + }, + { + "key": "LSEON", + "value": "00000000" + } + ], + "key": "RCC_BDCR" + }, + { + "fields": [ + { + "key": "RMVF", + "value": "00000000" + }, + { + "key": "MSISRANGE", + "value": "00000600" + }, + { + "key": "LSIPREDIV", + "value": "00000000" + }, + { + "key": "LSION", + "value": "00000000" + } + ], + "key": "RCC_CSR" + }, + { + "fields": { + "key": "HSI48ON", + "value": "00000000" + }, + "key": "RCC_CRRCR" + } + ] + } +} diff --git a/ARM/gcc_clang/schemas/STM32L4Q5VG/STM32L4Q5VG_CAN.schema b/ARM/gcc_clang/schemas/STM32L4Q5VG/STM32L4Q5VG_CAN.schema new file mode 100644 index 000000000..de49c50be --- /dev/null +++ b/ARM/gcc_clang/schemas/STM32L4Q5VG/STM32L4Q5VG_CAN.schema @@ -0,0 +1,234 @@ +{ + "compiler_flags": "", + "linker_flags": "", + "def_path": "ARM/gcc_clang/def/STM32L4Q5VG.json", + "flash": 0, + "ram": 0, + "settings": { + "clock": "120", + "scheme": "STM32L4Q5VG_CAN", + "mcu": "STM32L4Q5VG", + "core": "M4EF", + "delay_src_path": "delays/m4ef/__lib_delays.c", + "name": null, + "config_registers": [ + { + "fields": [ + { + "key": "PLLSAI2ON", + "value": "0" + }, + { + "key": "PLLSAI1ON", + "value": "0" + }, + { + "key": "PLLON", + "value": "1000000" + }, + { + "key": "CSSON", + "value": "0" + }, + { + "key": "HSEBYP", + "value": "0" + }, + { + "key": "HSEON", + "value": "0" + }, + { + "key": "HSIASFS", + "value": "0" + }, + { + "key": "HSIKERON", + "value": "0" + }, + { + "key": "HSION", + "value": "100" + }, + { + "key": "MSIRANGE", + "value": "00000060" + }, + { + "key": "MSIRGSEL", + "value": "0" + }, + { + "key": "MSIPLLEN", + "value": "0" + }, + { + "key": "MSION", + "value": "0" + } + ], + "key": "RCC_CR" + }, + { + "fields": [ + { + "key": "HSITRIM", + "value": "40000000" + }, + { + "key": "MSITRIM", + "value": "00000000" + } + ], + "key": "RCC_ICSCR" + }, + { + "fields": [ + { + "key": "MCOSEL", + "value": "00000000" + }, + { + "key": "STOPWUCK", + "value": "00000000" + }, + { + "key": "PPRE2", + "value": "00000000" + }, + { + "key": "PPRE1", + "value": "00000000" + }, + { + "key": "HPRE", + "value": "00000000" + }, + { + "key": "SW", + "value": "3" + } + ], + "key": "RCC_CFGR" + }, + { + "fields": [ + { + "key": "PLLPDIV", + "value": "00000000" + }, + { + "key": "PLLR", + "value": "00000000" + }, + { + "key": "PLLREN", + "value": "00000000" + }, + { + "key": "PLLQ", + "value": "00000000" + }, + { + "key": "PLLQEN", + "value": "00000000" + }, + { + "key": "PLLP", + "value": "00000000" + }, + { + "key": "PLLPEN", + "value": "00000000" + }, + { + "key": "PLLN", + "value": "00000f00" + }, + { + "key": "PLLM", + "value": "00000000" + }, + { + "key": "PLLSRC", + "value": "2" + } + ], + "key": "RCC_PLLCFGR" + }, + { + "fields": [ + { + "key": "LSCOSEL", + "value": "00000000" + }, + { + "key": "LSCOEN", + "value": "00000000" + }, + { + "key": "BDRST", + "value": "00000000" + }, + { + "key": "RTCEN", + "value": "00000000" + }, + { + "key": "RTCSEL", + "value": "00000000" + }, + { + "key": "LSESYSDIS", + "value": "00000000" + }, + { + "key": "LSECSSON", + "value": "00000000" + }, + { + "key": "LSEDRV", + "value": "00000000" + }, + { + "key": "LSEBYP", + "value": "00000000" + }, + { + "key": "LSEON", + "value": "00000000" + } + ], + "key": "RCC_BDCR" + }, + { + "fields": [ + { + "key": "RMVF", + "value": "00000000" + }, + { + "key": "MSISRANGE", + "value": "00000600" + }, + { + "key": "LSIPREDIV", + "value": "00000000" + }, + { + "key": "LSION", + "value": "00000000" + } + ], + "key": "RCC_CSR" + }, + { + "fields": { + "key": "HSI48ON", + "value": "00000000" + }, + "key": "RCC_CRRCR" + } + ] + } +} diff --git a/ARM/gcc_clang/schemas/STM32L4Q5ZG/STM32L4Q5ZG_CAN.schema b/ARM/gcc_clang/schemas/STM32L4Q5ZG/STM32L4Q5ZG_CAN.schema new file mode 100644 index 000000000..0d239442e --- /dev/null +++ b/ARM/gcc_clang/schemas/STM32L4Q5ZG/STM32L4Q5ZG_CAN.schema @@ -0,0 +1,234 @@ +{ + "compiler_flags": "", + "linker_flags": "", + "def_path": "ARM/gcc_clang/def/STM32L4Q5ZG.json", + "flash": 0, + "ram": 0, + "settings": { + "clock": "120", + "scheme": "STM32L4Q5ZG_CAN", + "mcu": "STM32L4Q5ZG", + "core": "M4EF", + "delay_src_path": "delays/m4ef/__lib_delays.c", + "name": null, + "config_registers": [ + { + "fields": [ + { + "key": "PLLSAI2ON", + "value": "0" + }, + { + "key": "PLLSAI1ON", + "value": "0" + }, + { + "key": "PLLON", + "value": "1000000" + }, + { + "key": "CSSON", + "value": "0" + }, + { + "key": "HSEBYP", + "value": "0" + }, + { + "key": "HSEON", + "value": "0" + }, + { + "key": "HSIASFS", + "value": "0" + }, + { + "key": "HSIKERON", + "value": "0" + }, + { + "key": "HSION", + "value": "100" + }, + { + "key": "MSIRANGE", + "value": "00000060" + }, + { + "key": "MSIRGSEL", + "value": "0" + }, + { + "key": "MSIPLLEN", + "value": "0" + }, + { + "key": "MSION", + "value": "0" + } + ], + "key": "RCC_CR" + }, + { + "fields": [ + { + "key": "HSITRIM", + "value": "40000000" + }, + { + "key": "MSITRIM", + "value": "00000000" + } + ], + "key": "RCC_ICSCR" + }, + { + "fields": [ + { + "key": "MCOSEL", + "value": "00000000" + }, + { + "key": "STOPWUCK", + "value": "00000000" + }, + { + "key": "PPRE2", + "value": "00000000" + }, + { + "key": "PPRE1", + "value": "00000000" + }, + { + "key": "HPRE", + "value": "00000000" + }, + { + "key": "SW", + "value": "3" + } + ], + "key": "RCC_CFGR" + }, + { + "fields": [ + { + "key": "PLLPDIV", + "value": "00000000" + }, + { + "key": "PLLR", + "value": "00000000" + }, + { + "key": "PLLREN", + "value": "00000000" + }, + { + "key": "PLLQ", + "value": "00000000" + }, + { + "key": "PLLQEN", + "value": "00000000" + }, + { + "key": "PLLP", + "value": "00000000" + }, + { + "key": "PLLPEN", + "value": "00000000" + }, + { + "key": "PLLN", + "value": "00000f00" + }, + { + "key": "PLLM", + "value": "00000000" + }, + { + "key": "PLLSRC", + "value": "2" + } + ], + "key": "RCC_PLLCFGR" + }, + { + "fields": [ + { + "key": "LSCOSEL", + "value": "00000000" + }, + { + "key": "LSCOEN", + "value": "00000000" + }, + { + "key": "BDRST", + "value": "00000000" + }, + { + "key": "RTCEN", + "value": "00000000" + }, + { + "key": "RTCSEL", + "value": "00000000" + }, + { + "key": "LSESYSDIS", + "value": "00000000" + }, + { + "key": "LSECSSON", + "value": "00000000" + }, + { + "key": "LSEDRV", + "value": "00000000" + }, + { + "key": "LSEBYP", + "value": "00000000" + }, + { + "key": "LSEON", + "value": "00000000" + } + ], + "key": "RCC_BDCR" + }, + { + "fields": [ + { + "key": "RMVF", + "value": "00000000" + }, + { + "key": "MSISRANGE", + "value": "00000600" + }, + { + "key": "LSIPREDIV", + "value": "00000000" + }, + { + "key": "LSION", + "value": "00000000" + } + ], + "key": "RCC_CSR" + }, + { + "fields": { + "key": "HSI48ON", + "value": "00000000" + }, + "key": "RCC_CRRCR" + } + ] + } +}