From 40e4c7ef7ff13c7220add95a8db0cb5199b283cf Mon Sep 17 00:00:00 2001 From: Maxpicca-Li Date: Thu, 28 Jul 2022 14:28:46 +0800 Subject: [PATCH] let forward_top in D and hi, lo, cp0_data be selected in E wns = 0.027ns, tns = 0.000ns, maxLevel = 0, clk-paths = bram access --- 2id/forward_mux.sv | 39 --- 2id/forward_top.sv | 107 -------- datapath.sv | 232 +++++++++--------- .../alu_res_select.sv | 9 +- util/forward_mux.sv | 41 ++++ util/forward_top.sv | 126 ++++++++++ 6 files changed, 288 insertions(+), 266 deletions(-) delete mode 100644 2id/forward_mux.sv delete mode 100644 2id/forward_top.sv rename 4mem/alu_res_selectM.sv => util/alu_res_select.sv (67%) create mode 100644 util/forward_mux.sv create mode 100644 util/forward_top.sv diff --git a/2id/forward_mux.sv b/2id/forward_mux.sv deleted file mode 100644 index 74507eb..0000000 --- a/2id/forward_mux.sv +++ /dev/null @@ -1,39 +0,0 @@ -`timescale 1ns / 1ps - -module forwarding_mux( - input E_slave_reg_wen, - input [ 4:0] E_slave_reg_waddr, - input [31:0] E_slave_reg_wdata, - input E_master_reg_wen, - input [ 4:0] E_master_reg_waddr, - input [31:0] E_master_reg_wdata, - input M_slave_reg_wen, - input [ 4:0] M_slave_reg_waddr, - input [31:0] M_slave_reg_wdata, - input M_master_reg_wen, - input [ 4:0] M_master_reg_waddr, - input [31:0] M_master_reg_wdata, - input [ 4:0] reg_addr, - input [31:0] reg_data, - output logic [31:0] result_data -); - - always_comb begin : get_result - if(|reg_addr) begin - if(E_slave_reg_wen && E_slave_reg_waddr == reg_addr) - result_data = E_slave_reg_wdata; - else if(E_master_reg_wen && E_master_reg_waddr == reg_addr) - result_data = E_master_reg_wdata; - else if(M_slave_reg_wen && M_slave_reg_waddr == reg_addr) - result_data = M_slave_reg_wdata; - else if(M_master_reg_wen && M_master_reg_waddr == reg_addr) - result_data = M_master_reg_wdata; - else - result_data = reg_data; - end - else begin - result_data = 32'd0; - end - end - -endmodule \ No newline at end of file diff --git a/2id/forward_top.sv b/2id/forward_top.sv deleted file mode 100644 index 028ce7f..0000000 --- a/2id/forward_top.sv +++ /dev/null @@ -1,107 +0,0 @@ -`timescale 1ns/1ps -module forward_top( - input E_slave_reg_wen, - input [ 4:0] E_slave_reg_waddr, - input [31:0] E_slave_reg_wdata, - input E_master_reg_wen, - input [ 4:0] E_master_reg_waddr, - input [31:0] E_master_reg_wdata, - input M_slave_reg_wen, - input [ 4:0] M_slave_reg_waddr, - input [31:0] M_slave_reg_wdata, - input M_master_reg_wen, - input [ 4:0] M_master_reg_waddr, - input [31:0] M_master_reg_wdata, - - input [ 4:0] D_master_rs, - input [31:0] D_master_rs_data, - output logic [31:0] D_master_rs_value, - input [ 4:0] D_master_rt, - input [31:0] D_master_rt_data, - output logic [31:0] D_master_rt_value, - - input [ 4:0] D_slave_rs, - input [31:0] D_slave_rs_data, - output logic [31:0] D_slave_rs_value, - input [ 4:0] D_slave_rt, - input [31:0] D_slave_rt_data, - output logic [31:0] D_slave_rt_value - -); - -forwarding_mux forwarding_mux_rs_master( - //ports - .E_slave_reg_wen ( E_slave_reg_wen ), - .E_slave_reg_waddr ( E_slave_reg_waddr ), - .E_slave_reg_wdata ( E_slave_reg_wdata ), - .E_master_reg_wen ( E_master_reg_wen ), - .E_master_reg_waddr ( E_master_reg_waddr ), - .E_master_reg_wdata ( E_master_reg_wdata ), - .M_slave_reg_wen ( M_slave_reg_wen ), - .M_slave_reg_waddr ( M_slave_reg_waddr ), - .M_slave_reg_wdata ( M_slave_reg_wdata ), - .M_master_reg_wen ( M_master_reg_wen ), - .M_master_reg_waddr ( M_master_reg_waddr ), - .M_master_reg_wdata ( M_master_reg_wdata ), - .reg_addr ( D_master_rs ), - .reg_data ( D_master_rs_data ), - .result_data ( D_master_rs_value) -); - -forwarding_mux forwarding_mux_rt_master( - //ports - .E_slave_reg_wen ( E_slave_reg_wen ), - .E_slave_reg_waddr ( E_slave_reg_waddr ), - .E_slave_reg_wdata ( E_slave_reg_wdata ), - .E_master_reg_wen ( E_master_reg_wen ), - .E_master_reg_waddr ( E_master_reg_waddr ), - .E_master_reg_wdata ( E_master_reg_wdata ), - .M_slave_reg_wen ( M_slave_reg_wen ), - .M_slave_reg_waddr ( M_slave_reg_waddr ), - .M_slave_reg_wdata ( M_slave_reg_wdata ), - .M_master_reg_wen ( M_master_reg_wen ), - .M_master_reg_waddr ( M_master_reg_waddr ), - .M_master_reg_wdata ( M_master_reg_wdata ), - .reg_addr ( D_master_rt ), - .reg_data ( D_master_rt_data ), - .result_data ( D_master_rt_value ) -); - -forwarding_mux forwarding_mux_rs_slave( - //ports - .E_slave_reg_wen ( E_slave_reg_wen ), - .E_slave_reg_waddr ( E_slave_reg_waddr ), - .E_slave_reg_wdata ( E_slave_reg_wdata ), - .E_master_reg_wen ( E_master_reg_wen ), - .E_master_reg_waddr ( E_master_reg_waddr ), - .E_master_reg_wdata ( E_master_reg_wdata ), - .M_slave_reg_wen ( M_slave_reg_wen ), - .M_slave_reg_waddr ( M_slave_reg_waddr ), - .M_slave_reg_wdata ( M_slave_reg_wdata ), - .M_master_reg_wen ( M_master_reg_wen ), - .M_master_reg_waddr ( M_master_reg_waddr ), - .M_master_reg_wdata ( M_master_reg_wdata ), - .reg_addr ( D_slave_rs ), - .reg_data ( D_slave_rs_data ), - .result_data ( D_slave_rs_value ) -); - -forwarding_mux forwarding_mux_rt_slave( - //ports - .E_slave_reg_wen ( E_slave_reg_wen ), - .E_slave_reg_waddr ( E_slave_reg_waddr ), - .E_slave_reg_wdata ( E_slave_reg_wdata ), - .E_master_reg_wen ( E_master_reg_wen ), - .E_master_reg_waddr ( E_master_reg_waddr ), - .E_master_reg_wdata ( E_master_reg_wdata ), - .M_slave_reg_wen ( M_slave_reg_wen ), - .M_slave_reg_waddr ( M_slave_reg_waddr ), - .M_slave_reg_wdata ( M_slave_reg_wdata ), - .M_master_reg_wen ( M_master_reg_wen ), - .M_master_reg_waddr ( M_master_reg_waddr ), - .M_master_reg_wdata ( M_master_reg_wdata ), - .reg_addr ( D_slave_rt ), - .reg_data ( D_slave_rt_data ), - .result_data ( D_slave_rt_value ) -); -endmodule \ No newline at end of file diff --git a/datapath.sv b/datapath.sv index 064792b..e52e5f9 100644 --- a/datapath.sv +++ b/datapath.sv @@ -117,8 +117,8 @@ wire D_master_alu_selb ,D_slave_alu_selb ; wire [4:0] D_master_rs ,D_slave_rs ; wire [4:0] D_master_rt ,D_slave_rt ; wire [4:0] D_master_rd ,D_slave_rd ; -wire [31:0] D_master_rs_data ,D_slave_rs_data ; -wire [31:0] D_master_rt_data ,D_slave_rt_data ; +wire [31:0] D_master_rs_value_tmp ,D_slave_rs_value_tmp ; +wire [31:0] D_master_rt_value_tmp ,D_slave_rt_value_tmp ; wire [31:0] D_master_rs_value ,D_slave_rs_value ; wire [31:0] D_master_rt_value ,D_slave_rt_value ; wire D_master_reg_wen ,D_slave_reg_wen ; @@ -175,7 +175,7 @@ wire E_master_alu_sela,E_slave_alu_sela; wire E_master_alu_selb,E_slave_alu_selb; wire [31:0] E_master_alu_srca,E_slave_alu_srca; wire [31:0] E_master_alu_srcb,E_slave_alu_srcb; -wire [31:0] E_master_alu_res_a; +wire [31:0] E_master_alu_res_tmp; wire [31:0] E_master_alu_res ,E_slave_alu_res; wire [31:0] E_master_mem_addr ; wire [63:0] E_master_alu_out64; @@ -385,56 +385,58 @@ decoder u_decoder_slave( regfile u_regfile( //ports - .clk ( clk ), - .rst ( rst ), + .clk ( clk ), + .rst ( rst ), - .ra1_a ( D_master_rs ), - .rd1_a ( D_master_rs_value ), - .ra1_b ( D_master_rt ), - .rd1_b ( D_master_rt_value ), + .ra1_a ( D_master_rs ), + .rd1_a ( D_master_rs_value_tmp ), + .ra1_b ( D_master_rt ), + .rd1_b ( D_master_rt_value_tmp ), .wen1 ( W_master_reg_wen & W_ena & ~(|W_master_except)), // 跟踪异常，该指令出现异常，则不 - .wa1 ( W_master_reg_waddr ), - .wd1 ( W_master_reg_wdata ), + .wa1 ( W_master_reg_waddr ), + .wd1 ( W_master_reg_wdata ), .ra2_a ( D_slave_rs ), - .rd2_a ( D_slave_rs_value ), + .rd2_a ( D_slave_rs_value_tmp ), .ra2_b ( D_slave_rt ), - .rd2_b ( D_slave_rt_value ), + .rd2_b ( D_slave_rt_value_tmp ), .wen2 ( W_slave_reg_wen & W_ena & ~(|W_slave_except)), - .wa2 ( W_slave_reg_waddr ), - .wd2 ( W_slave_reg_wdata ) + .wa2 ( W_slave_reg_waddr ), + .wd2 ( W_slave_reg_wdata ) +); + +// 前推计算结果和访存结果 EM->D +forward_top u_forward_top( + //ports + .alu_wen1 ( E_slave_reg_wen & (!E_slave_memtoReg)), + .alu_waddr1 ( E_slave_reg_waddr ), + .alu_wdata1 ( E_slave_alu_res ), + .alu_wen2 ( E_master_reg_wen & (!E_master_memtoReg)), + .alu_waddr2 ( E_master_reg_waddr ), + .alu_wdata2 ( E_master_alu_res ), + .alu_wen3 ( M_slave_reg_wen & (!M_slave_memtoReg)), + .alu_waddr3 ( M_slave_reg_waddr ), + .alu_wdata3 ( M_slave_alu_res ), + .alu_wen4 ( M_master_reg_wen & (!M_master_memtoReg)), + .alu_waddr4 ( M_master_reg_waddr ), + .alu_wdata4 ( M_master_alu_res ), + .memtoReg ( M_master_memtoReg ), + .mem_waddr ( M_master_reg_waddr ), + .mem_rdata ( M_master_mem_rdata ), + .master_rs ( D_master_rs ), + .master_rs_value_tmp ( D_master_rs_value_tmp ), + .master_rs_value ( D_master_rs_value ), + .master_rt ( D_master_rt ), + .master_rt_value_tmp ( D_master_rt_value_tmp ), + .master_rt_value ( D_master_rt_value ), + .slave_rs ( D_slave_rs ), + .slave_rs_value_tmp ( D_slave_rs_value_tmp ), + .slave_rs_value ( D_slave_rs_value ), + .slave_rt ( D_slave_rt ), + .slave_rt_value_tmp ( D_slave_rt_value_tmp ), + .slave_rt_value ( D_slave_rt_value ) ); -// // 只前推计算结果，访存数据通过stall解决 -// forward_top u_forward_top( -// //ports -// .E_slave_reg_wen ( E_slave_reg_wen & (!E_slave_memtoReg) ), -// .E_slave_reg_waddr ( E_slave_reg_waddr ), -// .E_slave_reg_wdata ( E_slave_alu_res ), -// .E_master_reg_wen ( E_master_reg_wen & (!E_master_memtoReg)), -// .E_master_reg_waddr ( E_master_reg_waddr ), -// .E_master_reg_wdata ( E_master_alu_res ), - -// .M_slave_reg_wen ( M_slave_reg_wen & (!M_slave_memtoReg)), -// .M_slave_reg_waddr ( M_slave_reg_waddr ), -// .M_slave_reg_wdata ( M_slave_alu_res ), -// .M_master_reg_wen ( M_master_reg_wen & (!M_master_memtoReg)), -// .M_master_reg_waddr ( M_master_reg_waddr ), -// .M_master_reg_wdata ( M_master_alu_res ), - -// .D_master_rs ( D_master_rs ), -// .D_master_rs_data ( D_master_rs_data ), -// .D_master_rs_value ( D_master_rs_value ), -// .D_master_rt ( D_master_rt ), -// .D_master_rt_data ( D_master_rt_data ), -// .D_master_rt_value ( D_master_rt_value ), -// .D_slave_rs ( D_slave_rs ), -// .D_slave_rs_data ( D_slave_rs_data ), -// .D_slave_rs_value ( D_slave_rs_value ), -// .D_slave_rt ( D_slave_rt ), -// .D_slave_rt_data ( D_slave_rt_data ), -// .D_slave_rt_value ( D_slave_rt_value ) -// ); // FIXME: 主线访存，一定要控制单发吗？如果满足不冲突条件，可以双发否？ issue_ctrl u_issue_ctrl( @@ -465,7 +467,7 @@ issue_ctrl u_issue_ctrl( // ====================================== Execute ====================================== wire D2E_clear1,D2E_clear2; -wire [31:0] E_master_rs_value_a,E_master_rt_value_a,E_slave_rs_value_a,E_slave_rt_value_a; +// wire [31:0] E_master_rs_value_tmp,E_master_rt_value_tmp,E_slave_rs_value_tmp,E_slave_rt_value_tmp; // 在使能的情况下跳转清空才成立 assign D2E_clear1 = M_except | (!D_master_is_in_delayslot & E_flush & E_ena) | (!D_ena & E_ena); assign D2E_clear2 = M_except | (E_flush & D_slave_ena) || (E_ena & !D_slave_ena); @@ -546,8 +548,8 @@ id_ex u_id_ex( .E_master_j_target ( E_master_j_target ), .E_master_pc ( E_master_pc ), .E_master_inst ( E_master_inst ), - .E_master_rs_value ( E_master_rs_value_a ), - .E_master_rt_value ( E_master_rt_value_a ), + .E_master_rs_value ( E_master_rs_value ), + .E_master_rt_value ( E_master_rt_value ), .E_master_imm_value ( E_master_imm_value ), .E_master_trap_type ( E_master_trap_type ), .E_master_cmov_type ( E_master_cmov_type ), @@ -566,8 +568,8 @@ id_ex u_id_ex( .E_slave_aluop ( E_slave_aluop ), .E_slave_except ( E_slave_except ), .E_slave_inst ( E_slave_inst ), - .E_slave_rs_value ( E_slave_rs_value_a ), - .E_slave_rt_value ( E_slave_rt_value_a ), + .E_slave_rs_value ( E_slave_rs_value ), + .E_slave_rt_value ( E_slave_rt_value ), .E_slave_rs ( E_slave_rs ), .E_slave_rt ( E_slave_rt ), .E_slave_imm_value ( E_slave_imm_value ), @@ -582,36 +584,37 @@ id_ex u_id_ex( // assign E_slave_rs_value = (W_master_memtoReg && ~(|(W_master_reg_waddr ^ E_slave_rs ))) ? W_master_mem_rdata : E_slave_rs_value_a ; // assign E_slave_rt_value = (W_master_memtoReg && ~(|(W_master_reg_waddr ^ E_slave_rt ))) ? W_master_mem_rdata : E_slave_rt_value_a ; -forwardE_top u_forwardE_top( - //ports - .M_slave_alu_wen ( M_slave_reg_wen & (!M_slave_memtoReg)), - .M_slave_alu_waddr ( M_slave_reg_waddr ), - .M_slave_alu_wdata ( M_slave_alu_res ), - .M_master_alu_wen ( M_master_reg_wen & (!M_master_memtoReg)), - .M_master_alu_waddr ( M_master_reg_waddr ), - .M_master_alu_wdata ( M_master_alu_res ), - .W_slave_alu_wen ( W_slave_reg_wen & (!W_slave_memtoReg)), - .W_slave_alu_waddr ( W_slave_reg_waddr ), - .W_slave_alu_wdata ( W_slave_alu_res ), - .W_master_alu_wen ( W_master_reg_wen & (!W_master_memtoReg)), - .W_master_alu_waddr ( W_master_reg_waddr ), - .W_master_alu_wdata ( W_master_alu_res ), - .W_master_memtoReg ( W_master_memtoReg ), - .W_master_mem_waddr ( W_master_reg_waddr ), - .W_master_mem_rdata ( W_master_mem_rdata ), - .E_master_rs ( E_master_rs ), - .E_master_rs_value_a ( E_master_rs_value_a ), - .E_master_rs_value ( E_master_rs_value ), - .E_master_rt ( E_master_rt ), - .E_master_rt_value_a ( E_master_rt_value_a ), - .E_master_rt_value ( E_master_rt_value ), - .E_slave_rs ( E_slave_rs ), - .E_slave_rs_value_a ( E_slave_rs_value_a ), - .E_slave_rs_value ( E_slave_rs_value ), - .E_slave_rt ( E_slave_rt ), - .E_slave_rt_value_a ( E_slave_rt_value_a ), - .E_slave_rt_value ( E_slave_rt_value ) -); +// 前推计算结果和访存结果 MW->E +// forwardE_top u_forwardE_top( +// //ports +// .M_slave_alu_wen ( M_slave_reg_wen & (!M_slave_memtoReg)), +// .M_slave_alu_waddr ( M_slave_reg_waddr ), +// .M_slave_alu_wdata ( M_slave_alu_res ), +// .M_master_alu_wen ( M_master_reg_wen & (!M_master_memtoReg)), +// .M_master_alu_waddr ( M_master_reg_waddr ), +// .M_master_alu_wdata ( M_master_alu_res ), +// .W_slave_alu_wen ( W_slave_reg_wen & (!W_slave_memtoReg)), +// .W_slave_alu_waddr ( W_slave_reg_waddr ), +// .W_slave_alu_wdata ( W_slave_alu_res ), +// .W_master_alu_wen ( W_master_reg_wen & (!W_master_memtoReg)), +// .W_master_alu_waddr ( W_master_reg_waddr ), +// .W_master_alu_wdata ( W_master_alu_res ), +// .W_master_memtoReg ( W_master_memtoReg ), +// .W_master_mem_waddr ( W_master_reg_waddr ), +// .W_master_mem_rdata ( W_master_mem_rdata ), +// .E_master_rs ( E_master_rs ), +// .E_master_rs_value_a ( E_master_rs_value_a ), +// .E_master_rs_value ( E_master_rs_value ), +// .E_master_rt ( E_master_rt ), +// .E_master_rt_value_a ( E_master_rt_value_a ), +// .E_master_rt_value ( E_master_rt_value ), +// .E_slave_rs ( E_slave_rs ), +// .E_slave_rs_value_a ( E_slave_rs_value_a ), +// .E_slave_rs_value ( E_slave_rs_value ), +// .E_slave_rt ( E_slave_rt ), +// .E_slave_rt_value_a ( E_slave_rt_value_a ), +// .E_slave_rt_value ( E_slave_rt_value ) +// ); // select_alusrc: 所有的pc要加8的，都在alu执行，进行电路复用 assign E_master_alu_srca = E_master_alu_sela ? {{27{1'b0}},E_master_shamt} : E_master_rs_value; @@ -669,7 +672,7 @@ alu_master u_alu_master( .a ( E_master_alu_srca ), .b ( E_master_alu_srcb ), .stall_alu ( E_alu_stall ), - .y ( E_master_alu_res_a ), + .y ( E_master_alu_res_tmp ), .aluout_64 ( E_master_alu_out64), .overflow ( E_master_overflow ) ); @@ -683,10 +686,32 @@ alu_slave u_alu_slave( .overflow ( E_slave_overflow ) ); -assign E_master_alu_res = E_master_is_link_pc8 ? (E_master_pc + 32'd8) : E_master_alu_res_a; +// assign E_master_alu_res = E_master_is_link_pc8 ? (E_master_pc + 32'd8) : E_master_alu_res_tmp; +alu_res_select u_alu_res_select_master( + //ports + .aluop ( E_master_aluop ), + .is_link_pc8 ( E_master_is_link_pc8 ), + .cp0_data ( cp0_data ), + .pc8 ( E_master_pc + 32'd8 ), + .alu_res_tmp ( E_master_alu_res_tmp ), + .hilo ( hilo ), + .alu_res ( E_master_alu_res ) +); + +// E阶段写，M阶段出结果 +hilo_reg u_hilo_reg( + //ports + .clk ( clk ), + .rst ( rst ), + .wen ( E_master_hilowrite & M_ena & ~M_flush), // 保证E_master_hilowrite能成功送到M + .aluop ( E_master_aluop ), + .rs_value ( E_master_rs_value ), + .hilo_i ( E_master_alu_out64), + .hilo_o ( hilo ) +); // ====================================== Memory ====================================== -wire [31:0] M_master_alu_res_tmp, M_slave_alu_res_tmp; +// wire [31:0] M_master_alu_res_tmp, M_slave_alu_res_tmp; ex_mem u_ex_mem( //ports .clk ( clk ), @@ -735,7 +760,7 @@ ex_mem u_ex_mem( .M_master_except_a ( M_master_except_a ), .M_master_inst ( M_master_inst ), .M_master_rt_value ( M_master_rt_value ), - .M_master_alu_res ( M_master_alu_res_tmp ), + .M_master_alu_res ( M_master_alu_res ), .M_master_pc ( M_master_pc ), .M_master_alu_out64 ( M_master_alu_out64 ), .M_master_mem_addr ( M_master_mem_addr ), @@ -748,7 +773,7 @@ ex_mem u_ex_mem( .M_slave_except ( M_slave_except ), .M_slave_pc ( M_slave_pc ), .M_slave_inst ( M_slave_inst ), - .M_slave_alu_res ( M_slave_alu_res_tmp ) + .M_slave_alu_res ( M_slave_alu_res ) ); mem_access u_mem_access( @@ -769,37 +794,6 @@ mem_access u_mem_access( .M_master_except ( M_master_except ) ); -alu_res_selectM u_alu_res_selectM_master( - //ports - .aluop ( M_master_aluop ), - .cp0_data ( cp0_data ), - .alu_res_tmp ( M_master_alu_res_tmp ), - .hilo ( hilo ), - .alu_res ( M_master_alu_res ) -); - - -alu_res_selectM u_alu_res_selectM_slave( - //ports - .aluop ( M_slave_aluop ), - .cp0_data ( cp0_data ), - .alu_res_tmp ( M_slave_alu_res_tmp ), - .hilo ( hilo ), - .alu_res ( M_slave_alu_res ) -); - -// E阶段写，M阶段出结果 -hilo_reg u_hilo_reg( - //ports - .clk ( clk ), - .rst ( rst ), - .wen ( E_master_hilowrite & M_ena & ~M_flush), // 保证E_master_hilowrite能成功送到M - .aluop ( E_master_aluop ), - .rs_value ( E_master_rs_value ), - .hilo_i ( E_master_alu_out64), - .hilo_o ( hilo ) -); - // master的异常优先级更高，故异常处理阶段先选择master异常 exception u_exp( //ports @@ -829,7 +823,7 @@ cp0_reg u_cp0_reg( .rst ( rst ), .we_i ( M_master_cp0write & M_ena ), // 只有master访问cp0_reg .waddr_i ( M_master_rd ), // M阶段写入CP0 // MTCP0 CP0[rd, sel] ← GPR[rt] - .raddr_i ( M_master_rd ), // E阶段读取CP0，这两步可以避免数据冒险处理 // MFCP0 GPR[rt] ← CP0[rd, sel] 写寄存器 + .raddr_i ( E_master_rd ), // E阶段读取CP0，这两步可以避免数据冒险处理 // MFCP0 GPR[rt] ← CP0[rd, sel] 写寄存器 .data_i ( M_master_rt_value ), .int_i ( ext_int ), .excepttype_i ( M_excepttype ), @@ -902,18 +896,22 @@ assign debug_wb_rf_wen = (rst) ? 4'b0000 : ((clk) ? {4{u_regfile.wen1}} : { assign debug_wb_rf_wnum = (clk) ? u_regfile.wa1 : u_regfile.wa2; assign debug_wb_rf_wdata = (clk) ? u_regfile.wd1 : u_regfile.wd2; // ascii +wire [47:0] master_asciiF; wire [47:0] master_asciiD; wire [47:0] master_asciiE; wire [47:0] master_asciiM; wire [47:0] master_asciiW; +wire [47:0] slave_asciiF ; wire [47:0] slave_asciiD ; wire [47:0] slave_asciiE ; wire [47:0] slave_asciiM ; wire [47:0] slave_asciiW ; +instdec u_master_asciiF(inst_rdata1,master_asciiF); instdec u_master_asciiD(D_master_inst,master_asciiD); instdec u_master_asciiE(E_master_inst,master_asciiE); instdec u_master_asciiM(M_master_inst,master_asciiM); instdec u_master_asciiW(W_master_inst,master_asciiW); +instdec u_slave_asciiF (inst_rdata2,slave_asciiF ); instdec u_slave_asciiD (D_slave_inst ,slave_asciiD ); instdec u_slave_asciiE (E_slave_inst ,slave_asciiE ); instdec u_slave_asciiM (M_slave_inst ,slave_asciiM ); diff --git a/4mem/alu_res_selectM.sv b/util/alu_res_select.sv similarity index 67% rename from 4mem/alu_res_selectM.sv rename to util/alu_res_select.sv index fe9d8ec..9fd34e0 100644 --- a/4mem/alu_res_selectM.sv +++ b/util/alu_res_select.sv @@ -1,9 +1,11 @@ `timescale 1ns / 1ps `include "defines.vh" -module alu_res_selectM( - input logic [7:0]aluop, +module alu_res_select( + input logic is_link_pc8, + input logic [7 :0]aluop, input logic [31:0]cp0_data, input logic [31:0]alu_res_tmp, + input logic [31:0]pc8, input logic [63:0]hilo, output logic [31:0]alu_res ); @@ -13,7 +15,8 @@ module alu_res_selectM( // 3. MFLO lo // 4. pc_link_8 (暂时在E解决) // 5. alu_res_tmp - assign alu_res = aluop==`ALUOP_MFC0 ? cp0_data : + assign alu_res = is_link_pc8 ? pc8 : + aluop==`ALUOP_MFC0 ? cp0_data : aluop==`ALUOP_MFHI ? hilo[63:32] : aluop==`ALUOP_MFLO ? hilo[31: 0] : alu_res_tmp; diff --git a/util/forward_mux.sv b/util/forward_mux.sv new file mode 100644 index 0000000..7f5ca74 --- /dev/null +++ b/util/forward_mux.sv @@ -0,0 +1,41 @@ +`timescale 1ns / 1ps + +module forward_mux( + input alu_wen1, + input [ 4:0] alu_waddr1, + input [31:0] alu_wdata1, + input alu_wen2, + input [ 4:0] alu_waddr2, + input [31:0] alu_wdata2, + input alu_wen3, + input [ 4:0] alu_waddr3, + input [31:0] alu_wdata3, + input alu_wen4, + input [ 4:0] alu_waddr4, + input [31:0] alu_wdata4, + + input memtoReg, + input [ 4:0] mem_waddr, + input [31:0] mem_rdata, + + input [ 4:0] reg_addr, + input [31:0] reg_data_tmp, + output logic [31:0] reg_data +); + + always_comb begin : get_result + if(alu_wen1 && ~(|(alu_waddr1 ^ reg_addr))) + reg_data = alu_wdata1; + else if(alu_wen2 && ~(|(alu_waddr2 ^ reg_addr))) + reg_data = alu_wdata2; + else if(alu_wen3 && ~(|(alu_waddr3 ^ reg_addr))) + reg_data = alu_wdata3; + else if(alu_wen4 && ~(|(alu_waddr4 ^ reg_addr))) + reg_data = alu_wdata4; + else if(memtoReg && ~(|(mem_waddr ^ reg_addr))) + reg_data = mem_rdata; + else + reg_data = reg_data_tmp; + end + +endmodule \ No newline at end of file diff --git a/util/forward_top.sv b/util/forward_top.sv new file mode 100644 index 0000000..fba6d40 --- /dev/null +++ b/util/forward_top.sv @@ -0,0 +1,126 @@ +`timescale 1ns/1ps +module forward_top( + // 计算结果 + input alu_wen1, + input [ 4:0] alu_waddr1, + input [31:0] alu_wdata1, + input alu_wen2, + input [ 4:0] alu_waddr2, + input [31:0] alu_wdata2, + input alu_wen3, + input [ 4:0] alu_waddr3, + input [31:0] alu_wdata3, + input alu_wen4, + input [ 4:0] alu_waddr4, + input [31:0] alu_wdata4, + // 访存结果 + input memtoReg, + input [ 4:0] mem_waddr, + input [31:0] mem_rdata, + + input [ 4:0] master_rs, + input [31:0] master_rs_value_tmp, + output logic [31:0] master_rs_value, + input [ 4:0] master_rt, + input [31:0] master_rt_value_tmp, + output logic [31:0] master_rt_value, + + input [ 4:0] slave_rs, + input [31:0] slave_rs_value_tmp, + output logic [31:0] slave_rs_value, + input [ 4:0] slave_rt, + input [31:0] slave_rt_value_tmp, + output logic [31:0] slave_rt_value + +); + +forward_mux u_forward_mux_master_rs_value( + //ports + .alu_wen1 ( alu_wen1 ), + .alu_waddr1 ( alu_waddr1 ), + .alu_wdata1 ( alu_wdata1 ), + .alu_wen2 ( alu_wen2 ), + .alu_waddr2 ( alu_waddr2 ), + .alu_wdata2 ( alu_wdata2 ), + .alu_wen3 ( alu_wen3 ), + .alu_waddr3 ( alu_waddr3 ), + .alu_wdata3 ( alu_wdata3 ), + .alu_wen4 ( alu_wen4 ), + .alu_waddr4 ( alu_waddr4 ), + .alu_wdata4 ( alu_wdata4 ), + .memtoReg ( memtoReg ), + .mem_waddr ( mem_waddr ), + .mem_rdata ( mem_rdata ), + .reg_addr ( master_rs ), + .reg_data_tmp ( master_rs_value_tmp ), + .reg_data ( master_rs_value ) +); + +forward_mux u_forward_mux_master_rt_value( + //ports + .alu_wen1 ( alu_wen1 ), + .alu_waddr1 ( alu_waddr1 ), + .alu_wdata1 ( alu_wdata1 ), + .alu_wen2 ( alu_wen2 ), + .alu_waddr2 ( alu_waddr2 ), + .alu_wdata2 ( alu_wdata2 ), + .alu_wen3 ( alu_wen3 ), + .alu_waddr3 ( alu_waddr3 ), + .alu_wdata3 ( alu_wdata3 ), + .alu_wen4 ( alu_wen4 ), + .alu_waddr4 ( alu_waddr4 ), + .alu_wdata4 ( alu_wdata4 ), + .memtoReg ( memtoReg ), + .mem_waddr ( mem_waddr ), + .mem_rdata ( mem_rdata ), + .reg_addr ( master_rt ), + .reg_data_tmp ( master_rt_value_tmp ), + .reg_data ( master_rt_value ) +); + +forward_mux u_forward_mux_slave_rs_value( + //ports + .alu_wen1 ( alu_wen1 ), + .alu_waddr1 ( alu_waddr1 ), + .alu_wdata1 ( alu_wdata1 ), + .alu_wen2 ( alu_wen2 ), + .alu_waddr2 ( alu_waddr2 ), + .alu_wdata2 ( alu_wdata2 ), + .alu_wen3 ( alu_wen3 ), + .alu_waddr3 ( alu_waddr3 ), + .alu_wdata3 ( alu_wdata3 ), + .alu_wen4 ( alu_wen4 ), + .alu_waddr4 ( alu_waddr4 ), + .alu_wdata4 ( alu_wdata4 ), + .memtoReg ( memtoReg ), + .mem_waddr ( mem_waddr ), + .mem_rdata ( mem_rdata ), + .reg_addr ( slave_rs ), + .reg_data_tmp ( slave_rs_value_tmp ), + .reg_data ( slave_rs_value ) +); + +forward_mux u_forward_mux_slave_rt_value( + //ports + .alu_wen1 ( alu_wen1 ), + .alu_waddr1 ( alu_waddr1 ), + .alu_wdata1 ( alu_wdata1 ), + .alu_wen2 ( alu_wen2 ), + .alu_waddr2 ( alu_waddr2 ), + .alu_wdata2 ( alu_wdata2 ), + .alu_wen3 ( alu_wen3 ), + .alu_waddr3 ( alu_waddr3 ), + .alu_wdata3 ( alu_wdata3 ), + .alu_wen4 ( alu_wen4 ), + .alu_waddr4 ( alu_waddr4 ), + .alu_wdata4 ( alu_wdata4 ), + .memtoReg ( memtoReg ), + .mem_waddr ( mem_waddr ), + .mem_rdata ( mem_rdata ), + .reg_addr ( slave_rt ), + .reg_data_tmp ( slave_rt_value_tmp ), + .reg_data ( slave_rt_value ) +); + + +endmodule \ No newline at end of file