From 3ae70531e7539cfaa54c493b5ee4fd29d6bab4cc Mon Sep 17 00:00:00 2001 From: Yangyu Chen Date: Tue, 19 Jul 2022 11:37:24 +0800 Subject: [PATCH] Revert "Revert "fix int"" This reverts commit bea13b99c7de14f0ab58447401fde2ffbeb4fe9c. --- exception.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/exception.sv b/exception.sv index 7011289..a5e109a 100644 --- a/exception.sv +++ b/exception.sv @@ -21,14 +21,14 @@ module exception( ); wire [ 7:0] except; - assign except = (|master_except) ? master_except:slave_except; - assign except_inst_addr = (|master_except) ? master_pc :slave_pc ; - assign except_in_delayslot = (|master_except) ? master_is_in_delayslot : slave_is_in_delayslot; + assign except = (|master_except || (~(|slave_except))) ? master_except:slave_except; + assign except_inst_addr = (|master_except || (~(|slave_except))) ? master_pc :slave_pc ; + assign except_in_delayslot = (|master_except || (~(|slave_except))) ? master_is_in_delayslot : slave_is_in_delayslot; always_comb begin: excepttype_define except_target = 32'hBFC00380; except_bad_addr = 0; - if(rst) begin + if(rst || master_pc == 0) begin excepttype = 32'b0; end else begin if(((cp0_cause[15:8] & cp0_status[15:8]) != 8'h00) && (cp0_status[1] == 1'b0) && (cp0_status[0] == 1'b1)) begin