diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index cd2427ecc68..028ae9beb34 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -280,7 +280,7 @@ module csr_regfile logic [3:0] index; localparam logic [CVA6Cfg.XLEN-1:0] IsaCode = (CVA6Cfg.XLEN'(CVA6Cfg.RVA) << 0) // A - Atomic Instructions extension - | (CVA6Cfg.XLEN'(CVA6Cfg.RVB) << 1) // C - Bitmanip extension + | (CVA6Cfg.XLEN'(CVA6Cfg.RVB) << 1) // B - Bitmanip extension | (CVA6Cfg.XLEN'(CVA6Cfg.RVC) << 2) // C - Compressed extension | (CVA6Cfg.XLEN'(CVA6Cfg.RVD) << 3) // D - Double precision floating-point extension | (CVA6Cfg.XLEN'(CVA6Cfg.RVF) << 5) // F - Single precision floating-point extension @@ -2459,38 +2459,42 @@ module csr_regfile //------------- // RVFI //------------- - assign rvfi_csr_o.fcsr_q = CVA6Cfg.FpPresent ? fcsr_q : '0; - assign rvfi_csr_o.dcsr_q = CVA6Cfg.DebugEn ? dcsr_q : '0; - assign rvfi_csr_o.dpc_q = CVA6Cfg.DebugEn ? dpc_q : '0; - assign rvfi_csr_o.dscratch0_q = CVA6Cfg.DebugEn ? dscratch0_q : '0; - assign rvfi_csr_o.dscratch1_q = CVA6Cfg.DebugEn ? dscratch1_q : '0; - assign rvfi_csr_o.mie_q = mie_q; - assign rvfi_csr_o.mip_q = mip_q; - assign rvfi_csr_o.stvec_q = CVA6Cfg.RVS ? stvec_q : '0; - assign rvfi_csr_o.scounteren_q = CVA6Cfg.RVS ? scounteren_q : '0; - assign rvfi_csr_o.sscratch_q = CVA6Cfg.RVS ? sscratch_q : '0; - assign rvfi_csr_o.sepc_q = CVA6Cfg.RVS ? sepc_q : '0; - assign rvfi_csr_o.scause_q = CVA6Cfg.RVS ? scause_q : '0; - assign rvfi_csr_o.stval_q = CVA6Cfg.RVS ? stval_q : '0; - assign rvfi_csr_o.satp_q = CVA6Cfg.RVS ? satp_q : '0; + assign rvfi_csr_o.fcsr_d = CVA6Cfg.FpPresent ? fcsr_d : '0; + assign rvfi_csr_o.dcsr_d = CVA6Cfg.DebugEn ? dcsr_d : '0; + assign rvfi_csr_o.dpc_d = CVA6Cfg.DebugEn ? dpc_d : '0; + assign rvfi_csr_o.dscratch0_d = CVA6Cfg.DebugEn ? dscratch0_d : '0; + assign rvfi_csr_o.dscratch1_d = CVA6Cfg.DebugEn ? dscratch1_d : '0; + assign rvfi_csr_o.mie_d = mie_d; + assign rvfi_csr_o.mip_d = mip_d; + assign rvfi_csr_o.stvec_d = CVA6Cfg.RVS ? stvec_d : '0; + assign rvfi_csr_o.scounteren_d = CVA6Cfg.RVS ? scounteren_d : '0; + assign rvfi_csr_o.sscratch_d = CVA6Cfg.RVS ? sscratch_d : '0; + assign rvfi_csr_o.sepc_d = CVA6Cfg.RVS ? sepc_d : '0; + assign rvfi_csr_o.scause_d = CVA6Cfg.RVS ? scause_d : '0; + assign rvfi_csr_o.stval_d = CVA6Cfg.RVS ? stval_d : '0; + assign rvfi_csr_o.satp_d = CVA6Cfg.RVS ? satp_d : '0; assign rvfi_csr_o.mstatus_extended = mstatus_extended; - assign rvfi_csr_o.medeleg_q = CVA6Cfg.RVS ? medeleg_q : '0; - assign rvfi_csr_o.mideleg_q = CVA6Cfg.RVS ? mideleg_q : '0; - assign rvfi_csr_o.mtvec_q = mtvec_q; - assign rvfi_csr_o.mcounteren_q = mcounteren_q; - assign rvfi_csr_o.mscratch_q = mscratch_q; - assign rvfi_csr_o.mepc_q = mepc_q; - assign rvfi_csr_o.mcause_q = mcause_q; - assign rvfi_csr_o.mtval_q = mtval_q; - assign rvfi_csr_o.fiom_q = fiom_q; - assign rvfi_csr_o.mcountinhibit_q = mcountinhibit_q; - assign rvfi_csr_o.cycle_q = cycle_q; - assign rvfi_csr_o.instret_q = instret_q; - assign rvfi_csr_o.dcache_q = dcache_q; - assign rvfi_csr_o.icache_q = icache_q; - assign rvfi_csr_o.acc_cons_q = CVA6Cfg.EnableAccelerator ? acc_cons_q : '0; - assign rvfi_csr_o.pmpcfg_q = pmpcfg_q; - assign rvfi_csr_o.pmpaddr_q = pmpaddr_q; - + assign rvfi_csr_o.medeleg_d = CVA6Cfg.RVS ? medeleg_d : '0; + assign rvfi_csr_o.mideleg_d = CVA6Cfg.RVS ? mideleg_d : '0; + assign rvfi_csr_o.mtvec_d = mtvec_d; + assign rvfi_csr_o.mcounteren_d = mcounteren_d; + assign rvfi_csr_o.mscratch_d = mscratch_d; + assign rvfi_csr_o.mepc_d = mepc_d; + assign rvfi_csr_o.mcause_d = mcause_d; + assign rvfi_csr_o.mtval_d = mtval_d; + assign rvfi_csr_o.fiom_d = fiom_d; + assign rvfi_csr_o.mcountinhibit_d = mcountinhibit_d; + assign rvfi_csr_o.cycle_d = cycle_d; + assign rvfi_csr_o.instret_d = instret_d; + assign rvfi_csr_o.dcache_d = dcache_d; + assign rvfi_csr_o.icache_d = icache_d; + assign rvfi_csr_o.acc_cons_d = CVA6Cfg.EnableAccelerator ? acc_cons_d : '0; + assign rvfi_csr_o.pmpcfg_d = pmpcfg_d; + assign rvfi_csr_o.pmpaddr_d = pmpaddr_d; + + assign rvfi_csr_o.csr_op_i = csr_op_i; + assign rvfi_csr_o.csr_addr_i = csr_addr_i ; + assign rvfi_csr_o.csr_wdata_i = csr_wdata_i; + assign rvfi_csr_o.csr_rdata_o = csr_rdata_o; endmodule diff --git a/core/cva6_rvfi.sv b/core/cva6_rvfi.sv index 11cc4bfaf8f..f340eba4513 100644 --- a/core/cva6_rvfi.sv +++ b/core/cva6_rvfi.sv @@ -236,7 +236,7 @@ module cva6_rvfi // PACK //---------------------------------------------------------------------------------------------------------- - always_ff @(posedge clk_i) begin + always_comb begin for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin logic exception; exception = commit_instr_valid[i][0] && ex_commit_valid; @@ -273,16 +273,10 @@ module cva6_rvfi // CSR //---------------------------------------------------------------------------------------------------------- - - `define CONNECT_RVFI_FULL(CSR_ENABLE_COND, CSR_NAME, CSR_SOURCE_NAME) \ - bit [CVA6Cfg.XLEN-1:0] ``CSR_NAME``_d; \ - always_ff @(posedge clk_i) begin \ - ``CSR_NAME``_d <= {{CVA6Cfg.XLEN - $bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME}; \ - end \ always_comb begin \ rvfi_csr_o.``CSR_NAME = CSR_ENABLE_COND ? \ - '{ rdata: ``CSR_NAME``_d , \ + '{ rdata: 0, \ wdata: { {{CVA6Cfg.XLEN-$bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME} }, \ rmask: '1, wmask: '1} \ : '0; \ @@ -291,13 +285,13 @@ module cva6_rvfi `define COMMA , `define CONNECT_RVFI_SAME(CSR_ENABLE_COND, CSR_NAME) \ - `CONNECT_RVFI_FULL(CSR_ENABLE_COND, CSR_NAME, csr.``CSR_NAME``_q) + `CONNECT_RVFI_FULL(CSR_ENABLE_COND, CSR_NAME, csr.``CSR_NAME``_d) - `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, fflags, csr.fcsr_q.fflags) - `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, frm, csr.fcsr_q.frm) - `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, fcsr, { csr.fcsr_q.frm `COMMA csr.fcsr_q.fflags}) + `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, fflags, csr.fcsr_d.fflags) + `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, frm, csr.fcsr_d.frm) + `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, fcsr, { csr.fcsr_d.frm `COMMA csr.fcsr_d.fflags}) - `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, ftran, csr.fcsr_q.fprec) + `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, ftran, csr.fcsr_d.fprec) `CONNECT_RVFI_SAME(CVA6Cfg.FpPresent, dcsr) `CONNECT_RVFI_SAME(CVA6Cfg.DebugEn, dpc) @@ -308,8 +302,8 @@ module cva6_rvfi `CONNECT_RVFI_FULL(CVA6Cfg.RVS, sstatus, csr.mstatus_extended & SMODE_STATUS_READ_MASK[CVA6Cfg.XLEN-1:0]) - `CONNECT_RVFI_FULL(CVA6Cfg.RVS, sie, csr.mie_q & csr.mideleg_q) - `CONNECT_RVFI_FULL(CVA6Cfg.RVS, sip, csr.mip_q & csr.mideleg_q) + `CONNECT_RVFI_FULL(CVA6Cfg.RVS, sie, csr.mie_d & csr.mideleg_d) + `CONNECT_RVFI_FULL(CVA6Cfg.RVS, sip, csr.mip_d & csr.mideleg_d) `CONNECT_RVFI_SAME(CVA6Cfg.RVS, stvec) @@ -343,7 +337,7 @@ module cva6_rvfi `CONNECT_RVFI_SAME(1'b1, mtval) `CONNECT_RVFI_SAME(1'b1, mip) - `CONNECT_RVFI_FULL(1'b1, menvcfg, csr.fiom_q) + `CONNECT_RVFI_FULL(1'b1, menvcfg, csr.fiom_d) `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, menvcfgh, 0) @@ -353,53 +347,37 @@ module cva6_rvfi `CONNECT_RVFI_SAME(1'b1, mcountinhibit) - `CONNECT_RVFI_FULL(1'b1, mcycle, csr.cycle_q[CVA6Cfg.XLEN-1:0]) - `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, mcycleh, csr.cycle_q[63:32]) + `CONNECT_RVFI_FULL(1'b1, mcycle, csr.cycle_d[CVA6Cfg.XLEN-1:0]) + `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, mcycleh, csr.cycle_d[63:32]) - `CONNECT_RVFI_FULL(1'b1, minstret, csr.instret_q[CVA6Cfg.XLEN-1:0]) - `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, minstreth, csr.instret_q[63:32]) + `CONNECT_RVFI_FULL(1'b1, minstret, csr.instret_d[CVA6Cfg.XLEN-1:0]) + `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, minstreth, csr.instret_d[63:32]) - `CONNECT_RVFI_FULL(1'b1, cycle, csr.cycle_q[CVA6Cfg.XLEN-1:0]) - `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, cycleh, csr.cycle_q[63:32]) + `CONNECT_RVFI_FULL(1'b1, cycle, csr.cycle_d[CVA6Cfg.XLEN-1:0]) + `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, cycleh, csr.cycle_d[63:32]) - `CONNECT_RVFI_FULL(1'b1, instret, csr.instret_q[CVA6Cfg.XLEN-1:0]) - `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, instreth, csr.instret_q[63:32]) + `CONNECT_RVFI_FULL(1'b1, instret, csr.instret_d[CVA6Cfg.XLEN-1:0]) + `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, instreth, csr.instret_d[63:32]) `CONNECT_RVFI_SAME(1'b1, dcache) `CONNECT_RVFI_SAME(1'b1, icache) `CONNECT_RVFI_SAME(CVA6Cfg.EnableAccelerator, acc_cons) - `CONNECT_RVFI_FULL(1'b1, pmpcfg0, csr.pmpcfg_q[CVA6Cfg.XLEN/8-1:0]) - `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, pmpcfg1, csr.pmpcfg_q[7:4]) + `CONNECT_RVFI_FULL(1'b1, pmpcfg0, csr.pmpcfg_d[CVA6Cfg.XLEN/8-1:0]) + `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, pmpcfg1, csr.pmpcfg_d[7:4]) - `CONNECT_RVFI_FULL(1'b1, pmpcfg2, csr.pmpcfg_q[8+:CVA6Cfg.XLEN/8]) - `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, pmpcfg3, csr.pmpcfg_q[15:12]) + `CONNECT_RVFI_FULL(1'b1, pmpcfg2, csr.pmpcfg_d[8+:CVA6Cfg.XLEN/8]) + `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, pmpcfg3, csr.pmpcfg_d[15:12]) - bit [CVA6Cfg.XLEN-1:0] pmpaddr_q; genvar i; generate for (i = 0; i < 16; i++) begin - always_ff @(posedge clk_i) begin - pmpaddr_q[i] = (csr.pmpcfg_q[i].addr_mode[1] == 1'b1) ? - {{CVA6Cfg.XLEN - (CVA6Cfg.PLEN - 2) {1'b0}}, csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:0]} - : {{CVA6Cfg.XLEN - (CVA6Cfg.PLEN - 2) {1'b0}} , csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:1] , 1'b0 }; - end always_comb begin rvfi_csr_o.pmpaddr[i] = '{ - rdata: {'0, pmpaddr_q[i]}, - wdata: - csr.pmpcfg_q[i].addr_mode[1] - == 1'b1 ? - {{CVA6Cfg.XLEN - (CVA6Cfg.PLEN - 2) {1'b0}}, csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:0]} - : { - {CVA6Cfg.XLEN - (CVA6Cfg.PLEN - 2) {1'b0}} - , - csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:1] - , - 1'b0 - }, - rmask: '1, + rdata: '0, + wdata: csr.pmpaddr_d[i][CVA6Cfg.PLEN-3:0], + rmask: '0, wmask: '1 }; end diff --git a/core/include/rvfi_types.svh b/core/include/rvfi_types.svh index 5db2f42de2c..16ea31742fb 100644 --- a/core/include/rvfi_types.svh +++ b/core/include/rvfi_types.svh @@ -127,38 +127,42 @@ } `define RVFI_PROBES_CSR_T(Cfg) struct packed { \ - riscv::fcsr_t fcsr_q; \ - riscv::dcsr_t dcsr_q; \ - logic [Cfg.XLEN-1:0] dpc_q; \ - logic [Cfg.XLEN-1:0] dscratch0_q; \ - logic [Cfg.XLEN-1:0] dscratch1_q; \ - logic [Cfg.XLEN-1:0] mie_q; \ - logic [Cfg.XLEN-1:0] mip_q; \ - logic [Cfg.XLEN-1:0] stvec_q; \ - logic [Cfg.XLEN-1:0] scounteren_q; \ - logic [Cfg.XLEN-1:0] sscratch_q; \ - logic [Cfg.XLEN-1:0] sepc_q; \ - logic [Cfg.XLEN-1:0] scause_q; \ - logic [Cfg.XLEN-1:0] stval_q; \ - logic [Cfg.XLEN-1:0] satp_q; \ + riscv::fcsr_t fcsr_d; \ + riscv::dcsr_t dcsr_d; \ + logic [Cfg.XLEN-1:0] dpc_d; \ + logic [Cfg.XLEN-1:0] dscratch0_d; \ + logic [Cfg.XLEN-1:0] dscratch1_d; \ + logic [Cfg.XLEN-1:0] mie_d; \ + logic [Cfg.XLEN-1:0] mip_d; \ + logic [Cfg.XLEN-1:0] stvec_d; \ + logic [Cfg.XLEN-1:0] scounteren_d; \ + logic [Cfg.XLEN-1:0] sscratch_d; \ + logic [Cfg.XLEN-1:0] sepc_d; \ + logic [Cfg.XLEN-1:0] scause_d; \ + logic [Cfg.XLEN-1:0] stval_d; \ + logic [Cfg.XLEN-1:0] satp_d; \ logic [Cfg.XLEN-1:0] mstatus_extended; \ - logic [Cfg.XLEN-1:0] medeleg_q; \ - logic [Cfg.XLEN-1:0] mideleg_q; \ - logic [Cfg.XLEN-1:0] mtvec_q; \ - logic [Cfg.XLEN-1:0] mcounteren_q; \ - logic [Cfg.XLEN-1:0] mscratch_q; \ - logic [Cfg.XLEN-1:0] mepc_q; \ - logic [Cfg.XLEN-1:0] mcause_q; \ - logic [Cfg.XLEN-1:0] mtval_q; \ - logic fiom_q; \ - logic [ariane_pkg::MHPMCounterNum+3-1:0] mcountinhibit_q; \ - logic [63:0] cycle_q; \ - logic [63:0] instret_q; \ - logic [Cfg.XLEN-1:0] dcache_q; \ - logic [Cfg.XLEN-1:0] icache_q; \ - logic [Cfg.XLEN-1:0] acc_cons_q; \ - riscv::pmpcfg_t [15:0] pmpcfg_q; \ - logic [15:0][Cfg.PLEN-3:0] pmpaddr_q; \ + logic [Cfg.XLEN-1:0] medeleg_d; \ + logic [Cfg.XLEN-1:0] mideleg_d; \ + logic [Cfg.XLEN-1:0] mtvec_d; \ + logic [Cfg.XLEN-1:0] mcounteren_d; \ + logic [Cfg.XLEN-1:0] mscratch_d; \ + logic [Cfg.XLEN-1:0] mepc_d; \ + logic [Cfg.XLEN-1:0] mcause_d; \ + logic [Cfg.XLEN-1:0] mtval_d; \ + logic fiom_d; \ + logic [ariane_pkg::MHPMCounterNum+3-1:0] mcountinhibit_d; \ + logic [63:0] cycle_d; \ + logic [63:0] instret_d; \ + logic [Cfg.XLEN-1:0] dcache_d; \ + logic [Cfg.XLEN-1:0] icache_d; \ + logic [Cfg.XLEN-1:0] acc_cons_d; \ + riscv::pmpcfg_t [15:0] pmpcfg_d; \ + logic [15:0][Cfg.PLEN-3:0] pmpaddr_d; \ + logic [Cfg.XLEN-1:0] csr_op_i; \ + logic [Cfg.XLEN-1:0] csr_addr_i ; \ + logic [Cfg.XLEN-1:0] csr_wdata_i; \ + logic [Cfg.XLEN-1:0] csr_rdata_o; \ } `endif // RVFI_TYPES_SVH diff --git a/corev_apu/tb/common/spike.sv b/corev_apu/tb/common/spike.sv index dd85ce47d52..119de329db5 100644 --- a/corev_apu/tb/common/spike.sv +++ b/corev_apu/tb/common/spike.sv @@ -46,12 +46,17 @@ module spike #( st_core_cntrl_cfg st; initial begin + string core_name = "cva6"; st = cva6pkg_to_core_cntrl_cfg(st); st.boot_addr_valid = 1'b1; st.boot_addr = 64'h0x10000; + if ($test$plusargs("CORE_NAME")) begin + $value$plusargs("CORE_NAME=%s", core_name); + end + rvfi_initialize(st); - rvfi_initialize_spike("cva6", st); + rvfi_initialize_spike(core_name, st); end @@ -101,24 +106,30 @@ module spike #( s_core.csr_wdata[CSR_INDEX] = rvfi_csr_i.``CSR_NAME``.wdata;\ s_core.csr_wmask[CSR_INDEX] = rvfi_csr_i.``CSR_NAME``.wmask; - `GET_RVFI_CSR (CSR_MSTATUS , mstatus , 0) - `GET_RVFI_CSR (CSR_MCAUSE , mcause , 1) - `GET_RVFI_CSR (CSR_MEPC , mepc , 2) - `GET_RVFI_CSR (CSR_MTVEC , mtvec , 3) - `GET_RVFI_CSR (CSR_MISA , misa , 4) - `GET_RVFI_CSR (CSR_MTVAL , mtval , 5) - `GET_RVFI_CSR (CSR_MIDELEG , mideleg , 6) - `GET_RVFI_CSR (CSR_MEDELEG , medeleg , 7) - `GET_RVFI_CSR (CSR_SATP , satp , 8) - `GET_RVFI_CSR (CSR_MIE , mie , 9) - `GET_RVFI_CSR (CSR_STVEC , stvec , 10) - `GET_RVFI_CSR (CSR_SSCRATCH , sscratch , 11) - `GET_RVFI_CSR (CSR_SEPC , sepc , 12) - `GET_RVFI_CSR (CSR_MSCRATCH , mscratch , 13) - `GET_RVFI_CSR (CSR_STVAL , stval , 14) - `GET_RVFI_CSR (CSR_SCAUSE , scause , 15) - `GET_RVFI_CSR (CSR_PMPADDR0 , pmpaddr[0] , 16) - `GET_RVFI_CSR (CSR_PMPCFG0 , pmpcfg0 , 17) + `GET_RVFI_CSR (CSR_MSTATUS , mstatus , 0) + `GET_RVFI_CSR (CSR_MCAUSE , mcause , 1) + `GET_RVFI_CSR (CSR_MEPC , mepc , 2) + `GET_RVFI_CSR (CSR_MTVEC , mtvec , 3) + `GET_RVFI_CSR (CSR_MISA , misa , 4) + `GET_RVFI_CSR (CSR_MTVAL , mtval , 5) + `GET_RVFI_CSR (CSR_MIDELEG , mideleg , 6) + `GET_RVFI_CSR (CSR_MEDELEG , medeleg , 7) + `GET_RVFI_CSR (CSR_SATP , satp , 8) + `GET_RVFI_CSR (CSR_MIE , mie , 9) + `GET_RVFI_CSR (CSR_STVEC , stvec , 10) + `GET_RVFI_CSR (CSR_SSCRATCH , sscratch , 11) + `GET_RVFI_CSR (CSR_SEPC , sepc , 12) + `GET_RVFI_CSR (CSR_MSCRATCH , mscratch , 13) + `GET_RVFI_CSR (CSR_STVAL , stval , 14) + `GET_RVFI_CSR (CSR_SCAUSE , scause , 15) + `GET_RVFI_CSR (CSR_PMPCFG0 , pmpcfg0 , 16) + `GET_RVFI_CSR (CSR_PMPCFG1 , pmpcfg1 , 17) + `GET_RVFI_CSR (CSR_PMPCFG2 , pmpcfg2 , 18) + `GET_RVFI_CSR (CSR_PMPCFG3 , pmpcfg3 , 19) + for (int i = 0; i < 16; i++) begin + `GET_RVFI_CSR (CSR_PMPADDR0 + i , pmpaddr[i] , 20 + i) + end + `GET_RVFI_CSR (CSR_MINSTRET , instret , 37) rvfi_spike_step(s_core, s_reference_model); rvfi_compare(s_core, s_reference_model); diff --git a/verif/env/uvme/uvme_cva6_cfg.sv b/verif/env/uvme/uvme_cva6_cfg.sv index fb6fb481aec..b5a8cc1ed18 100644 --- a/verif/env/uvme/uvme_cva6_cfg.sv +++ b/verif/env/uvme/uvme_cva6_cfg.sv @@ -233,6 +233,8 @@ function uvme_cva6_cfg_c::new(string name="uvme_cva6_cfg"); isacov_cfg.core_cfg = this; rvfi_cfg.core_cfg = this; + $value$plusargs("CORE_NAME", this.core_name); + endfunction : new function void uvme_cva6_cfg_c::sample_parameters(uvma_core_cntrl_cntxt_c cntxt); diff --git a/verif/sim/Makefile b/verif/sim/Makefile index fad6f7524a3..ba946f05e79 100644 --- a/verif/sim/Makefile +++ b/verif/sim/Makefile @@ -121,7 +121,7 @@ endif ############################################################################### spike: LD_LIBRARY_PATH="$$(realpath ../../tools/spike/lib):$$LD_LIBRARY_PATH" \ - $(tool_path)/spike $(spike_stepout) $(spike_extension) --log-commits --isa=$(variant) --priv=$(priv) -l $(elf) + $(tool_path)/spike $(spike_stepout) $(spike_extension) --log-commits --isa=$(variant)_zicntr --priv=$(priv) -l $(elf) --extension=cv32a60x cp $(log).iss $(log) ############################################################################### @@ -135,7 +135,7 @@ vcs-testharness: +elf_file=$(elf) +permissive-off ++$(elf) $(issrun_opts) \ $(if $(spike-tandem),-sv_lib $(SPIKE_INSTALL_DIR)/lib/libdisasm) \ $(if $(spike-tandem),-sv_lib $(SPIKE_INSTALL_DIR)/lib/libriscv) \ - -sv_lib $(SPIKE_INSTALL_DIR)/lib/libfesvr + -sv_lib $(SPIKE_INSTALL_DIR)/lib/libfesvr +CORE_NAME=$(target) # TODO: Add support for waveform collection. # Generate disassembled log. $(tool_path)/spike-dasm --isa=$(variant) < ./trace_rvfi_hart_00.dasm > $(log) @@ -144,7 +144,7 @@ vcs-testharness: veri-testharness: make -C $(path_var) verilate verilator="verilator --no-timing" target=$(target) defines=$(subst +define+,,$(isscomp_opts)) $(path_var)/work-ver/Variane_testharness $(if $(TRACE_COMPACT), -f verilator.fst) $(if $(TRACE_FAST), -v verilator.vcd) $(elf) $(issrun_opts) \ - +elf_file=$(elf) +tohost_addr=$(shell $$RISCV/bin/${CV_SW_PREFIX}nm -B $(elf) | grep -w tohost | cut -d' ' -f1) + +elf_file=$(elf) +tohost_addr=$(shell $$RISCV/bin/${CV_SW_PREFIX}nm -B $(elf) | grep -w tohost | cut -d' ' -f1) +CORE_NAME=$(target) # If present, move default waveform files to log directory. # Keep track of target in waveform file name. [ ! -f verilator.fst ] || mv verilator.fst `dirname $(log)`/`basename $(log) .log`.fst @@ -213,7 +213,7 @@ COMMON_RUN_UVM_FLAGS = \ ++$(elf) \ +elf_file=$(elf) \ +tohost_addr=$(shell $$RISCV/bin/$(CV_SW_PREFIX)nm -B $(elf) | grep -w tohost | cut -d' ' -f1) \ - +signature=$(elf).signature_output +UVM_TESTNAME=uvmt_cva6_firmware_test_c + +signature=$(elf).signature_output +UVM_TESTNAME=uvmt_cva6_firmware_test_c +CORE_NAME=$(target) ALL_UVM_FLAGS = -lca -sverilog +incdir+$(VCS_HOME)/etc/uvm/src \ $(VCS_HOME)/etc/uvm/src/uvm_pkg.sv -ntb_opts uvm-1.2 -timescale=1ns/1ps \ diff --git a/verif/tb/core/custom_uvm_macros.svh b/verif/tb/core/custom_uvm_macros.svh index e8866f86cbc..a813d60d71f 100644 --- a/verif/tb/core/custom_uvm_macros.svh +++ b/verif/tb/core/custom_uvm_macros.svh @@ -67,7 +67,7 @@ function void uvm_report_info(string id, string filename = "", int line = 0); if (verbosity <= current_verbosity_level) - $display($sformatf("UVM_INFO @ %t ns : %s %s", $time, id, message)); + $display($sformatf("UVM_INFO @ %t ns : %s %s", $time, id, message)); endfunction diff --git a/verif/tb/core/uvma_core_cntrl_pkg.sv b/verif/tb/core/uvma_core_cntrl_pkg.sv index 534ccc2e0db..2a025efd09d 100644 --- a/verif/tb/core/uvma_core_cntrl_pkg.sv +++ b/verif/tb/core/uvma_core_cntrl_pkg.sv @@ -6,6 +6,7 @@ package uvma_core_cntrl_pkg; // Constants / Structs / Enums `include "uvma_core_cntrl_constants.sv" `include "uvma_core_cntrl_tdefs.sv" + `include "uvma_core_cntrl_utils.sv" endpackage : uvma_core_cntrl_pkg diff --git a/verif/tb/core/uvma_cva6pkg_utils.sv b/verif/tb/core/uvma_cva6pkg_utils.sv index 2b88a1b3142..9178f7ae4c0 100644 --- a/verif/tb/core/uvma_cva6pkg_utils.sv +++ b/verif/tb/core/uvma_cva6pkg_utils.sv @@ -7,6 +7,9 @@ function st_core_cntrl_cfg cva6pkg_to_core_cntrl_cfg(st_core_cntrl_cfg base); base.ilen = cva6_config_pkg::CVA6ConfigXlen; + base.marchid = ariane_pkg::ARIANE_MARCHID; + base.mvendorid = ariane_pkg::OPENHWGROUP_MVENDORID; + base.ext_i_supported = 1; base.ext_a_supported = CVA6Cfg.RVA; base.ext_m_supported = 1; @@ -30,6 +33,8 @@ function st_core_cntrl_cfg cva6pkg_to_core_cntrl_cfg(st_core_cntrl_cfg base); base.ext_zicsr_supported = 1; base.ext_zicntr_supported = 1; + base.ext_cv32a60x_supported = 1; + base.mode_s_supported = CVA6Cfg.RVS; base.mode_u_supported = CVA6Cfg.RVU; @@ -41,6 +46,9 @@ function st_core_cntrl_cfg cva6pkg_to_core_cntrl_cfg(st_core_cntrl_cfg base); base.unsupported_csr_mask['h643] = 1; // HTVAL base.unsupported_csr_mask['h64A] = 1; // HTINST + // MHPMEVENT + for (int i = 32'h323; i < 32'h33F; i++) + base.unsupported_csr_mask[i] = 1; return base; diff --git a/verif/tb/core/uvma_cva6pkg_utils_pkg.sv b/verif/tb/core/uvma_cva6pkg_utils_pkg.sv index 2548641f7fd..9cb4908a7e8 100644 --- a/verif/tb/core/uvma_cva6pkg_utils_pkg.sv +++ b/verif/tb/core/uvma_cva6pkg_utils_pkg.sv @@ -3,6 +3,7 @@ package uvma_cva6pkg_utils_pkg; + import ariane_pkg::*; import cva6_config_pkg::*; import uvma_core_cntrl_pkg::*; `include "uvma_cva6pkg_utils.sv"