From 296d99145a6ea0b41042607e56ebfc93233a385c Mon Sep 17 00:00:00 2001 From: Mario Date: Fri, 6 Oct 2023 17:24:29 +0000 Subject: [PATCH] Spike TANDEM Makefile: * adding rvfi_pkg * adding absolute paths to the incdir to avoid relative path issues * move spike.sv from tbs to src core/cva6.sv: * change tval for new instr field of the scoreboard_entry_t * change trap to support all kinds of exceptions and interrupts core/decoder.sv: * change tval for 0 and add the old tval value to instr field core/include/ariane_pkg.sv: * add instr field on scoreboard_entry_t core/include/rvfi_pkg.sv: * new file that has: * st_rvfi struct, compare function, spike init function corev_apu/tb/common/spike.sv * change module to support rvfi_pkg verif/env/uvme/uvme_cva6_cfg.sv: * rename scooreboarding_enable to scoreboard_enable * rvfi_cfg.nret now properly set verif/env/uvme/uvme_cva6_constants.sv: * delete RVFI_NRET to avoid misconfigurations verif/env/uvme/uvme_cva6_env.sv: * rename scoreboarding * unify rvfi_monitors into one verif/env/uvme/uvme_cva6_pkg.sv: * add cva6_config_pkg to be available in the components verif/regress/install-spike.sh: * change SPIKE_SRC_DIR to core-v-verif verif/sim/Makefile: * avoid reconfigure if a config.log exists * add core_v_verif variable * add spike-tandem variable * add elfloader lib instead of ariane_dpi verif/sim/cva6.py: * solve trailing issues verif/sim/cva6.yaml: * delete steps variable #TODO add new timeout impl verif/sim/cva6_spike_log_to_trace_csv.py: * adapt for new spike impl verif/tb/uvmt/cva6_tb_wrapper.sv: * PRELOAD to elf_file verif/tb/uvmt/uvmt_cva6_pkg.sv: * add rvfi_pkg verif/tb/uvmt/uvmt_cva6_tb.sv: * add localparam RVFI_NRET * add rvfi_cause verif/tests/uvmt/compliance-tests/uvmt_cva6_firmware_test.sv: * add factory override for spike --- Makefile | 15 +- core/cva6.sv | 14 +- core/decoder.sv | 4 +- core/include/ariane_pkg.sv | 2 +- core/include/rvfi_pkg.sv | 53 +----- corev_apu/tb/common/spike.sv | 162 ++++-------------- verif/env/uvme/uvme_cva6_cfg.sv | 16 +- verif/env/uvme/uvme_cva6_constants.sv | 1 - verif/env/uvme/uvme_cva6_env.sv | 16 +- verif/env/uvme/uvme_cva6_pkg.sv | 1 + verif/regress/install-spike.sh | 6 +- verif/sim/Makefile | 112 ++++++------ verif/sim/cva6.py | 12 +- verif/sim/cva6.yaml | 2 +- verif/sim/cva6_spike_log_to_trace_csv.py | 2 +- verif/tb/uvmt/cva6_tb_wrapper.sv | 3 +- verif/tb/uvmt/uvmt_cva6_pkg.sv | 1 + verif/tb/uvmt/uvmt_cva6_tb.sv | 11 +- .../uvmt_cva6_firmware_test.sv | 13 ++ 19 files changed, 169 insertions(+), 277 deletions(-) diff --git a/Makefile b/Makefile index b0959e20e29..93a6103fb8f 100644 --- a/Makefile +++ b/Makefile @@ -154,7 +154,8 @@ endif # this list contains the standalone components src := core/include/$(target)_config_pkg.sv \ - core/include/rvfi_pkg.sv \ + $(if $(spike-tandem),core/include/rvfi_pkg.sv) \ + $(if $(spike-tandem),corev_apu/tb/common/spike.sv) \ corev_apu/src/ariane.sv \ $(wildcard corev_apu/bootrom/*.sv) \ $(wildcard corev_apu/clint/*.sv) \ @@ -224,7 +225,6 @@ fpga_src := $(addprefix $(root-dir), $(fpga_src)) # look for testbenches tbs := core/include/$(target)_config_pkg.sv \ corev_apu/tb/ariane_tb.sv \ - $(if $(spike-tandem),corev_apu/tb/common/spike.sv) \ corev_apu/tb/ariane_testharness.sv tbs := $(addprefix $(root-dir), $(tbs)) @@ -245,7 +245,9 @@ riscv-fp-tests := $(shell xargs printf '\n%s' < $(riscv-fp-tests-list riscv-benchmarks := $(shell xargs printf '\n%s' < $(riscv-benchmarks-list) | cut -b 1-) # Search here for include files (e.g.: non-standalone components) -incdir := vendor/pulp-platform/common_cells/include/ vendor/pulp-platform/axi/include/ corev_apu/register_interface/include/ +incdir := $(CVA6_REPO_DIR)/vendor/pulp-platform/common_cells/include/ $(CVA6_REPO_DIR)/vendor/pulp-platform/axi/include/ \ + $(CVA6_REPO_DIR)/corev_apu/register_interface/include/ $(CVA6_REPO_DIR)/corev_apu/tb/common/ \ + $(CVA6_REPO_DIR)/vendor/pulp-platform/axi/include/ $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_rvfi/ # Compile and sim flags compile_flag += +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive -svinputport=compat +define+$(defines) @@ -292,12 +294,12 @@ endif vcs_build: $(dpi-library)/ariane_dpi.so mkdir -p $(vcs-library) cd $(vcs-library) &&\ - vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog +define+$(defines) -assert svaext -f ../core/Flist.cva6 &&\ + vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog +define+$(defines) -assert svaext -f ../core/Flist.cva6 $(list_incdir) &&\ vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog +define+$(defines) $(filter %.sv,$(ariane_pkg)) +incdir+core/include/+$(VCS_HOME)/etc/uvm-1.2/dpi &&\ vhdlan $(if $(VERDI), -kdb,) -full64 -nc $(filter %.vhd,$(uart_src)) &&\ - vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -assert svaext +define+$(defines) $(filter %.sv,$(src)) +incdir+../vendor/pulp-platform/common_cells/include/+../vendor/pulp-platform/axi/include/+../corev_apu/register_interface/include/ &&\ + vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -assert svaext +define+$(defines) +incdir+$(VCS_HOME)/etc/uvm/src $(VCS_HOME)/etc/uvm/src/uvm_pkg.sv $(filter %.sv,$(src)) $(list_incdir) &&\ vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -ntb_opts uvm-1.2 &&\ - vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -ntb_opts uvm-1.2 $(tbs) +define+$(defines) +incdir+../vendor/pulp-platform/axi/include/ &&\ + vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -ntb_opts uvm-1.2 $(tbs) +define+$(defines) $(list_incdir) &&\ vcs $(if $(VERDI), -kdb -debug_access+all -lca,) -full64 -timescale=1ns/1ns -ntb_opts uvm-1.2 work.ariane_tb -error="IWNF" vcs: vcs_build @@ -603,6 +605,7 @@ verilate: sim-verilator: verilate $(ver-library)/Variane_testharness $(elf-bin) + $(addsuffix -verilator,$(riscv-asm-tests)): verilate $(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@) diff --git a/core/cva6.sv b/core/cva6.sv index 52cc7254057..f0555720f8a 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -1268,15 +1268,15 @@ module cva6 import ariane_pkg::*; #( end for (int i = 0; i < CVA6ExtendCfg.NrCommitPorts; i++) begin if (commit_ack[i] && !commit_instr_id_commit[i].ex.valid) begin - $fwrite(f, "%d 0x%0h %s (0x%h) DASM(%h)\n", cycles, commit_instr_id_commit[i].pc, mode, commit_instr_id_commit[i].ex.tval[31:0], commit_instr_id_commit[i].ex.tval[31:0]); + $fwrite(f, "%d 0x%0h %s (0x%h) DASM(%h)\n", cycles, commit_instr_id_commit[i].pc, mode, commit_instr_id_commit[i].instr[31:0], commit_instr_id_commit[i].instr[31:0]); end else if (commit_ack[i] && commit_instr_id_commit[i].ex.valid) begin if (commit_instr_id_commit[i].ex.cause == 2) begin - $fwrite(f, "Exception Cause: Illegal Instructions, DASM(%h) PC=%h\n", commit_instr_id_commit[i].ex.tval[31:0], commit_instr_id_commit[i].pc); + $fwrite(f, "Exception Cause: Illegal Instructions, DASM(%h) PC=%h\n", commit_instr_id_commit[i].instr[31:0], commit_instr_id_commit[i].pc); end else begin if (debug_mode) begin - $fwrite(f, "%d 0x%0h %s (0x%h) DASM(%h)\n", cycles, commit_instr_id_commit[i].pc, mode, commit_instr_id_commit[i].ex.tval[31:0], commit_instr_id_commit[i].ex.tval[31:0]); + $fwrite(f, "%d 0x%0h %s (0x%h) DASM(%h)\n", cycles, commit_instr_id_commit[i].pc, mode, commit_instr_id_commit[i].instr[31:0], commit_instr_id_commit[i].instr[31:0]); end else begin - $fwrite(f, "Exception Cause: %5d, DASM(%h) PC=%h\n", commit_instr_id_commit[i].ex.cause, commit_instr_id_commit[i].ex.tval[31:0], commit_instr_id_commit[i].pc); + $fwrite(f, "Exception Cause: %5d, DASM(%h) PC=%h\n", commit_instr_id_commit[i].ex.cause, commit_instr_id_commit[i].instr[31:0], commit_instr_id_commit[i].pc); end end end @@ -1312,10 +1312,10 @@ module cva6 import ariane_pkg::*; #( (exception && (ex_commit.cause == riscv::ENV_CALL_MMODE || ex_commit.cause == riscv::ENV_CALL_SMODE || ex_commit.cause == riscv::ENV_CALL_UMODE)); - rvfi_o[i].insn = ex_commit.valid ? ex_commit.tval[31:0] : commit_instr_id_commit[i].ex.tval[31:0]; + rvfi_o[i].insn = commit_instr_id_commit[i].instr[31:0]; // when trap, the instruction is not executed - rvfi_o[i].trap = mem_exception; - rvfi_o[i].cause = ex_commit.cause; + rvfi_o[i].trap = exception; + rvfi_o[i].cause = commit_instr_id_commit[i].ex.cause; rvfi_o[i].mode = debug_mode ? 2'b10 : priv_lvl; rvfi_o[i].ixl = riscv::XLEN == 64 ? 2 : 1; rvfi_o[i].rs1_addr = commit_instr_id_commit[i].rs1[4:0]; diff --git a/core/decoder.sv b/core/decoder.sv index dd6e3f34670..44977807fd0 100644 --- a/core/decoder.sv +++ b/core/decoder.sv @@ -1276,7 +1276,9 @@ module decoder import ariane_pkg::*; #( if (~ex_i.valid) begin // if we didn't already get an exception save the instruction here as we may need it // in the commit stage if we got a access exception to one of the CSR registers - instruction_o.ex.tval = (is_compressed_i) ? {{riscv::XLEN-16{1'b0}}, compressed_instr_i} : {{riscv::XLEN-32{1'b0}}, instruction_i}; + //instruction_o.ex.tval = (is_compressed_i) ? {{riscv::XLEN-16{1'b0}}, compressed_instr_i} : {{riscv::XLEN-32{1'b0}}, instruction_i}; + instruction_o.instr = (is_compressed_i) ? {{riscv::XLEN-16{1'b0}}, compressed_instr_i} : {{riscv::XLEN-32{1'b0}}, instruction_i}; + instruction_o.ex.tval = 'h0; // instructions which will throw an exception are marked as valid // e.g.: they can be committed anytime and do not need to wait for any functional unit // check here if we decoded an invalid instruction or if the compressed decoder already decoded diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv index 91896ebe784..6bd17587830 100644 --- a/core/include/ariane_pkg.sv +++ b/core/include/ariane_pkg.sv @@ -35,7 +35,6 @@ package ariane_pkg; localparam ASID_WIDTH = (riscv::XLEN == 64) ? 16 : 1; localparam BITS_SATURATION_COUNTER = 2; - localparam ENABLE_RENAME = cva6_config_pkg::CVA6ConfigRenameEn; localparam ISSUE_WIDTH = 1; // depth of store-buffers, this needs to be a power of two @@ -530,6 +529,7 @@ package ariane_pkg; typedef struct packed { logic [riscv::VLEN-1:0] pc; // PC of instruction + riscv::xlen_t instr; // Instruction value logic [TRANS_ID_BITS-1:0] trans_id; // this can potentially be simplified, we could index the scoreboard entry // with the transaction id in any case make the width more generic fu_t fu; // functional unit to use diff --git a/core/include/rvfi_pkg.sv b/core/include/rvfi_pkg.sv index efaefd763d6..9bbf6a30e7d 100644 --- a/core/include/rvfi_pkg.sv +++ b/core/include/rvfi_pkg.sv @@ -1,53 +1,16 @@ -`ifndef __UVMA_RVFI_TDEFS_SV__ -`define __UVMA_RVFI_TDEFS_SV__ +`ifndef __UVMA_RVFI_PKG_SV__ +`define __UVMA_RVFI_PKG_SV__ -package rvfi_pkg; - -typedef struct { - longint unsigned nret_id; - longint unsigned cycle_cnt; - longint unsigned order; - longint unsigned insn; - byte unsigned trap; - byte unsigned halt; - byte unsigned intr; - int unsigned mode; - int unsigned ixl; - int unsigned dbg; - int unsigned dbg_mode; - longint unsigned nmip; - - longint unsigned insn_interrupt; - longint unsigned insn_interrupt_id; - longint unsigned insn_bus_fault; - longint unsigned insn_nmi_store_fault; - longint unsigned insn_nmi_load_fault; - - longint unsigned pc_rdata; - longint unsigned pc_wdata; - longint unsigned rs1_addr; - longint unsigned rs1_rdata; - - longint unsigned rs2_addr; - longint unsigned rs2_rdata; - - longint unsigned rs3_addr; - longint unsigned rs3_rdata; - - longint unsigned rd1_addr; - longint unsigned rd1_wdata; +package rvfi_pkg; - longint unsigned rd2_addr; - longint unsigned rd2_wdata; +`include "uvm_macros.svh" +import uvm_pkg::*; - longint unsigned mem_addr; - longint unsigned mem_rdata; - longint unsigned mem_rmask; - longint unsigned mem_wdata; - longint unsigned mem_wmask; +`include "uvma_rvfi_constants.sv" +`include "uvma_rvfi_tdefs.sv" +`include "uvma_rvfi_utils.sv" -} st_rvfi; endpackage `endif diff --git a/corev_apu/tb/common/spike.sv b/corev_apu/tb/common/spike.sv index 6d85dbb844d..37f955903ad 100644 --- a/corev_apu/tb/common/spike.sv +++ b/corev_apu/tb/common/spike.sv @@ -13,20 +13,14 @@ // Description: Wrapped Spike Model for Tandem Verification import ariane_pkg::*; -import uvm_pkg::*; import rvfi_pkg::*; `include "uvm_macros.svh" -import "DPI-C" function int spike_create(string filename); -import "DPI-C" function void spike_set_param_uint64_t(string base, string name, longint unsigned value); -import "DPI-C" function void spike_set_param_str(string base, string name, string value); -import "DPI-C" function void spike_set_default_params(string profile); - -import "DPI-C" function void spike_step(output st_rvfi rvfi); +import "DPI-C" function void spike_step(inout st_rvfi rvfi); module spike #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_default, + parameter config_pkg::cva6_cfg_t CVA6Cfg = cva6_config_pkg::cva6_cfg, parameter type rvfi_instr_t = struct packed { logic [config_pkg::NRET-1:0] valid; logic [config_pkg::NRET*64-1:0] order; @@ -58,9 +52,8 @@ module spike #( input logic clk_i, input logic rst_ni, input logic clint_tick_i, - input rvfi_instr_t[CVA6Cfg.NrCommitPorts:1-0] rvfi_i + input rvfi_instr_t[CVA6Cfg.NrCommitPorts-1:0] rvfi_i ); - static uvm_cmdline_processor uvcl = uvm_cmdline_processor::get_inst(); string binary = ""; string rtl_isa = ""; @@ -68,140 +61,45 @@ module spike #( logic clint_tick_q, clint_tick_qq, clint_tick_qqq, clint_tick_qqqq; initial begin - `uvm_info("Spike Tandem", "Setting up Spike...", UVM_NONE); - void'(uvcl.get_arg_value("+PRELOAD=", binary)); - assert(binary != "") else $error("We need a preloaded binary for tandem verification"); - // ISA string format: RVIM?A?C?F?D?C?(_)* (FORNOW no RV64GC) - // Base string - rtl_isa = $sformatf("RV%-2dIM%s%s%s%s", - riscv::XLEN, - CVA6Cfg.RVA ? "A" : "", - CVA6Cfg.RVF ? "F" : "", - CVA6Cfg.RVD ? "D" : "", - CVA6Cfg.RVC ? "C" : ""); - // TODO Fixme - //if (CVA6Cfg.CVA6ConfigBExtEn) begin - // rtl_isa = $sformatf("%s_zba_zbb_zbc_zbs", rtl_isa); - //end - // TODO: build the ISA string with extensions - void'(spike_set_default_params("cva6")); - void'(spike_set_param_uint64_t("/top/core/0/", "boot_addr", 'h10000)); - void'(spike_set_param_str("/top/", "isa", rtl_isa)); - void'(spike_set_param_str("/top/core/0/", "isa", rtl_isa)); - void'(spike_create(binary)); - + rvfi_initialize_spike('h1); end - st_rvfi rvfi; + st_rvfi t_core, t_reference_model; logic [63:0] pc64; logic [31:0] rtl_instr; logic [31:0] spike_instr; string cause; - const string format_instr_str = "%15s | RVFI | %8d | %6d | %8x | %8x | %x | x%-8x | %-8x | x%-16x | %-16x | x%-8x | %-8x"; string instr; always_ff @(posedge clk_i) begin if (rst_ni) begin - for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin - pc64 = {{riscv::XLEN-riscv::VLEN{rvfi_i[i].pc_rdata[riscv::VLEN-1]}}, rvfi_i[i].pc_rdata}; - - if (rvfi_i[i].trap) begin -`ifdef SPIKE_MISSING_DATA - assert (rvfi.trap === rvfi_i[i].trap) else begin - $warning("\x1B[38;5;221m[Tandem] Exception not detected\x1B[0m"); - $display("\x1B[91mCVA6: %p\x1B[0m", rvfi_i[i].trap); - $display("\x1B[91mSpike: %p\x1B[0m", rvfi.trap); - $finish; - end -`endif - case (rvfi_i[i].cause) - 32'h0 : cause = "INSTR_ADDR_MISALIGNED"; - 32'h1 : cause = "INSTR_ACCESS_FAULT"; - 32'h2 : cause = "ILLEGAL_INSTR"; - 32'h3 : cause = "BREAKPOINT"; - 32'h4 : cause = "LD_ADDR_MISALIGNED"; - 32'h5 : cause = "LD_ACCESS_FAULT"; - 32'h6 : cause = "ST_ADDR_MISALIGNED"; - 32'h7 : cause = "ST_ACCESS_FAULT"; - 32'h8 : cause = "USER_ECALL"; - 32'h9 : cause = "SUPERVISOR_ECALL"; - 32'ha : cause = "VIRTUAL_SUPERVISOR_ECALL"; - 32'hb : cause = "MACHINE_ECALL"; - 32'hc : cause = "FETCH_PAGE_FAULT"; - 32'hd : cause = "LOAD_PAGE_FAULT"; - 32'hf : cause = "STORE_PAGE_FAULT"; - 32'h14: cause = "FETCH_GUEST_PAGE_FAULT"; - 32'h15: cause = "LOAD_GUEST_PAGE_FAULT"; - 32'h16: cause = "VIRTUAL_INSTRUCTION"; - 32'h17: cause = "STORE_GUEST_PAGE_FAULT"; - default: $error("[Spike Tandem] *** Unhandled trap ID %d (0x%h)\n", - rvfi_i[i].cause, rvfi_i[i].cause); - endcase; - - $display("\x1B[91mCVA6 exception %s at 0x%h\n", cause, pc64); - spike_step(rvfi); - end - if (rvfi_i[i].valid) begin - spike_step(rvfi); - spike_instr = (rvfi.insn[1:0] != 2'b11) ? {16'b0, rvfi.insn[15:0]} : rvfi.insn; - rtl_instr = rvfi_i[i].insn; - // $display("[Spike Tandem] commit_log = %p", commit_log); - // $display("\x1B[32mSpike: PC = 0x%h, instr = 0x%h\x1B[0m", commit_log.pc, spike_instr); - // $display("\x1B[91mCVA6: PC = 0x%h, instr = 0x%h\x1B[0m", pc64, rtl_instr); - assert (rvfi.pc_rdata === pc64) else begin - $warning("\x1B[38;5;221m[Tandem] PC Mismatch\x1B[0m"); - $display("\x1B[91mSpike: 0x%16h\x1B[0m", rvfi.pc_rdata); - $display("\x1B[91mCVA6: 0x%16h\x1B[0m", pc64); - $finish; - end - if (!rvfi_i[i].trap) begin - assert (rvfi.mode === rvfi_i[i].mode) else begin - $warning("\x1B[38;5;221m[Tandem] Privilege level mismatch\x1B[0m"); - $display("\x1B[91mSpike: %2d @ PC 0x%16h\x1B[0m", rvfi.mode, rvfi.pc_rdata); - $display("\x1B[91mCVA6: %2d @ PC 0x%16h\x1B[0m", rvfi_i[i].mode, pc64); - $finish; - end - - assert (spike_instr === rtl_instr) else begin - $warning("\x1B[38;5;221m[Tandem] Decoded instruction mismatch\x1B[0m"); - $display("\x1B[91m0x%h != 0x%h @ PC 0x%h\x1B[0m", rtl_instr, spike_instr, rvfi.pc_rdata); - $finish; - end - - // TODO(zarubaf): Adapt for floating point instructions - if (rvfi_i[i].rd_addr != 0) begin - // check the return value - // $display("\x1B[37m%h === %h\x1B[0m", commit_instr_i[i].rd, commit_log.rd); - assert (rvfi_i[i].rd_addr[4:0] === rvfi.rd1_addr[4:0]) else begin - $warning("\x1B[38;5;221m[Tandem] Destination register mismatch\x1B[0m"); - $display("\x1B[91mSpike: x%-4d @ PC 0x%16h\x1B[0m", - rvfi.rd1_addr[4:0], rvfi.pc_rdata); - $display("\x1B[91mCVA6: x%-4d @ PC 0x%16h\x1B[0m", - rvfi_i[i].rd_addr[4:0], pc64); - $finish; - end - assert (rvfi_i[i].rd_wdata === rvfi.rd1_wdata) else begin - $warning("\x1B[38;5;221m[Tandem] Write back data mismatch\x1B[0m"); - $display("\x1B[91mSpike: x%-4d <- 0x%16h @ PC 0x%16h\x1B[0m", - rvfi.rd1_wdata[4:0], rvfi.rd1_wdata, rvfi.pc_rdata); - $display("\x1B[91mCVA6: x%-4d <- 0x%16h @ PC 0x%16h\x1B[0m", - rvfi_i[i].rd_addr[4:0], rvfi_i[i].rd_wdata, pc64); - $finish; - end - end - end - instr = $sformatf(format_instr_str, $sformatf("%t", $time), - rvfi.cycle_cnt, - rvfi.order, - rvfi.pc_rdata, - rvfi.insn, - rvfi.mode, - rvfi.rs1_addr, rvfi.rs1_rdata, - rvfi.rs2_addr, rvfi.rs2_rdata, - rvfi.rd1_addr, rvfi.rd1_wdata); - $display(instr); + if (rvfi_i[i].valid || rvfi_i[i].trap) begin + spike_step(t_reference_model); + t_core.order = rvfi_i[i].order; + t_core.insn = rvfi_i[i].insn; + t_core.trap = rvfi_i[i].trap; + t_core.cause = rvfi_i[i].cause; + t_core.halt = rvfi_i[i].halt; + t_core.intr = rvfi_i[i].intr; + t_core.mode = rvfi_i[i].mode; + t_core.ixl = rvfi_i[i].ixl; + t_core.rs1_addr = rvfi_i[i].rs1_addr; + t_core.rs2_addr = rvfi_i[i].rs2_addr; + t_core.rs1_rdata = rvfi_i[i].rs1_rdata; + t_core.rs2_rdata = rvfi_i[i].rs2_rdata; + t_core.rd1_addr = rvfi_i[i].rd_addr; + t_core.rd1_wdata = rvfi_i[i].rd_wdata; + t_core.pc_rdata = rvfi_i[i].pc_rdata; + t_core.pc_wdata = rvfi_i[i].pc_wdata; + t_core.mem_addr = rvfi_i[i].mem_addr; + t_core.mem_rmask = rvfi_i[i].mem_rmask; + t_core.mem_wmask = rvfi_i[i].mem_wmask; + t_core.mem_rdata = rvfi_i[i].mem_rdata; + t_core.mem_wdata = rvfi_i[i].mem_wdata; + + rvfi_compare(t_core, t_reference_model); end end end diff --git a/verif/env/uvme/uvme_cva6_cfg.sv b/verif/env/uvme/uvme_cva6_cfg.sv index 27d7168c17e..461795274d2 100644 --- a/verif/env/uvme/uvme_cva6_cfg.sv +++ b/verif/env/uvme/uvme_cva6_cfg.sv @@ -31,7 +31,7 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c; // Integrals rand bit enabled; - rand bit scoreboarding_enabled; + rand bit scoreboard_enabled; rand bit cov_model_enabled; rand bit cov_cvxif_model_enabled; rand bit cov_isa_model_enabled; @@ -51,7 +51,7 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c; `uvm_object_utils_begin(uvme_cva6_cfg_c) `uvm_field_int ( enabled , UVM_DEFAULT ) `uvm_field_enum(uvm_active_passive_enum, is_active , UVM_DEFAULT ) - `uvm_field_int ( scoreboarding_enabled , UVM_DEFAULT ) + `uvm_field_int ( scoreboard_enabled , UVM_DEFAULT ) `uvm_field_int ( cov_model_enabled , UVM_DEFAULT ) `uvm_field_int ( trn_log_enabled , UVM_DEFAULT ) `uvm_field_int ( ext_zicond_supported , UVM_DEFAULT ) @@ -73,7 +73,7 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c; constraint defaults_cons { soft enabled == 1; soft is_active == UVM_ACTIVE; - soft scoreboarding_enabled == 1; + soft scoreboard_enabled == 1; soft cov_model_enabled == 1; soft trn_log_enabled == 1; soft sys_clk_period == uvme_cva6_sys_default_clk_period; // see uvme_cva6_constants.sv @@ -147,15 +147,15 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c; isacov_cfg.enabled == 1; rvfi_cfg.enabled == 1; } - + isacov_cfg.seq_instr_group_x2_enabled == 1; isacov_cfg.seq_instr_group_x3_enabled == 0; isacov_cfg.seq_instr_group_x4_enabled == 0; isacov_cfg.seq_instr_x2_enabled == 1; isacov_cfg.reg_crosses_enabled == 0; isacov_cfg.reg_hazards_enabled == 1; - rvfi_cfg.nret == RVFI_NRET; - + rvfi_cfg.nret == cva6_config_pkg::CVA6ConfigNrCommitPorts; + if (is_active == UVM_ACTIVE) { clknrst_cfg.is_active == UVM_ACTIVE; isacov_cfg.is_active == UVM_PASSIVE; @@ -177,6 +177,10 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c; cov_isa_model_enabled == 1; } + if (scoreboard_enabled) { + rvfi_cfg.scoreboard_enabled == 1; + } + } /** diff --git a/verif/env/uvme/uvme_cva6_constants.sv b/verif/env/uvme/uvme_cva6_constants.sv index aea0364e17f..c77ec837467 100644 --- a/verif/env/uvme/uvme_cva6_constants.sv +++ b/verif/env/uvme/uvme_cva6_constants.sv @@ -26,6 +26,5 @@ parameter uvme_cva6_debug_default_clk_period = 10_000; // 10ns parameter XLEN = 32; parameter ILEN = 32; -parameter RVFI_NRET = 1; `endif // __UVME_CVA6_CONSTANTS_SV__ diff --git a/verif/env/uvme/uvme_cva6_env.sv b/verif/env/uvme/uvme_cva6_env.sv index 9889a2c2b05..98f2664c36d 100644 --- a/verif/env/uvme/uvme_cva6_env.sv +++ b/verif/env/uvme/uvme_cva6_env.sv @@ -50,7 +50,7 @@ class uvme_cva6_env_c extends uvm_env; virtual uvmt_axi_switch_intf axi_switch_vif; //CSR register model - cva6_csr_reg_block csr_reg_block; + cva6_csr_reg_block csr_reg_block; cva6_csr_reg_adapter csr_reg_adapter; cva6_csr_reg_predictor#(uvma_isacov_mon_trn_c) csr_reg_predictor; @@ -184,7 +184,7 @@ function void uvme_cva6_env_c::build_phase(uvm_phase phase); csr_reg_block = cva6_csr_reg_block::type_id::create("csr_reg_block", this); csr_reg_predictor = cva6_csr_reg_predictor#(uvma_isacov_mon_trn_c)::type_id::create("csr_reg_predictor", this); csr_reg_adapter = cva6_csr_reg_adapter::type_id::create("csr_reg_adapter",, get_full_name()); - csr_reg_block.build(); + csr_reg_block.build(); end endfunction : build_phase @@ -195,7 +195,7 @@ function void uvme_cva6_env_c::connect_phase(uvm_phase phase); super.connect_phase(phase); if (cfg.enabled) begin - if (cfg.scoreboarding_enabled) begin + if (cfg.scoreboard_enabled) begin connect_predictor (); connect_scoreboard(); end @@ -207,7 +207,7 @@ function void uvme_cva6_env_c::connect_phase(uvm_phase phase); connect_coverage_model(); end end - + if (csr_reg_block.get_parent() == null) begin csr_reg_block.default_map.set_base_addr('h0); csr_reg_predictor.map = csr_reg_block.default_map; @@ -269,7 +269,7 @@ endfunction: create_agents function void uvme_cva6_env_c::create_env_components(); - if (cfg.scoreboarding_enabled) begin + if (cfg.scoreboard_enabled) begin predictor = uvme_cva6_prd_c::type_id::create("predictor", this); sb = uvme_cva6_sb_c ::type_id::create("sb" , this); end @@ -361,11 +361,9 @@ function void uvme_cva6_env_c::connect_coverage_model(); if (cfg.cov_isa_model_enabled) begin isacov_agent.monitor.ap.connect(cov_model.isa_covg.mon_trn_fifo.analysis_export); end - foreach (rvfi_agent.instr_mon_ap[i]) begin - rvfi_agent.instr_mon_ap[i].connect(isacov_agent.monitor.rvfi_instr_imp); - end - + clknrst_agent.mon_ap.connect(cov_model.reset_export); + rvfi_agent.rvfi_core_ap.connect(isacov_agent.monitor.rvfi_instr_imp); endfunction: connect_coverage_model diff --git a/verif/env/uvme/uvme_cva6_pkg.sv b/verif/env/uvme/uvme_cva6_pkg.sv index 0e5a79fc276..725ea04248d 100644 --- a/verif/env/uvme/uvme_cva6_pkg.sv +++ b/verif/env/uvme/uvme_cva6_pkg.sv @@ -37,6 +37,7 @@ */ package uvme_cva6_pkg; + import cva6_config_pkg ::*; import uvm_pkg ::*; import uvml_hrtbt_pkg ::*; import uvml_sb_pkg ::*; diff --git a/verif/regress/install-spike.sh b/verif/regress/install-spike.sh index 287aaab0710..1a5eb94aff1 100755 --- a/verif/regress/install-spike.sh +++ b/verif/regress/install-spike.sh @@ -34,7 +34,7 @@ else # Use the in-tree vendorized Spike if SPIKE_SRC_DIR is not set # or when a fully local installation was requested. if [ -z "$SPIKE_SRC_DIR" -o "$SPIKE_INSTALL_DIR" = "__local__" ]; then - export SPIKE_SRC_DIR=$ROOT_PROJECT/vendor/riscv/riscv-isa-sim + export SPIKE_SRC_DIR=$ROOT_PROJECT/verif/core-v-verif/vendor/riscv/riscv-isa-sim fi # Set the installation location of Spike. @@ -55,7 +55,9 @@ else # Build and install Spike (including extensions). mkdir -p build cd build - ../configure --prefix="$SPIKE_INSTALL_DIR" + if [[ ! -f config.log ]]; then + ../configure --prefix="$SPIKE_INSTALL_DIR" + fi make -j${NUM_JOBS} echo "Installing Spike in '$SPIKE_INSTALL_DIR'..." make install diff --git a/verif/sim/Makefile b/verif/sim/Makefile index 8af6ebf5b7f..f9c55efa443 100644 --- a/verif/sim/Makefile +++ b/verif/sim/Makefile @@ -14,6 +14,7 @@ ifndef CVA6_REPO_DIR $(warning must set CVA6_REPO_DIR to point at the root of CVA6 sources and CVA6_TB_DIR to point here -- doing it for you...) export CVA6_REPO_DIR = $(abspath $(root-dir)../..) export CVA6_TB_DIR = $(root-dir)/../tb/core +export CORE_V_VERIF = $(root-dir)/../core-v-verif endif ifndef TARGET_CFG export TARGET_CFG = $(target) @@ -26,7 +27,9 @@ export HPDCACHE_TARGET_CFG .DEFAULT_GOAL := help -FLIST_TB := $(CVA6_TB_DIR)/Flist.cva6_tb +FLIST_TB := $(CVA6_TB_DIR)/Flist.cva6_tb +FLIST_COSIM := $(CVA6_TB_DIR)/Flist.cva6_tandem_cosim + # target takes one of the following cva6 hardware configuration: # cv64a6_imafdc_sv39, cv32a6_imac_sv0, cv32a6_imac_sv32, cv32a6_imafc_sv32 target ?= cv64a6_imafdc_sv39 @@ -42,6 +45,10 @@ issrun_opts ?= isspostrun_opts ?= log ?= variant ?= + +# Spike tandem mode: default to environment setting (DISABLED if envariable SPIKE_TANDEM is not set). +export spike-tandem ?= $(SPIKE_TANDEM) + # Set Spike step count limit if the caller provided a step count value in variable 'steps'. ifneq ($(steps),) spike_stepout = --steps=$(steps) @@ -120,17 +127,20 @@ spike: ############################################################################### # testharness specific commands, variables ############################################################################### -vcs-testharness: - make -C $(path_var) vcs_build target=$(target) defines=$(subst +define+,,$(isscomp_opts)) - $(path_var)/work-vcs/simv +vcs+lic+wait $(if $(VERDI), -verdi -do $(path_var)/init_testharness.do,) +permissive -sv_lib $(path_var)/work-dpi/ariane_dpi \ +vcs-testharness: elf_library + make -C $(path_var) work-dpi/ariane_dpi.so + make -C $(path_var) vcs_build target=$(target) defines=$(subst +define+,,$(isscomp_opts))$(if $(spike-tandem),SPIKE_TANDEM=1) + $(path_var)/work-vcs/simv $(if $(VERDI), -verdi -do $(path_var)/init_testharness.do,) +permissive \ +tohost_addr=$(shell $$RISCV/bin/${CV_SW_PREFIX}nm -B $(elf) | grep -w tohost | cut -d' ' -f1) \ - +PRELOAD=$(elf) +permissive-off ++$(elf) $(issrun_opts) + +PRELOAD=$(elf) +elf_file=$(elf) +permissive-off ++$(elf) $(issrun_opts) $(if $(spike-tandem),-sv_lib $(SPIKE_INSTALL_DIR)/lib/libriscv) \ + -sv_lib $(CORE_V_VERIF)/vendor/elfloader/elfloader $(tool_path)/spike-dasm --isa=$(variant) < ./trace_rvfi_hart_00.dasm > $(log) grep $(isspostrun_opts) ./trace_rvfi_hart_00.dasm veri-testharness: make -C $(path_var) verilate verilator="verilator --no-timing" target=$(target) defines=$(subst +define+,,$(isscomp_opts)) - $(path_var)/work-ver/Variane_testharness $(if $(TRACE_COMPACT), -f verilator.fst) $(if $(TRACE_FAST), -v verilator.vcd) $(elf) $(issrun_opts) +PRELOAD=$(elf) \ + $(path_var)/work-ver/Variane_testharness $(if $(TRACE_COMPACT), -f verilator.fst) $(if $(TRACE_FAST), -v verilator.vcd) $(elf) $(issrun_opts) \ + +elf-bin=$(elf) +PRELOAD=$(elf) \ +tohost_addr=$(shell $$RISCV/bin/${CV_SW_PREFIX}nm -B $(elf) | grep -w tohost | cut -d' ' -f1) $(tool_path)/spike-dasm --isa=$(variant) < ./trace_rvfi_hart_00.dasm > $(log) # If present, move default trace files to per-test directory. @@ -156,23 +166,23 @@ export CVA6_UVMT_PATH = $(CVA6_REPO_DIR)/verif/tb/uvmt export CVA6_UVME_PATH = $(CVA6_REPO_DIR)/verif/env/uvme export CV_CORE_LC = cva6 export CV_CORE_UC = CVA6 -export DV_UVMT_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/$(CV_CORE_LC)/tb/uvmt -export DV_UVME_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/$(CV_CORE_LC)/env/uvme -export DV_UVML_HRTBT_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_libs/uvml_hrtbt -export DV_UVMA_CORE_CNTRL_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_core_cntrl -export DV_UVMA_RVFI_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_rvfi -export DV_UVMA_ISACOV_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_isacov -export DV_UVMA_CLKNRST_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_clknrst -export DV_UVMA_CVXIF_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_cvxif -export DV_UVMA_AXI_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_axi -export DV_UVMA_INTERRUPT_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_interrupt -export DV_UVMA_DEBUG_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_debug -export DV_UVMA_OBI_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_obi -export DV_UVML_TRN_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_libs/uvml_trn -export DV_UVML_MEM_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_libs/uvml_mem -export DV_UVML_LOGS_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_libs/uvml_logs -export DV_UVML_SB_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_libs/uvml_sb -export CV_CORE_PKG = $(CVA6_REPO_DIR)/verif/core-v-verif/core-v-cores/$(CV_CORE_LC) +export DV_UVMT_PATH = $(CVA6_REPO_DIR)/verif/tb/uvmt +export DV_UVME_PATH = $(CVA6_REPO_DIR)/verif/env/uvme +export DV_UVML_HRTBT_PATH = $(CORE_V_VERIF)/lib/uvm_libs/uvml_hrtbt +export DV_UVMA_CORE_CNTRL_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_core_cntrl +export DV_UVMA_RVFI_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_rvfi +export DV_UVMA_ISACOV_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_isacov +export DV_UVMA_CLKNRST_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_clknrst +export DV_UVMA_CVXIF_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_cvxif +export DV_UVMA_AXI_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_axi +export DV_UVMA_INTERRUPT_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_interrupt +export DV_UVMA_DEBUG_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_debug +export DV_UVMA_OBI_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_obi +export DV_UVML_TRN_PATH = $(CORE_V_VERIF)/lib/uvm_libs/uvml_trn +export DV_UVML_MEM_PATH = $(CORE_V_VERIF)/lib/uvm_libs/uvml_mem +export DV_UVML_LOGS_PATH = $(CORE_V_VERIF)/lib/uvm_libs/uvml_logs +export DV_UVML_SB_PATH = $(CORE_V_VERIF)/lib/uvm_libs/uvml_sb +export CV_CORE_PKG = $(CORE_V_VERIF)/core-v-cores/$(CV_CORE_LC) export DESIGN_RTL_DIR = $(CV_CORE_PKG)/rtl DPI_DASM_PKG = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/dpi_dasm @@ -180,7 +190,7 @@ DPI_DASM_SPIKE_PKG = $(CVA6_REPO_DIR)/verif/core-v-verif/$(CV_CORE_LC export DPI_DASM_ROOT = $(DPI_DASM_PKG) export DPI_DASM_SPIKE_ROOT = $(DPI_DASM_SPIKE_PKG) export TBSRC_HOME = $(CVA6_REPO_DIR)/verif/tb -export DV_OVPM_HOME = $(CVA6_REPO_DIR)/verif/core-v-verif/$(CV_CORE_LC)/vendor_lib/imperas +export DV_OVPM_HOME = $(CORE_V_VERIF)/$(CV_CORE_LC)/vendor_lib/imperas export DV_OVPM_MODEL = $(DV_OVPM_HOME)/riscv_$(CV_CORE_UC)_OVPsim export DV_OVPM_DESIGN = $(DV_OVPM_HOME)/design @@ -188,44 +198,46 @@ ALL_UVM_FLAGS = -lca -sverilog +incdir+$(VCS_HOME)/etc/uvm/src \ $(VCS_HOME)/etc/uvm/src/uvm_pkg.sv +UVM_VERBOSITY=UVM_MEDIUM -ntb_opts uvm-1.2 -timescale=1ns/1ps \ -assert svaext -race=all -ignore unique_checks -full64 -q +incdir+$(VCS_HOME)/etc/uvm/src \ +incdir+$(CVA6_REPO_DIR)/verif/env/uvme +incdir+$(CVA6_REPO_DIR)/verif/tb/uvmt \ - $(if $(DEBUG), -debug_access+all $(if $(VERDI), -kdb) $(if $(TRACE_COMPACT),+vcs+fsdbon))\ - -cm_seqnoconst -diag noconst + $(if $(DEBUG), -debug_access+all $(if $(VERDI), -kdb) $(if $(TRACE_COMPACT),+vcs+fsdbon)) \ + $(if $(spike-tandem), +define+SPIKE_TANDEM=1) -ALL_SIMV_UVM_FLAGS = +vcs+lic+wait $(issrun_opts) \ - -sv_lib $(CVA6_REPO_DIR)/verif/core-v-verif/lib/dpi_dasm/lib/Linux64/libdpi_dasm +signature=I-ADD-01.signature_output \ +ALL_SIMV_UVM_FLAGS = $(if $(spike-tandem), +permissive) -licwait 20 $(issrun_opts) \ + $(if $(spike-tandem),-sv_lib $(CORE_V_VERIF)/tools/spike/lib/libdisasm) \ + -sv_lib $(CORE_V_VERIF)/lib/dpi_dasm/lib/Linux64/libdpi_dasm +signature=I-ADD-01.signature_output \ +UVM_TESTNAME=uvmt_cva6_firmware_test_c ifneq ($(DEBUG),) # If RTL DEBUG support requested ifneq ($(VERDI),) # If VERDI interactive mode requested, use GUI and do not run simulation ALL_SIMV_UVM_FLAGS += \ - -gui -do $(CVA6_REPO_DIR)/verif/sim/init_uvm.do + -gui -do $(CORE_V_VERIF)/cva6/sim/init_uvm.do else # else: *not* VERDI, use CLI mode and appropriate batch dump controls ifneq ($(TRACE_FAST),) # TRACE_FAST: Generate waveform trace in VPD format ALL_SIMV_UVM_FLAGS += \ - -ucli -do $(CVA6_REPO_DIR)/verif/sim/init_run_uvm_vpd.do + -ucli -do $(CORE_V_VERIF)/cva6/sim/init_run_uvm_vpd.do SIMV_TRACE_EXTN = vpd endif ifneq ($(TRACE_COMPACT),) # TRACE_COMPACT: Generate waveform trace in FSDB format ALL_SIMV_UVM_FLAGS += \ - -ucli -do $(CVA6_REPO_DIR)/verif/sim/init_run_uvm_fsdb.do + -ucli -do $(CORE_V_VERIF)/cva6/sim/init_run_uvm_fsdb.do SIMV_TRACE_EXTN = fsdb endif endif endif -dpi-library = $(VCS_WORK_DIR)/work-dpi +dpi-library = $(CVA6_REPO_DIR)/work-dpi dpi_build: - mkdir -p $(dpi-library) - g++ -shared -fPIC -std=c++17 -Bsymbolic -I../corev_apu/tb/dpi -O3 -I$(SPIKE_INSTALL_DIR)/include \ - -I$(VCS_HOME)/include -I$(RISCV)/include -c $(CVA6_REPO_DIR)/corev_apu/tb/dpi/elfloader.cc \ - -o $(dpi-library)/elfloader.o - g++ -shared -m64 -o $(dpi-library)/ariane_dpi.so $(dpi-library)/elfloader.o -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib + $(MAKE) -C $(CVA6_REPO_DIR) $@ + +elf_library: + $(MAKE) -C $(CORE_V_VERIF)/vendor/elfloader/ -vcs_uvm_comp: dpi_build + +vcs_uvm_comp: elf_library @echo "[VCS] Building Model" mkdir -p $(VCS_WORK_DIR) cd $(VCS_WORK_DIR) && vcs $(ALL_UVM_FLAGS) \ -f $(FLIST_CORE) -f $(FLIST_TB) \ + \ -f $(CVA6_UVMT_DIR)/uvmt_cva6.flist \ $(cov-comp-opt) +define+UNSUPPORTED_WITH+ $(isscomp_opts)\ -top uvmt_cva6_tb @@ -233,31 +245,25 @@ vcs_uvm_comp: dpi_build vcs_uvm_run: $(if $(TRACE_FAST), unset VERDI_HOME ;) \ cd $(VCS_WORK_DIR)/ && \ - $(VCS_WORK_DIR)/simv ${ALL_SIMV_UVM_FLAGS} \ + $(VCS_WORK_DIR)/simv \ + -sv_lib $(CORE_V_VERIF)/vendor/elfloader/elfloader \ + -sv_lib $(SPIKE_INSTALL_DIR)/lib/libriscv \ + ${ALL_SIMV_UVM_FLAGS} \ ++$(elf) \ - +PRELOAD=$(elf) \ - +tohost_addr=$(shell $$RISCV/bin/riscv-none-elf-nm -B $(elf) | grep -w tohost | cut -d' ' -f1) \ - -sv_lib $(dpi-library)/ariane_dpi \ - $(cov-run-opt) $(issrun_opts) && \ - mv $(VCS_WORK_DIR)/trace_rvfi_hart_00.dasm $(CVA6_REPO_DIR)/verif/sim/ && \ - { [ -z "`ls $(VCS_WORK_DIR)/*.$(SIMV_TRACE_EXTN)`" ] || \ - for i in `ls $(VCS_WORK_DIR)/*.$(SIMV_TRACE_EXTN)` ; do mv $$i $(CVA6_REPO_DIR)/verif/sim/`basename $$i` ; done || \ - true ; } + +PRELOAD=$(elf) +elf_file=$(elf) \ + +tohost_addr=$(shell $$RISCV/bin/$(CV_SW_PREFIX)nm -B $(elf) | grep -w tohost | cut -d' ' -f1) \ + $(cov-run-opt) $(issrun_opts) vcs-uvm: make vcs_uvm_comp make vcs_uvm_run - $(tool_path)/spike-dasm --isa=$(variant) < ./trace_rvfi_hart_00.dasm > $(log) - grep $(isspostrun_opts) ./trace_rvfi_hart_00.dasm - [ -z "`ls *.$(SIMV_TRACE_EXTN)`" ] || \ - for i in `ls *.$(SIMV_TRACE_EXTN)` ; do mv $$i `dirname $(log)`/`basename $(log) .log`.$(target).$$i ; done || true generate_cov_dash: - urg -hvp_proj cva6_embedded -format both -group instcov_for_score -hvp_attributes description -dir vcs_results/default/vcs.d/simv.vdb -plan cva6.hvp -mod modifier_embedded.hvp -tgl portsonly + urg -hvp_proj cva6_embedded -format both -group instcov_for_score -hvp_attributes description -dir $(VCS_WORK_DIR)/simv.vdb -plan cva6.hvp -mod modifier_embedded.hvp -tgl portsonly vcs_clean_all: @echo "[VCS] Cleanup (entire vcs_work dir)" - rm -rf $(CVA6_REPO_DIR)/verif/sim/vcs_results/ verdiLog/ simv* *.daidir *.vpd *.fsdb *.db csrc ucli.key vc_hdrs.h novas* inter.fsdb uart + rm -rf $(CORE_V_VERIF)/cva6/sim/vcs_results/ verdiLog/ simv* *.daidir *.vpd *.fsdb *.db csrc ucli.key vc_hdrs.h novas* inter.fsdb uart ############################################################################### # Common targets and rules diff --git a/verif/sim/cva6.py b/verif/sim/cva6.py index 6700f9da5fe..ae5babb2d35 100644 --- a/verif/sim/cva6.py +++ b/verif/sim/cva6.py @@ -561,7 +561,7 @@ def run_c(c_test, iss_yaml, isa, target, mabi, gcc_opts, iss_opts, output_dir, -nostartfiles %s \ -I%s/dv/user_extension \ -T%s %s -o %s " % \ - (get_env_var("RISCV_GCC", debug_cmd = debug_cmd), c_test, cwd, + (get_env_var("RISCV_GCC", debug_cmd = debug_cmd), c_test, cwd, linker, gcc_opts, elf)) cmd += (" -march=%s" % isa) cmd += (" -mabi=%s" % mabi) @@ -849,9 +849,9 @@ def load_config(args, cwd): Returns: Loaded configuration dictionary. """ - + global isa_extension_list - isa_extension_list = args.isa_extension.split(",") + isa_extension_list = args.isa_extension.split(",") isa_extension_list.append("zicsr") isa_extension_list.append("zifencei") @@ -1017,13 +1017,13 @@ def main(): cfg = load_config(args, cwd) # Create output directory output_dir = create_output(args.o, args.noclean, cwd+"/out_") - + #add z,s,x extensions to the isa if there are some - if isa_extension_list !=['']: + if isa_extension_list !=['']: for i in isa_extension_list: if i!= "": args.isa += (f"_{i}") - + if args.verilog_style_check: logging.debug("Run style check") style_err = run_cmd("verilog_style/run.sh") diff --git a/verif/sim/cva6.yaml b/verif/sim/cva6.yaml index 4112c73fb9e..be4fea18917 100644 --- a/verif/sim/cva6.yaml +++ b/verif/sim/cva6.yaml @@ -18,7 +18,7 @@ # Always keep this value in sync with the settings of RTL simulators (cf. # values below). cmd: > - make spike steps=2000000 variant= elf= tool_path= log= + make spike variant= elf= tool_path= log= ############################################################################### # Verilator diff --git a/verif/sim/cva6_spike_log_to_trace_csv.py b/verif/sim/cva6_spike_log_to_trace_csv.py index 486c8d9750f..855a04c8242 100644 --- a/verif/sim/cva6_spike_log_to_trace_csv.py +++ b/verif/sim/cva6_spike_log_to_trace_csv.py @@ -121,7 +121,7 @@ def read_spike_trace(path, full_trace): # true. Otherwise, we are in state EFFECT if instr is not None, otherwise we # are in state INSTR. - end_trampoline_re = re.compile(r'core.*: 0x0*1010 ') + end_trampoline_re = re.compile(r'core.*: 0x0*10010 ') in_trampoline = True instr = None diff --git a/verif/tb/uvmt/cva6_tb_wrapper.sv b/verif/tb/uvmt/cva6_tb_wrapper.sv index ebeba3dd602..7abe87f94df 100644 --- a/verif/tb/uvmt/cva6_tb_wrapper.sv +++ b/verif/tb/uvmt/cva6_tb_wrapper.sv @@ -244,12 +244,11 @@ module cva6_tb_wrapper import uvmt_cva6_pkg::*; #( longint address; longint len; byte buffer[]; - void'(uvcl.get_arg_value("+PRELOAD=", binary)); + void'(uvcl.get_arg_value("+elf_file=", binary)); if (binary != "") begin void'(read_elf(binary)); - wait(clk_i); // while there are more sections to process diff --git a/verif/tb/uvmt/uvmt_cva6_pkg.sv b/verif/tb/uvmt/uvmt_cva6_pkg.sv index 7469c8a90b8..91092835213 100644 --- a/verif/tb/uvmt/uvmt_cva6_pkg.sv +++ b/verif/tb/uvmt/uvmt_cva6_pkg.sv @@ -38,6 +38,7 @@ package uvmt_cva6_pkg; import uvm_pkg::*; import uvme_cva6_pkg::*; + import uvma_rvfi_pkg::*; import uvml_hrtbt_pkg::*; import uvml_logs_pkg::*; diff --git a/verif/tb/uvmt/uvmt_cva6_tb.sv b/verif/tb/uvmt/uvmt_cva6_tb.sv index 0c89a510e6f..986f165f778 100644 --- a/verif/tb/uvmt/uvmt_cva6_tb.sv +++ b/verif/tb/uvmt/uvmt_cva6_tb.sv @@ -30,6 +30,8 @@ module uvmt_cva6_tb; import uvmt_cva6_pkg::*; import uvme_cva6_pkg::*; + localparam RVFI_NRET = cva6_config_pkg::CVA6ConfigNrCommitPorts; + // CVA6 config localparam config_pkg::cva6_cfg_t CVA6Cfg = cva6_config_pkg::cva6_cfg; localparam bit IsRVFI = bit'(cva6_config_pkg::CVA6ConfigRvfiTrace); @@ -82,9 +84,9 @@ module uvmt_cva6_tb; uvma_rvfi_instr_if #( uvme_cva6_pkg::ILEN, uvme_cva6_pkg::XLEN - ) rvfi_instr_if [uvme_cva6_pkg::RVFI_NRET-1:0] (); + ) rvfi_instr_if [RVFI_NRET-1:0] (); - uvma_rvfi_csr_if#(uvme_cva6_pkg::XLEN) rvfi_csr_if [uvme_cva6_pkg::RVFI_NRET-1:0](); + uvma_rvfi_csr_if#(uvme_cva6_pkg::XLEN) rvfi_csr_if [RVFI_NRET-1:0](); uvmt_default_inputs_intf default_inputs_vif(); @@ -132,13 +134,14 @@ module uvmt_cva6_tb; .rvfi_o(rvfi_if.rvfi_o) ); - for (genvar i = 0; i < uvme_cva6_pkg::RVFI_NRET; i++) begin + for (genvar i = 0; i < RVFI_NRET; i++) begin assign rvfi_instr_if[i].clk = clknrst_if.clk; assign rvfi_instr_if[i].reset_n = clknrst_if.reset_n; assign rvfi_instr_if[i].rvfi_valid = rvfi_if.rvfi_o[i].valid; assign rvfi_instr_if[i].rvfi_order = rvfi_if.rvfi_o[i].order; assign rvfi_instr_if[i].rvfi_insn = rvfi_if.rvfi_o[i].insn; assign rvfi_instr_if[i].rvfi_trap = rvfi_if.rvfi_o[i].trap; + assign rvfi_instr_if[i].rvfi_cause = rvfi_if.rvfi_o[i].cause; assign rvfi_instr_if[i].rvfi_halt = rvfi_if.rvfi_o[i].halt; assign rvfi_instr_if[i].rvfi_intr = rvfi_if.rvfi_o[i].intr; assign rvfi_instr_if[i].rvfi_mode = rvfi_if.rvfi_o[i].mode; @@ -165,7 +168,7 @@ module uvmt_cva6_tb; assign default_inputs_vif.debug_req = 1'b0; - for (genvar i = 0; i < uvme_cva6_pkg::RVFI_NRET; i++) begin + for (genvar i = 0; i < RVFI_NRET; i++) begin initial begin uvm_config_db#(virtual uvma_rvfi_instr_if )::set(null,"*", $sformatf("instr_vif%0d", i), rvfi_instr_if[i]); diff --git a/verif/tests/uvmt/compliance-tests/uvmt_cva6_firmware_test.sv b/verif/tests/uvmt/compliance-tests/uvmt_cva6_firmware_test.sv index e6d73a71a19..703b94f1a7f 100644 --- a/verif/tests/uvmt/compliance-tests/uvmt_cva6_firmware_test.sv +++ b/verif/tests/uvmt/compliance-tests/uvmt_cva6_firmware_test.sv @@ -61,6 +61,11 @@ class uvmt_cva6_firmware_test_c extends uvmt_cva6_base_test_c; */ extern virtual task configure_phase(uvm_phase phase); + /** + * Override types with the UVM Factory + */ + extern virtual function void build_phase(uvm_phase phase); + /** * Enable program execution, wait for completion. */ @@ -92,6 +97,14 @@ task uvmt_cva6_firmware_test_c::reset_phase(uvm_phase phase); endtask : reset_phase +function void uvmt_cva6_firmware_test_c::build_phase(uvm_phase phase); + super.build_phase(phase); + + `uvm_info("firmware_test", "Overriding Reference Model with Spike", UVM_NONE) + set_type_override_by_type(uvma_rvfi_reference_model::get_type(),uvma_rvfi_spike::get_type()); + +endfunction : build_phase + task uvmt_cva6_firmware_test_c::configure_phase(uvm_phase phase);